IS42S16400B

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IS42S16400B
Clock frequency: 166, Fully synchronous; signals referenced positive clock edge Internal bank hiding access/precharge Single 3.3V power supply LVTTL interface Programmable burst length full page) Programmable burst sequence: Sequential/Interleave Self refresh modes 4096 refresh cycles every Random column address every clock cycle Programmable latency clocks) Burst read/write operations capability Burst termination burst stop precharge command Byte controlled LDQM UDQM Industrial temperature availability Package: 400-mil 54-pin TSOP Lead-free package available
ISSI
FEBRUARY 2005
OVERVIEW ISSI's 64Mb Synchronous DRAM IS42S16400B organized
1,048,576 bits 16-bit 4-bank improved performance. synchronous DRAMs achieve high-speed data transfer using pipeline architecture. inputs outputs signals refer rising edge clock input.
CONFIGURATIONS
54-Pin TSOP (Type
VDDQ GNDQ VDDQ GNDQ LDQM DQ15 GNDQ DQ14 DQ13 VDDQ DQ12 DQ11 GNDQ DQ10 VDDQ UDQM
DESCRIPTIONS
A0-A11 BA0, DQ15 Address Input Bank Select Address Data System Clock Input Clock Enable Chip Select Address Strobe Command Column Address Strobe Command LDQM UDQM VDDQ GNDQ Write Enable Lower Bye, Input/Output Mask Upper Bye, Input/Output Mask Power Ground Power Supply Ground Connection
Copyright 2005 Integrated Silicon Solution, Inc. rights reserved. ISSI reserves right make changes this specification products time without notice. ISSI assumes liability arising application information, products services described herein. Customers advised obtain latest version this device specification before relying published information before placing orders products.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 02/10/05
IS42S16400B
ISSI
GENERAL DESCRIPTION
64Mb SDRAM high speed CMOS, dynamic random-access memory designed operate 3.3V memory systems containing 67,108,864 bits. Internally configured quad-bank DRAM with synchronous interface. Each 16,777,216-bit bank organized 4,096 rows columns bits. 64Mb SDRAM includes AUTO REFRESH MODE, power-saving, power-down mode. signals registered positive edge clock signal, CLK. inputs outputs LVTTL compatible. 64Mb SDRAM ability synchronously burst data high data rate with automatic column-address generation, ability interleave between internal banks hide precharge time capability randomly change column addresses each clock cycle during burst access. self-timed precharge initiated burst sequence available with AUTO PRECHARGE function enabled. Precharge bank while accessing other three banks will hide precharge cycles provide seamless, high-speed, random-access operation. SDRAM read write accesses burst oriented starting selected location continuing programmed number locations programmed sequence. registration ACTIVE command begins accesses, followed READ WRITE command. ACTIVE command conjunction with address bits registered used select bank accessed (BA0, select bank; A0-A11 select row). READ WRITE commands conjunction with address bits registered used select starting column location burst access. Programmable READ WRITE burst lengths consist locations, full page, with burst terminate option.
FUNCTIONAL BLOCK DIAGRAM
COMMAND DECODER CLOCK GENERATOR
DATA BUFFER
MODE REGISTER
REFRESH CONTROLLER
0-15
SELF REFRESH CONTROLLER
DATA BUFFER
VDD/VDDQ GND/GNDQ
REFRESH COUNTER
4096 4096 4096 4096
DECODER
MULTIPLEXER
MEMORY CELL ARRAY
ADDRESS LATCH
ADDRESS BUFFER
BANK
SENSE GATE
COLUMN ADDRESS LATCH
256K
BANK CONTROL LOGIC
BURST COUNTER
COLUMN DECODER
COLUMN ADDRESS BUFFER
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IS42S16400B
ISSI
Type Input Function Detail) Address Inputs: A0-A11 sampled during ACTIVE command (row-address A0-A11) READ/WRITE command (A0-A7 with defining auto precharge) select location memory array respective bank. sampled during PRECHARGE command determine banks precharged (A10 HIGH) bank selected BA0, (LOW). address inputs also provide op-code during LOAD MODE REGISTER command. Input Input Input Bank Select Address: defines which bank ACTIVE, READ, WRITE PRECHARGE command being applied. CAS, conjunction with forms device command. "Command Truth Table" details device commands.
FUNCTIONS
Symbol A0-A11
BA0,
input determines whether input enabled. next rising edge signal will valid when HIGH invalid when LOW. When LOW, device will either power-down mode, clock suspend mode, self refresh mode. asynchronous input. master clock input this device. Except CKE, inputs this device acquired synchronization with rising edge this pin. input determines whether command input enabled within device. Command input enabled when LOW, disabled with HIGH. device remains previous state when HIGH. DQ15 pins. through these pins controlled byte units using LDQM UDQM pins. LDQM UDQM control lower upper bytes buffers. read mode, LDQM UDQM control output buffer. When LDQM UDQM LOW, corresponding buffer byte enabled, when HIGH, disabled. outputs HIGH impedance state when LDQM/UDQM HIGH. This function corresponds conventional DRAMs. write mode, LDQM UDQM control input buffer. When LDQM UDQM LOW, corresponding buffer byte enabled, data written device. When LDQM UDQM HIGH, input data masked cannot written device. RAS, conjunction with forms device command. "Command Truth Table" item details device commands. conjunction with CAS, forms device command. "Command Truth Table" item details device commands. VDDQ output buffer power supply. device internal power supply. GNDQ output buffer ground. device internal ground.
Input Input
DQ15 LDQM, UDQM
11,13,
Input
VDDQ GNDQ
Input Input Power Supply Power Supply Power Supply Power Supply
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IS42S16400B
FUNCTION Detail)
A0-A11 address inputs sampled during ACTIVE (row-address A0-A11) READ/WRITE command (A0-A7 with defining auto PRECHARGE). sampled during PRECHARGE command determine banks PRECHARGED (A10 HIGH) bank selected BA0, (LOW). address inputs also provide op-code during LOAD MODE REGISTER command. Bank Select Address (BA0 BA1) defines which bank ACTIVE, READ, WRITE PRECHARGE command being applied. CAS, conjunction with forms device command. "Command Truth Table" details device commands. input determines whether input enabled. next rising edge signal will valid when HIGH invalid when LOW. When LOW, device will either power-down mode, CLOCK SUSPEND mode, SELF-REFRESH mode. asynchronous input. master clock input this device. Except CKE, inputs this device acquired synchronization with rising edge this pin. input determines whether command input enabled within device. Command input enabled when LOW, disabled with HIGH. device remains previous state when HIGH. DQ15 pins. through these pins controlled byte units using LDQM UDQM pins. LDQM UDQM control lower upper bytes buffers. read mode, LDQM UDQM control output buffer. When LDQM UDQM LOW, corresponding buffer byte enabled, when HIGH, disabled. outputs HIGH Impedance State when LDQM/UDQM HIGH. This function corresponds conventional DRAMs. write mode, LDQM UDQM control input buffer. When LDQM UDQM LOW, corresponding buffer byte enabled, data written device. When LDQM UDQM HIGH, input data masked cannot written device. RAS, conjunction with forms device command. "Command Truth Table" item details device commands. conjunction with forms device command. "Command Truth Table" item details device commands. VDDQ output buffer power supply. device internal power supply. GNDQ output buffer ground. device internal ground.
ISSI
READ
READ command selects bank from BA0, inputs starts burst read access active row. Inputs A0-A7 provides starting column location. When HIGH, this command functions AUTO PRECHARGE command. When auto precharge selected, being accessed will precharged READ burst. will remain open subsequent accesses when AUTO PRECHARGE selected. DQ's read data subject logic level inputs clocks earlier. When given signal registered HIGH, corresponding DQ's will High-Z clocks later. DQ's will provide valid data when signal registered LOW.
WRITE
burst write access active initiated with WRITE command. BA0, inputs selects bank, starting column location provided inputs A0-A7. Whether AUTO-PRECHARGE used determined A10. being accessed will precharged WRITE burst, AUTO PRECHARGE selected. AUTO PRECHARGE selected, will remain open subsequent accesses. memory array written with corresponding input data DQ's input logic level appearing same time. Data will written memory when signal LOW. When HIGH, corresponding data inputs will ignored, WRITE will executed that byte/column location.
PRECHARGE
PRECHARGE command used deactivate open particular bank open banks. BA0, used select which bank precharged they treated "Don't Care". determined whether banks precharged. After executing this command, next command selected banks(s) executed after passage period tRP, which period required bank precharging. Once bank been precharged, idle state must activated prior READ WRITE commands being issued that bank.
AUTO PRECHARGE
AUTO PRECHARGE function ensures that precharge initiated earliest valid stage within burst. This function allows individual-bank precharge without requiring explicit command. enables AUTO PRECHARGE function conjunction with specific READ WRITE command. each individual READ WRITE command, auto precharge either
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IS42S16400B
BURST TERMINATE
enabled disabled. AUTO PRECHARGE does apply except full-page burst mode. Upon completion READ WRITE burst, precharge bank/row that addressed automatically performed.
ISSI
AUTO REFRESH COMMAND
This command executes AUTO REFRESH operation. address bank refreshed automatically generated during this operation. stipulated period (tRC) required single refresh operation, other commands executed during this period. This command executed least 4096 times every 64ms. During AUTO REFRESH command, address bits "Don't Care". This command corresponds Auto-refresh.
BURST TERMINATE command forcibly terminates burst read write operations truncating either fixedlength full-page bursts most recently registered READ WRITE command prior BURST TERMINATE.
COMMAND INHIBIT
COMMAND INHIBIT prevents commands from being executed. Operations progress affected, apart from whether signal enabled
OPERATION
When low, command prevents unwanted commands from being registered during idle wait states.
SELF REFRESH
During SELF REFRESH operation, address refreshed, bank, refresh interval generated automatically internally. SELF REFRESH used retain data SDRAM without external clocking, even rest system powered down. SELF REFRESH operation started dropping from HIGH LOW. During SELF REFRESH operation other inputs SDRAM become "Don't Care". device must remain self refresh mode minimum period equal tRAS remain self refresh mode indefinite period beyond that. SELFREFRESH operation continues long remains there need external control other pins. next command cannot executed until device internal recovery period (tRC) elapsed. Once goes HIGH, command must issued (minimum clocks) provide time completion internal refresh progress. After self-refresh, since impossible determine address last refreshed, AUTO-REFRESH should immediately performed addresses.
LOAD MODE REGISTER
During LOAD MODE REGISTER command mode register loaded from A0-A11. This command only issued when banks idle.
ACTIVE COMMAND
When ACTIVE COMMAND activated, BA0, inputs selects bank accessed, address inputs A0-A11 selects row. Until PRECHARGE command issued bank, remains open accesses.
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IS42S16400B
TRUTH TABLE COMMANDS OPERATION(1)
FUNCTION COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row)
ISSI
L/H(8) L/H(8)
ADDR Bank/Row Bank/Col Bank/Col Code Op-Code
Valid Active Active High-Z
READ (Select bank/column, start READ burst) BURST TERMINATE
WRITE (Select bank/column, start WRITE burst)
PRECHARGE (Deactivate bank banks) AUTO REFRESH SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER
(6,7)
Write Enable/Output Enable Write Inhibit/Output High-Z
NOTES: HIGH commands except SELF REFRESH. A0-A11 define op-code written mode register. A0-A11 provide address, BA0, determine which bank made active. A0-A7 (x16) provide column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge; BA0, determine which bank being read from written LOW: BA0, determine bank being precharged. HIGH: banks precharged BA0, "Don't Care." AUTO REFRESH HIGH, SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. Activates deactivates during WRITEs (zero-clock delay) READs (two-clock delay).
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IS42S16400B
TRUTH TABLE (1-4)
CURRENT STATE Power-Down Self Refresh Clock Suspend Power-Down Self Refresh
ISSI
COMMANDn COMMAND INHIBIT COMMAND INHIBIT COMMAND INHIBIT AUTO REFRESH VALID ACTIONn Maintain Power-Down Maintain Self Refresh Maintain Clock Suspend Exit Power-Down Exit Self Refresh Exit Clock Suspend Power-Down Entry Self Refresh Entry Clock Suspend Entry CKEn-1 CKEn
Clock Suspend Banks Idle Banks Idle
Reading Writing
TRUTH TABLE CURRENT STATE BANK COMMAND BANK
NOTES: CKEn logic state clock edge CKEn-1 state previous clock edge. Current state state SDRAM immediately prior clock edge COMMANDn command registered clock edge ACTONn result COMMANDn. states sequences shown illegal reserved. Exiting power-down clock edge will device banks idle state time clock edge (provided that tCKS met). Exiting self refresh clock edge will device banks idle state once tXSR met. COMMAND INHIBIT commands should issued clock edges occurring during tXSR period. minimum commands must sent during tXSR period. After exiting clock suspend clock edge device will resume operation recognize next command clock edge n+1.
TRUTH TABLE CURRENT STATE BANK COMMAND BANK (1-6)
CURRENT STATE Idle COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) OPERATION (NOP/Continue previous operation) ACTIVE (Select activate row) AUTO REFRESH(7) LOAD MODE REGISTER(7) PRECHARGE Active
(11) (10)
(10) (10) (10)
READ (Select column start READ burst)
WRITE (Select column start WRITE burst)(10) PRECHARGE (Deactivate bank banks) Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) WRITE (Select column start WRITE burst) BURST TERMINATE
READ (Select column start READ burst)
(10)
PRECHARGE (Truncate READ burst, start PRECHARGE)(8) READ (Select column start READ burst)
WRITE (Select column start WRITE burst) BURST TERMINATE(9)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)(8)
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ISSI
NOTE: This table applies when HIGH HIGH (see Truth Table CKE) after tXSR been previous state SELF REFRESH). This table bank-specific, except where noted; i.e., current state specific bank commands shown those allowed issued that bank when that state. Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: READ burst been initiated, with auto precharge disabled, terminated been terminated. Write: WRITE burst been initiated, with auto precharge disabled, terminated been terminated. following states must interrupted command issued same bank. COMMAND INHIBIT commands, allowable commands other bank should issued clock edge occurring during these states. Allowable commands other bank determined current state CURRENT STATE BANK truth tables. Precharging: Starts with registration PRECHARGE command ends when met. Once met, bank will idle state. Activating: Starts with registration ACTIVE command ends when tRCD met. Once tRCD met, bank will active state. Read w/Auto Precharge Enabled: Starts with registration READ command with auto precharge enabled ends when been met. Once met, bank will idle state. Write w/Auto Precharge Enabled: Starts with registration WRITE command with auto precharge enabled ends when been met. Once met, bank will idle state. following states must interrupted executable command; COMMAND INHIBIT commands must applied each positive clock edge during these states. Refreshing: Starts with registration AUTO REFRESH command ends when met. Once met, SDRAM will banks idle state. Accessing Mode Register: Starts with registration LOAD MODE REGISTER command ends when tMRD been met. Once tMRD met, SDRAM will banks idle state. Precharging All: Starts with registration PRECHARGE command ends when met. Once met, banks will idle state. states sequences shown illegal reserved. bank-specific; requires that banks idle. bank-specific; banks precharged, must valid state precharging. bank-specific; BURST TERMINATE affects most recent READ WRITE burst, regardless bank. READs WRITEs listed Command (Action) column include READs WRITEs with auto precharge enabled READs WRITEs with auto precharge disabled. Does affect state bank acts that bank.
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IS42S16400B
TRUTH TABLE CURRENT STATE BANK COMMAND BANK (1-6)
CURRENT STATE Idle Activating, Active, Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (With Auto Precharge) Write (With Auto Precharge) COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) OPERATION (NOP/Continue previous operation) Command Otherwise Allowed Bank ACTIVE (Select activate row) READ (Select column start READ burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE(9) ACTIVE (Select activate row) READ (Select column start READ burst) PRECHARGE(9) ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE(9) ACTIVE (Select activate row) READ (Select column start READ burst) PRECHARGE(9)
(7,8,16) (7,8,17) (7,8,14) (7,8,15) (7,12) (7,13) (7,10) (7,11)
ISSI
WRITE (Select column start WRITE burst)
WRITE (Select column start WRITE burst)
WRITE (Select column start WRITE burst)
NOTE: This table applies when HIGH HIGH (Truth Table CKE) after tXSR been previous state self refresh). This table describes alternate bank operation, except where noted; i.e., current state bank commands shown those allowed issued bank (assuming that bank such state that given command allowable). Exceptions covered notes below. Current state definitions: Idle: bank been precharged, been met. Active: bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: READ burst been initiated, with auto precharge disabled, terminated been terminated. Write: WRITE burst been initiated, with auto precharge disabled, terminated been terminated. Read w/Auto Precharge Enabled: Starts with registration READ command with auto precharge enabled, ends when been met. Once met, bank will idle state. Write w/Auto Precharge Enabled: Starts with registration WRITE command with auto precharge enabled, ends when been met. Once met, bank will idle state. AUTO REFRESH, SELF REFRESH LOAD MODE REGISTER commands only issued when banks idle. BURST TERMINATE command cannot issued another bank; applies bank represented current state only. states sequences shown illegal reserved.
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ISSI
READs WRITEs bank listed Command (Action) column include READs WRITEs with auto precharge enabled READs WRITEs with auto precharge disabled. CONCURRENT AUTO PRECHARGE: Bank will initiate AUTO PRECHARGE command when burst been interrupted bank burst. Burst bank continues initiated. READ without auto precharge interrupted READ (with without auto precharge), READ bank will interrupt READ bank latency later (Consecutive READ Bursts). READ without auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt READ bank when registered (READ WRITE). should used clock prior WRITE command prevent contention. WRITE without auto precharge interrupted READ (with without auto precharge), READ bank will interrupt WRITE bank when registered (WRITE READ), with data-out appearing latency later. last valid WRITE bank will data-in registered clock prior READ bank WRITE without auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt WRITE bank when registered (WRITE WRITE). last valid WRITE bank will data-in registered clock prior READ bank READ with auto precharge interrupted READ (with without auto precharge), READ bank will interrupt READ bank latency later. PRECHARGE bank will begin when READ bank registered (Fig READ with auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt READ bank when registered. should used clocks prior WRITE command prevent contention. PRECHARGE bank will begin when WRITE bank registered (Fig WRITE with auto precharge interrupted READ (with without auto precharge), READ bank will interrupt WRITE bank when registered, with data-out appearing latency later. PRECHARGE bank will begin after met, where begins when READ bank registered. last valid WRITE bank will data-in registered clock prior READ bank (Fig WRITE with auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt WRITE bank when registered. PRECHARGE bank will begin after met, where begins when WRITE bank registered. last valid WRITE bank will data registered clock prior WRITE bank (Fig
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IS42S16400B
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDDQ VOUT TOPR TSTG Parameters Maximum Supply Voltage Maximum Supply Voltage Output Buffer Input Voltage Output Voltage Allowable Power Dissipation Output Shorted Current Operating Temperature Com. Ind. Storage Temperature Rating -1.0 +4.6 -1.0 +4.6 -1.0 +4.6 -1.0 +4.6 +150 Unit
ISSI
RECOMMENDED OPERATING CONDITIONS(2) +70°C)
Symbol VDD, VDDQ Parameter Supply Voltage Input High Voltage Input Voltage Min. -0.3 Typ. Max. +0.8 Unit
CAPACITANCE CHARACTERISTICS(1,2) +25°C, VDDQ 0.3V, MHz)
Symbol CIN1 CIN2 CI/O Parameter Input Capacitance: A0-A11, BA0, Input Capacitance: (CLK, CKE, RAS, CAS, LDQM, UDQM) Data Input/Output Capacitance: I/O0-I/O15 Typ. Max. Unit
Notes: Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. voltages referenced GND.
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ISSI
Speed Min. Max. Unit
ELECTRICAL CHARACTERISTICS (Recommended Operation Conditions unless otherwise noted.)
Symbol ICC1 Test Condition VDD, with pins other than tested Output Leakage Current Output disabled, VOUT Output High Voltage Level IOUT Output Voltage Level IOUT Operating Current(1,2) Bank Operation, latency Com. Burst Length=1 Com. (min.) Ind. IOUT Precharge Standby Current (MAX) (MIN) Com. Ind. Power-Down Mode) Com. Ind. Precharge Standby Current (MIN) (MIN) Power-Down Mode) Com. Ind. Active Standby Current (MAX) (MIN) Com. Ind. Power-Down Mode) Com. Ind. Active Standby Current (MIN) (MIN) Power-Down Mode) Com. Ind. Operating Current (MIN) latency Com. Burst Mode)(1) IOUT Com. Ind. latency Com. Com. Ind. Auto-Refresh Current (MIN) latency Com. Com. Ind. latency Com. Com. Ind. Self-Refresh Current 0.2V Parameter Input Leakage Current
ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4
ICC5
ICC6
Notes: These values minimum cycle time. Since currents transient, these values decrease cycle time increases. Also note that bypass capacitor least 0.01 should inserted between each memory chip suppress power supply voltage noise (voltage drops) these transient currents. Icc1 Icc4 depend output load. maximum values Icc1 Icc4 obtained with output open state.
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IS42S16400B
ELECTRICAL CHARACTERISTICS
Symbol Parameter tCK3 tCK2 tAC3 tAC2 tCHI tOH3 tOH2 tHZ3 tHZ2 tCKS tCKH tCKA tRAS tRCD tRRD tDPL3 tDPL2 tDAL3 tDAL2 tREF Clock Cycle Time Access Time From CLK(4) HIGH Level Width Level Width Output Data Hold Time Output Impedance Time Output HIGH Impedance Time Input Data Setup Time Input Data Hold Time Address Setup Time Address Hold Time Setup Time Hold Time Recovery Delay Time Command Setup Time (CS, RAS, CAS, DQM) Command Hold Time (CS, RAS, CAS, DQM) Command Period (REF ACT) Command Period (ACT PRE) Command Period (PRE ACT) Active Command Read Write Command Delay Time Command Period (ACT ACT[1]) Input Data Precharge Command Delay time Latency Latency Input Data Active Refresh Latency Command Delay time (During Auto-Precharge) Latency Transition Time Refresh Cycle Time (4096)
ISSI
(1,2,3)
Min. Latency Latency Latency Latency Latency Latency Latency Latency 1CLK+3 2CLK 2CLK 2CLK+tRP 2CLK+tRP Max. 50,000 Min.
Max. 50,000 Units
1CLK+3 2CLK 2CLK 2CLK+tRP 2CLK+tRP
Notes: When power first applied, memory operation should started after VDDQ reach their stipulated voltages. Also note that power-on sequence must executed before starting memory operation. Measured with reference level when measuring input signal timing. Rise fall times measured between (min.) (max.). Access time measured 1.4V with load shown figure below. time (max.) defined time required output voltage transition from (min.) (max.) when output high impedance state.
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ISSI
UNITS cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
OPERATING FREQUENCY LATENCY RELATIONSHIPS
SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH PARAMETER Clock Cycle Time Operating Frequency READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay data mask during WRITEs data high-impedance during READs WRITE command input data delay Data-in ACTIVE command Data-in PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command Last data-in PRECHARGE command LOAD MODE REGISTER command ACTIVE REFRESH command Data-out high-impedance from PRECHARGE command
TEST CONDITIONS (Input/Output Reference Level: 1.5V) Input Load
tCHI
2.8V
Output Load
1.5V
0.2V
+1.5V
2.8V
INPUT 1.5V
0.2V
OUTPUT
1.5V
1.5V
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FUNCTIONAL DESCRIPTION
64Mb SDRAMs banks) quad-bank DRAMs which operate 3.3V include synchronous interface (all signals registered positive edge clock signal, CLK). Each 16,777,216-bit banks organized 4,096 rows columns bits. Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select bank accessed (BA0 select bank, A0-A11 select row). address bits (A0-A7) registered coincident with READ WRITE command used select starting column location burst access. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions device operation.
ISSI
Initialization
SDRAMs must powered initialized predefined manner. SDRAM initialized after power applied VDDQ (simultaneously) clock stable. 100µs delay required prior issuing command other than COMMAND INHIBIT NOP. COMMAND INHIBIT applied during 100us period continue should least through period. With least COMMAND INHIBIT command having been applied, PRECHARGE command should applied once 100µs delay been satisfied. banks must precharged. This will leave banks idle state where AUTO REFRESH cycles must performed. After AUTO REFRESH cycles complete, SDRAM then ready mode register programming. mode register should loaded prior applying operational command because will power unknown state.
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REGISTER DEFINITION Mode Register
mode register used define specific mode operation SDRAM. This definition includes selection burst length, burst type, CAS\ latency, operating mode write burst mode, shown MODE REGISTER DEFINITION. mode register programmed LOAD MODE REGISTER command will retain stored information
ISSI
until programmed again device loses power. Mode register bits M0-M2 specify burst length, specifies type burst (sequential interleaved), specify latency, specify operating mode reserved future use. mode register must loaded when banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation.
MODE REGISTER DEFINITION
Address
Mode Register (Mx)
Reserved
Burst Length Burst Type Latency Mode Operating Mode M6-M0 Defined Mode Standard Operation Other States Reserved Latency Reserved Reserved Reserved Reserved Reserved Reserved Type Sequential Interleaved M3=0 Reserved Reserved Reserved Full Page M3=1 Reserved Reserved Reserved Reserved
ensure compatibility with future devices, should program M9-M13
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Burst Length
Read write accesses SDRAM burst oriented, with burst length being programmable, shown MODE REGISTER DEFINITION. burst length determines maximum number column locations that accessed given READ WRITE command. Burst lengths locations available both sequential interleaved burst types, full-page burst available sequential type. full-page burst used conjunction with BURST TERMINATE command generate arbitrary burst lengths. Reserved states should used, unknown operation incompatibility with future versions result. When READ WRITE command issued, block columns equal burst length effectively selected. accesses that burst take place within this block,
ISSI
meaning that burst will wrap within block boundary reached. block uniquely selected A1-A7 (x16) when burst length two; A2-A7 (x16) when burst length four; A3-A7 (x16) when burst length eight. remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached.
Burst Type
Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst length, burst type starting column address, shown BURST DEFINITION table.
BURST DEFINITION
Burst Length Full Page A0-A7 (location 0-y) Starting Column Address 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Supported 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 Order Accesses Within Burst Type Sequential Type Interleaved
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IS42S16400B
Latency
latency delay, clock cycles, between registration READ command availability first piece output data. latency three clocks. READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, READ command registered latency programmed clocks, will start driving after data will valid shown Latency diagrams. Allowable Operating Frequency table indicates operating frequencies which each latency setting used. Reserved states should used unknown operation incompatibility with future versions result.
ISSI
Operating Mode
normal operating mode selected setting zero; other combinations values reserved future and/or test modes. programmed burst length applies both READ WRITE bursts. Test modes reserved states should used because unknown operation incompatibility with future versions result.
Latency Allowable Operating Frequency (MHz)
Speed Latency Latency
Latency
COMMAND
READ
DOUT
Latency
COMMAND
READ
DOUT
Latency
DON'T CARE UNDEFINED
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IS42S16400B
OPERATION BANK/ROW ACTIVATION
Before READ WRITE commands issued bank within SDRAM, that bank must "opened." This accomplished ACTIVE command, which selects both bank activated (see Activating Specific Within Specific Bank). After opening (issuing ACTIVE command), READ WRITE command issued that row, subject tRCD specification. Minimum tRCD should divided clock period rounded next whole number determine earliest clock edge after ACTIVE command which READ WRITE command entered. example, tRCD specification 20ns with clock (8ns period) results clocks, rounded This reflected following example, which covers case where [tRCD (MIN)/tCK] (The same procedure used convert other specification limits from time units clock cycles). subsequent ACTIVE command different same bank only issued after previous active been "closed" (precharged). minimum time interval between successive ACTIVE commands same bank defined tRC. subsequent ACTIVE command another bank issued while first bank being accessed, which results reduction total row-access overhead. minimum time interval between successive ACTIVE commands different banks defined tRRD.
A0-A11 BA0, HIGH
ISSI
Activating Specific Within Specific Bank
ADDRESS BANK ADDRESS
Example: Meeting tRCD (MIN) when [tRCD (min)/tCK]
COMMAND
ACTIVE
tRCD
READ WRITE
DON'T CARE
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READS
READ bursts initiated with READ command, shown READ COMMAND diagram. starting column bank addresses provided with READ command, auto precharge either enabled disabled that burst access. auto precharge enabled, being accessed precharged completion burst. generic READ commands used following illustrations, auto precharge disabled. During READ bursts, valid data-out element from starting column address will available following latency after READ command. Each subsequent data-out element will valid next positive clock edge. Latency diagram shows general timing each possible latency setting. Upon completion burst, assuming other commands have been initiated, will High-Z. full-page burst will continue until terminated. page, will wrap column continue.) Data from READ burst truncated with subsequent READ command, data from fixed-length READ burst immediately followed data from READ command. either case, continuous flow data maintained. first data element from burst follows either last element completed burst last desired data element longer burst which being truncated. READ command should issued cycles before clock edge which last desired data element valid, where equals latency minus one. This shown Consecutive READ Bursts latencies three; data element either last burst four last desired longer burst. 64Mb SDRAM uses pipelined architecture therefore does require rule associated with prefetch architecture. READ command initiated clock cycle following previous READ command. Full-speed random read accesses performed same bank, shown Random READ Accesses, each subsequent READ performed different bank. Data from READ burst truncated with subsequent WRITE command, data from fixed-length READ burst immediately followed data from WRITE command (subject turnaround limitations). WRITE burst initiated clock edge immediately following last last desired) data element from READ burst, provided that contention avoided. given system design, there possibility that device driving input data will Low-Z before SDRAM High-Z. this case, least single-cycle delay should occur between last read data WRITE command.
ISSI
READ COMMAND
A0-A7
AUTO PRECHARGE COLUMN ADDRESS HIGH-Z
PRECHARGE
BA0,
BANK ADDRESS
input used avoid contention, shown Figures RW2. signal must asserted (HIGH) least clocks prior WRITE command (DQM latency clocks output buffers) suppress data-out from READ. Once WRITE command registered, will High-Z remain High-Z), regardless state signal, provided active clock just prior WRITE command that truncated READ command. not, second WRITE will invalid WRITE. example, during Figure RW2, then WRITEs would valid, while WRITE would invalid. signal must de-asserted prior WRITE command (DQM latency zero clocks input buffers) ensure that written data masked. Figure shows case where clock frequency allows contention avoided without adding cycle, Figure shows case where additional needed. fixed-length READ burst followed truncated with, PRECHARGE command same bank (provided that auto precharge activated), full-page burst truncated with PRECHARGE command
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same bank. PRECHARGE command should issued cycles before clock edge which last desired data element valid, where equals latency minus one. This shown READ PRECHARGE diagram each possible latency; data element either last burst four last desired longer burst. Following PRECHARGE command, subsequent command same bank cannot issued until met. Note that part precharge time hidden during access last data element(s). case fixed-length burst being executed completion, PRECHARGE command issued optimum time described above) provides same operation that would result from same fixed-length burst with auto precharge. disadvantage
ISSI
PRECHARGE command that requires that command address buses available appropriate time issue command; advantage PRECHARGE command that used truncate fixed-length full-page bursts. Full-page READ bursts truncated with BURST TERMINATE command, fixed-length READ bursts truncated with BURST TERMINATE command, provided that auto precharge activated. BURST TERMINATE command should issued cycles before clock edge which last desired data element valid, where equals latency minus one. This shown READ Burst Termination diagram each possible latency; data element last desired data element longer burst.
Latency
COMMAND
READ
DOUT
Latency
COMMAND
READ
DOUT
Latency
DON'T CARE UNDEFINED
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Consecutive READ Bursts
ISSI
COMMAND
READ
READ cycle
ADDRESS
BANK,
BANK,
Latency
DOUT
DOUT
DOUT
DOUT
DOUT
DON'T CARE
COMMAND
READ
READ
cycles
ADDRESS
BANK,
BANK,
Latency
DOUT
DOUT
DOUT
DOUT
DOUT
DON'T CARE
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Random READ Accesses
ISSI
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
BANK,
BANK,
BANK,
Latency
DOUT
DOUT
DOUT
DOUT
DON'T CARE
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
BANK,
BANK,
BANK,
Latency
DOUT
DOUT
DOUT
DOUT
DON'T CARE
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IS42S16400B
READ WRITE
ISSI
COMMAND
READ
WRITE
ADDRESS
BANK,
BANK,
DOUT
DON'T CARE
READ WRITE With Extra Clock Cycle
COMMAND
READ
WRITE
ADDRESS
BANK,
BANK,
DOUT
DON'T CARE
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IS42S16400B
READ PRECHARGE
ISSI
COMMAND
READ
PRECHARGE
ACTIVE
cycle
ADDRESS
BANK
BANK all)
BANK
Latency
DOUT
DOUT
DOUT
DOUT
DON'T CARE
COMMAND
READ
PRECHARGE
cycles
ACTIVE
ADDRESS
BANK,
BANK,
BANK
Latency
DOUT
DOUT
DOUT
DOUT
DON'T CARE
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READ Burst Termination
ISSI
COMMAND
READ
BURST TERMINATE
cycle
ADDRESS
BANK
Latency
DOUT
DOUT
DOUT
DOUT
DON'T CARE
COMMAND
READ
BURST TERMINATE
cycles
ADDRESS
BANK,
Latency
DOUT
DOUT
DOUT
DOUT
DON'T CARE
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WRITEs
WRITE bursts initiated with WRITE command, shown WRITE Command diagram.
ISSI
WRITE Command
A0-A7
AUTO PRECHARGE COLUMN ADDRESS HIGH
PRECHARGE
BA0,
BANK ADDRESS
starting column bank addresses provided with WRITE command, auto precharge either enabled disabled that access. auto precharge enabled, being accessed precharged completion burst. generic WRITE commands used following illustrations, auto precharge disabled. During WRITE bursts, first valid data-in element will registered coincident with WRITE command. Subsequent data elements will registered each successive positive clock edge. Upon completion fixed-length burst, assuming other commands have been initiated, will remain High-Z additional input data will ignored (see WRITE Burst). full-page burst will continue until terminated. page, will wrap column continue.) Data WRITE burst truncated with subsequent WRITE command, data fixed-length WRITE burst immediately followed data WRITE command. WRITE command issued clock following previous WRITE command, data provided coincident with command applies command.
example shown WRITE WRITE diagram. Data either last burst last desired longer burst. 64Mb SDRAM uses pipelined architecture therefore does require rule associated with prefetch architecture. WRITE command initiated clock cycle following previous WRITE command. Full-speed random write accesses within page performed same bank, shown Random WRITE Cycles, each subsequent WRITE performed different bank. Data WRITE burst truncated with subsequent READ command, data fixed-length WRITE burst immediately followed subsequent READ command. Once READ command registered, data inputs will ignored, WRITEs will executed. example shown WRITE READ. Data either last burst last desired longer burst. Data fixed-length WRITE burst followed truncated with, PRECHARGE command same bank (provided that auto precharge activated), fullpage WRITE burst truncated with PRECHARGE command same bank. PRECHARGE command should issued after clock edge which last desired input data element registered. auto precharge mode requires least clock plus time, regardless frequency. addition, when truncating WRITE burst, signal must used mask input data clock edge prior clock edge coincident with, PRECHARGE command. example shown WRITE PRECHARGE diagram. Data either last burst last desired longer burst. Following PRECHARGE command, subsequent command same bank cannot issued until met. case fixed-length burst being executed completion, PRECHARGE command issued optimum time described above) provides same operation that would result from same fixed-length burst with auto precharge. disadvantage PRECHARGE command that requires that command address buses available appropriate time issue command; advantage PRECHARGE command that used truncate fixed-length full-page bursts. Fixed-length full-page WRITE bursts truncated with BURST TERMINATE command. When truncating WRITE burst, input data applied coincident with BURST TERMINATE command will ignored. last data written (provided that that time) will input data applied clock previous BURST TERMINATE command. This shown WRITE Burst Termination, where data last desired data element longer burst.
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WRITE Burst
ISSI
COMMAND
WRITE
ADDRESS
BANK,
DON'T CARE
WRITE WRITE
COMMAND
WRITE
WRITE
ADDRESS
BANK,
BANK,
DON'T CARE
Random WRITE Cycles
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
BANK,
BANK,
BANK,
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IS42S16400B
WRITE READ
ISSI
COMMAND
WRITE
READ
ADDRESS
BANK,
BANK,
DOUT
DOUT
DON'T CARE
WRITE PRECHARGE (tWR 15ns)
COMMAND WRITE
PRECHARGE
ACTIVE
ADDRESS
BANK
BANK all)
BANK
DON'T CARE
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WRITE PRECHARGE (tWR 15ns)
ISSI
COMMAND WRITE
PRECHARGE
ACTIVE
ADDRESS
BANK
BANK all)
BANK
DON'T CARE
WRITE Burst Termination
COMMAND
WRITE
BURST TERMINATE
NEXT COMMAND
ADDRESS
BANK,
(ADDRESS)
(DATA)
DON'T CARE
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PRECHARGE
PRECHARGE command (see figure) used deactivate open particular bank open banks. bank(s) will available subsequent access some specified time (tRP) after PRECHARGE command issued. Input determines whether banks precharged, case where only bank precharged, inputs BA0, select bank. When banks precharged, inputs BA0, treated "Don't Care." Once bank been precharged, idle state must activated prior READ WRITE commands being issued that bank.
ISSI
PRECHARGE Command
HIGH
POWER-DOWN
Power-down occurs registered coincident with COMMAND INHIBIT when accesses progress. power-down occurs when banks idle, this mode referred precharge power-down; power-down occurs when there active either bank, this mode referred active power-down. Entering power-down deactivates input output buffers, excluding CKE, maximum power savings while standby. device remain powerdown state longer than refresh period (64ms) since refresh operations performed this mode. power-down state exited registering COMMAND INHIBIT HIGH desired clock edge (meeting tCKS). figure below.
A0-A9,
BANKS
BANK SELECT
BA0,
BANK ADDRESS
POWER-DOWN
tCKS tCKS
COMMAND
Input buffers gated
ACTIVE tRCD tRAS DON'T CARE
banks idle
Enter power-down mode
Exit power-down mode
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CLOCK SUSPEND
Clock suspend mode occurs when column access/burst progress registered LOW. clock suspend mode, internal clock deactivated, "freezing" synchronous logic. each positive clock edge which sampled LOW, next internal positive clock edge suspended.
ISSI
command data present input pins time suspended internal clock edge ignored; data present pins remains driven; burst counters incremented, long clock suspended. (See following examples.) Clock suspend mode exited registering HIGH; internal clock related operation will resume subsequent positive clock edge.
Clock Suspend During WRITE Burst
INTERNAL CLOCK COMMAND WRITE
ADDRESS
BANK
DON'T CARE
Clock Suspend During READ Burst
INTERNAL CLOCK COMMAND READ
ADDRESS
BANK
DOUT
DOUT
DOUT
DOUT
DON'T CARE
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BURST READ/SINGLE WRITE
burst read/single write mode entered programming write burst mode (M9) mode register logic this mode, WRITE commands result access single column location (burst one), regardless programmed burst length. READ commands access columns according programmed burst length sequence, just normal mode operation
ISSI
READ with Auto Precharge
Four cases where CONCURRENT AUTO PRECHARGE occurs defined below. Interrupted READ (with without auto precharge): READ bank will interrupt READ bank latency later. PRECHARGE bank will begin when READ bank registered. Interrupted WRITE (with without auto precharge): WRITE bank will interrupt READ bank when registered. should used clocks prior WRITE command prevent contention. PRECHARGE bank will begin when WRITE bank registered.
CONCURRENT AUTO PRECHARGE
access command (READ WRITE) another bank while access command with auto precharge enabled executing allowed SDRAMs, unless SDRAM supports CONCURRENT AUTO PRECHARGE. ISSI SDRAMs support CONCURRENT AUTO PRECHARGE.
READ With Auto Precharge interrupted READ
COMMAND
READ BANK
READ BANK
BANK
Page Active
READ with Burst
Interrupt Burst, Precharge BANK
Idle BANK Precharge
Internal States
BANK
BANK
Page Active
READ with Burst
BANK
ADDRESS
DOUT Latency (BANK
DOUT
DOUT
DOUT DON'T CARE
Latency (BANK
READ With Auto Precharge interrupted WRITE
COMMAND
WRITE BANK
WRITE BANK
BANK
READ with Burst Page Active Page Active
BANK BANK
Interrupt Burst, Precharge BANK WRITE with Burst
Idle BANK Write-Back
Internal States
BANK ADDRESS
DOUT Latency (BANK
DON'T CARE
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WRITE with Auto Precharge
Interrupted READ (with without auto precharge): READ bank will interrupt WRITE bank when registered, with data-out appearing latency later. PRECHARGE bank will begin after met, where begins when READ bank registered. last valid WRITE bank will data-in registered clock prior READ bank
ISSI
Interrupted WRITE (with without auto precharge): AWRITE bank will interrupt WRITE bank when registered. PRECHARGE bank will begin after met, where begins when WRITE bank registered. last valid data WRITE bank will data registered clock prior WRITE bank
WRITE With Auto Precharge interrupted READ
COMMAND
WRITE BANK
READ BANK
BANK
Page Active
WRITE with Burst
Interrupt Burst, Write-Back BANK
Precharge BANK BANK Precharge
Internal States
BANK Page Active
READ with Burst
ADDRESS
BANK
BANK
Latency (BANK
DOUT
DOUT DON'T CARE
WRITE With Auto Precharge interrupted WRITE
COMMAND
WRITE BANK
WRITE BANK
BANK
Page Active
WRITE with Burst
Interrupt Burst, Write-Back BANK
Precharge BANK BANK Write-Back
Internal States
BANK Page Active
WRITE with Burst
ADDRESS
BANK
BANK
DON'T CARE
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INITIALIZE LOAD MODE REGISTER(1)
ISSI
tCKS tCKH tCMH tCMS COMMAND DQM/ DQML, DQMH
Tn+1
To+1
Tp+1
Tp+2
Tp+3
tCMH tCMS PRECHARGE
tCMH tCMS
AUTO REFRESH
AUTO REFRESH
Load MODE REGISTER
ACTIVE
A0-A9, BANKS SINGLE BANK BA0, Power-up: stable 100µs Min. Precharge banks tRFC AUTO REFRESH tRFC AUTO REFRESH tMRD Program MODE REGISTER DON'T CARE BANKS BANK CODE CODE
Notes: High clock High time, commands applied NOP. Mode register loaded prior Auto-Refresh cycles desired. JEDEC PC100 specify three clocks. Outputs guaranteed High-Z after command issued.
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POWER-DOWN MODE CYCLE
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BANKS SINGLE BANK BA0, BANK BANK PRECHARGE ACTIVE tCKS tCKS Tn+1 Tn+2
ISSI
High-Z clock cycles Precharge active banks banks idle, enter power-down mode Input buffers gated while power-down mode banks idle
Exit power-down mode
DON'T CARE
latency
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CLOCK SUSPEND MODE
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, BANK DOUT DOUT BANK DOUT COLUMN m(2) COLUMN n(2) READ tCMS tCMH WRITE tCKS tCKH
ISSI
DOUT DON'T CARE UNDEFINED
latency burst length
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AUTO-REFRESH CYCLE
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BANKS SINGLE BANK BA0, BANK(s) High-Z tRFC tRFC PRECHARGE
Auto Refresh
ISSI
Tn+1 To+1
Auto Refresh
ACTIVE
BANK
DON'T CARE
latency
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SELF-REFRESH CYCLE
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BANKS SINGLE BANK BA0, BANK PRECHARGE
Auto Refresh
ISSI
tCKS tRAS tCKS
Auto Refresh
Tn+1
To+1
To+2
High-Z Precharge active banks Enter self refresh mode
tXSR stable prior exiting Exit self refresh mode self refresh mode (Restart refresh time base) DON'T CARE
latency
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READ WITHOUT AUTO PRECHARGE
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, tRCD tRAS Latency BANK COLUMN m(2) BANKS ACTIVE READ tCMS tCMH PRECHARGE
ISSI
ACTIVE
DISABLE AUTO PRECHARGE BANK DOUT DOUT
SINGLE BANK BANK DOUT DOUT DON'T CARE UNDEFINED BANK
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READ WITH AUTO PRECHARGE
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, tRCD tRAS Latency BANK BANK DOUT DOUT DOUT DOUT COLUMN m(2) ENABLE AUTO PRECHARGE ACTIVE READ tCMS tCMH
ISSI
ACTIVE
BANK
DON'T CARE UNDEFINED
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SINGLE READ WITHOUT AUTO PRECHARGE
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, tRCD tRAS Latency BANK COLUMN m(2) BANKS DISABLE AUTO PRECHARGE BANK DOUT SINGLE BANK BANK BANK ACTIVE READ tCMS tCMH PRECHARGE ACTIVE
ISSI
DON'T CARE UNDEFINED
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SINGLE READ WITH AUTO PRECHARGE
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, BANK BANK tRCD tRAS Latency DOUT COLUMN m(2) ENABLE AUTO PRECHARGE BANK
ACTIVE READ ACTIVE
ISSI
tCMS tCMH
DON'T CARE UNDEFINED
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ALTERNATING BANK READ ACCESSES
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, BANK BANK tRCD BANK tRRD tRAS BANK BANK Latency BANK tRCD BANK COLUMN m(2) ENABLE AUTO PRECHARGE BANK DOUT DOUT BANK DOUT BANK Latency BANK DOUT COLUMN b(2) ENABLE AUTO PRECHARGE ACTIVE READ tCMS tCMH ACTIVE READ
ISSI
ACTIVE
BANK DOUT tRCD BANK
DON'T CARE
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ISSI
Tn+1 Tn+2 Tn+3 Tn+4
READ FULL-PAGE BURST
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, BANK
ACTIVE
READ
BURST TERM
tCMS tCMH
COLUMN m(2)
BANK DOUT DOUT DOUT DOUT DOUT DOUT DON'T CARE Full page Full-page burst self-terminating. completion BURST TERMINATE command. UNDEFINED
tRCD
Latency
each (x4) 1,024 locations
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ISSI
READ OPERATION
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, BANK ACTIVE
READ tCMS tCMH
COLUMN m(2)
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK DOUT DOUT DOUT DON'T CARE UNDEFINED
tRCD Latency
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ISSI
WRITE WITHOUT AUTO PRECHARGE
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, BANK COLUMN m(3) BANKS DISABLE AUTO PRECHARGE BANK tRCD tRAS SINGLE BANK BANK BANK ACTIVE WRITE tCMS tCMH PRECHARGE ACTIVE
tWR(2)
DON'T CARE
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ISSI
WRITE WITH AUTO PRECHARGE
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, BANK BANK tRCD tRAS COLUMN m(2) ENABLE AUTO PRECHARGE BANK ACTIVE WRITE tCMS tCMH ACTIVE
DON'T CARE
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IS42S16400B
ISSI
SINGLE WRITE WITHOUT AUTO PRECHARGE
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, BANK ACTIVE
WRITE tCMS tCMH
NOP(4)
NOP(4)
PRECHARGE
ACTIVE
COLUMN m(3)
BANKS
DISABLE AUTO PRECHARGE SINGLE BANK
BANK
BANK
BANK
tRCD tRAS
tWR(3) DON'T CARE
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ISSI
SINGLE WRITE WITH AUTO PRECHARGE
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, BANK BANK tRCD tRAS DON'T CARE COLUMN m(2) ENABLE AUTO PRECHARGE BANK ACTIVE NOP(3) NOP(3) NOP(3) WRITE tCMS tCMH ACTIVE
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ISSI
ALTERNATING BANK WRITE ACCESS
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, BANK BANK tRCD BANK tRRD tRAS BANK BANK COLUMN m(2) ENABLE AUTO PRECHARGE BANK BANK COLUMN b(2) ENABLE AUTO PRECHARGE BANK ACTIVE WRITE tCMS tCMH ACTIVE WRITE ACTIVE
tRCD BANK BANK
BANK tRCD BANK
BANK
DON'T CARE
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 02/10/05
IS42S16400B
ISSI
Tn+1 Tn+2
WRITE FULL PAGE BURST
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, BANK BANK tRCD DON'T CARE COLUMN m(2)
ACTIVE WRITE BURST TERM
tCMS tCMH
Full page completed
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 02/10/05
IS42S16400B
ISSI
WRITE OPERATION
tCKS tCKH tCMS tCMH COMMAND DQM/ DQML, DQMH A0-A9, BA0, BANK COLUMN m(2)
ENABLE AUTO PRECHARGE
ACTIVE
WRITE tCMS tCMH
DISABLE AUTO PRECHARGE
BANK tRCD DON'T CARE
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 02/10/05
IS42S16400B
ORDERING INFORMATION Commercial Range: 70°C
Frequency Speed (ns) Order Part IS42S16400B-6T IS42S16400B-6TL IS42S16400B-7T IS42S16400B-7TL Package 400-mil TSOP 400-mil TSOP Lead-free 400-mil TSOP 400-mil TSOP Lead-free
ISSI
Industrial Range: -40°C 85°C
Frequency Speed (ns) Order Part IS42S16400B-7TI Package 400-mil TSOP
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 02/10/05
PACKAGING INFORMATION
Plastic TSOP 54-Pin, 86-Pin Package Code: (Type
ISSI
N/2+1
Notes: Controlling dimension: millimieters, unless otherwise specified. Basic lead spacing between centers. Dimensions include mold flash protrusions should
measured from bottom package.
Formed leads shall planar with respect another within 0.004 inches seating plane.
SEATING PLANE
Symbol Ref. Std. Leads
Plastic TSOP Type Millimeters Inches 0.047 0.002 0.006 0.012 0.018 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.031 0.016 0.024
Plastic TSOP Type Millimeters Inches Symbol Ref. Std. Leads 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.12 0.21 22.02 22.42 10.16 11.56 11.96 0.50 0.40 0.60 0.80 0.61 0.047 0.002 0.006 0.037 0.041 0.007 0.011 0.005 0.008 0.867 0.8827 0.400 0.455 0.471 0.020 0.016 0.024 0.031 0.024
1.20 0.05 0.15 0.30 0.45 0.12 0.21 22.02 22.42 10.03 10.29 11.56 11.96 0.80 0.40 0.60 0.71
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. 01/28/02

IS42S16400B

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