IS25C01

Datasheets.org.uk - 100 Million Datasheets from 7500 Manufacturers.

Datasheet Thumbnail

Top Searches for this datasheet

IS25C01 - IS25C01

IS25C01
1K-BIT SERIAL ELECTRICALLY ERASABLE PROM
Serial Peripheral Interface (SPI) Compatible Supports Modes (0,0) (1,1) Low-voltage Operation 1.8V 5.5V power CMOS Active current less than (2.5V) Standby current less than (2.5V) Block Write Protection Protect 1/4, 1/2, Entire Array byte page write mode Partial page writes allowed Clock Rate (5V) Self timed write cycles max. 2.5V High-reliability Endurance: million cycles byte Data retention: years 8-pin PDIP, 8-pin SOIC, 8-pin TSSOP packages available Lead-free available
DESCRIPTION
IS25C01 electrically erasable PROM device that uses Serial Peripheral Interface (SPI) communications. IS25C01 1Kbit (128 IS25C01 EEPROM offered wide operating voltage range 1.8V 5.5V compatible with most application voltages. ISSI designed IS25C01 efficient EEPROM solution. device packaged 8-pin PDIP, 8-pin SOIC, 8-pin TSSOP. functional features IS25C01 allow among most versatile serial non-volatile memories available. Each device Chip-Select (CS) pin, 3-wire interface Serial Data (SI), Serial Data (SO), Serial Clock (SCK). While 3-wire interface IS25C01 provides high-speed access, HOLD allows memories ignore interface suspended state; later HOLD re-activates communication without re-initializing serial sequence. Status Register facilitates flexible write protection mechanism, device-ready (RDY).
Copyright 2006 Integrated Silicon Solution, Inc. rights reserved. ISSI reserves right make changes this specification products time without notice. ISSI assumes liability arising application information, products services described herein. Customers advised obtain latest version this device specification before relying published information before placing orders products.
Integrated Silicon Solution, Inc.
Rev. 05/08/07
IS25C01
CONFIGURATION 8-Pin DIP, TSSOP, SOIC
HOLD
DESCRIPTIONS
HOLD Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Write Protect Suspends Serial Input Connect
Chip Select activates device. CS): Upon power-up, should follow Vcc. When device enabled instruction input, signal requires High-to-Low transition. While stable Low, master slave will communicate SCK, signals. Upon completion communication, must driven High. this moment, slave device start internal write cycle. When high, device enters power-saving standby mode, unless internal write operation underway. During this mode, becomes high impedance. Write Protect purpose this input signal WP): initiate Hardware Write Protection mode. This mode prevents byte array Status Register from being altered. cause Hardware Write Protection, must Low. hardwired GND. HOLD (HOLD This input signal used suspend HOLD): HOLD device middle serial sequence temporarily ignore further communication (SI, SCK). Together with Chip Select, HOLD signal allows multiple slaves share bus. HOLD signal transitions must occur only when Low, held stable during transitions. (See Figure Hold timing) disable this feature, HOLD hardwired Vcc.
DESCRIPTIONS
Serial Clock (SCK): This timing signal provides synchronization between microcontroller IS25C01. Op-Codes, byte addresses, data latched with rising edge SCK. Data refreshed falling edge modes (0,0) (1,1). Serial Data Input (SI): This input data that IS25C01 required receive. Serial Data Output (SO): This output data transmitted from IS25C01.
Integrated Silicon Solution, Inc.
Rev. 05/08/07
IS25C01
SERIAL INTERFACE DESCRIPTION
MASTER: device that provides clock signal. SLAVE: IS25C01 slave because clock signal input. TRANSMITTER/RECEIVER: IS25C01 both data input (SI) data output (SO). MSB: most significant bit. always first transmitted received. OP-CODE: first byte transmitted slave following transition LOW. OP-CODE valid member IS25C01 instruction (Table then decoded appropriately. OP-CODE valid, remains high impedance.
BLOCK DIAGRAM
STATUS REGISTER
MEMORY ARRAY
DATA REGISTER MODE DECODE LOGIC ADDRESS DECODER OUTPUT BUFFER
CLOCK
HOLD
Integrated Silicon Solution, Inc.
Rev. 05/08/07
IS25C01
STATUS REGISTER
status register contains 8-bits write protection control write status. (See Table only region memory other than main array that accessible user. Block Protect (BP1, BP0), Bits 2-3: Together, these bits represent four block protection configurations implemented memory array. (See Table details.) non-volatile cells similar regular array cells, factory programmed block memory defined these bits always protected, regardless setting WEN.
Table Status Register Format
Bit1
Note: Don't care bit. Status Register Read-Only either: Hardware Write Protection enabled neither true, modified valid instruction.
Table Block Protection
Status Register Bits
Level 1(1/4) 2(1/2) 3(All)
Array Addresses Protected
IS25C01 None -7Fh -7Fh -7Fh
Ready (RDY When indicates that RDY), device busy with write cycle. indicates that device ready instruction. only command that will handled device Read Status Register. Write Enable (WEN), This represents status device write protection. Status Register entire array protected from modification, regardless setting block protection. only Write Enable command (WREN). reset upon power-up, successful completion Write, WRDI, WRSR, being Low.
Don't Care, Bits 4-7: Each these bits receive either values will retained. When these bits read from register, they always
Integrated Silicon Solution, Inc.
Rev. 05/08/07
IS25C01
DEVICE OPERATION
operations IS25C01 controlled instructions that clocked-in serially pin. (See Table begin instruction, chip select (CS) should dropped Low. Subsequently, each Low-to-High transition clock (SK) will latch stable value pin. After 8-bit op-code, appropriate continue input address data output data from During data output, values appear falling edge bits transferred with first. Upon last communication, prior following Low-to-High transition should raised High transaction. device then would enter Standby Mode internal programming were underway.
Table Instruction
Name
WREN WRDI RDSR WRSR READ
Op-code
0000 X110 0000 X100 0000 X101 0000 X001 0000 X011
Operation
Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Array Write Data Array
Address
A7-A0 A7-A0
Data(SI)
D7-D0,.
Data (SO)
D7-D0,. D7-D0,.
WRITE 0000 X010
Don't care bit. consistency, best "0". bits clocked-in op-code invalid, remains high impedance, upon going High there affect. valid op-code with invalid number bits clocked-in address data will cause attempt modify array Status Register ignored. WRITE ENABLE (WREN) When initially applied, device powers with both status register entire array write-disabled state. Upon completion Write Disable (WRDI), Write Status Register (WRSR), Write Data Array (WRITE), device resets Status Register Prior data modification, WREN instruction necessary (See Figure timing). WRITE DISABLE (WRDI) device completely protected from modification resetting through WRDI instruction. (See Figure timing). READ STATUS REGISTER (RDSR) Read Status instruction indicates status Block Protection setting (see Table Write Enable state, status. RDSR only instruction accepted when write cycle underway. recommended that status checked, especially prior attempted modification data. bits Status Register repeatedly output after initial Op-code. (See Figure timing).
Integrated Silicon Solution, Inc.
Rev. 05/08/07
IS25C01
WRITE STATUS REGISTER (WRSR) This instruction lets user choose Block Protection setting. values other data bits incorporated into WRSR stored Status Register. WRSR will ignored unless both following true: prior WREN instruction; Hardware Write Protection enabled. (See Table details). Except status, values Status Register remain unchanged until moment when write cycle complete register updated. Once successfully completed, reset complete chip write protection. (See Figure timing).
WRITE DATA (WRITE) WRITE instruction begins with op-code, 8-bit address first byte modified, first data byte. Additional data bytes written sequentially array after first byte. Each WRITE instruction affect contents byte page, more. page begins address XXXXX 000, ends with XXXXX 111. last byte page input, address rolls over beginning same page. More than data bytes input during same instruction, upon completed write cycle, page would only contain last bytes. region array defined within Block Protection cannot modified long that block configuration selected. region array outside Block Protection only modified Write Enable (WEN) Therefore, necessary that WREN instruction occur prior WRITE. addition, Hardware Write Protection enabled, memory array cannot modified. Once Write successfully completed, reset complete chip write protection. (See Figure timing).
READ DATA (READ) This instruction begins with op-code 8-bit address, causes selected data byte shifted Following this first data byte, additional sequential bytes output. data byte highest address output, address rolls-over lowest address array, output could loop indefinitely. time, rising signal completes operation. (See Figure timing).
Table Write Protection
Hardware Write Protection
Enabled Enabled Enabled
Inside Block
Read-only Read-only Read-only
Outside Block
Read-only Read-only Unprotected
Status Register
Read-only Read-only Unprotected
Note: Don't care bit.
Integrated Silicon Solution, Inc.
Rev. 05/08/07
IS25C01
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TBIAS TSTG IOUT Parameter Supply Voltage Voltage Temperature Under Bias Storage Temperature Output Current Value -0.5 -0.5 +125 +150 Unit
Notes: Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions outside those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
OPERATING RANGE (IS25C01-2)
Range Industrial Ambient Temperature -40°C +85°C 1.8V 5.5V
Note: ISSI offers Industrial grade Commercial applications. (0oC +70oC).
OPERATING RANGE (IS25C01-3)
Range Automotive Ambient Temperature -40°C +125°C 2.5V 5.5V
CAPACITANCE(1,2)
Symbol COUT Parameter Input Capacitance Output Capacitance Conditions VOUT Max. Unit
Notes: Tested initially after design process changes that affect these parameters 100% tested. Test conditions: 25°C, MHz, 5.0V.
Integrated Silicon Solution, Inc.
Rev. 05/08/07
IS25C01
ELECTRICAL CHARACTERISTICS
-40°C +85°C Industrial, -40°C +125°C Automotive. Symbol Parameter VOL1 VOL2 VOL3 VOH1 VOH2 VOH3 Output Voltage Output Voltage Output Voltage Output HIGH Voltage Output HIGH Voltage Output HIGH Voltage Input HIGH Voltage Input Voltage Input Leakage Current Output Leakage Current VOUT VCC, Test Conditions 2.5V, 1.8V, 0.15 2.5V, -0.4mA 1.8V, -0.1mA Min. 0.7X -0.3 Max. Unit
POWER SUPPLY CHARACTERISTICS
-40°C +85°C Industrial. Symbol Parameter ICC1 ICC2 ICC3 ISB1 ISB2 ISB3 Operating Current Operating Current Operating Current Standby Current Standby Current Standby Current Test Conditions Read/Write (Vcc Read/Write (Vcc 2.5V) Read/Write (Vcc 1.8V) 5.0V, 2.5V, 1.8V, Min. Max. Unit
POWER SUPPLY CHARACTERISTICS
-40°C +125°C Automotive. Symbol Parameter ICC1 ICC2 ISB1 ISB2 Operating Current Operating Current Standby Current Standby Current Test Conditions Read/Write (Vcc Read/Write (Vcc 2.5V) 5.0V, =2.5V, Min. Max. Unit
Integrated Silicon Solution, Inc.
Rev. 05/08/07
IS25C01
Characteristics
-40°C +85°C Industrial. Symbol fSCK tCSS tCSH tDIS 100pF Parameter Clock Frequency Input Rise Time Input Fall Time High Time Time High Time Setup Time Hold Time Data Setup Time Data Hold Time Hold Setup Time Hold Hold Time Output Valid Output Hold Time Hold Output Hold Output High Output Disable Time Write Cycle Time 1.8V 2.5V 2.5V 4.5V 4.5V 5.5V Units
Integrated Silicon Solution, Inc.
Rev. 05/08/07
IS25C01
Characteristics
-40°C +125°C Automotive. Symbol fSCK tCSS tCSH tDIS 100pF Parameter Clock Frequency Input Rise Time Input Fall Time High Time Time High Time Setup Time Hold Time Data Setup Time Data Hold Time Hold Setup Time Hold Hold Time Output Valid Output Hold Time Hold Output Hold Output High Output Disable Time Write Cycle Time 2.5V 4.5V 4.5V 5.5V Units
Integrated Silicon Solution, Inc.
Rev. 05/08/07
IS25C01
TIMING DIAGRAMS
Figure Synchronous Data Timing
tCSS tCSH
VALID tDIS
HIGH-Z
DOUT
HIGH-Z
Figure WREN Timing
WREN OP-CODE HIGH-Z
DOUT
Figure WRDI Timing
WRDI OP-CODE HIGH-Z
DOUT
Integrated Silicon Solution, Inc.
Rev. 05/08/07
IS25C01
Figure RDSR Timing
Instruction DATA
Dout
Figure WRSR Timing
Instruction DATA
Dout
Figure READ Timing
Instruction BYTE Address DATA
Integrated Silicon Solution, Inc.
Rev. 05/08/07
Dout
IS25C01
Figure WRITE Timing
Instruction BYTE Address DATA
Dout
Figure HOLD Timing
HOLD DOUT
Integrated Silicon Solution, Inc.
Rev. 05/08/07
IS25C01
ORDERING INFORMATION Industrial Range: -40°C +85°C
Range 1.8V 5.5V Voltage Part Number IS25C01-2PI IS25C01-2GI IS25C01-2ZI Package 300-mil Plastic Small Outline (JEDEC STD) 169-mil TSSOP
ORDERING INFORMATION Industrial Range: -40°C +85°C, Lead-free
Range 1.8V 5.5V Voltage Part Number IS25C01-2PLI IS25C01-2GLI IS25C01-2ZLI Package 300-mil Plastic Small Outline (JEDEC STD) 169-mil TSSOP
ORDERING INFORMATION Automotive Range: -40°C +125°C, Lead-free
Range 2.5V 5.5V Voltage Part Number IS25C01-3PLA3 IS25C01-3GLA3 IS25C01-3ZLA3 Package 300-mil Plastic Small Outline (JEDEC STD) 169-mil TSSOP
Integrated Silicon Solution, Inc.
Rev. 05/08/07
PACKAGING INFORMATION
300-mil Plastic Package Code:
SEATING PLANE
32-PIN ONLY
MILLIMETERS Sym.
Leads
INCHES Min. Max.
Min.
Max.
Notes: Controlling dimension: inches, unless otherwise specified. Basic lead spacing between centers. Dimensions include mold flash protrusions should measured from bottom package. Formed leads shall planar with respect another within 0.004 inches seating plane.
3.68 0.38 0.36 1.14 0.81 0.20 9.12 7.62
6.20 8.13 3.18 0.64
4.57 0.56 1.52 1.17 0.33
9.53 8.26
6.60 9.65 0.762
0.145 0.015 0.014 0.045 0.032 0.008 0.359 0.300
0.244 0.320 0.125 0.025
0.180 0.022 0.060 0.046 0.013
0.375 0.325
0.260 0.380 0.030
2.54
0.100
Copyright 2003 Integrated Silicon Solution, Inc. rights reserved. ISSI reserves right make changes this specification products time without notice. ISSI assumes liability arising application information, products services described herein. Customers advised obtain latest version this device specification before relying published information before placing orders products.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 02/14/03
PACKAGING INFORMATION
300-mil Plastic Package Code:
MILLIMETERS Sym.
Leads
INCHES Min. Max. Sym.
Leads
MILLIMETERS Min.
INCHES Min. Max.
Min.
Max.
Max.
3.68 0.25
4.57
0.46 1.52
0.38
0.145 0.180 0.010 0.018 0.060
0.015
3.68 0.38 0.36 1.14
4.57 0.56 1.78 0.36
0.145 0.015 0.014 0.045
0.180 0.022 0.070 0.014
0.13 18.92 7.44
6.22 8.13 3.05 0.38
19.18 8.13
6.48 9.65 3.56 0.89
0.005 0.745 0.293
0.245 0.320 0.120 0.015
0.755 0.320
0.255 0.380 0.140 0.035
0.20 25.91 7.49
6.01 3.05 1.02
26.42 8.26
7.11 10.92
0.008 1.020 0.295
0.240 0.120 0.040
1.040 0.325
0.280 0.430
2.54
0.100
2.54 3.81 1.52
0.100 0.150 0.060
MILLIMETERS Sym.
Leads
INCHES Min. Max. Sym.
Leads
MILLIMETERS Min.
INCHES Min. Max.
Min.
Max.
Max.
3.68 0.25 0.41
1.27
4.57
0.56
1.78
0.81 0.20 35.05 7.49
6.99 7.87 3.05 0.51
1.17
0.38
35.56 8.00
7.49 10.16 3.81 1.06
0.145 0.010 0.016 0.050 0.032 0.008 1.380 0.295
0.275 0.310 0.120 0.020
0.180
0.022 0.070 0.046
0.015
3.56 0.38 0.38 1.02
4.57 0.53 1.78 0.38
0.140 0.015 0.015 0.040
0.180 0.021 0.070 0.015
1.400 0.315
0.295 0.400 0.150 0.042
0.13 40.51 7.75
7.24 8.38 3.05 1.65
40.77 8.26
7.22 9.40 3.81 2.16
0.005 1.595 0.305
0.285 0.33 0.120 0.065
1.605 0.325
0.292 0.370 0.150 0.085
2.54
0.100
2.54
0.100
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
Rev. 02/14/03
PACKAGING INFORMATION
150-mil Plastic Package Code:
SEATING PLANE
Symbol Ref. Std. Leads
150-mil Plastic Inches 0.068 1.73 0.004 0.009 0.23 0.013 0.020 0.33 0.51 0.007 0.010 0.18 0.25 0.189 0.197 0.150 0.157 3.81 3.99 0.228 0.245 5.79 6.22 0.050 1.27 0.020 0.035 0.51 0.89
Notes: Controlling dimension: inches, unless otherwise specified. Basic lead spacing between centers. Dimensions include mold flash protrusions should measured from bottom package. Formed leads shall planar with respect another within 0.004 inches seating plane.
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. 10/03/01
PACKAGING INFORMATION
Thin Shrink Small Outline TSSOP Package Code: pin, pin)
TSSOP Ref. Std. JEDEC MO-153 Leads Millimeters Inches Symbol 1.20 0.047 0.05 0.15 0.002 0.006 0.80 1.05 0.032 0.041 0.19 0.30 0.007 0.012 0.09 0.20 0.004 0.008 2.90 3.10 0.114 0.122 4.30 4.50 0.169 0.177 6.40 0.252 0.65 0.026 0.45 0.75 0.018 0.030
TSSOP Ref. Std. JEDEC MO-153 Leads Millimeters Inches Symbol 1.20 0.047 0.05 0.15 0.002 0.006 0.80 1.05 0.031 0.041 0.19 0.30 0.007 0.012 0.09 0.20 0.0035 0.008 4.90 5.10 0.193 0.201 4.30 4.50 0.170 0.177 6.40 0.252 0.65 0.026 0.45 0.75 0.0177 0.0295
reserves right make changes products time without notice order improve design supply best possible product. assume responsibility errors which appear this publication. Copyright 2002, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc.
02/01/02

IS25C01

Top Searches for this datasheet

Other recent searches