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IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
CMOS SyncFIFO512 1024 2048
IDT723631 IDT723641 IDT723651
Integrated Device Technology, Inc.
FEATURES:
Free-running CLKA CLKB asynchronous coincident (permits simultaneous reading writing data single clock edge) Clocked FIFO buffering data from Port Port Storage capacity: IDT723631 IDT723641 1024 IDT723651 2048 Synchronous read retransmit capability Mailbox register each direction Programmable Almost-Full Almost-Empty flags Microprocessor interface control logic Input-Ready (IR) Almost-Full (AF) flags synchronized CLKA Output-Ready (OR) Almost-Empty (AE) flags synchronized CLKB Low-power 0.8-micron advanced CMOS technology
Supports clock frequencies Fast access times Available 132-pin plastic quad flat package (PQF) space-saving 120-pin thin quad flat package (TQFP)
DESCRIPTION:
IDT723631/723641/723651 monolithic highspeed, low-power, CMOS clocked FIFO memory. supports clock frequencies read access times fast 12ns. 512/1024/2048 dual-port SRAM FIFO buffers data from port Port FIFO memory retransmit capability, which allows previously read data accessed again. FIFO flags indicate empty full conditions programmable flags (almost full almost empty) indicate when selected number words stored memory. Communication between each port take place with 36-bit mailbox registers. Each mailbox
FUNCTIONAL BLOCK DIAGRAM
MBF1
CLKA
Input Register
Sync Retransmit Logic
Reset Logic
Output Register
W/RA
Mail Register Port-A Control Logic 1024 2048 SRAM
RRFM
Write Pointer
Read Pointer
FS0/SD FS1/SEN
Status Flag Logic
Flag Offset Registers CLKB Port-B Control Logic
W/RB
Mail Register
MBF2
3023
logo registered trademark SyncFIFO trademark Integrated Device Technology, Inc.
©1996 Integrated Device Technology, Inc. latest information contact IDT's site www.idt.com fax-on-demand 408-492-8391.
DECEMBER 1995
DSC-3023/2
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
DESCRIPTION (CONTINUED)
register flag signal when mail been stored. more devices used parallel create wider data paths. Expansion also possible word depth. IDT723631/723641/723651 clocked FIFO, which means each port employs synchronous interface. data transfers through port gated LOW-to-HIGH transition continuous (free-running) port clock enable signals. continuous clocks each port independent another asynchronous coincident. enables each port arranged provide simple
interface between microprocessors and/or buses with synchronous control. input-ready (IR) flag almost-full (AF) flag FIFO two-stage synchronized CLKA. output-ready (OR) flag almost-empty (AE) flag FIFO twostage synchronized CLKB. Offset values almost-full almost empty flags FIFO programmed from port through serial input.
CONFIGURATION
RFS1/SEN FS0/SD
MBF1
CLKB W/RB
MBF2
W/RA
CLKA
132-1
*Electrical center beveled edge. identifier corner.
Notes: internal connection Uses Yamaichi socket IC51-1324-828
3023
PACKAGE VIEW
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
CONFIGURATION (CONTINUED)
CLKA W/RA
FS0/SD FS1/SEN RRFM
MBF2
W/RB
CLKB
MBF1
PN120
3023
Note: internal connection
TQFP VIEW
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
DESCRIPTION
Symbol A0-A35 Name Port-A Data Almost-Empty Flag Description 36-bit bidirectional data port side Programmable flag synchronized CLKB. when number words FIFO less than equal value almost-empty register (X). Programmable flag synchronized CLKA. when number empty locations FIFO less than equal value almost-full offset register (Y). 36-bit bidirectional data port side CLKA continuous clock that synchronizes data transfers through port-A aynchronous coincident CLKB. synchronous LOW-to-HIGH transition CLKA. CLKB continuous clock that synchronizes data transfers through port-B asynchronous coincident CLKA. synchro nous LOW-to-HIGH transition CLKB. must enable LOW-to-HIGH transition CLKA read write data port-A. A0-A35 outputs high-impedance state when HIGH. must enable LOW-to-HIGH transition CLKB read write data port-B. B0-B35 outputs high-impedance state when HIGH. must HIGH enable LOW-to-HIGH transition CLKA read write data port-A. must HIGH enable LOW-to-HIGH transition CLKB read write data port-B. FS1/SEN FS0/SD dual-purpose inputs used flag offset register programming. During device reset, FS1/SEN FS0/SD selects flag offset programming method. Three offset register programming methods available: automatically load preset values, parallel load from port serial load. When serial load selected flag offset register programming, FS1/SEN used enable synchronous LOW-to-HIGH transition CLKA. When FS1/SEN LOW, rising edge CLKA load present FS0/SD into registers. number writes required program offset registers 18/20/22. first write stores Y-register last write stores X-register LSB. synchronized LOW-to-HIGH transition CLKA. When LOW, FIFO full writes array disabled. When FIFO retransmit mode, indicates when memory been filled point retransmit data prevents further writes. during reset HIGH after reset. HIGH level chooses mailbox register port-A read write operation. HIGH level chooses mailbox register port-B read write operation. When B0-B35 outputs active, HIGH level selects data from mail1 register output level selects FIFO data output.
B0-B35 CLKA
Almost-Full Flag.
Port-B Data. Port-A Clock
CLKB
Port-B Clock
FS1/SEN, FS0/SD
Port-A Chip Select
Port-B Chip Select
Port-A Enable Port-B Enable Flag-Offset Select Serial Enable, Flag Offset Serial Data
Input-Ready Flag
Port-A Mailbox Select Port-B Mailbox Select
MBF1
Mail1 Register Flag
reset.
MBF1 LOW-to-HIGH transition CLKA that writes data mail1 register. MBF1 HIGH LOW-to-HIGH transition CLKB when port-B read selected HIGH. MBF1 HIGH
3023
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
DESCRIPTION (CONTINUED)
Symbol Name Mail2 Register Flag Description MBF2 LOW-to-HIGH transition CLKB that writes data mail2 register. MBF2 HIGH LOW-to-HIGH transition CLKA when port-A read selected HIGH. MBF2 HIGH reset. synchronized LOW-to-HIGH transition CLKB. When LOW, FIFO empty reads disabled. Ready data present output register FIFO when HIGH. forced during reset goes HIGH third LOW-to-HIGH transition CLKB after word loaded empty memory. When FIFO retransmit mode, HIGH enables LOW-toHIGH transition CLKB reset read pointer beginning retransmit location output first selected retransmit data. reset device, four LOW-to-HIGH transitions CLKA four LOW-toHIGH transitions CLKB must occur while LOW. LOW-to-HIGH transition latches status offset selection. When HIGH valid data present FIFO output register HIGH), LOW-to-HIGH transition CLKB selects data beginning retransmit puts FIFO retransmit mode. selected word remains initial retransmit point until LOW-to-HIGH transition CLKB occurs while LOW, taking FIFO retransmit mode. HIGH selects write operation selects read operation port LOW-to-HIGH transition CLKA. A0-A35 outputs high-impedance state when W/RA HIGH. selects write operation HIGH selects read operation port LOW-to-HIGH transition CLKB. B0-B35 outputs high-impedance state when W/RB HIGH.
3023
MBF2
Output-Ready Flag
Read From Mark
Reset
R
Retransmit Mode
W/RA
Port-A Write/Read Select Port-B Write/Read Select
W/RB
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)(2)
Symbol
Rating Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current, VCC) Output Clamp Current, VCC) Continuous Output Current, VCC) Continuous Current Through Operating Free Temperature Range Storage Temperature Range
Commercial -0.5 -0.5 VCC+0.5 -0.5 VCC+0.5 ±400
Unit
3023
IOUT TSTG
NOTES: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "Recommended Operating Conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. input output voltage ratings exceeded provided input output current ratings observed.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Supply Voltage HIGH Level Input Voltage LOW-Level Input Voltage HIGH-Level Output Current LOW-Level Output Current Operating Free-air Temperature Min. Max. Unit
3023
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter
Test Conditions 4.5V, -0.2 Input
Min.
Typ.(1)
Max.
Unit
Other Inputs
Other Inputs
A0-A35 B0-B35 A0-A35 B0-35
COUT
3023
NOTES: typical values 25°C. This supply current when each input least specified voltage levels rather than VCC.
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES SUPPLY VOLTAGE OPERATING FREE-AIR TEMPERATURE
IDT723631L15 IDT723631L20 IDT723631L30 IDT723641L15 IDT723641L20 IDT723641L30 IDT723651L15 IDT723651L20 IDT723651L30 Min. Max. Min. Max. Min. Max.
Symbol tCLK tCLKH tCLKL tENS1 tENS2 tRMS tRSTS tFSS tSDS tENH1 tENH2 tRMH tRSTH tFSH tSPH
Parameter Clock Frequency, CLKA CLKB Clock Cycle Time, CLKA CLKB Pulse Duration, CLKA CLKB HIGH Pulse Duration, CLKA CLKB Setup Time, A0-A35 before CLKA B0-B35 before CLKB Setup Time, CLKA; CLKB Setup Time, CSA, W/RA, CLKA; CSB, W/RB, CLKB Setup Time, Rand CLKB Setup Time, before CLKA CLKB(1) Setup Time, before HIGH Setup Time, FS0/SD before CLKA Setup Time, FS1/SEN before CLKA Hold Time, A0-A35 after CLKA B0-B35 after CLKB Hold Time, after CLKA; after CLKB Hold Time, CSA, W/RA, after CLKA; CSB, W/RB, after CLKB Hold Time, Rand after CLKB Hold Time, after CLKA CLKB Hold Time, after HIGH Hold Time, FS0/SD after CLKA Hold Time, FS1/SEN after CLKA Skew Time, between CLKA CLKB Hold Time, FS1/SEN HIGH after HIGH
Unit
3023
66.7
33.4
tSENS
tSDH
tSENH
tSKEW1
tSKEW2(3) Skew Time, between CLKA CLKB
NOTES: Requirement count clock edge least four needed reset FIFO. Only applies when serial load method used program flag offset registers. Skew time timimg constraint proper device operation only included illustrate timing relationship between CLKA cycle CLKB cycle.
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
ELECTRICAL CHARACTERISTICS
IDT723631L15 IDT723631L20 IDT723631L30 IDT723641L15 IDT723641L20 IDT723641L30 IDT723651L15 IDT723651L20 IDT723651L30 Min. Max. Min. Max. Min. Max. 66.7 33.4
Symbol tPIR tPOR tPAE tPAF tPMF
Parameter Clock Frequency, CLKA CLKB Access Time, CLKB B0-B35 Propagation Delay Time, CLKA Propagation Delay Time, CLKB Propagation Delay Time, CLKB Propagation Delay Time, CLKA Propagation Delay Time, CLKA MBF1 MBF2 HIGH CLKB MBF2 MBF1 HIGH Propagation Delay Time, CLKA B0-B35(1) CLKB A0-A35(2) Propagation Delay Time, B0-B35 Valid Propagation Delay Time, HIGH
Unit
tPMR tMDV tRSF
13.5
Enable Time, W/RA A0-A35 Active W/RB HIGH B0-B35 Active Disable Time, W/RA HIGH A0-A35 high impedance HIGH W/RB B0-B35 high impedance
tDIS
3023
NOTES: Writing data mail1 register when B0-B35 outputs active HIGH. Writing data mail2 register when A0-A35 outputs active HIGH.
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
SIGNAL DESCRIPTION RESET IDT723631/723641/723651 reset taking reset (RST) input least four port-A clock (CLKA) four port-B (CLKB) LOW-to-HIGH transitions. reset input switch asynchronously clocks. reset initializes memory read write pointers forces input-ready (IR) flag LOW, output-ready (OR) flag HIGH, almost-empty (AE) flag LOW, almost-full (AF) flag HIGH. Resetting device also forces mailbox flags (MBF1, MBF2) HIGH. After FIFO reset, input-ready flag HIGH after least clock cycles begin normal operation. FIFO must reset after power before data written memory. ALMOST-EMPTY FLAG ALMOST-FULL FLAG OFFSET PROGRAMMING registers IDT723631/723641/723651 used hold offset values almost-empty almost full flags. almost-empty (AE) flag offset register labeled almost-full (AF) flag offset register labeled offset register loaded with value three ways: preset values loaded into offset registers, parallel load from port serial load. offset register programming mode chosen flag select (FS1, FS0) inputs during LOW-to-HIGH transition input (See Table PRESET VALUES preset value chosen inputs time LOW-to-HIGH transition according Table preset value automatically loaded into registers. other device initialization necessary begin normal operation, flag HIGH after LOW-to-HIGH transitions CLKA. PARALLEL LOAD FROM PORT program registers from port device reset with during LOW-to-HIGH transition RST. After this reset complete, flag HIGH after LOW-to-HIGH transitions CLKA. first writes FIFO store data memory load offset registers order Each offset register IDT723631, IDT723641, IDT723651 uses port-A inputs (A8-A0), (A9-A0), (A10-A0), respectively. highest number input used most significant binary number each case. Each register value programmed from (IDT723631), 1020 (IDT723641), 2044 (IDT723651). After both offset registers programmed from port subsequent FIFO writes store data SRAM. SERIAL LOAD program registers serially, device reset with FS0/SD FS1/SEN HIGH during LOW-toHIGH transition RST. After this reset complete,
register values loaded bitwise through FS0/SD input each LOW-to-HIGH transition CLKA that FS1/SEN input LOW. Eighteen-, 20-, 22-bit writes needed complete programming IDT723631, IDT723641, IDT723651, respectively. first-bit write stores most significant register, last-bit write stores least significant register. Each register value programmed from (IDT723631), 1020 (IDT723641), 2044 (IDT723651). When option program offset registers serially chosen, input-ready (IR) flag remains until register bits written. flag HIGH LOW-toHIGH transition CLKA after last loaded allow normal FIFO operation. FIFO WRITE/READ OPERATION state port-A data (A0-A35) outputs controlled port-A chip select (CSA) port-A write/read select (W/RA). A0-A35 outputs high-impedance state when either W/RA HIGH. A0-A35 outputs active when both W/RA LOW. Data loaded into FIFO from A0-A35 inputs LOW-to-HIGH transition CLKA when port-A mailbox select (MBA) LOW, W/RA, port-A enable (ENA), input-ready (IR) flag HIGH (see Table Writes FIFO independent concurrent FIFO read. port-B control signals identical those port-A with exception that port-B write/read select (W/RB) inverse port-A write/read select (W/RA). state port-B data (B0-B35) outputs controlled portB chip select (CSB) port-B write/read select (W/RB). B0-B35 outputs high-impedance state when either HIGH W/RB LOW. B0-B35 outputs active when W/RB HIGH. Data read from FIFO output register LOWto-HIGH transition CLKB when port-B mailbox select (MBB) LOW, W/RB, port-B enable (ENB), output-ready (OR) flag HIGH (see Table Reads from FIFO independent concurrent FIFO writes. setup- hold-time constraints port clocks port-chip selects write/read selects only enabling write read operations related high-
Registers Serial Load Parallel Load From Port
3023
NOTE: register holds offset register holds offset Table Flag Programming
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
impedance control data outputs. port enable during clock cycle, port chip select write/read select change states during setup- hold time window cycle. When output-ready (OR) flag LOW, next data word sent FIFO output register automatically CLKB LOW-to-HIGH transition that sets output-ready flag HIGH. When HIGH, available data word clocked FIFO output register only when FIFO read selected port-B chip select (CSB), write/read select (W/RB), enable (ENB), mailbox select (MBB). SYNCHRONIZED FIFO FLAGS Each IDT723631/723641/723651 FIFO flag synchronized port clock through least flip-flop stages. This done improve flags' reliability reducing probability metastable events their outputs when CLKA CLKB operate asynchronously another. synchronized CLKB. synchronized CLKA. Table shows relationship each flag number words stored memory. OUTPUT-READY FLAG (OR) output-ready flag FIFO synchronized port clock that reads data from array (CLKB). When outputready flag HIGH, data present FIFO output
register. When output-ready flag LOW, previous data word present FIFO output register attempted FIFO reads ignored. FIFO read pointer incremented each time word clocked output register. state machine that controls output-ready flag monitors write-pointer read-pointer comparator that indicates when FIFO SRAM status empty, empty+1, empty+2. From time word written FIFO, shifted FIFO output register minimum three cycles CLKB. Therefore, outputready flag word memory next data sent FIFO output register three CLKB cycles have elapsed since time word written. outputready flag FIFO remains until third LOW-toHIGH transition CLKB occurs, simultaneously forcing output-ready flag HIGH shifting word FIFO output register. LOW-to-HIGH transition CLKB begins first synchronization cycle write clock transition occurs time tSKEW1 greater after write. Otherwise, subsequent CLKB cycle first synchronization cycle (see Figure INPUT READY FLAG (IR) input ready flag FIFO synchronized port clock that writes data array (CLKA). When input-
W/RA
CLKA
A0-A35 Outputs High-Impedance State High-Impedance State High-Impedance State High-Impedance State Active, Mail2 Register Active, Mail2 Register Active, Mail2 Register Active, Mail2 Register
Port Functions None None FIFO Write Mail1 Write None None None Mail2 Read (Set MBF2 HIGH)
3023
Table Port-A Enable Function Table
W/RB
CLKB
B0-A35 Outputs High-Impedance State High-Impedance State High-Impedance State High-Impedance State Active, FIFO Output Register Active, FIFO Output Register Active, Mail1 Register Active, Mail1 Register
Port Functions None None None Mail2 Write None FIFO read None Mail1 Read (Set MBF1 HIGH)
3023
Table Port-B Enable Function Table
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
ready flag HIGH, memory location free SRAM write data. memory locations free when inputready flag attempted writes FIFO ignored. Each time word written FIFO, write pointer incremented. state machine that controls input-ready flag monitors write-pointer read pointer comparator that indicates when FIFO SRAM status full, full-1, full-2. From time word read from FIFO, previous memory location ready written minimum three cycles CLKA. Therefore, input-ready flag less than cycles CLKA have elapsed since next memory write location been read. second LOW-to-HIGH transition CLKA after read sets input-ready flag HIGH, data written following cycle. LOW-to-HIGH transition CLKA begins first synchronization cycle read clock transition occurs time tSKEW1 greater after read. Otherwise, subsequent CLKA cycle first synchronization cycle (see Figure ALMOST-EMPTY FLAG (AE) almost-empty flag FIFO synchronized port clock that reads data from array (CLKB). state machine that controls almost-empty flag monitors writepointer read-pointer comparator that indicates when FIFO SRAM status almost empty, almost empty+1, almost empty+2. almost-empty state defined contents register This register loaded with preset value during FIFO reset,programmed from port programmed serially (see almost-empty flag almost-full flag offset programming above). almost-empty flag when FIFO contains less words HIGH when FIFO contains (X+1) more words. data word present FIFO output register been read from memory. LOW-to-HIGH transitions CLKB required after FIFO write almost-empty flag reflect level fill; therefore, almost-empty flag FIFO containing (X+1) more words remains cycles CLKB have elapsed since write that filled memory (X+1)
level. almost-empty flag HIGH second LOWto-HIGH transition CLKB after FIFO write that fills memory (X+1) level. LOW-to-HIGH transition CLKB begins first synchronization cycle occurs time tSKEW2 greater after write that fills FIFO (X+1) words. Otherwise, subsequent CLKB cycle first synchronization cycle (see Figure ALMOST-FULL FLAG (AF) almost-full flag FIFO synchronized port clock that writes data array (CLKA). state machine that controls almost-full flag monitors write-pointer read-pointer comparator that indicates when FIFO SRAM status almost full, almost full-1, almost full-2. almostfull state defined contents register This register loaded with preset value during FIFO reset, programmed from port programmed serially (see almost-empty flag almost-full flag offset programming). almost-full flag when number words FIFO greater than equal (512-Y), (1024-Y), (2048-Y) IDT723631, IDT723641, IDT723651, respectively. almost-full flag HIGH when number words FIFO less than equal [512-(Y+1)], [1024-(Y+1)], [2048-(Y+1)] IDT723631, IDT723641, IDT723651, respectively. data word present FIFO output register been read from memory. LOW-to-HIGH transitions CLKA required after FIFO read almost-full flag reflect level fill. Therefore, almost-full flag FIFO containing [512/1024/ 2048-(Y+1)] less words remains cycles CLKA have elapsed since read that reduced number words memory [512/1024/2048-(Y+1)]. almost-full flag HIGH second LOW-to-HIGH transition CLKA after FIFO read that reduces number words memory [512/1024/2048-(Y+1)]. LOW-to-HIGH transition CLKA begins first synchronization cycle occurs time tSKEW2 greater after read that reduces number words memory [512/1024/2048-(Y+1)]. Otherwise, subsequent CLKA cycle first synchronization cycle (see Figure
Number Words FIFO(1,2) IDT723631 (X+1) [512-(Y+1)] (512-Y) IDT723641 (X+1) [1024-(Y+1)] (1024-Y) 1023 1024 IDT723651 (X+1) [2048-(Y+1)] (2048-Y) 2047 2048
Synchronized CLKB
Synchronized CLKA
3023
NOTES: almost-empty offset almost-full offset When word present FIFO output register, previous memory location free. Table FIFO Flag Operation
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
SYNCHRONOUS RETRANSMIT synchronous retransmit feature IDT723631/ 723641/723651 allows FIFO data read repeatedly starting user-selected position. FIFO first into retransmit mode select beginning word prevent ongoing FIFO write operations from destroying retransmit data. Data vectors with minimum length three words retransmit repeatedly starting selected word. FIFO taken retransmit mode time allow normal device operation. FIFO retransmit mode LOW-to-HIGH transition CLKB when retransmit mode (RTM) input HIGH HIGH. rising CLKB edge marks data present FIFO output register first retransmit data. FIFO remains retransmit mode until LOW-to-HIGH transition occurs while LOW. When more reads have been done past initial retransmit word, retransmit initiated LOW-to-HIGH transition CLKB when read-from-mark (RFM) input HIGH. This rising CLKB edge shifts first retransmit word FIFO output register subsequent reads begin immediately. Retransmit loops done endlessly while FIFO retransmit mode. must during CLKB rising edge that takes FIFO retransmit mode. When FIFO into retransmit mode, operates with read pointers. current read pointer operates normally, incrementing each time word shifted FIFO output register used flags. shadow read pointer stores SRAM location time device into retransmit mode does change until device taken retransmit mode. shadow read pointer used flags. Data writes proceed while FIFO retransmit mode, write that stores (512 (1024 (2048 words after first retransmit word IDT723631, IDT723641, IDT723651, respectively. flag 512th, 1024th, 2048th write after first retransmit word IDT723631, IDT723641, IDT723651, respectively. When FIFO retransmit mode HIGH, rising CLKB edge loads current read pointer with shadow read-pointer value flag reflects
level fill immediately. retransmit changes FIFO status almost-empty range, CLKB rising edges after retransmit cycle needed switch high (see Figure 11).The rising CLKB edge that takes FIFO retransmit mode shifts read pointer used flags from shadow current read pointer. change read pointer used should cause both flags transmit HIGH, least CLKA synchronizing cycles needed before flags reflect change. rising CLKA edge after FIFO taken retransmit mode first synchronizing cycle occurs time tSKEW1 greater after rising CLKB edge (see Figure 12). rising CLKA edge after FIFO taken retransmit mode first synchronizing cycle occurs time tSKEW2 greater after rising CLKB edge (see Figure 14). MAILBOX REGISTERS 36-bit bypass registers IDT723631/723641/ 723651 pass command control information between port port mailbox-select (MBA, MBB) inputs choose between mail register FIFO port data transfer operation. LOW-to-HIGH transition CLKA writes A0-A35 data mail1 register when port-A write selected CSA, W/RA, with HIGH. LOWto-HIGH transition CLKB writes B0-B35 data mail2 register when port-B write selected CSB, W/RB, with HIGH. Writing data mail register sets corresponding flag (MBF1 MBF2) LOW. Attempted writes mail register ignored while mail flag LOW. When port-B data (B0-B35) outputs active, data comes from FIFO output register when port-B mailbox select (MBB) input from mail1 register when HIGH. Mail2 data always present port-A data (A0-A35) outputs when they active. mail1 register flag (MBF1) HIGH LOW-to-HIGH transition CLKB when port-B read selected CSB, with HIGH. mail2 register flag (MBF2) HIGH LOW-to-HIGH transition CLKA when port-A read selected CSA, W/RA, with HIGH. data mail register remains intact after read changes only when data written register.
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
CLKA RSTH CLKB RSTS
FS1,FS0
MBF1, MBF2
3023
Figure FIFO Reset Loading with Preset Value Eight
CLKA
FS1,FS0 ENS1 ENH1
Offset
Offset
First Word Stored FIFO
3023
NOTE: LOW, W/RA HIGH, LOW. necessary program offset register consecutive clock cycles.
Figure Programming Almost-Full Flag Almost-Empty Flag Offset Values from Port
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
CLKA
tPIR tFSS FS1/SEN tFSS FS0/SD tFSH tSPH tSENS tSENH tSENS tSENH
tSDS
tSDH
tSDS
tSDH
Offset
Offset
3023
NOTE: necessary program offset register bits consecutive clock cycles. FIFO write attempts ignored until HIGH. Figure Programming Almost-Full Flag Almost-Empty Flag Offset Values Serially
CLKH CLKA HIGH CLKL
ENS2 ENS2
ENH2 ENH2
ENS2 ENS1
ENH2
ENH1
ENS1
ENH1
ENS1
ENH1
Operation
3023
CLKH CLKB HIGH CLKL
Figure FIFO Write-Cycle Timing
W/RB
ENS1
Figure FIFO Read-Cycle Timing 5.13
ENH1
ENS1
ENH1 ENS1
ENH1 Operation
3023
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
CLKH CLKA
CLKL
HIGH ENS2 ENS1 ENH2 ENH1
HIGH SKEW1 CLKB
CLKH
CLKL
Data FIFO1 Output Register HIGH ENS1 ENH1
W/RB
-B35 Data FIFO Output Register
3023
NOTE: tSKEW1 minimum time between rising CLKA edge rising CLKB edge transition HIGH clock next word FIFO output register three CLKB cycles. time between rising CLKA edge rising CLKB edge less than tSKEW1, then transition HIGH first word load output register occur CLKB cycle later than shown.
Figure Flag Timing First Data Word Fallthrough when FIFO Empty
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
CLKH CLKB CLKL
W/RB
HIGH ENS1 ENH1
-B35
HIGH
Previous Word FIFO Output Register Next Word From FIFO
SKEW1 CLKA FIFO Full HIGH
CLKH CLKL
ENS2 ENS1
ENH2 ENH1 Write
3023
NOTE: tSKEW1 minimum time between rising CLKB edge rising CLKA edge transition HIGH next CLKA cycle. time between rising CLKB edge rising CLKA edge less than tSKEW1, then transition HIGH CLKA cycle later than shown. Figure Flag Timing First Available Write when FIFO Full
CLKA ENS1 SKEW2 CLKB
ENH1
(X+1) Words FIFO ENS1
Word FIFO
ENH1
3023
NOTES: tSKEW2 minimum time between rising CLKA edge rising CLKB edge transition HIGH next CLKB cycle. time between rising CLKA edge rising CLKB edge less than tSKEW2, then transition HIGH CLKB cycle later than shown. FIFO write (CSA LOW, W/RA HIGH, LOW), FIFO read (CSB LOW, W/RB HIGH, LOW). Figure Timing when FIFO Almost Empty
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
SKEW2 CLKA ENS1 ENH1
(Depth
CLKB
[Depth
-(Y+1)]
Words FIFO
Words FIFO
ENS1
ENH1
3023
NOTES: tSKEW2 minimum time between rising CLKA edge rising CLKB edge transition HIGH next CLKA cycle. time between rising CLKB edge rising CLKA edge less than tSKEW2, then transition HIGH CLKA cycle later than shown. Depth IDT723631, 1024 IDT723641, 2048 IDT723651. FIFO write (CSA LOW, W/RA HIGH, LOW), FIFO read (CSB LOW, W/RB HIGH, LOW). Figure Timing when FIFO Almost Full
CLKB tENS1 tRMS R
tENH1 tRMS tRMS tRMH tRMH
tRMH
B0-B35 HIGH Initiate Retransmit Mode with First Word Retransmit from Selected Position Retransmit Mode
3023
NOTE: LOW, W/RB HIGH, LOW. input enables other than Rand needed control retransmit mode begin retransmit. Other enables shown only relate retransmit operations FIFO output register. Figure Retransmit Timing Showing Minimum Retransmit Length
CLKB
HIGH tRMS tRMH
R
tPAE
fewer words from Empty
(X+1) more words from Empty
3023
NOTE: value loaded almost empty flag offset register. Figure Maximum Latency When Retransmit Increases Number Stored Words Above
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
tSKEW1 CLKA CLKB tRMS RtRMH
FIFO Filled First Restransmit Word
tPIR
More Write Locations Available
3023
NOTE: tSKEW1 minimum time between rising CLKB edge rising CLKA edge transition HIGH next CLKA cycle. time between rising CLKB edge rising CLKA edge less than tSKEW1, then transition HIGH CLKA cycle later than shown.
Figure Timing from Retransmit Mode when More Write Locations Available
tSKEW2 CLKA
(Depth More Words Past First Restransmit Word
tPAE
(Y+1) More Write Locations Available
CLKB
tRMS R
tRMH
3023
NOTES: tSKEW2 minimum time between rising CLKB edge rising CLKA edge transition HIGH next CLKA cycle. time between rising CLKB edge rising CLKA edge less than tSKEW2, then transition HIGH CLKA cycle later than shown. Depth IDT723631, 1024 IDT723641, 2048 IDT723651. value loaded almost-full flag offset register. Figure Timing from Retransmit Mode when (Y+1) More Write Locations Available
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
CLKA tENS2 tENH2
W/RA
CLKB
MBF1 W/RB
tPMF
tPMF
tENS1 FIFO Output Register tMDV tPMR
tENH1
tDIS (Remains valid Mail1 Register after read)
3023
Figure Timing Mail1 Register MBF1 Flag
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
CLKB
tENS2
tENH2
W/RB
CLKA
MBF2
W/RA
tPMF
tPMF
tENS1 tPMR
tENH1
tDIS (Remains valid Mail2 Register after read)
3023
Figure Timing Mail2 Register MBF2 Flag
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
TYPICAL CHARACTERISTICS SUPPLY CURRENT CLOCK FREQUENCY fdata 25°C
Supply Current CC(f)
3023
Clock Frequency
Figure
CALCULATING POWER DISSIPATION ICC(f) current graph Figure taken while simultaneously reading writing FIFO IDT723641 with CLKA CLKB data inputs data outputs change state during each clock cycle consume highest supply current. Data outputs were disconnected normalize graph zero-capacitance load. Once capacitance load data-output channel number IDT723631/723641/723651 inputs driven HIGH levels known, power dissipation calculated with equation below. With ICC(f) taken from FIgure maximum power dissipation (PT) IDT723631/723641/723651 calculated [ICC(f) dc)] VCC2 where: number inputs driven levels increase power supply current each input HIGH level duty cycle inputs HIGH level output capacitance load switching frequency output
When reads writes occurring IDT723631/723641/723651, power dissipated single clock (CLKA CLKB) input running frequency calculated 0.209 mA/MHz
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
PARAMETER MEASUREMENT INFORMATION
From Output Under Test
Timing Input Data, Enable Input Low-Level Input High-Level Input
VOLTAGE WAVEFORMS SETUP HOLD TIMES
VOLTAGE WAVEFORMS PULSE DURATIONS
Output Enable tPLZ Low-Level Output
tPZL tPZH In-Phase Output Input
High-Level Output
tPHZ
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
3023
NOTE: Includes probe capacitance Figure Load Circuit Voltage Waveforms
5.13
IDT723631/723641/723651 CMOS SyncFIFO512 1024 2048
ORDERING INFORMATION
XXXXXX Device Type Power Speed Package Process/ Temperature Range
BLANK
Commercial (0°C +70°C)
Thin Quad Flat Pack Plastic Quad Flat Pack Commercial Only Clock Cycle Time (tCLK) Speed Nanoseconds
Power
723631 Synchronous FIFO 723641 1024 Synchronous FIFO 723651 2048 Synchronous FIFO
3023
5.13
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