ICL7135
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ICL7135
Data Sheet August 2007 FN3093.4
Digit, Output, Converter
Intersil ICL7135 precision converter, with multiplexed output digit drivers, combines dualslope conversion reliability with 20,000 count accuracy ideally suited visual display DVM/DPM market. 2.0000V full scale capability, auto-zero, autopolarity combined with true ratiometric operation, almost ideal differential linearity true differential input. necessary active devices contained single CMOS with exception display drivers, reference, clock. ICL7135 brings together unprecedented combination high accuracy, versatility, true economy. features auto-zero less than 10V, zero drift less than 1V/oC, input bias current 10pA (Max), rollover error less than count. versatility multiplexed outputs increased addition several pins which allow operate more sophisticated systems. These include STROBE, OVERRANGE, UNDERRANGE, RUN/HOLD BUSY lines, making possible interface circuit microprocessor UART.
Features
Accuracy Guaranteed Count Over Entire ±20000 Counts (2.0000V Full Scale) Guaranteed Zero Reading Input Typical Input Leakage Current True Differential Input True Polarity Zero Count Precise Null Detection Single Reference Voltage Required Overrange Underrange Signals Available AutoRange Capability Outputs Compatible Blinking Outputs Gives Visual Indication Overrange Auxiliary Inputs/Outputs Available Interfacing UARTs, Microprocessors, Other Circuitry Multiplexed Outputs Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER ICL7135CPI PART MARKING ICL7135CPI TEMP. RANGE (°C) PACKAGE PKG. DWG. E28.6
Pinout
ICL7135 (PDIP) VIEW
REFERENCE NALOG COMMON BUFF (MSD) (LSB) UNDERRANGE OVERRANGE STROBE DIGITAL CLOCK BUSY (LSD) (MSB)
PDIP
ICL7135CPIZ ICL7135CPIZ PDIP E28.6 (Note (Pb-free) (Note NOTES: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020. Pb-free PDIPs used through hole wave solder processing only. They intended Reflow solder processing applications.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2004. Rights Reserved other trademarks mentioned property their respective owners.
ICL7135 Typical Application Schematic
VREF 1.000V VREF ANALOG 100k 0.47F 100k 100k SIGNAL INPUT 100K 0.1F ICL7135 SEVEN SEG. DECODE ANODE DRIVER TRANSISTORS DISPLAY CLOCK 120kHz
FN3093.4
ICL7135
Absolute Maximum Ratings
Supply Voltage .+6V Analog Input Voltage (Either Input) (Note VReference Input Voltage (Either Input) VClock Input Voltage
Thermal Information
Thermal Resistance (Typical, Note (oC/W) PDIP Package Maximum Junction Temperature .+150oC Maximum Storage Temperature Range -65oC +150oC Maximum Lead Temperature (Soldering 10s) .+300oC NOTE: Pb-free PDIPs used through hole wave solder processing only. They intended Reflow solder processing applications.
Operating Conditions
Temperature Range. +70oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: Input voltages exceed supply voltages provided input current limited +100A. measured with component mounted effective thermal conductivity test board free air. Tech Brief TB379 details.
Electrical Specifications
ANALOG (Notes Zero Input Reading Ratiometric Error (Note
+5V, -5V, +25oC, fCLK Readings/s, Unless Otherwise Specified TEST CONDITIONS VREF 1.000V VREF 1.000V -VlN +VlN Full scale 2.000V +70oC -00000 +00000 0.01 +00000 UNITS Counts Counts V/oC
PARAMETER
Linearity Over Full Scale (Error Reading from Best Straight Line) Differential Linearity (Difference Between Worse Case Step Adjacent Counts Ideal Step) Rollover Error (Difference Reading Equal Positive Negative Voltage Near Full Scale) Noise (Peak-to-Peak Value Exceeded Time), Input Leakage Current, IILK Zero Reading Drift (Note Scale Factor Temperature Coefficient, (Notes DIGITAL INPUTS Clock Run/Hold (See Figure VINH VINL IINL IINH DIGITAL OUTPUTS Outputs, BUSY, STROBE, OVERRANGE, UNDERRANGE, POLARITY, SUPPLY Supply Range, Supply Range, V+5V Supply Current, Supply Current, IPower Dissipation Capacitance, CLOCK Clock Frequency (Note
+2V, +70oC Ext. Ref. 0ppm/oC
1.6mA -1mA -10A Clock Frequency
0.02 0.25 4.99 2000
0.40 1200
NOTES: Tested 41/2 digit (20.000 count) circuit shown Figure (Clock frequency 120kHz.) Tested with dielectric absorption integrating capacitor, resistor shorted, RlNT Component Value Selection Discussion. temperature range extended +70oC beyond long auto-zero reference capacitors increased absorb higher leakage ICL7135. This specification relates clock frequency range over which lCL7135 will correctly perform various functions "Max Clock Frequency" section limitations clock frequency range system. Parameter guaranteed design characterization. production tested.
FN3093.4
ICL7135
VREF 1.000V ICL7135 VREF 100k ANALOG 100k LO10 UNDERRANGE OVERRANGE RUN/HOLD DIGITAL POLARITY BUSY CLOCK 120kHz
ANALOG STROBE 0.47F 100k
SIGNAL INPUT
100K
CLOCK
0.1F
FIGURE ICL7135 TEST CIRCUIT
FIGURE ICL7135 DIGITAL LOGIC INPUT
CREF CREF+ CREF
RINT BUFFER
AUTO ZERO INTEGRATOR
CINT
ANALOG COMMON DE(+) DE(-) DE(-) DE(+) INPUT INPUT HIGH COMPARATOR
ZEROCROSSING DETECTOR
POLARITY
A/Z, DE(±),
FIGURE ANALOG SECTION ICL7135
FN3093.4
ICL7135 Detailed Description
Analog Section Figure shows Block Diagram Analog Section ICL7135. Each measurement cycle divided into four phases. They auto-zero (AZ), signal-integrate (INT), de-integrate (DE) zero-integrator (Zl). Auto-Zero Phase During auto-zero, three things happen. First, input high disconnected from pins internally shorted analog COMMON. Second, reference capacitor charged reference voltage. Third, feedback loop closed around system charge auto-zero capacitor compensate offset voltages buffer amplifier, integrator, comparator. Since comparator included loop, accuracy limited only noise system. case, offset referred input less than 10V. Signal Integrate Phase During signal integrate, auto-zero loop opened, internal short removed, internal input high connected external pins. converter then integrates differential voltage between fixed time. This differential voltage within wide common mode range; within volt either supply. other hand, input signal return with respect converter power supply, tied analog COMMON establish correct common-mode voltage. this phase, polarity integrated signal latched into polarity F/F. De-Integrate Phase third phase de-integrate reference integrate. Input internally connected analog COMMON input high connected across previously charged reference capacitor. Circuitry within chip ensures that capacitor will connected with correct polarity cause integrator output return zero. time required output return zero proportional input signal. Specifically digital reading displayed
OUTPUT COUNT 10,000
However, since integrator also swings with common mode voltage, care must exercised assure integrator output does saturate. worst case condition would large positive common-mode voltage with near full scale negative differential input voltage. negative input signal drives integrator positive when most swing been used positive common mode voltage. these critical applications integrator swing reduced less than recommended full scale swing with some loss accuracy. integrator output swing within 0.3V either supply without loss linearity. Analog COMMON Analog COMMON used input return during autozero de-integrate. different from analog COMMON, common mode voltage exists system taken care excellent CMRR converter. However, most applications will fixed known voltage (power supply common instance). this application, analog COMMON should tied same point, thus removing common mode voltage from converter. reference voltage referenced analog COMMON. Reference reference input must generated positive voltage with respect COMMON, shown Figure
ICL7135 6.8V ZENER
COMMON
FIGURE
Zero Integrator Phase final phase zero integrator. First, input shorted analog COMMON. Second, feedback loop closed around system input high cause integrator output return zero. Under normal condition, this phase lasts from clock pulses, after overrange conversion, extended 6200 clock pulses. Differential Input input accept differential voltages anywhere within common mode range input amplifier; specifically from 0.5V below positive supply above negative supply. this range system CMRR 86dB typical.
ICL7135
6.8k
ICL8069 1.2V REFERENCE
COMMON
FIGURE FIGURE USING EXTERNAL REFERENCE
FN3093.4
ICL7135
Digital Section Figure shows Digital Section ICL7135. ICL7135 includes several pins which allow operate conveniently more sophisticated systems. These include: Run/HOLD (Pin When high open) will free-run with equally spaced measurement cycles every 40,002 clock pulses. taken low, converter will continue full measurement cycle that doing then hold this reading long held low. short positive pulse (greater than 300ns) will initiate measurement cycle, beginning with between 10,001 counts auto zero. pulse occurs before full measurement cycle (40,002 counts) completed, will recognized converter will simply complete measurement doing. external indication that full measurement cycle been completed that first strobe pulse (see below) will occur counts after this cycle. Thus, Run/HOLD been least counts, converter holding ready start measurement when pulsed high. STROBE (Pin This negative going output pulse that aids transferring data external latches, UARTs, microprocessors. There negative going STROBE pulses that occur center each digit drive pulses occur once only once each measurement cycle starting clock pulses after full measurement cycle. Digit (MSD) goes high measurement cycle stays counts. center this digit pulse avoid race conditions between changing digit drives) first STROBE pulse goes negative clock pulse width. Similarly, after digit digit goes high (for clock pulses) pulses later STROBE goes negative second time. This continues through digit (LSD) when fifth last STROBE pulse sent. digit drive will continue scan (unless
POLARITY ANALOG SECTION POLARITY ZERO CROSS. DET. LATCH
previous signal overrange) additional STROBE pulses will sent until measurement available. BUSY (Pin BUSY goes high beginning signal integrate stays high until first clock pulse after zero crossing after measurement case overrange). internal latches enabled (i.e., loaded) during first clock pulse after busy latched this clock pulse. circuit automatically reverts auto-zero when BUSY, also considered signal. very simple means transmitting data down single wire pair from remote location would BUSY with clock subtract 10,001 counts from number pulses received mentioned previously there "NO-count" pulse each reference integrate cycle. OVERRANGE (Pin This goes positive when input signal exceeds range (20,000) converter. output BUSY reset zero beginning reference integrate next measurement cycle. UNDERRANGE (Pin This goes positive when reading range less. output BUSY reading 1800 less) reset beginning signal integrate next reading. POLARlTY (Pin This positive positive input signal. valid even zero reading. other words, +0000 means signal positive less than least significant bit. converter used null detector forcing equal frequency readings. null this point should less than LSB. This output becomes valid beginning reference integrate remains correct until revalidated next measurement.
LATCH
MULTIPLEXER
LATCH
LATCH
LATCH
COUNTERS
CONTROL LOGIC
DIGITAL
CLOCK
RUN/ HOLD
OVER UNDER STROBE BUSY RANGE RANGE
FIGURE DIGITAL SECTION ICL7135
FN3093.4
ICL7135
Digit Drives (Pins Each digit drive positive going signal that lasts clock pulses. scan sequence (MSD), (LSD). five digits scanned this scan continuous unless overrange occurs. Then digit drives blanked from strobe sequence until beginning Reference Integrate when will start scan again. This give blinking display visual indication overrange. (Pins Binary coded Decimal bits positive logic signals that simultaneously with digit driver signal. Auto-Zero Reference Capacitor physical size auto-zero capacitor influence noise system. larger capacitor value reduces system noise. larger physical size increases system noise. reference capacitor should large enough such that stray capacitance ground from nodes negligible. dielectric absorption reference auto-zero only important power-on when circuit recovering from overload. Thus, smaller cheaper caps used here accurate readings required first seconds recovery. Reference Voltage analog input required generate full scale output 2VREF stability reference voltage major factor overall absolute accuracy converter. this reason, recommended that high quality reference used where high-accuracy absolute measurements being made. Rollover Resistor Diode small rollover error occurs ICL7135, this easily corrected adding diode resistor series between INTegrator OUTput analog COMMON ground. value shown schematics optimum recommended conditions, integrator swing clock frequency modified, adjustment needed. diode silicon diode such 1N914. These components eliminated rollover error important altered value correct other (small) sources rollover needed. Clock Frequency maximum conversion rate most dual-slope converters limited frequency response comparator. comparator this circuit follows integrator ramp with delay, clock frequency 160kHz period) half first reference integrate clock period lost delay. This means that meter reading will change from with input, with 150V input, with 250V input, etc. This transition midpoint considered desirable most users; however, clock frequency increased appreciably above 160kHz, instrument will flash noise peaks even when input shorted. many dedicated applications where input signal always polarity, delay comparator need limitation. Since non-linearity noise increase substantially with frequency, clock rates ~1MHz used. fixed clock frequency, extra count counts caused comparator delay will constant subtracted digitally. clock frequency extended above 160kHz without this error, however, using value resistor
Component Value Selection
optimum performance analog section, care must taken selection values integrator capacitor resistor, auto-zero capacitor, reference voltage, conversion rate. These values must chosen suit particular application. Integrating Resistor integrating resistor determined full scale input voltage output current buffer used charge integrator capacitor. Both buffer amplifier integrator have class output stage with 100A quiescent current. They supply drive current with negligible non-linearity. Values give good results, with nominal 20A, exact value integrating resistor chosen
full scale voltage
Integrating Capacitor product integrating resistor capacitor should selected give maximum voltage swing which ensures that tolerance built-up will saturate integrator swing (approx. 0.3V from either supply). supplies analog COMMON tied supply ground, ±3.5V full scale integrator swing fine, 0.47F nominal. general, value ClNT given
10,000 clock period integrator output voltage swing (10,000) (clock period) (20A) integrator output voltage swing
very important characteristic integrating capacitor that dielectric absorption prevent roll-over ratiometric errors. good test dielectric absorption capacitor with input tied reference. This ratiometric condition should read half scale 0.9999, deviation probably dielectric absorption. Polypropylene capacitors give undetectable errors reasonable cost. Polystyrene polycarbonate capacitors also used less critical applications.
FN3093.4
ICL7135
series with integrating capacitor. effect resistor introduce small pedestal voltage integrator output beginning reference integrate phase. careful selection ratio between this resistor integrating resistor tens ohms recommended circuit), comparator delay compensated maximum clock frequency extended approximately factor higher frequencies, ringing second order breaks will cause significant nonlinearities first counts instrument. Application Note AN017. minimum clock frequency established leakage auto-zero reference caps. With most devices, measurement cycles long give measurable leakage error. achieve maximum rejection 60Hz pickup, signal integrate cycle should multiple 60Hz. Oscillator frequencies 300kHz, 200kHz, 150kHz, 120kHz, 100kHz, 40kHz, 331/3kHz, etc. should selected. 50Hz rejection, oscillator frequencies 250kHz, 1662/3kHz, 125kHz, 100kHz, etc. would suitable. Note that 100kHz (2.5 readings/sec) will reject both 50Hz 60Hz. clock used should free from significant phase frequency jitter. Several suitable low-cost oscillators shown Typical Applications section. multiplexed output means that display takes significant current from logic supply, clock should have good PSRR. Zero-Crossing Flip-Flop flip-flop interrogates data once every clock pulse after transients previous clock pulse half-clock pulse have died down. False zero-crossings caused clock pulses recognized. course, flip-flop delays true zero-crossing count every instance, correction were made, display would always count high. Therefore, counter disabled clock pulse beginning phase This one-count delay compensates delay zero-crossing flip-flop, allows correct number latched into display. Similarly, one-count delay beginning phase gives overload display 0000 instead 0001. delay occurs during phase that true ratiometric readings result.
Evaluating Error Sources
Errors from "ideal" cycle caused Capacitor droop leakage.
INTEGRATOR OUTPUT
AUTO SIGNAL REFERENCE ZERO INT. INTEGRATE 10,001/ 10,000/ 20,001/ COUNTS COUNTS COUNTS MAX. FULL MEASUREMENT CYCLE 40,002 COUNTS
Capacitor voltage change charge "suck-out" (the reverse charge injection) when switches turn off. Non-linearity buffer integrator. High-frequency limitations buffer, integrator, comparator. Integrating capacitor non-linearity (dielectric absorption). Charge lost CREF charging CSTRAY Charge lost ClNT charge CSTRAY Each error analyzed error contribution converter application notes listed back page, specifically Application Note AN017 Application Note AN032.
BUSY OVER-RANGE WHEN APPLICABLE UNDER-RANGE WHEN APPLICABLE DIGIT SCAN OVER-RANGE EXPANDED SCALE BELOW FIRST COUNT LONGER REFERENCE INTEGRATE
Noise
peak-to-peak noise around zero approximately (peak-to-peak value exceeded time). Near full scale, this value increases approximately 30V. Much noise originates auto-zero loop, proportional ratio input signal reference.
1000/ COUNTS STROBE DIGIT SCAN OVER-RANGE
AUTO ZERO SIGNAL INTEGRATE
Analog Digital Grounds
Extreme care must taken avoid ground loops layout ICL7135 circuits, especially high-sensitivity circuits. most important that return currents from digital loads into analog ground line.
FIGURE TIMING DIAGRAM OUTPUTS
FN3093.4
ICL7135 Power Supplies
ICL7135 designed work from supplies. However, selected applications negative supply required. conditions single supply are: input signal referenced center common mode range converter. signal less than ±1.5V. "differential input" discussion effects this will have integrator swing without loss linearity. decoder. 2-gate clock circuit should CMOS gates maintain good power supply rejection. suitable circuit driving plasma-type display shown Figure high voltage anode driver buffer made Dionics. gates caps driving "BI" needed interdigit blanking multiple-digit display elements, omitted needed. 2.5k resistors current levels display. similar arrangement used with Nixie® tubes. popular displays interfaced outputs ICL7135 with suitable display drivers, such ICM7211A shown Figure standard CMOS 4030 QUAD gate used displaying digit, polarity, "overrange" flag. similar circuit used with ICL7212A driver ICM7235A vacuum fluorescent driver with appropriate arrangements made "extra" outputs. course, another full driver circuit could ganged shown required. This would useful additional annunciators were needed. Figure shows complete circuit 41/2 digit (±2.000V) A/D. Figure shows more complicated circuit driving displays. Here data latched into ICM7211 STROBE signal "Overrange" indicated blanking full digits.
Typical Applications
circuits which follow show some wide variety possibilities serve illustrate exceptional versatility this converter. Figure shows complete circuit 41/2 digit (±2.000V) full scale) with readout using ICL8069 1.2V temperature compensated voltage reference. uses band-gap principal achieve excellent stability noise reverse currents down 50A. circuit also shows typical input filter. Depending application, time-constant this filter made faster, slower, filter deleted completely. digit driven from segment decoder, with zero reading blanked connecting signal input
6.8k ICL8069 VREF 1.000V (NOTE VICL7135 STROBE DIG. CLOCK BUSY 4.7K
7447
ANALOG COMMON ANALOG 0.47F AZIN 100k 100k 100K SIGNAL INPUT INPUT 0.1F INPUT
NETWORK
0.45/RC
NOTE: finer resolution scale factor adjust, turn small series with fixed resistor. FIGURE 41/2 DIGIT CONVERTER WITH MULTIPLEXED COMMON ANODE DISPLAY
FN3093.4
ICL7135
VOLTAGE BUFFER
8880 PROG
This shift occurs during reference integrate phase conversion causing display reading just after overrange recovery. Both above circuits have considerable current flowing digital supply from drivers, etc. clock source using LM311 voltage comparator with positive feedback (Figure could minimize clock frequency shift problem. ICL7135 designed work from supplies. However, negative supply available, generated with ICL7660 capacitors (Figure 12).
0.02F
2.5K GATES 7409
0.02F
0.02F
0.02F
0.02F DGND
Interfacing with UARTs Microprocessors
Figure shows very simple interface between free-running ICL7135 UART. five STROBE pulses start transmission five data words. digit word 0000XXXX, digit 1000XXXX, digit 0100XXXX, etc. Also polarity transmitted indirectly using drive Even Parity Enable (EPE). receiver held low, parity flag receiver decoded positive signal, flag negative. complex arrangement shown Figure Here UART instruct begin measurement sequence word RRl. BUSY signal resets Data Ready Reset (DRR). Again STROBE starts transmit sequence. quad input multiplexer used superimpose polarity, over-range, under-range onto word since this instance known that correct operation important that UART clock fast enough that each word transmitted before next STROBE pulse arrives. Parity locked into UART load time does change this connection during output stream. Circuits interface ICL7135 directly with three popular microprocessors shown Figure Figure 8080/8048 MC6800 groups with 8-bit buses need have polarity, over-range under-range multiplexed onto Digit Sword UART circuit. each case microprocessor instruct when begin measurement when hold this measurement.
ICL7135
FIGURE ICL7135 PLASMA DISPLAY CIRCUIT
41/2 DIGIT DISPLAY
STROBE ICL7135 CD4071
CD4030
CD4081
CD4030
CD4011 ICM7211A
Application Notes
NOTE AN016 AN017 DESCRIPTION Selecting Converters Integrating Converter Do's Don'ts Applying Converters Cost Digital Panel Meter Designs Building Auto-Ranging Using 8052A/7103A Converter Pair Display Driver Family Combines Convenience with Microprocessor Interfaceability Basic Analog Digital Designers Overcoming Common Mode Range Issues When Using Intersil Integrating Converters
CD4030
AN018 AN023 AN028 AN054 AN9510 AN9609
FIGURE DISPLAY WITH DIGIT BLANKING OVERRANGE
problem sometimes encountered with both plasmatype display driving that clock source supply line variations. Since supply shared with display, variation voltage display reading cause clock supply voltage modulation. When overrange display alternates between blank display 0000 overrange indication.
FN3093.4
ICL7135
VOLTAGE
41/2 DIGIT DISPLAY V+5V
1412
SEGMENTS D1-D4
ANALOG 100k 0.47F 100k 100k INPUT 0.1F
ICL7135 ANALOG STROBE COMMON AZIN INPUT INPUT DIG. CLOCK BUSY
CD4054A
1110
BACKPLANE 120kC READINGS/SEC CLOCK ICM7211A 22-100pF 2,3,4 6-26 37-40 OPTIONAL CAPACITOR
300pF
FIGURE DRIVING DISPLAYS
390pF ICL7660
0.22F
LM311
VOUT
FIGURE LM311 CLOCK SOURCE
FIGURE GENERATING NEGATIVE SUPPLY FROM
FN3093.4
ICL7135
SERIAL OUTPUT RECEIVING UART UART IM6402/3 ICL7135 RUN/HOLD TBRL
IM6402/3
TBRL
74C157
SELECT
ENABLE
OVER
STROBE
ICL7135
STROBE RUN/HOLD BUSY 100pF
FIGURE ICL7135 UART INTERFACE
FIGURE COMPLEX ICL7135 UART INTERFACE
SELECT 74C157
74C157 MC680X MCS650X SELECT
80C48 8080 8085, ETC.
OVER ICL7135 MC6820
OVER ICL7135 8255 (MODE1) STBA
UNDER
RUN/ HOLD STROBE
RUN/ HOLD STROBE
FIGURE ICL7135 MC6800, MCS650X INTERFACED
FIGURE ICL7135 MCS-48, -80, INTERFACE
UNDER
UNDER
FN3093.4
ICL7135 Design Information Summary Sheet
CLOCK INPUT ICL7135 does have internal oscillator. requires external clock. fCLOCK (Typ) 120kHz CLOCK PERIOD tCLOCK 1/fCLOCK INTEGRATION PERIOD tINT 10,000 tCLOCK 60/50Hz REJECTION CRITERION tINT /t60Hz tINT /t50Hz Integer OPTIMUM INTEGRATION CURRENT IINT FULL-SCALE ANALOG INPUT VOLTAGE VlNFS (Typ) 200mV INTEGRATE RESISTOR
INFS
DISPLAY COUNT
COUNT
CONVERSION CYCLE tCYC tCL0CK 40002 when fCLOCK 120kHz, tCYC 333ms COMMON MODE INPUT VOLTAGE 0.5V) AUTO-ZERO CAPACITOR 0.01F REFERENCE CAPACITOR 0.1F CREF POWER SUPPLY: DUAL OUTPUT TYPE Nibbles with Polarity Overrange Bits There internal reference available ICL7135. external reference required ICL7135's 41/2 digit resolution.
INTEGRATE CAPACITOR
INTEGRATOR OUTPUT VOLTAGE SWING
VINT MAXIMUM SWING: 0.5) VINT 0.5V) VINT Typically 2.7V Typical Integrator Amplifier Output Waveform (INT Pin)
AUTO ZERO PHASE (COUNTS) 30001 10001
INTEGRATE PHASE FIXED 10000 COUNTS
DE-INTEGRATE PHASE 20001 COUNTS
TOTAL CONVERSION TIME 40002 tCLOCK
FN3093.4
ICL7135 Characteristics
DIMENSIONS: (120 mils mils) 525m ±25m METALLIZATION: Type: Thickness: PASSIVATION: Type: Nitride/Silox Sandwich Thickness: Nitride over Silox
Metallization Mask Layout
ICL7135
CAP+ CAP+ BUFF
ANALOG COMMON REFERENCE
(MSD)
(LSB) UNDERRANGE
(MSB)
OVERRANGE
STROBE
(LSD)D1 BUSY
CLOCK
DIGITAL
FN3093.4
ICL7135 Dual-In-Line Plastic Packages (PDIP)
INDEX AREA -B-AD BASE PLANE SEATING PLANE 0.010 (0.25) -CA2
E28.6 (JEDEC MS-011-AB ISSUE
LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580 MILLIMETERS 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES Rev. 12/00
NOTES: Controlling Dimensions: INCH. case conflict between English Metric dimensions, inch dimensions control. Dimensioning tolerancing ANSI Y14.5M-1982. Symbols defined Series Symbol List" Section Publication Dimensions measured with package seated JEDEC seating plane gauge GS-3. dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010 inch (0.25mm). measured with leads constrained perpendicular datum measured lead tips with leads unconstrained. must zero greater. maximum dimensions include dambar protrusions. Dambar protrusions shall exceed 0.010 inch (0.25mm). maximum number terminal positions. Corner leads E8.3, E16.3, E18.3, E28.3, E42.6 will have dimension 0.030 0.045 inch (0.76 1.14mm).
0.100 0.600 0.115 0.700 0.200
2.54 15.24 17.78 5.08 2.93
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FN3093.4
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