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HT82K95EE HT82K95AE


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HT82K95EE - HT82K95EE  
HT82K95AE - HT82K95AE  

HT82K95EE/HT82K95AE
Multimedia Keyboard Encoder 8-Bit
Tools Information FAQs Application Note
Features
Operating voltage: data memory data EEPROM ports support wake-up options HALT function wake-up feature reduce power
fSYS=6M/12MHz: 3.3V~5.5V
voltage reset function bidirectional lines (max.) 8-bit programmable timer/event counter with
consumption
8-level subroutine nesting 0.33ms instruction cycle with 12MHz system
overflow interrupt
16-bit programmable timer/event counter
overflow interrupts
Crystal oscillator (6MHz 12MHz) Watchdog Timer modes supported speed function endpoints supported (endpoint included) program memory
clock VDD=5V
manipulation instruction 15-bit table read instruction powerful instructions instructions machine cycles 28-pin package
General Description
This device 8-bit high performance RISC architecture microcontroller designed product applications. particularly suitable products such keyboards. HALT feature included reduce power consumption. mask version HT82K95A fully functionally compatible with version HT82K95E device. There dice HT82K95EE/HT82K95AE package: HT82K95E/HT82K95A MCU, other bits EEPROM used data memory purpose. dice wrie-bonded from HT82K95EE/HT82K95AE
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Block Diagram
ifte
Assignment
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Description
Name Code Option Description
PA0~PA5 PA6/TMR0 PA7/TMR1
Bidirectional 8-bit input/output port. Each configured wake-up input code option. input output mode controlled control register). Pull-high Pull-high resistor options: PA0~PA7 Wake-up CMOS/NMOS/PMOS CMOS/NMOS/PMOS options: PA0~PA7 Wake options: PA0~PA7 pin-shared with TMR0 TMR1 input, respectively. Pull-high Wake-up Bidirectional 8-bit input/output port. Software instructions determine CMOS output Schmitt trigger input with pull-high resistor (determined pull-high options). Wake-up options: PB0~PB7 Bidirectional lines. Software instructions determine CMOS output Schmitt trigger input with pull-high resistor (determined pull-high options). Wake-up options: PD0~PD7 Negative power supply, ground Bidirectional lines. Software instructions determine CMOS output Schmitt trigger input with pull-high resistor (determined pull-high options). Wake-up options: PC0~PC7 Schmitt trigger reset input. Active Positive power supply 3.3V regulator output USBD+ line function controlled software control register USBD- DATA line function controlled software control register OSC1, OSC2 connected 6MHz 12MHz Crystal/resonator (determined software instructions) internal system clock.
PB0~PB7
PD0~PD7
Pull-high Wake-up Pull-high Wake-up
PC0~PC7
V33O USBD+/CLK USBD-/DATA OSC1 OSC2
Absolute Maximum Ratings
Supply Voltage .VSS-0.3V VSS+6.0V Input Voltage.VSS-0.3V VDD+0.3V Total .150mA Total Power Dissipation .500mW Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability. Storage Temperature .-50°C 125°C Operating Temperature.0°C 70°C Total.-100mA
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
D.C. Characteristics
Symbol Parameter Test Conditions Conditions fSYS=6MHz fSYS=12MHz load, fSYS=6MHz load, fSYS=12MHz load, system HALT, suspend* load, system HALT, input/output mode, SUSPEND2 [1CH] VOL=3.4V VOL=0.4V VOL=0.4V VOH=3.4V VOH=3.4V IV33O=-5mA Min. 0.9VDD Typ. Max. Ta=25°C Unit
IDD1 IDD2 ISTB1
Operating Voltage Operating Current (6MHz Crystal) Operating Current (12MHz Crystal) Standby Current
ISTB2 VIL1 VIH1 VIL2 VIH2 IOL1 IOL2 IOL3 IOH1 IOH2 VLVR VV33O COSC1 COSC2
Standby Current (WDT Enabled) Input Voltage Ports Input High Voltage Ports Input Voltage (RES) Input High Voltage (RES) Port Sink Current PA1~PA7, Port Sink Current PA1~PA7, Port Sink Current Port Source Current PA1~PA7, Port Source Current Pull-high Resistance Voltage Reset 3.3V Regulator Output Build_in Capacitance OSC1 Build_in Capacitance OSC2
0.4VDD
Note: include 15kW loading USBD+, USBD- line host terminal.
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
A.C. Characteristics
Symbol fSYS fTIMER Parameter System Clock (Crystal OSC) Timer Frequency (TMR) Test Conditions Conditions Without prescaler Without prescaler Wake-up from HALT tSST System Start-up Timer Period Power-up, Watchdog Time-out from normal Min. Typ. Max. 1024 1024 1024 Ta=25°C Unit tSYS tSYS tWDTOSC Ta=25°C Remark Note Note After this period first clock pulse generated Only relevant repeated START condition Time which must free before transmission start Noise suppression time Standard Mode* Min. tHIGH tLOW tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tBUF Clock Frequency Clock High Time Clock Time Rise Time Fall Time START Condition Hold Time START Condition Setup Time Data Input Hold Time Data Input Setup Time STOP Condition Setup Time Output Valid from Clock Free Time Input Filter Time Constant (SDA Pins) Write Cycle Time 4000 4700 4000 4000 4000 4700 Max. 1000 3500 VCC=5V±10% Min. 1200 1200 Max. Unit
tWDTOSC Watchdog Oscillator tWDT1 tWDT2 tRES Watchdog Time-out Period (WDT OSC) Watchdog Time-out Period (System Clock) External Reset Pulse Width
tINT
Interrupt Pulse Width
EEPROM A.C. Characteristics Symbol Parameter
Note: These parameters periodically sampled 100% tested standard mode means VCC=2.2V 5.5V relative timing, refer timing diagrams
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Functional Description
Execution Flow system clock microcontroller derived from crystal. system clock internally divided into four non-overlapping clocks. instruction cycle consists four system clock cycles. Instruction fetching execution pipelined such that fetch takes instruction cycle while decoding execution takes next instruction cycle. However, pipelining scheme allows each instruction effectively executed cycle. instruction changes program counter, cycles required complete instruction. Program Counter program counter (PC) controls sequence which instructions stored program executed contents specify full range program memory. After accessing program memory word fetch instruction code, contents program counter incremented one. program counter then points memory word containing next instruction code. When executing jump instruction, conditional skip execution, loading register, subroutine call return from subroutine, initial reset, internal interrupt, external interrupt return from interrupts, manipulates program transfer loading address corresponding each instruction. conditional skip activated instructions. Once condition met, next instruction, fetched during current instruction execution, discarded dummy cycle replaces proper instruction. Otherwise proceed next instruction. lower byte program counter (PCL) readable writeable register (06H). Moving data into performs short jump. destination will within current program page. When control transfer takes place, additional dummy cycle required.
Execution Flow
Mode Initial reset interrupt Timer/Event Counter overflow Timer/Event Counter overflow Skip Loading Jump, call branch Return from subroutine
Program Counter
Program Counter+2
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 1.30 S11~S0: Stack register bits @7~@0: bits December 2008
HT82K95EE/HT82K95AE
Program Memory program memory used store program instructions which executed. also contains data, table, interrupt entries, organized into bits, addressed program counter table pointer. Certain locations program memory reserved special usage:
Location 000H Location 00CH
This location reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 00CH.
Table location
This area reserved program initialization. After chip reset, program always begins execution location 000H.
Location 004H
location program memory used look-up tables. There three method read data table read instructions: transfer contents lower-order byte specified data memory, higher-order byte TBLH (08H). three methods shown follows:
This area reserved interrupt service program. interrupt activated, interrupt enabled stack full, program begins execution location 004H.
Location 008H
instructions (the current page, page=256words), where table locations defined TBLP (07H) current page. code option TBHP disabled (default). instructions where table locations defined registers TBLP (07H) TBHP (01FH). code option TBHP enabled. instructions where table locations defined Registers TBLP (07H) last page (0F00H~0FFFH).
This area reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program begins execution location 008H.
itia
Program Memory
Only destination lower-order byte table well-defined, other bits table word transferred lower portion TBLH, remaining 1-bit words read Table Higher-order byte register (TBLH) read only. table pointer (TBLP, TBHP) read/write register (07H, 1FH), which indicates table location. Before accessing table, location must placed TBLP TBHP option TBHP disabled, value TBHP effect). TBLH read only cannot restored. main routine (Interrupt Service Routine) both employ table read instruction, contents TBLH main routine likely changed table read instruction used ISR. Errors occur. other words, using table read instruction main routine simultaneously should avoided. However, table read instruction applied both main routine ISR, interrupt should disabled prior table read instruction.
Instruction TABRDC TABRDL
Table Location
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits P11~P8: Current program counter bits when TBHP disabled TBHP register bit3~bit0 when TBHP enabled
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
will enabled until TBLH been backed table related instructions require cycles complete operation. These areas function normal program memory depending requirements. Once TBHP enabled, instruction reads data defined TBLP TBHP value. Otherwise, code option TBHP disabled, instruction reads data defined TBLP current program counter bits. Stack Register STACK This special part memory which used save contents program counter only. stack organized into levels neither part data part program space, neither readable writeable. activated level indexed stack pointer (SP) neither readable writeable. subroutine call interrupt acknowledge signal, contents program counter pushed onto stack. subroutine interrupt routine, signaled return instruction (RET RETI), program counter restored previous value from stack. After chip reset, will point stack. stack full non-masked interrupt takes place, interrupt request flag will recorded acknowledge signal will inhibited. When stack pointer decremented RETI), interrupt will serviced. This feature prevents stack overflow allowing programmer structure more easily. similar case, stack full subsequently executed, stack overflow occurs first entry will lost (only most recent return addresses stored). Data Memory Bank data memory designed with bits. data memory divided into functional groups: special function registers general purpose data memory Most read/write, some read only. special function registers include indirect addressing registers (R0;00H, R1;02H), Bank register (BP, 04H), Timer/Event Counter (TMR0;0DH), Timer/Event Counter control register (TMR0C;0EH), Timer/Event Counter higher order byte register (TMR1H;0FH), Timer/Event Counter lower order byte register (TMR1L;10H), Timer/Event Counter control register (TMR1C;11H), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H, TBHP;1FH), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register (INTC;0BH), Rev. 1.30
Bank Mapping Watchdog Timer option setting register (WDTS;09H), registers (PA;12H, PB;14H, PC;16H, PD;18H), control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H). USB/PS2 status control register (USC;1AH), endpoint interrupt status register (USR;1BH), system clock control register (SCC;1CH). remaining space before reserved future expansion usage reading these locations will general purpose data memory, addressed from BFH, used data control information under instruction commands. data memory areas handle arithmetic, logic, increment, decrement rotate operations directly. Except some dedicated bits, each data memory reset They also indirectly accessible through memory pointer registers (MP0 MP1). December 2008
HT82K95EE/HT82K95AE
Data Memory Bank special function registers used interface located bank order access Bank1 register, only Indirect addressing pointer used Bank register should mapping bank shown. Indirect Addressing Register Location indirect addressing registers that physically implemented. read/write operation [00H] ([02H]) will access data memory pointed (MP1). Reading location (02H) itself indirectly will return result 00H. Writing indirectly results operation. indirect addressing pointer (MP0) always point Bank0 addresses regardless value Bank Register (BP). indirect addressing pointer (MP1) access Bank0 Bank1 data according value which respectively. memory pointer registers (MP0 MP1) 8-bit registers.
Accumulator accumulator closely related operations. also mapped location data memory carry immediate data operations. data movement between data memory locations must pass through accumulator. Arithmetic Logic Unit This circuit performs 8-bit arithmetic logic operations. provides following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, XOR, CPL) Rotation (RL, RLC, RRC) Increment Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, SDZ)
only saves results data operation also changes status register. Status Register STATUS This 8-bit register (0AH) contains zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), watchdog time-out flag (TO). also records status information controls operation sequence. With exception flags, bits status register altered instructions like most other registers. data written into status register will change flag. addition operations related status register give different results from those intended. flag affected only system power-up, time-out executing instruction. flag affected only executing instruction during system power-up. flags generally reflect status latest operations. Function
Bank Mapping Label
operation results carry during addition operation borrow does take place during subtraction operation; otherwise cleared. also affected rotate through carry instruction. operation results carry nibbles addition borrow from high nibble into nibble subtraction; otherwise cleared. result arithmetic logic operation zero; otherwise cleared. operation results carry into highest-order carry highest-order bit, vice versa; otherwise cleared. cleared system power-up executing instruction. executing instruction. cleared system power-up executing instruction. time-out. Unused bit, read Status (0AH) Register
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
addition, entering interrupt sequence executing subroutine call, status register will pushed onto stack automatically. contents status important subroutine corrupt status register, precautions must taken save properly. Interrupt device provides external interrupt internal timer/event counter interrupts. Interrupt Control Register (INTC;0BH) contains interrupt control bits enable/disable interrupt request flags. Once interrupt subroutine serviced, other interrupts will blocked clearing bit). This scheme prevent further interrupt nesting. Other interrupt requests occur during this interval only interrupt request flag recorded. certain interrupt requires servicing within service routine, corresponding INTC allow interrupt nesting. stack full, interrupt request will acknowledged, even related interrupt enabled, until decremented. immediate service desired, stack must prevented from becoming full. these kinds interrupts have wake-up capability. interrupt serviced, control transfer occurs pushing program counter onto stack, followed branch subroutine specified location program memory. Only program counter pushed onto stack. contents register status register (STATUS) altered interrupt service program which corrupts desired control sequence, contents should saved advance. interrupts triggered following events related interrupt request flag (USBF; INTC) will set.
corresponding FIFO accessed from
When interrupt enabled, stack full external interrupt active, subroutine call location will occur. interrupt request flag (USBF) bits will cleared disable other interrupts. When Host access FIFO HT82K95E/ HT82K95A, corresponding request set, interrupt triggered. user easily decide which FIFO accessed. When interrupt been served, corresponding should cleared firmware. When HT82K95EE/HT82K95AE receives Suspend signal from Host suspend line (bit0 USC) HT82K95EE/HT82K95AE interrupt also triggered. Also when HT82K95EE/HT82K95AE receives Resume signal from Host resume line (bit3 USC) HT82K95EE/HT82K95AE interrupt triggered. Whenever reset signal detected, interrupt triggered. internal Timer/Event Counter interrupt initialized setting Timer/Event Counter interrupt request flag (T0F; INTC), caused timer overflow. When interrupt enabled, stack full set, subroutine call location will occur. related interrupt request flag (T0F) will reset cleared disable further interrupts. internal Timer/Even Counter interrupt initialized setting Timer/Event Counter interrupt request flag (T1F; INTC), caused timer overflow. When interrupt enabled, stack full set, subroutine call location will occur. related interrupt request flag (T1F) will reset cleared disable further interrupts. During execution interrupt subroutine, other interrupt acknowledge signals held until instruction executed related interrupt control stack full). return from interrupt subroutine, invoked. RETI will enable interrupt service, will not. Function
suspends signal from resumes signal from sends Reset signal
Label ET0I ET1I USBF
Controls master (global) interrupt enabled; disabled) Controls interrupt enabled; disabled) Controls Timer/Event Counter interrupt enabled; disabled) Controls Timer/Event Counter interrupt enabled; disabled) interrupt request flag active; inactive) Internal Timer/Event Counter request flag active; inactive) Internal Timer/Event Counter request flag active; inactive) Unused bit, read INTC (0BH) Register
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Interrupts, occurring interval between rising edges consecutive pulses, will serviced latter pulses, corresponding interrupts enabled. case simultaneous requests following table shows priority that applied. These masked resetting EMIbit. Interrupt Source interrupt Timer/Event Counter overflow Timer/Event Counter overflow Priority Vector crystal across OSC1 OSC2 needed provide feedback phase shift required oscillator. other external components required. stead crystal, resonator also connected between OSC1 OSC2 frequency reference, external capacitors OSC1 OSC2 required. oscillator free running on-chip oscillator, external components required. Even system enters power down mode, system clock stopped, oscillator still works within period approximately 31ms. oscillator disabled code option conserve power. Watchdog Timer clock source implemented dedicated oscillator (WDT oscillator), instruction clock (system clock divided determines code option. This timer designed prevent software malfunction sequence from jumping unknown location with unpredictable results. Watchdog Timer disabled code option. Watchdog Timer disabled, executions related result operation. Once internal oscillator oscillator, normally with period 31ms/5V) selected, first divided (8-stage) nominal time-out period 8ms/5V. This time-out period vary with temperatures, process variations. invoking prescaler, longer time-out periods realized. Writing data WS2, WS1, (bits WDTS) give different time-out periods. WS2, WS1, equal division ratio 1:128, maximum time-out period 1s/5V. oscillator disabled, clock still come from instruction clock operates same manner except that HALT state stop counting lose protecting purpose. this situation logic only restarted external logic. high nibble WDTS reserved defined flags, which only (WDTS.7~WDTS.3). device operates noisy environment, using on-chip 32kHz oscillator (WDT OSC) strongly recommended, since HALT will stop system clock.
Timer/Event Counter interrupt request flag (T0F/T1F), interrupt request flag (USBF), enable Timer/Event Counter interrupt (ET0I/ET1I), enable interrupt (EUI) enable master interrupt (EMI) constitute interrupt control register (INTC) which located data memory. EMI, EUI, used control enabling/disabling interrupts. These bits prevent requested interrupt from being serviced. Once interrupt request flags (TF, USBF) set, they will remain INTC register until interrupts serviced cleared software instruction. recommended that program does within interrupt subroutine. Interrupts often occur unpredictable manner need serviced immediately some applications. only stack left enabling interrupt well controlled, original control sequence will damaged once operates interrupt subroutine. Oscillator Configuration There oscillator circuits microcontroller.
illa
System Oscillator This oscillator designed system clocks. HALT mode stops system oscillator ignores external signal conserve power.
Watchdog Timer
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Division Ratio 1:16 1:32 1:64 1:128 cuting instruction. flag time-out occurs, causes wake-up that only resets Program Counter others remain their original status. ports wake-up interrupt methods considered continuation normal execution. Each Port independently selected wake device option. also selected wake device option. Upon awakening from port stimulus, program will resume execution next instruction. awakens from interrupt, sequence occur. related interrupt disabled interrupt enabled stack full, program will resume execution next instruction. interrupt enabled stack full, regular interrupt response takes place. interrupt request flag before entering HALT mode, wake-up function related interrupt will disabled. Once wake-up event occurs, takes 1024 tSYS (system clock period) resume normal operation. other words, dummy period will inserted after wake-up. wake-up results from interrupt acknowledge signal, actual interrupt subroutine execution will delayed more cycles. wake results next instruction execution, this will executed immediately after dummy period completed. minimize power consumption, pins should carefully managed before entering HALT status. Reset There three ways which reset occur:
reset during normal operation reset during HALT time-out reset during normal operation
WDTS (09H) Register overflow under normal operation will initialize status HALT mode, overflow will initialize only Program Counter reset zero. clear contents (including prescaler), three methods employed; external reset level RES), software instruction instruction. software instruction include other these types instruction, only active depending code option times selection selected (i.e. CLRWDT times equal one), execution instruction will clear WDT. case wherein chosen (i.e. CLRWDT times equal two), these instructions must executed clear WDT, otherwise, reset chip result time-out. Power Down Operation HALT HALT mode initialized instruction results following:
system oscillator will turned
oscillator remains running oscillator selected). contents on-chip registers remain unchanged.
prescaler will cleared
counted again clock from oscillator). ports maintain their original status.
flag flag cleared.
time-out during HALT different from other chip reset conditions, since perform that resets only Program Counter leaving other circuits their original state. Some registers remain unchanged during other reset conditions. Most registers reset when reset conditions met. examining flags, program distinguish between different RESET Conditions reset during power-up reset during normal operation wake-up HALT time-out during normal operation wake-up HALT
system leave HALT mode means external reset, interrupt, external falling edge signal ports overflow. external reset causes device initialization overflow performs After flags examined, cause chip reset determined. flag cleared system power-up executing instruction when exe-
Note: stands guarantee that system oscillator started stabilized, (System Start-up Timer) provides December 2008
Rev. 1.30
HT82K95EE/HT82K95AE
extra delay 1024 system clock pulses when system resets (power-up, time-out reset) when system awakes from HALT state. When system reset occurs, delay added during reset period. wake from HALT will enable delay.
Reset Configuration Reset Timing Chart
functional unit chip reset status shown below. Program Counter Interrupt Prescaler 000H Disable Clear Clear. After master reset, begins counting
Timer/event Counter Input/output Ports Reset Circuit Stack Pointer Input mode Points stack
status registers summarized following table. Reset (Power xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 00-0 1-000H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx -xxx xxxx xxxx -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 Time-out (Normal Operation) 0000 0000 00-0 1000 0000 0000 0000 0000 00-0 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 Reset (Normal Operation) 0000 0000 00-0 1000 0000 0000 0000 0000 00-0 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 Reset (HALT) 0000 0000 00-0 1000 0000 0000 0000 0000 00-0 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 Time-Out (HALT)* uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uu-u u-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu USB-Reset (Normal) uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 USB-Reset (HALT) uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 00-0 1-000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu -000 0000 1000 0111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111
Register TMR0 TMR0C TMR1H TMR1L TMR1C Program Counter TBLP TBLH STATUS INTC WDTS
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Reset (Power 0000 0110 0000 0000 0000 0000 0000 0110 0100 0000 0x00 0000 0000 0111 xxxx xxxx xxxx xxxx xxxx xxxx 11xx 0000 0000 0000 0000 0000 xxxx Time-out (Normal Operation) 0000 uuuu uuuu uuuu xxxx xxxx 0000 uuuu uxux xuuu uxuu uuuu 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuxx uuuu uuuu uuuu uuuu uuuu uuuu Reset (Normal Operation) 0000 0110 0000 0000 0000 0000 0000 0110 0100 0000 0x00 0000 0000 0111 uuuu uuuu uuuu uuuu uuuu uuuu 11xx 0000 0000 0000 0000 0000 uuuu Reset (HALT) 0000 0110 0000 0000 0000 0000 0000 0110 0100 0000 0x00 0000 0000 0111 uuuu uuuu uuuu uuuu uuuu uuuu 11xx 0000 0000 0000 0000 0000 uuuu Time-Out (HALT)* 0000 uuuu uuuu uuuu xxxx xxxx 0000 uuuu uxux xuuu uxuu uuuu 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuxx uuuu uuuu uuuu uuuu uuuu uuuu USB-Reset (Normal) 0000 0110 0000 0000 0000 0000 0000 0110 0100 0000 0x00 0000 0000 0111 0000 0000 0000 0000 0000 0000 uu00 0u00 u1uu 0000 0uu0 u000 uuuu USB-Reset (HALT) 0000 0110 0000 0000 0000 0000 0000 0110 0100 0000 0x00 0000 0000 0111 0000 0000 0000 0000 0000 0000 uu00 0u00 u1uu 0000 0uu0 u000 uuuu
Register PIPE_CTRL PIPE STALL SIES MISC Endpt_EN FIFO0 FIFO1 FIFO2 TBHP
Note: stands stands stands Timer/Event Counter timer/event counters (TMR0, TMR1) implemented microcontroller. Timer/Event Counter contains 8-bit programmable count-up counter clock comes from external source from fSYS/4. 0~2, Label T0ON Unused bit, read define TMR0 active edge Timer/Event Counter (0=active high; 1=active high low) enable/disable timer counting (0=disabled; 1=enabled) define operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR0C (0EH) Register 0~2, Label T1ON Unused bit, read define TMR1 active edge Timer/Event Counter (0=active high; 1=active high low) enable/disable timer counting (0=disabled; 1=enabled) define operating mode 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMR1C (11H) Register Function Timer/Event Counter contains 16-bit programmable count-up counter clock come from external source from system clock divided
Function
T0M0 T0M1
T1M0 T1M1
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Timer/Event Counter
Timer/Event Counter Using internal clock source, there only reference time-base Timer/Event Counter internal clock source coming from fSYS/4. external clock input allows user count external events, measure time intervals pulse widths. Using internal clock source, there only reference time-base Timer/Event Counter internal clock source coming from fSYS/4. external clock input allows user count external events, measure time intervals pulse widths. There registers related Timer/Event Counter TMR0 ([0DH]), TMR0C ([0EH]). physical registers mapped TMR0 location; writing TMR0 makes starting value placed Timer/Event Counter preload register reading TMR0 gets contents Timer/Event Counter TMR0C timer/event counter control register, which defines some options. There registers related Timer/Event Counter TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing TMR1L will only written data internal lower-order byte buffer bits) writing TMR1H will transfer specified data contents lower-order byte buffer TMR1H TMR1L preload registers, respectively. Timer/Event Counter preload register changed each writing TMR1H operations. Reading TMR1H will latch contents TMR1H TMR1L counters destination lower-order byte buffer, respectively. Reading TMR1L will read contents lower-order byte buffer. TMR1C Timer/Event Counter control register, which defines operating mode, counting enable disable active edge. T0M0/T0M1, T1M0/T1M1 bits define operating mode. event count mode used count external events, which means clock source comes from external (TMR0/TMR1) pin. timer mode functions normal timer with clock source coming from fSYS/4 (Timer0/Timer1). pulse width measurement mode used count high level duration external signal (TMR0/TMR1). counting based fSYS/4 (Timer0/Timer1). event count timer mode, once Timer/Event Counter starts counting, will count from current contents Timer/Event Counter FFFFH. Once overflow occurs, counter reloaded from Timer/Event Counter preload register generates interrupt request flag (T0F/T1F; INTC) same time. pulse width measurement mode with T0ON/T1ON bits equal one, once TMR0/TMR1 received transient from high high T0E/T1E bits will start counting until TMR0/TMR1 returns original level resets T0ON/T1ON. measured result will remain Timer/Event Counter even activated transient occurs again. other words, only cycle measurement done. Until setting T0ON/T1ON, cycle measurement will function again long receives further transient pulse. Note that, this operating mode, Timer/Event Counter starts counting according logic level according transient edges. case counter overflows, counter reloaded from Timer/Event Counter preload register issues interrupt request just like other modes. enable counting operation, timer (T0ON/T1ON; TMR0C/TMR1C) should December 2008
Rev. 1.30
HT82K95EE/HT82K95AE
pulse width measurement mode, T0ON/T1ON will cleared automatically after measurement cycle completed. other modes T0ON/T1ON only reset instructions. overflow Timer/Event Counter wake-up sources. matter what operation mode writing ET0I/ET1I disable corresponding interrupt services. case Timer/Event Counter condition, writing data Timer/Event Counter preload register will also reload that data Timer/Event Counter 0/1. Timer/Event Counter turned data written will only kept Timer/Event Counter preload register. Timer/Event Counter will still operate until overflow occurs Timer/Event Counter reloading will occur same time). When Timer/Event Counter (reading TMR0/TMR1) read, clock will blocked avoid errors. clock blocking results counting error, this must taken into consideration programmer. Input/Output Ports There bidirectional input/output lines microcontroller, labeled from which mapped data memory [12H], [14H], [16H] [18H] respectively. these ports used input output operations. input operation, these ports non-latching, that inputs must ready rising edge instruction (m=12H, 14H, 18H). output operation, data latched remains unchanged until output latch rewritten. Each line control register (PAC, PBC, PCC, PDC) control input/output configuration. With this control register, CMOS/NMOS/PMOS output Schmitt trigger input with without pull-high resistor structures reconfigured dynamically under software control. function input, corresponding latch control register must write input source also depends control register. control register input will read state. control register contents latches will move internal bus. latter possible instruction. output function, CMOS/NMOS/PMOS configurations selected (NMOS PMOS available only). These control registers mapped locations 13H, 15H, 19H. After chip reset, these input/output lines remain high levels floating state (depending pull-high options). Each these input/output latches cleared (m=12H, 14H, 18H) instructions. Some instructions first input data then follow output operations. example, read entire port states into CPU, execute defined operations (bit-operation), then write results back latches accumulator. Each line ports have capability waking device. There pull-high only) options available lines. Once pull-high option line selected, line have pull-high resistor. Otherwise, pull-high resistor absent. should noted that non-pull-high line operating input mode will cause floating state. recommended that unused bonded lines should output pins software instruction avoid consuming power under input floating state.
Input/Output Ports
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Voltage Reset microcontroller contains voltage reset circuit order monitor supply voltage device. supply voltage device drops within range 0.9V~VLVR such might occur when changing battery, will automatically reset device internally. includes following specifications:
valid signal, voltage i.e. voltage
Data EEPROM Functional Description
Serial clock (SCL)
input used positive edge clock data into each EEPROM device negative edge clock data each device.
Serial data (SDA)
range between 0.9V~VLVR must exist greater than 1ms. voltage state does exceed 1ms, will ignore perform reset function.
uses function with external
bidirectional serial data transfer. open-drain driven wired-OR with number other open-drain open collector devices. Memory Organization
Serial EEPROM
signal perform chip reset. relationship between VLVR shown below.
Internally organized with 8-bit words, requires 8-bit data word address random word addressing. Device Operations
Clock data transition
Data transfer initiated only when busy. During data transfer, data line must remain stable whenever clock line high. Changes data line while clock line high will interpreted START STOP condition.
Start condition
Note: VOPR voltage range proper chip operation 4MHz system clock.
high-to-low transition with high start condition which must precede other command (refer Start Stop Definition Timing diagram).
Stop condition
low-to-high transition with high stop condition. After read sequence, stop command will place EEPROM standby power mode (refer Start Stop Definition Timing Diagram).
Voltage Reset Note: make sure that system oscillator stabilized, provides extra delay 1024 system clock pulses before entering normal operation. Since voltage maintained over original state, therefore delay before entering reset mode Rev. 1.30 December 2008
HT82K95EE/HT82K95AE
Acknowledge
addresses data words serially transmitted from EEPROM 8-bit words. EEPROM sends zero acknowledge that received each word. This happens during ninth clock cycle.
vice, such microcontroller, must terminate write sequence with stop condition. this time EEPROM enters internally-timed write cycle non-volatile memory. inputs disabled during this write cycle EEPROM will respond until write completed (refer Byte write timing).
Acknowledge polling
itio
itio
maximise throughput, technique allow master poll acknowledge signal after start condition control byte write command have been sent. device still busy implementing write cycle, then will returned. master send next read/write command when signal finally been received.
Device Addressing EEPROM devices require 8-bit device address word following start condition enable chip read write operation. device address word consist mandatory one, zero sequence first four most significant bits (refer diagram showing Device Address). This common EEPROM device. next three bits fixed device address read/write operation select bit. read operation initiated this high write operation initiated this low. comparison device address succeed EEPROM will output zero bit. not, chip will return standby state.
itio itia
Acknowledge Polling Flow
Read operations
Write Operations
Byte write
write operation requires 8-bit data word address following device address word acknowledgment. Upon receipt this address, EEPROM will again respond with zero then clock first 8-bit data word. After receiving 8-bit data word, EEPROM will output zero addressing
data EEPROM supports three read operations, namely, current address read, random address read sequential read. During read operation execution, read/write select should
Current address read
internal data word address counter maintains last address accessed during last read write operation, incremented one. This address stays valid
Byte Write Timing
Current Read Timing
Rev. 1.30
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HT82K95EE/HT82K95AE
between operations long chip power maintained. address roll over during read from last byte last memory page first byte first page. address roll over during write from last byte current page first byte same page. Once device address with read/write select clocked acknowledged EEPROM, current address data word serially clocked out. microcontroller should respond (High) signal following stop condition (refer Current read timing).
Random read
read/write select high. EEPROM acknowledges device address serially clocks data word. microcontroller should respond with signal (high) followed stop condition. (refer Random read timing).
Sequential read
random read requires dummy byte write sequence load data word address which then clocked acknowledged EEPROM. microcontroller must then generate another start condition. microcontroller initiates current address read sending device address with
Sequential reads initiated either current address read random address read. After microcontroller receives data word, responds with acknowledgment. long EEPROM receives acknowledgment, will continue increment data word address serially clock sequential data words. When memory address limit reached, data word address will roll over sequential read continues. sequential read operation terminated when microcontroller responds with signal (high) followed stop condition.
Random Read Timing
Sequential Read Timing
Data EEPROM Timing Diagrams
itio
itio
Note: write cycle time time from valid stop condition write sequence valid start condition sequential command.
Rev. 1.30
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HT82K95EE/HT82K95AE
Suspend Wake-Up Remote Wake-Up there signal over 3ms, HT82K95EE/HT82K95AE will into suspend mode. Suspend line (bit USC) will interrupt triggered indicate that HT82K95EE/HT82K95AE should jump suspend state meet 500mA suspend current spec. order meet 500mA suspend current, firmware should disable clock clearing USBCKEN (bit3 SCC) suspend current 400mA. User further decrease suspend current 250mA setting SUSP2 (bit4 SCC). mode this must disable When resume signal sent host, HT82K95EE/HT82K95AE will wake interrupt Resume line (bit USC) set. order make HT82K95EE/HT82K95AE function properly, firmware must USBCKEN (bit SCC) clear SUSP2 (bit4 SCC). Since Resume signal will cleared before Idle signal sent host, Suspend line (bit USC) will when detecting Suspend line (bit0 USC), Resume line should remembered taken into consideration. After finishing resume signal, suspend line will inactive interrupt triggered. following timing diagram.
Configure HT82K95EE/HT82K95AE Device HT82K95EE/HT82K95AE configured interface interface device, configuring SPS2 (bit USR) SUSB (bit USR). SPS2=1, SUSB=0, HT82K95EE/HT82K95AE configured interface, USBD- configured Data USBD+ configured pin. User easily read write Data accessing corresponding PS2DAI (bit USC), PS2CKI (bit USC), PS2DAO (bit USC) S2CKO (bit USC) respectively. User should make sure that order read data properly, corresponding output must example, desired read Data reading PS2DAI, PS2DAO should Otherwise always read SPS2=0, SUSB=1, HT82K95EE/HT82K95AE configured interface. Both USBD- USBD+ driven HT82K95E/ HT82K95A. User only write read data through corresponding FIFO. Both SPS2 SUSB default Interface There registers, including PIPE_CTRL (41H bank (address remote wake-up bank STALL (43H bank PIPE (44H bank SIES (45H bank MISC (46H bank Endpt_EN (47H bank FIFO0 (48H bank FIFO1 (49H bank FIFO2 (4AH bank used function. register contains current address remote wake function control bit. initial value address value extracted from command loaded into this register until SETUP stage completed. Label WKEN AD6~AD0 Function Remote wake-up enable/disable device address
device with remote wake function wake Host sending wake-up pulse through RMWK (bit USC). Once Host receives wake-up signal from HT82K95EE/HT82K95AE, will send Resume signal device. timing follows:
(42H) Register STALL PIPE, PIPE_CTRL, Endpt_EN Registers PIPE register represents whether endpoint corresponding accessed host not. After ACT_EN signal being sent out, check which endpoint been accessed. This register only after time when host access corresponding endpoint. STALL register shows whether endpoint corresponding works not. soon endpoint work improperly, corresponding must set.
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HT82K95EE/HT82K95AE
PIPE_CTRL Register used configuring (Bit=1) (Bit=0)Pipe. default define pipe. Where Bit0 (DATA0) PIPE_CTRL Register used setting data toggle endpoint (except endpoint0) using data toggles value DATA0. Once user want endpoint (except endpoint0) using data toggles value DATA0. user output pulse this bit. pulse period must least instruction cycle. Endpt_EN Register used enable disable corresponding endpoint (except endpoint Enable Endpoint (Bit=1) disable Endpoint (Bit=0)
bitmaps list follows: Register Name PIPE_CTRL STALL PIPE Endpt_EN Register Address 01000001B 01000011B 01000100B 01000001B Bit7~Bit3 Reserved Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Pipe Default Value 00000110 00000110 00000000 00000111
PIPE_CTRL (41H), STALL (43H), PIPE (44H) Endpt_EN (47H) Registers SIES Register used indicate present signal state which receives also defines whether change device address automatically. Function F0_ERR Adr_set Read/Write SIES (45H) Register Table Func. Name Description This used configure automatically change device address with value Address+Remote_WakeUp Register (42H). When this F/W, will update device address with value Address+Remote_WakeUp Register (42H) after Host successfully read data from device operation. will clear after updating device address. Otherwise, when this cleared will update device address immediately after address written Address+Remote_WakeUp Register (42H) Default This used indicate that some errors have occurred when accessing FIFO0. This cleared F/W. Default Unused bit, read This used control whether interrupt output response Host token. Only Endpoint0 only interrupt, data transmitted host data received from Host always interrupt accesses FIFO0 Default SIES Function Table 01000001B Register Address
Adr_
F0_Err
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HT82K95EE/HT82K95AE
MISC register combines command status control desired endpoint FIFO action show status desired endpoint FIFO. MISC will cleared reset signal. Label Function After setting other status desired MISC, endpoint FIFO requested setting this After been done, this cleared This defines direction data transferring between endpoint FIFO. When this means that wants write data endpoint FIFO. After been done, this cleared before terminating request represent transferring. reading action, this cleared represent that wants read data from endpoint FIFO after done. Clear requested endpoint FIFO, even endpoint FIFO ready. Defines which endpoint FIFO selected, SELP1,SELP0: endpoint FIFO0 endpoint FIFO1 endpoint FIFO2 reserved Used show that data endpoint FIFO SETUP command. This cleared firmware. That say, even busy, device will miss SETUP commands from host. Read only status bit, this used indicate that desired endpoint FIFO ready work. Used indicate that 0-sized packet sent from host MCU. This should cleared firmware. MISC (46H) Register communicate with endpoint FIFO setting corresponding registers, which address listed following table. After reading current data, next data will show after 2ms, used check endpoint FIFO status response MISC register, read/write action still going Registers FIFO0 FIFO1 FIFO2 Bank Address Bit7~Bit0 Data7~Data0 Data7~Data0 Data7~Data0
CLEAR
SELP1 SELP0
SCMD
READY LEN0
There some timing constrains usages illustrated here. setting MISC register, perform reading, writing clearing actions. There some examples shown following table endpoint FIFO reading, writing clearing. Actions Read FIFO0 sequence Write FIFO1 sequence Check whether FIFO0 read Check whether FIFO1 written Read 0-sized packet sequence form FIFO0 Write 0-sized packet sequence FIFO1 MISC Setting Flow Status 00H®01H®delay 2ms, check 41H®read* from FIFO0 register check ready (01H)®03H®02H 0AH®0BH®delay 2ms, check 4BH®write* FIFO1 register check ready (0BH)®09H®08H 00H®01H®delay 2ms, check (ready) (not ready)®00H 0AH®0BH®delay 2ms, check (ready) (not ready)®0AH 00H®01H®delay 2ms, check 81H®read once (01H)®03H®02H 0AH®0BH®delay 2ms, check 0BH®0FH®0DH®08H
Note: There existing between reading action between writing action
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
definitions USB/PS2 status control register (USC; 1AH) shown. Label SUSP Function Read only, suspend indication. When this (set SIE), indicates enters suspend mode. interrupt also triggered changes this bit. remote wake command. force host leaving suspend mode. When this delay clearing this needed insure RMWK command accepted SIE. reset indication. This set/cleared SIE. This used detect which (PS2 USB) attached. When URST this indicates that reset occurred (the attached USB) interrupt will initialized. resume indication. When leaves suspend mode, this (set SIE). This will appear 20ms waiting detect. When RESUME SIE, interrupt will generated wake-up MCU. order detect suspend state, should USBCKEN clear SUSP2 register) enable detecting function. RESUME will cleared while SUSP going When detecting SUSP, RESUME (wakes-up should remembered taken into consideration. Read only, USBD-/DATA input Read only, USBD+/CLK input Data driving USBD-/DATA when working under mouse function. Data driving USBD+/CLK when working under mouse function. (1AH) Register (USB endpoint interrupt status register) register used indicate which endpoint accessed select serial (PS2 USB). endpoint request flags (EP0IF, EP1IF EP2IF) used indicate which endpoints accessed. endpoint accessed, related endpoint request flag will interrupt will occur interrupt enabled stack full). When active endpoint request flag served, endpoint request flag cleared Label EP0IF Function When this (set SIE), indicates endpoint accessed interrupt will occur. When interrupt been served, this should cleared firmware. When this (set SIE), indicates endpoint accessed interrupt will occur. When interrupt been served, this should cleared firmware. When this (set SIE), indicates endpoint accessed interrupt will occur. When interrupt been served, this should cleared firmware. Reserved function selected when this function selected when this This flag used show mode. (Bit=1) This will cleared after power-on reset. (1BH) Register
RMWK
URST
RESUME
PS2DAI PS2CKI PS2DAO PS2CKO
EP1IF
EP2IF SPS2 SUSB USB_flag
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December 2008
HT82K95EE/HT82K95AE
There system clock control register implemented select clock used MCU. This register consists clock control (USBCKEN), second suspend mode control (SUSP2) system clock selection (SYSCLK). 2~0, Label Undefined, should cleared clock control bit. When this indicates that clock enabled. Otherwise, clock turned-off. This used reduce power consumption suspend mode. normal mode this must cleared zero (Default=0). HALT mode this should high reduce power consumption. mode this must disable This flag used show under mode. (Bit=1) This will cleared after power-on reset. This used specify system oscillator frequency used MCU. 6MHz crystal oscillator resonator used, this should 12MHz crystal oscillator resonator used, this should cleared (default). (1CH) Register Table High Byte Pointer Current Table Read TBHP (Address 0X1F) Register TBHP (0X1F) Options following table shows kinds option microcontroller. options must defined ensure proper system functioning. Chip lock bit) PA0~PA7 pull-high resistor enabled disabled bit) PB0~PB7 pull-high resistor enabled disabled nibble) PC0~PC7 pull-high resistor enabled disabled nibble) PD0~PD7 pull-high resistor enabled disabled nibble) enable disable enable disable clock source: fSYS/4 WDTOSC instruction(s): PA0~PA7 output structures: CMOS/NMOS open-drain/PMOS open-drain bit) PA0~PA7 wake-up enabled disabled bit) PB0~PB7 wake-up enabled disabled nibble) PC0~PC7 wake-up enabled disabled nibble) PD0~PD7 wake-up enabled disabled nibble) TBHP enable disable (default disable) Option Bits Labels PGC3~PGC0 Read/Write Option Functions Store current table read bit11~bit8 data Function
USBCKEN
SUSP2
PS2_flag
SYSCLK
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December 2008
HT82K95EE/HT82K95AE
Application Circuits
Crystal Ceramic Resonator Multiple Applications HT82K95EE
Note: resistance capacitance reset circuit should designed such ensure that stable remains within valid operating voltage range before bringing high. 6MHz 12MHz, close OSC1 OSC2 possible. Components with used issue. Components with used resonator only necessary. Components with used 12MHz application.
Crystal Ceramic Resonator Multiple Applications HT82K95AE
Note: 6MHz 12MHz, close OSC1 OSC2 possible. Components with used resonator only necessary.
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Instruction
Introduction Central successful operation microcontroller instruction set, which program instruction codes that directs microcontroller perform certain operations. case Holtek microcontrollers, comprehensive flexible over instructions provided enable programmers implement their application with minimum programming overheads. easier understanding various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions implemented within instruction cycle. exceptions this branch, call, table read instructions where instruction cycles required. instruction cycle equal system clock cycles, therefore case 8MHz system oscillator, most instructions would implemented within 0.5ms branch call instructions would implemented within 1ms. Although instructions which require more cycle implement generally limited JMP, CALL, RET, RETI table read instructions, important realize that other instructions which involve manipulation Program Counter register will also take more cycle implement. instructions which change contents will imply direct jump that address, more cycle will required. Examples such instructions would PCL, case skip instructions, must noted that result comparison involves skip operation then this will also take more cycle, skip involved then only cycle required. Moving Transferring Data transfer data within microcontroller program most frequently used operations. Making three kinds instructions, data transferred from registers Accumulator vice-versa well being able move specific immediate data directly into Accumulator. most important data transfer applications receive data from input ports transfer data output ports. Arithmetic Operations ability perform certain arithmetic operations data manipulation necessary feature most microcontroller applications. Within Holtek microcontroller instruction range subtract instruction mnemonics enable necessary arithmetic carried out. Care must taken ensure correct handling carry borrow data when results exceed addition less than subtraction. increment decrement instructions INC, INCA, DECA provide simple means increasing decreasing value values destination specified. Logical Rotate Operations standard logical operations such AND, have their instruction within Holtek microcontroller instruction set. with case most instructions involving data manipulation, data must pass through Accumulator which involve additional programming steps. logical data operations, zero flag result operation zero. Another form logical data manipulation comes from rotate instructions such which provide simple means rotating right left. Different rotate instructions exist depending program requirements. Rotate instructions useful serial port programming applications where data rotated from internal register into Carry from where examined necessary serial high low. Another application where rotate data operations used implement multiplication division calculations. Branches Control Transfer Program branching takes form either jumps specified locations using instruction subroutine using CALL instruction. They differ sense that case subroutine call, program must return instruction immediately when subroutine been carried out. This done placing return instruction subroutine which will cause program jump back address right after CALL instruction. case instruction, program simply jumps desired location. There requirement jump back original jumping point case CALL instruction. special extremely useful branch instructions conditional branches. Here decision first made regarding condition certain data memory individual bits. Depending upon conditions, program will continue with next instruction skip over jump following instruction. These instructions decision making branching within program perhaps determined condition certain input switches condition internal data bits.
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HT82K95EE/HT82K95AE
Operations ability provide single operations Data Memory extremely flexible feature Holtek microcontrollers. This feature especially useful output port programming where individual bits port pins directly high using either instructions respectively. feature removes need programmers first read 8-bit output port, manipulate input data ensure that other bits changed then output port with correct data. This read-modify-write process taken care automatically when these operation instructions used. Table Read Operations Data storage normally implemented using registers. However, when working with large amounts fixed data, volume involved often makes inconvenient store fixed data Data Memory. overcome this problem, Holtek microcontrollers allow area Program Memory setup table where data directly stored. easy instructions provides means which this fixed data referenced retrieved from Program Memory. Other Operations addition above functional instructions, range other instructions also exist such instruction Power-down operations instructions control operation Watchdog Timer reliable program operations under extreme electric electromagnetic environments. their relevant operations, refer functional related sections. Instruction Summary following table depicts summary instruction categorised according function consulted basic instruction reference using following listed conventions. Table conventions: Bits immediate data Data Memory address Accumulator number bits addr: Program memory address
Mnemonic Arithmetic A,[m] ADDM A,[m] A,[m] ADCM A,[m] A,[m] SUBM A,[m] A,[m] SBCM A,[m] A,[m] A,[m] A,[m] ANDM A,[m] A,[m] XORM A,[m] CPLA INCA DECA
Description
Cycles
Flag Affected
Data Memory Data Memory immediate data Data Memory with Carry Data memory with Carry Subtract immediate data from Subtract Data Memory from Subtract Data Memory from with result Data Memory Subtract Data Memory from with Carry Subtract Data Memory from with Carry, result Data Memory Decimal adjust Addition with result Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical Data Memory Logical immediate Data Logical immediate Data Logical immediate Data Complement Data Memory Complement Data Memory with result Increment Data Memory with result Increment Data Memory Decrement Data Memory with result Decrement Data Memory
1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note
Logic Operation
Increment Decrement
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HT82K95EE/HT82K95AE
Mnemonic Rotate RRCA RLCA Data Move A,[m] [m],A Operation [m].i [m].i Branch addr [m].i [m].i SIZA SDZA CALL addr RETI Table Read TABRDC TABRDL Miscellaneous WDT1 WDT2 SWAP SWAPA HALT operation Clear Data Memory Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles Data Memory Swap nibbles Data Memory with result Enter power down mode 1Note 1Note 1Note None None None None None Read table (current page) TBLH Data Memory Read table (last page) TBLH Data Memory 2Note 2Note None None Jump unconditionally Skip Data Memory zero Skip Data Memory zero with data movement Skip Data Memory zero Skip Data Memory zero Skip increment Data Memory zero Skip decrement Data Memory zero Skip increment Data Memory zero with result Skip decrement Data Memory zero with result Subroutine call Return from subroutine Return from subroutine load immediate data Return from interrupt 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note None None None None None None None None None None None None None Clear Data Memory Data Memory 1Note 1Note None None Move Data Memory Move Data Memory Move immediate data 1Note None None None Rotate Data Memory right with result Rotate Data Memory right Rotate Data Memory right through Carry with result Rotate Data Memory right through Carry Rotate Data Memory left with result Rotate Data Memory left Rotate Data Memory left through Carry with result Rotate Data Memory left through Carry 1Note 1Note 1Note 1Note None None None None Description Cycles Flag Affected
Note: skip instructions, result comparison involves skip then cycles required, skip takes place only cycle required. instruction which changes contents will also require cycles execution. instructions flags affected execution status. flags cleared after both instructions consecutively executed. Otherwise flags remain unchanged.
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HT82K95EE/HT82K95AE
Instruction Definition
A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) Data Memory with Carry contents specified Data Memory, Accumulator carry flag added. result stored Accumulator. Data Memory with Carry contents specified Data Memory, Accumulator carry flag added. result stored specified Data Memory. Data Memory contents specified Data Memory Accumulator added. result stored Accumulator. immediate data contents Accumulator specified immediate data added. result stored Accumulator. Data Memory contents specified Data Memory Accumulator added. result stored specified Data Memory. Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator. Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory.
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HT82K95EE/HT82K95AE
CALL addr Description Subroutine call Unconditionally calls subroutine specified address. Program Counter then increments obtain address next instruction which then pushed onto stack. specified address then loaded program continues execution from this address. this instruction requires additional operation, cycle instruction. Stack Program Counter Program Counter addr None Clear Data Memory Each specified Data Memory cleared None Clear Data Memory specified Data Memory cleared [m].i None Clear Watchdog Timer flags cleared. cleared Pre-clear Watchdog Timer flags cleared. Note that this instruction works conjunction with WDT2 must executed alternately with WDT2 have effect. Repetitively executing this instruction without alternately executing WDT2 will have effect. cleared Pre-clear Watchdog Timer flags cleared. Note that this instruction works conjunction with WDT1 must executed alternately with WDT1 have effect. Repetitively executing this instruction without alternately executing WDT1 will have effect. cleared
Operation Affected flag(s) Description Operation Affected flag(s) [m].i Description Operation Affected flag(s) Description Operation
Affected flag(s) WDT1 Description
Operation
Affected flag(s) WDT2 Description
Operation
Affected flag(s)
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HT82K95EE/HT82K95AE
Description Operation Affected flag(s) CPLA Description Complement Data Memory Each specified Data Memory logically complemented complement). Bits which previously contained changed vice versa. Complement Data Memory with result Each specified Data Memory logically complemented complement). Bits which previously contained changed vice versa. complemented result stored Accumulator contents Data Memory remain unchanged. Decimal-Adjust addition with result Data Memory Convert contents Accumulator value Binary Coded Decimal) value resulting from previous addition variables. nibble greater than flag set, then value will added nibble. Otherwise nibble remains unchanged. high nibble greater than flag set, then value will added high nibble. Essentially, decimal conversion performed adding 00H, 06H, depending Accumulator flag conditions. Only flag affected this instruction which indicates that original greater than 100, allows multiple precision decimal addition. Decrement Data Memory Data specified Data Memory decremented Decrement Data Memory with result Data specified Data Memory decremented result stored Accumulator. contents Data Memory remain unchanged. Enter power down mode This instruction stops program execution turns system clock. contents Data Memory registers retained. prescaler cleared. power down flag time-out flag cleared.
Operation Affected flag(s) Description
Operation
Affected flag(s) Description Operation Affected flag(s) DECA Description Operation Affected flag(s) HALT Description
Operation Affected flag(s)
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Description Operation Affected flag(s) INCA Description Operation Affected flag(s) addr Description Increment Data Memory Data specified Data Memory incremented Increment Data Memory with result Data specified Data Memory incremented result stored Accumulator. contents Data Memory remain unchanged. Jump unconditionally contents Program Counter replaced with specified address. Program execution then continues from this address. this requires insertion dummy instruction while address loaded, cycle instruction. Program Counter addr None Move Data Memory contents specified Data Memory copied Accumulator. None Move immediate data immediate data specified loaded into Accumulator. None Move Data Memory contents Accumulator copied specified Data Memory. None operation operation performed. Execution continues with next instruction. operation None Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator.
Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) [m],A Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s)
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HT82K95EE/HT82K95AE
Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Description Operation Affected flag(s) RETI Description Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. Return from subroutine Program Counter restored from stack. Program execution continues restored address. Program Counter Stack None Return from subroutine load immediate data Program Counter restored from stack Accumulator loaded with specified immediate data. Program execution continues restored address. Program Counter Stack None Return from interrupt Program Counter restored from stack interrupts re-enabled setting bit. master interrupt global enable bit. interrupt pending when RETI instruction executed, pending Interrupt routine will processed before returning main program. Program Counter Stack None Rotate Data Memory left contents specified Data Memory rotated left with rotated into [m].(i+1) [m].i; 0~6) [m].0 [m].7 None Rotate Data Memory left with result contents specified Data Memory rotated left with rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.(i+1) [m].i; 0~6) ACC.0 [m].7 None
Operation Affected flag(s) Description Operation Affected flag(s) Description
Operation Affected flag(s)
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December 2008
HT82K95EE/HT82K95AE
Description Operation Rotate Data Memory left through Carry contents specified Data Memory carry flag rotated left bit. replaces Carry original carry flag rotated into [m].(i+1) [m].i; 0~6) [m].0 [m].7 Rotate Data Memory left through Carry with result Data specified Data Memory carry flag rotated left bit. replaces Carry original carry flag rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.(i+1) [m].i; 0~6) ACC.0 [m].7 Rotate Data Memory right contents specified Data Memory rotated right with rotated into [m].i [m].(i+1); 0~6) [m].7 [m].0 None Rotate Data Memory right with result Data specified Data Memory carry flag rotated right with rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.i [m].(i+1); 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry contents specified Data Memory carry flag rotated right bit. replaces Carry original carry flag rotated into [m].i [m].(i+1); 0~6) [m].7 [m].0 Rotate Data Memory right through Carry with result Data specified Data Memory carry flag rotated right bit. replaces Carry original carry flag rotated into rotated result stored Accumulator contents Data Memory remain unchanged. ACC.i [m].(i+1); 0~6) ACC.7 [m].0
Affected flag(s) RLCA Description
Operation
Affected flag(s) Description Operation Affected flag(s) Description
Operation Affected flag(s) Description Operation
Affected flag(s) RRCA Description
Operation
Affected flag(s)
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
A,[m] Description Subtract Data Memory from with Carry contents specified Data Memory complement carry flag subtracted from Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract Data Memory from with Carry result Data Memory contents specified Data Memory complement carry flag subtracted from Accumulator. result stored Data Memory. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Skip decrement Data Memory contents specified Data Memory first decremented result following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip decrement Data Memory zero with result contents specified Data Memory first decremented result following instruction skipped. result stored Accumulator specified Data Memory contents remain unchanged. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Data Memory Each specified Data Memory None Data Memory specified Data Memory [m].i None
Operation Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) Description
Operation Affected flag(s) SDZA Description
Operation Affected flag(s) Description Operation Affected flag(s) [m].i Description Operation Affected flag(s)
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Description Skip increment Data Memory contents specified Data Memory first incremented result following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip increment Data Memory zero with result contents specified Data Memory first incremented result following instruction skipped. result stored Accumulator specified Data Memory contents remain unchanged. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip [m].i None Subtract Data Memory from specified Data Memory subtracted from contents Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract Data Memory from with result Data Memory specified Data Memory subtracted from contents Accumulator. result stored Data Memory. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will Subtract immediate data from immediate data specified code subtracted from contents Accumulator. result stored Accumulator. Note that result subtraction negative, flag will cleared otherwise result positive zero, flag will
Operation Affected flag(s) SIZA Description
Operation Affected flag(s) [m].i Description
Operation Affected flag(s) A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) Description
Operation Affected flag(s)
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
SWAP Description Operation Affected flag(s) SWAPA Description Operation Affected flag(s) Description Swap nibbles Data Memory low-order high-order nibbles specified Data Memory interchanged. [m].3~[m].0 [m].7 [m].4 None Swap nibbles Data Memory with result low-order high-order nibbles specified Data Memory interchanged. result stored Accumulator. contents Data Memory remain unchanged. ACC.3 ACC.0 [m].7 [m].4 ACC.7 ACC.4 [m].3 [m].0 None Skip Data Memory contents specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory with data movement contents specified Data Memory copied Accumulator. value zero, following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip None Skip Data Memory specified Data Memory following instruction skipped. this requires insertion dummy instruction while next instruction fetched, cycle instruction. result program proceeds with following instruction. Skip [m].i None Read table (current page) TBLH Data Memory byte program code (current page) addressed table pointer (TBLP) moved specified Data Memory high byte moved TBLH. program code (low byte) TBLH program code (high byte) None Read table (last page) TBLH Data Memory byte program code (last page) addressed table pointer (TBLP) moved specified Data Memory high byte moved TBLH. program code (low byte) TBLH program code (high byte) None
Operation Affected flag(s) Description
Operation Affected flag(s) [m].i Description
Operation Affected flag(s) TABRDC Description Operation Affected flag(s) TABRDL Description Operation Affected flag(s)
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Logical Data Memory Data Accumulator specified Data Memory perform bitwise logical operation. result stored Accumulator. Logical Data Memory Data specified Data Memory Accumulator perform bitwise logical operation. result stored Data Memory. Logical immediate data Data Accumulator specified immediate data perform bitwise logical operation. result stored Accumulator.
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Package Information
28-pin (300mil) Outline Dimensions
MS-013
Symbol
Dimensions Min. Nom. Max.
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Product Tape Reel Specifications
Reel Dimensions
(300mil) Symbol Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Slit Width Space Between Flange Reel Thickness Dimensions 330.0±1.0 100.0±1.5 13.0+0.5/-0.2 2.0±0.5 24.8+0.3/-0.2 30.2±0.2
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Carrier Tape Dimensions
(300mil) Symbol Description Carrier Tape Width Cavity Pitch Perforation Position Cavity Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions 24.0±0.3 12.0±0.1 1.75±0.10 11.5±0.1 1.5+0.1/-0.0 1.50+0.25/-0.00 4.0±0.1 2.0±0.1 10.85±0.10 18.34±0.10 2.97±0.10 0.35±0.01 21.3±0.1
Rev. 1.30
December 2008
HT82K95EE/HT82K95AE
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) Room, Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103 Tel: 86-21-5422-4590 Fax: 86-21-5422-4705 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) Unit Productivity Building, Gaoxin 2nd, Middle Zone High-Tech Industrial Park, ShenZhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, 94538, Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright 2008 HOLTEK SEMICONDUCTOR INC. information appearing this Data Sheet believed accurate time publication. However, Holtek assumes responsibility arising from specifications described. applications mentioned herein used solely purpose illustration Holtek makes warranty representation that such applications will suitable without further modification, recommends products application that present risk human life malfunction otherwise. products authorized critical components life support devices systems. Holtek reserves right alter products without prior notification. most up-to-date information, please visit site http://www.holtek.com.tw.
Rev. 1.30
December 2008

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