GXM12864DSL
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User's Guide
GXM12864DSL
Liquid Crystal Display Module
NANJING GUOXIAN ELECTRONICS CORP. Add: Nanjing Zhongshan East Road Tel: 025-4594900 Fax: 025-4641600 Website: http://www.guoxian.com Email: gvision@jlonline.com sales@guoxian.com
GXM12864D
Use's Guide
Contents
Chapter Introduction GXM12864D
Features Mechanical Specifications Temperature Characteristics External Dimensions Application Diagram Electro- Optical characteristics Interface Connections Electrical Absolute Maximum Rating (KS0107B) Electrical Characteristics (KS0107B) Electrical Absolute Maximum Rating (KS0108B) Electrical Characteristics (KS0108B) Chapter Driver (KS0107B) Function Description
Introduction Characteristics Master Mode Slave Mode Functional Description Oscillator Timing Generation Circuit Data Shift Phase Select Control Chapter
Driver (KS0108B) Function Description
Introduction Characteristics Operating Principles Methods Display Control Instruction
Chapter
Introduction GXM12864D
CHAPTER
Introduction GXM12864D
GXM12864D matrix graphic module which fabricated power COMS technology. display 128*64 dots size panel using 128*64 bit-mapped Display Data (DDRAM). interfaces with 8-bit microprocessor.
Features
Display format: 128*64 dots matrix graphic yellow-green mode Easy interface with 8-bit power consumption back-light Viewing angle: O'clock Driving method 1/64 duty bias driver KS0108B(2 )KS0107B Connector: Zebra
Mechanical Specifications
Item Module Size(W*H*T) Viewing Area(W*H) Number Dots Size(W*H) Pitch(W*H) Module Size With Dimension 93.0*70.0*10.0 72.0*40.0 128.0*64.0 0.48*0.48 0.52*0.52 93.0*70.0*15.0 Unit
Temperature Characteristics
Parameter Operating temperature Storage temperature Symbol Topr Tstg Rating -25~+65 -30~+70 Unit
Chapter
Introduction GXM12864D
Figure External Dimensions
SIGNAL SIGNAL
*NOTE: 1.All units 2.Tolerances unless otherwise specified ±0.2.
Chapter
Introduction GXM12864D
Figure Application Diagram
SEG1 SEG64
COM64 SEG65
SEG128
panel (128X64)
COM1
CLK1 CLK2 PCLK2
KS0107B
CLK1 CLK2
KS0108B
(Bottom view)
DB[0:7] RESETB
CS2B
DB[0:7] RESETB
CS1B
VVEE
CS1B DB[0:7] RESETB
DCDC
CONVERTOR
CS2B
CLK1 CLK2
KS0108B
(Bottom view)
*Note 1/64 duty, bias VDD>V1>V2>V3>V4>V5>VEE
Chapter
Introduction GXM12864D
Electro-Optical characteristics
Type (Twisted Nematic Item Symbol Viewing Angle Contrast Ratio Response Time (rise) Response Time (fall) Min. Typ. Max. Unit deg. Condition Condition
Note
Type (Super Twisted Nematic Item Symbol Viewing Angle Contrast Ratio Response Time (rise) Response Time (fall)
Min.
Typ.
Max.
Unit deg.
Note
Definition angle
Definition viewing angle
Y(=180
1<20
Y'(=0
Definition contrast
Definition optical response
100% Intensity Selected Dots
Nonselected Dots Intensity 100% 100% Driving Voltage Time
Point
Negative Positive
Interface Connections
Chapter Symbol Type Supply Supply Supply Description Ground Power supply
Introduction GXM12864D
driver supply voltage
Data input/output internal shift register DIO1 Output Output Input Output DIO2 Output Output Output Input
Read Write
Description Data appears DB[7:0] read while CS1B=L,CS2B=L CS3=H. Display data DB[7:0] written falling edge when CS1B=L, CS2B=L CS3=H. Description Read data DB[7:0] appears while "High". Display data DB[7:0] latched falling edge
Enable signal
Data [0~7]
Bi-directional data
Chip selection When CS1=H,CS2=L, select
RESETB
When CS1=L,CS2=H, select Reset signal. When RSTB=L
1ON/OFF register becomes 0.(display off) 2display start line register becomes (Z-address set, display from line 3After releasing reset this condition changed only instruction.
Power
connected same voltage. Back-light anode Back-light cathode
Electrical Absolute Maximum Ratings (KS0107B)
Parameter Operating voltage Supply voltage Driver supply voltage *Notes: Based Symbol VLCD Rating -0.3 +7.0 VDD-19.0 VDD+0.3 -0.3 VDD+0.3 VEE-0.3 VDD+0.3 Unit Note *1,2 *3,4
Chapter
Introduction GXM12864D
Applies input terminals terminals high impedance. (Except V0L, V1L, V4L, V5L) Applies V0L, V1L, V4L, V5L. Voltage level: VDDV0V1V2V3V4V5VEE
Electrical Characteristics(KS0107B)
(VDD= 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= +85) Item Symbol Condition Min. Operating voltage Input voltage 0.7VDD output voltage IOH= -0.4mA VDD-0.4 IOL= 0.4mA Input leakage current ILKG VIN= -1.0 Frequency fosc Rf=47k±2% Cf=20pF±5% Resistance RONS VDD-VEE=17V (Vdiv-Ci) Load current±150A Operating current IDD1 Master mode 1/128 Duty Master mode IDD2 1/128 Duty Supply Current Master mode 1/128 Duty Master mode Operating fop1 External Duty Frequency fop2 Slave mode Typ. Max. 0.3VDD +1.0 1500 Unit Note
Notes Applies input terminals DS1, DS2, SHL, PCLK2 terminals DIO1, DIO2, input state. Applies output terminals CLK1, CLK2 terminals DIO1, DIO2, output state. This value specified about current flowing through VSS. Internal oscillation circuit: Rf=47k, cf=20pF Each terminals DS1, DS2, SHL, connected load. This value specified about current flowing through VSS. Each terminals DS1, DS2, SHL, PCLK2 connected VDD,MS connected CL2, DIO1 external clock. This value specified about current flowing through VEE, Don't connect VLCD (V1~V5).
Chapter
Introduction GXM12864D
Electrical Absolute Maximum Ratings(KS0108B)
Parameter Operating voltage Supply voltage Driver supply voltage Symbol VLCD Rating -0.3 +7.0 VDD-19.0 VDD+0.3 -0.3 VDD+0.3 VEE-0.3 VDD+0.3 Unit Note *1,3
*Notes: Based Applies same supply voltage VEE. VLCD=VDD-VEE. Applies FRM, CLK1,CLK2, RESETB, ADC, CS1B, CS2B,CS3, R/W, DB0~DB7. Applies V0L,V2L,V3L V5L. Voltage level: VDDV0V1V2V3V4V5VEE
Electrical Characteristics(KS0108B)
(VDD= 5.5V, VSS=0V,VDD-VEE=8~17V,Ta= +85) Item Symbol Condition Min. Operating voltage Input High voltage VIH1 0.7VDD VIH2 Input voltage VIL1 VIL2 Output High Voltage IOH= -0.2mA Output Voltage IOL= 1.6mA Input leakage current ILKG VIN= -1.0 Three-state (OFF) ITSL VIN= -5.0 Input Current Driver Input leakage IDIL VIN= -2.0 current Resistance RONS VDD-VEE=15V (Vdiv-Ci) Load current±100A Operating current IDD1 During Display During Access IDD2 Access Cycle=1MHz Typ. Max. 0.3VDD +1.0 Unit Note
Notes FRM, RSTB, CLK1, CLK2 CS1B, CS2B, CS3, R/W, DB0~DB7 DB0~DB7 Except DB0~DB7 DB0~DB7 high impedance 1/64 duty FCLK=250KHZ, Frame Frequency=70HKZ, Output: Load VDD-VEE=13.5V V0L>V2L>= VDD-2/7(VDD-VEE)>V3L= VEE+2/7(VDD-VEE)>V5L
64CH Common Driver Matrix
CHAPTER
Driver Function Description
KS0107 Driver 64COM graphic driver matrix
Introduction
KS0107B driver with channel outputs matrix liquid crystal graphic display systems. This device provides shift registers output drivers. generates timing signal control KS0108B channel segment drover.). KS0107B fabricated power CMOS high voltage process technology, composed liquid crystal display system combination with KS0108B channel segment drover.).
64CH Common Driver Matrix
Characteristics (VDD=4.5~5.5V, Ta=-30~+85)
Master mode (MS=VDD, PCLK2=VDD, Cf=20pF, Rf=47K)
0.7VDD 0.3VDD
tWLC tWHC tWHC
DIO1(SHL=VDD) DIO2(SHL=VSS) DIO2(SHL=VDD) DIO1(SHL=VSS)
CLK1 CLK2 tWL1 tD12 tD21 tWH2 tWH1
0.7VDD 0.3VDD
Characteristic Data Setup Time Data Hold Time Data Delay Time Delay Time Delay Time Level Width High Level Width CLK1 Level Width CLK2 Level Width CLK1 High Level Width CLK2 High Level Width CLK1-CLK2 Phase Difference CLK2-CLK1 Phase Difference CLK1,CLK2 Rise/Fall Time
Symbol tWLC tWHC tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR/t
2100 2100
Unit
64CH Common Driver Matrix
Slave mode (MS=VSS)
(PLK2=VSS)
tWLC1 0.7VDD tWHC1 tWLC2 tWLC 0.3VDD
(PLK2=VDD) DIO1(SHL=VDD) DIO2(SHL=VSS) Input Data DIO1(SHL=VDD) DIO2(SHL=VSS) Output Data
0.7VDD 0.3VDD 0.7VDD 0.3VDD tHCL
Characteristics Level Width High Level Width Level Width High Level Width Data Setup Time Data Hold Time Data Delay Time Output Data Hold Time Rise/Fall Time
Symbol tWLC1 tWHC1 tWLC2 tWHL tR/tF
Unit
Note PCLK2=VSS PCLK2=VSS PCLK2=VDD PCLK2=VDD
Connect load CL=30pF OUTPUT 30pF
64CH Common Driver Matrix
FUNCTIONAL DESCRIPTION
Oscillator Oscillator generates CL2, FRM, KS0107B CLK1, CLK2 KS0107B oscillation resister capacitor When selecting master/slave, oscillation circuit following: Master Mode
KS0107B open
KS0107B
open External clock
Slave Mode
KS0107B open open
Timing Generation circuit generates CL2, FRM, CLK1, CLK2 frequency from oscillation circuit. Selection Master/Slave (M/S) When "H", generates CL2, FRM, CLK1, CLK2 internally. When "L", operates receiving CLK2 from master device. Frequency Selection (FS) adjust 70Hz, oscillation frequency should following: Oscillation Frequency fOSC=430KHz fOSC=215KHz
slave mode, connected VDD.
64CH Common Driver Matrix
Duty Selection (DS1, DS2) provides various duty selection according DS1, DS2. DUTY 1/48 1/64 1/96 1/128
Data shift Phase Select Control Phase Selection circuit shift data synchronization rising edge falling edge according PCLK2. PCLK2 Phase Selection Data shift rising edge Data shift falling edge
Data shift Direction Selection When connected VDD, DIO1 DIO2 terminal only output. When connected VSS, depends SHL. DIO1 Output Output Input Output DIO2 Output Output Output Input Direction Data C1~C64 C64~C1 DIO1~C1~C64~DIO2 DIO2~C64~C1~DIO1
64CH Segment Driver Matrix
CHAPTER
Driver Function Description
KS0108 Driver graphic driver matrix
Introduction
KS0108B driver with channel outputs matrix liquid crystal graphic display systems. This device consists display RAM, data latch drivers decoder logics. internal display storing display data transferred from micro controller generates matrix liquid crystal driving signals corresponding stored data. KS0108B composed liquid crystal display system combination with KS0107B(64 common driver).
Characteristics (VDD=4.5~5.5V ,VSS=0V, Ta=-30~+85)
Clock Timing Characteristic CLK1, CLK2 Cycle Time CLK1`LOW'Level Width CLK2`LOW'Level Width CLK1`HIGH'Level Width CLK2`HIGH'Level Width CLK1-CLK2 Phase Difference CLK2-CLK1 Phase Difference CLK1, CLK2 Rise Time CLK1, CLK2 Fall Time Symbol tWL1 tWL2 tWH1 tWH2 tD12 tD21 1875 1875 Unit
64CH Segment Driver Matrix
2.Display Control Timing Characteristic Delay Time Delay Time `LOW'Level Width CL`HIGH'Level Width Symbol Unit
0.7VDD 0.3VDD 7VDD 3VDD 7VDD 3VDD
64CH Segment Driver Matrix
Interface Characteristic Cycle High Level Width Level Width Rise Time Fall Time Address Set-Up Time Address Hold Time Data Set-Up Time Data Delay Time Data Hold Time (Write) Data Hold Time (Read) Symbol tASU tDHW tDHR 1000 Unit
tASU tASU CS1B,CS2B CS3,RS tDSU DB0~DB7 tDHW
Write timing
64CH Segment Driver Matrix
tASU tASU CS1B,CS2B CS3,RS DB0~DB7
Read timing
OPERATING PRINCIPLES METHODS
Buffer Input buffer controls status between enable disable chip. Unless CS1B active mode, Input output data instruction does execute. Therefore internal state change. RSTB operate regardless CS!B-CS3.
Input register Input register provided interface with which different operating frequency. Input register stores data temporarily before writing into display RAM. When CS1B active mode, select input register. data from written into input register. Then writing into display RAM. Data latched falling signal write automatically into display data internal operation.
Output register Output register stores data temporarily from display data when CS1B, CS2B active mode RS=H, stored data display data latched output register. When CS1B active mode R/W=H RS=L, status data (busy check) read out. read contents display data RAM, twice access read instruction needed. first access, data display data latched into output register. second access, read data which latched. That read data display data RAM, needs dummy read. status read needed dummy read.
64CH Segment Driver Matrix
Function Instruction Status read (busy check) Data write (from input register display data Data read (from display data output register)
Reset system initialized setting RSTB terminal level when turning power receiving instruction from MPU. When RSTB becomes low, following procedure occurred. Display Display start line register become 0.(Z-address While RSTB low, instruction except status read accepted. Therefore, execute other instructions after making sure that DB4= (clear RSTB) DB7=0 (ready) status read instruction. conditions power supply initial power shown table Table Power Supply Initial Conditions Item Reset Time Rise Time Symbol
4.5[V] RSTB 0.7VDD 0.3VDD
Unit
Busy flag Busy flag indicates that KS0108B operating operating. When busy flag high, KS0108B internal operating When busy flag low, KS0108B accept data instruction. DB7indicates busy flag KS0108B.
Busy Flag
Busy
1/fCLK<T Busy<3/fCLK
fCLK CLK1, CLK2 Frequency
64CH Segment Driver Matrix
Display On/Off Flip-Flop display on/off flip-flop makes on/off liquid crystal display. When flip-flop reset (logical low), selective voltage selective voltage appears segment output terminals. When flip-flop (logic high), selective voltage appears segment output terminals regardless display data. display on/off flip-flop changes status instruction. display data segment disappear while RSTB low. status flip-flop output status read instruction. display on/off flip-flop synchronized signal. Page Register page register designates pages internal display data RAM. Count function available. address instruction. address counter address counter designates address internal display data RAM. address instruction increased automatically read write operations display data. Display Data Display data stores display data liquid crystal display. indicate state matrix liquid crystal display write datra1. other state, writes Display data address segment output controlled signal. ADC=H Y-address S1~Y address ADC=L Y-address S64~Yaddress terminal connect VSS.
Display Start Line Register
display start line register indicates display data display line liquid crystal display. data (DB<0.5>) display start line instruction latched display start line register. Latched data transferred address counter while high, presetting address counter. used scrolling liquid crystal display screen.
64CH Segment Driver Matrix
Display Control Instruction
display control instructions control internal state KS0108B. Instruction received from KS0108B display control. following table shows various instructions.
Instruction Read Display Date
Read data
Write Display Date
Write data
Status Read
Busy
Reset
Address address) Display Start Line Address address)
address (0~63) Display start line (0~63) Page (0~7)
Display On/off
Function Reads data (DB[7:0]) from display data data bus. Writes data (DB[7:0]) into DDRAM. After writing instruction, address incriminated automatically Reads internal status BUSY Ready operation ON/OFF Display Display RESET Normal Reset Sets address column address counter Indicates Display Data displayed screen. Sets address address register. Controls display OFF. internal status DDRAM data affected. OFF,
Display On/Off display data appears when disappears when Though data screen with D=0, remains display data RAM. Therefore, make appear changing into D=1.
Address Address) address (AC0~AC5) display data address counter. address instruction increased automatically read write operations display data.
64CH Segment Driver Matrix
Page Address) address (AC0~AC2) display data address register. Writing reading from executed this specified page until next page set.
Display Start Line Address) address (AC0~AC5) display data display start line register displayed screen. When display duty cycle 1/64 others (1/32~1/64), data total line number screen, from line specified display start line instruction, displayed.
Status Read BUSY ON/OFF RESET
BUSY When BUSY Chip executing internal operation instructions accepted. When BUSY Chip ready accept instructions. ON/OFF When ON/OFF display When ON/OFF display off. RESET When RESET system being initialized. this condition, instructions except status read accepted. When RESET initializing finished system usual operation condition. Write Display Data Writes data (D0~D7) into display data RAM. After writing instruction, address increased automatically.
Read Display Data Reads data (D0~D7) from display data RAM. After reading instruction, address increased automatically.
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