GVT71512C18

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GVT71512C18 - GVT71512C18

CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
256K 36/512K Pipelined SRAM
Fast access times: Fast clock speed: MHz, MHz, MHz, Fast access times: Optimal performance (two cycle chip deselect, depth expansion without wait state) 3.3V +10% power supply 3.3V 2.5V supply tolerant inputs except I/Os Clamp diodes inputs outputs Common data inputs data outputs Byte Write Enable Global Write control Multiple chip enables depth expansion: three chip enables TA(GVTI)/A(CY) package version chip enables B(GVTI)/BG(CY) T(GVTI)/AJ(CY) package versions Address pipeline capability Address, data control registers Internally self-timed Write Cycle Burst control pins (interleaved linear burst sequence) Automatic power-down portable applications JTAG boundary scan package version profile 119-bump, 14-mm 22-mm PBGA (Ball Grid Array) 100-pin TQFP packages 2-bit counter internal burst operation. synchronous inputs gated registers controlled positive-edge-triggered Clock Input (CLK). synchronous inputs include addresses, data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 CE2), Burst Control Inputs (ADSC, ADSP, ADV), Write Enables (BWa, BWb, BWc, BWd, BWE), Global Write (GW). However, Chip Enable input only available TA(GVTI)/A(CY) package version. Asynchronous inputs include Output Enable (OE) Burst Mode Control (MODE). data outputs (Q), enabled also asynchronous. Addresses chip enables registered with either Address Status Processor (ADSP) Address Status Controller (ADSC) input pins. Subsequent burst addresses internally generated controlled Burst Advance (ADV). Address, data inputs, write controls registered on-chip initiate self-timed WRITE cycle. WRITE cycles four bytes wide, controlled write control inputs. Individual byte write allows individual byte written. controls DQa. controls DQb. controls DQc. controls DQd. BWa, BWb, BWc, active only with being LOW. being causes bytes written. version only data inputs/outputs (DQa DQb) along with BWc, BWd, DQc, DQd). B(GVTI)/BG(CY) T(GVTI)/AJ(CY) package versions, four pins used implement JTAG test capabilities: Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK), Test Data-Out (TDO). JTAG circuitry used serially shift data from device. JTAG inputs LVTTL/LVCMOS levels shift data during this testing mode operation. package version does offer JTAG capability. CY7C1366A/GVT71256C36 CY7C1367A/ GVT71512C18 operate from +3.3V power supply. inputs outputs LVTTL compatible.
Functional Description
Cypress Synchronous Burst SRAM family employs high-speed, power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists four transistors high valued resistors. CY7C1366A/GVT71256C36 CY7C1367A/ GVT71512C18 SRAMs integrate 262,144 524,288 SRAM cells with advanced synchronous peripheral circuitry
Selection Guide
7C1366A-225/ 71256C36-4.4 7C1367A-225/ 71512C18-4.4 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Commercial 7C1366A-200/ 71256C36-5 7C1367A-200/ 71512C18-5 7C1366A-166/ 71256C36-6 7C1367A-166/ 71512C18-6 7C1366A-150/ 71256C36-6.7 7C1367A-150/ 71512C18-6.7
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134
408-943-2600 June 2001
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Functional Block Diagram-256K 36[1]
BYTE WRITE
BWa# BWE#
BYTE WRITE
BWb#
BYTE WRITE
BWc#
BYTE WRITE
BWd#
byte write byte write byte write DQa,DQb DQc,DQd byte write Output Buffers
CE2#
ENABLE
Power Down Logic Input Register
ADSP#
Address Register 256K SRAM Array
ADSC#
OUTPUT REGISTER
ADV# A1-A0 MODE Binary Counter Logic
Functional Block Diagram-512K 18[1]
BYTE WRITE
BWb# BWE#
BYTE WRITE
BWa#
byte write byte write Output Buffers
CE2# ADSP# Power Down Logic
ENABLE
Input Register
Address Register 512K SRAM Array
ADSC# ADV# A1-A0 MODE Binary Counter Logic
OUTPUT REGISTER
DQa,D
Notes: Functional Block Diagram illustrates simplified device operation. Truth Table, descriptions timing diagrams detailed information. version only.
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Configurations
100-Pin TQFP View
ADSC ADSP ADSC ADSP VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ VCCQ
VCCQ VCCQ VCCQ VCCQ
CY7C1366A/GVT71256C36 (256K Package Version
CY7C1367A/GVT71512C18 (512K Package Version
VCCQ VCCQ VCCQ VDDQ
MODE
ADSC ADSP
VCCQ VCCQ VCCQ VCCQ
CY7C1366A/GVT71256C36 (256K Package Version
VCCQ VCCQ VCCQ VCCQ
VCCQ VCCQ VCCQ VCCQ
ADSC ADSP
MODE
CY7C1367A/GVT71512C18 (512K Package Version
VCCQ VCCQ VCCQ VCCQ
MODE
MODE
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Configurations (continued)
119-Ball View 256Kx36 VCCQ VCCQ VCCQ VCCQ VCCQ MODE ADSP ADSC VCCQ VCCQ VCCQ VCCQ VCCQ
512Kx18 VCCQ VCCQ VCCQ VCCQ VCCQ MODE ADSP ADSC VCCQ VCCQ VCCQ VCCQ VCCQ
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
256K Descriptions
PBGA Pins Pins 100, Version) Version) Name Type InputSynchronous Description Addresses: These inputs registered must meet hold times around rising edge CLK. burst counter generates internal addresses associated with during burst cycle wait cycle.
InputSynchronous
Byte Write: byte write WRITE cycle HIGH READ cycle. controls DQa. controls DQb. controls DQc. controls DQd. Data high impedance either these inputs LOW, conditioned being LOW. Write Enable: This active input gates byte write operations must meet set-up hold times around rising edge CLK. Global Write: This active input allows full 36-bit Write occur independent lines must meet set-up hold times around rising edge CLK. Clock: This signal registers addresses, data, chip enables, write control, burst control inputs rising edge. synchronous inputs must meet hold times around clock's rising edge. Chip Enable: This active input used enable device gate ADSP Chip Enable: This active HIGH input used enable device. Chip Enable: This active input used enable device. available package versions. Output Enable: This active asynchronous input enables data output drivers. Address Advance: This active input used control internal burst counter. HIGH this generates wait cycle address advance). Address Status Processor: This active input, along with being LOW, causes external address registered READ cycle initiated using address. Address Status Controller: This active input causes device deselected selected along with external address registered. Read Write cycle initiated depending upon write control inputs. Mode: This input selects burst sequence. this selects Linear Burst. HIGH this selects Interleaved Burst.
InputSynchronous InputSynchronous InputSynchronous
(not available PBGA)
(for Version only)
InputSynchronous InputSynchronous InputSynchronous Input InputSynchronous InputSynchronous InputSynchronous
ADSP
ADSC
MODE
InputStatic
InputSnooze: This active HIGH input puts device power Asynchronous consumption standby mode. normal operation, this input either Connect).
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
256K Descriptions (continued)
PBGA Pins Pins version version 41,65, Name Type Input/ Output Description Data Inputs/Outputs: First Byte DQa. Second Byte DQb. Third Byte DQc. Fourth Byte DQd. Input data must meet set-up hold times around rising edge CLK.
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. available package version.
Output
IEEE 1149.1 test output. LVTTL-level output. available package version. Core power Supply: +3.3V +10% Ground: GND.
Supply Ground
Version
VCCQ
Supply
Output Buffer Supply: +2.5V +3.3V. Connect: These signals internally connected. User leave floating connect VSS.
512K Descriptions
PBGA Pins Pins 100, Version) Version) Name Type InputSynchronous Description Addresses: These inputs registered must meet set-up hold times around rising edge CLK. burst counter generates internal addresses associated with during burst cycle wait cycle.
InputSynchronous
Byte Write Enables: byte write enable WRITE cycle HIGH READ cycle. controls DQa. controls DQb. Data high impedance either these inputs LOW, conditioned being LOW. Write Enable: This active input gates byte write operations must meet hold times around rising edge CLK. Global Write: This active input allows full 18-bit WRITE occur independent lines must meet hold times around rising edge CLK. Clock: This signal registers addresses, data, chip enables, write control burst control inputs rising edge. synchronous inputs must meet setup hold times around clock's rising edge. Chip Enable: This active input used enable device gate ADSP
InputSynchronous InputSynchronous InputSynchronous
InputSynchronous
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
512K Descriptions (continued)
PBGA Pins (not available PBGA) Pins (for Version only) Name Type InputSynchronous InputSynchronous Input InputSynchronous InputSynchronous InputSynchronous Description Chip Enable: This active HIGH input used enable device. Chip Enable: This active input used enable device. available package versions. Output Enable: This active asynchronous input enables data output drivers. Address Advance: This active input used control internal burst counter. HIGH this generates wait cycle address advance). Address Status Processor: This active input, along with being LOW, causes external address registered Read cycle initiated using address. Address Status Controller: This active input causes device deselected selected along with external address registered. Read Write cycle initiated depending upon write control inputs. Mode: This input selects burst sequence. this selects Linear Burst. HIGH this selects Interlinear Burst.
ADSP
ADSC
MODE
InputStatic
InputSnooze: This active HIGH input puts device power Asynchronous consumption standby mode. normal operation, this input either Connect). Input/ Output Data Inputs/Outputs: Byte DQa. High Byte DQb. Input data must meet hold times around rising edge CLK. IEEE 1149.1 test inputs. LVTTL-level inputs. available package version.
version version 41,65,
Input
Output
IEEE 1149.1 test output. LVTTL-level output. available package version. Core power Supply: +3.3V +10% Ground: GND.
Supply Ground
1-3, 28-30, 51-53, Version
VCCQ
Supply
Output Buffer Supply: +2.5V +3.3V. Connect: These signals internally connected. User leave floating connect VSS.
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Burst Address Table (MODE NC/VCC)
First Address (external) A.A00 A.A01 A.A10 A.A11 Second Address (internal) A.A01 A.A00 A.A11 A.A10 Third Address (internal) A.A10 A.A11 A.A00 A.A01 Fourth Address (internal) A.A11 A.A10 A.A01 A.A00
Burst Address Table (MODE GND)
First Address (external) A.A00 A.A01 A.A10 A.A11 Second Address (internal) A.A01 A.A10 A.A11 A.A00 Third Address (internal) A.A10 A.A11 A.A00 A.A01 Fourth Address (internal) A.A11 A.A00 A.A01 A.A10
Truth Table[3,
Operation Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down Deselected Cycle, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current ADSP ADSC WRITE High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z
Notes: "Don't Care." logic HIGH. logic LOW. product, WRITE means [BWE BWa*BWb*BWc*BWd]*GW equals LOW. WRITE means [BWE BWa*BWb*BWc*BWd]*GW equals HIGH. product, WRITE means [BWE BWa*BWb]*GW equals LOW. WRITE means [BWE BWa*BWb]*GW equals HIGH. enables write DQa. enables write DQb. enables write DQc. enables write DQd. inputs except must meet hold times around rising edge (LOW HIGH) CLK. Suspending burst generates wait cycle. write operation following read operation, must HIGH before input data required set-up time plus High-Z time staying HIGH throughout input data hold time. This device contains circuitry that will ensure outputs will High-Z during power-up. ADSP along with chip being selected always initiates Read cycle edge CLK. WRITE cycle performed setting WRITE edge subsequent wait cycle. Refer Write timing diagram clarification.
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Partial Truth Table READ/WRITE[10]
Function READ READ WRITE byte WRITE bytes WRITE bytes
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview This device incorporates serial boundary scan access port (TAP). This port designed operate manner consistent with IEEE Standard 1149.1-1990 (commonly referred JTAG), does implement functions required IEEE 1149.1 compliance. Certain functions have been modified eliminated because their implementation places extra delays critical speed path device. Nevertheless, device supports standard controller architecture (the controller state machine that controls TAPs operation) expected function manner that does conflict with operation devices with IEEE Standard 1149.1 compliant TAPs. operates using LVTTL/ LVCMOS logic level signaling. Disabling JTAG Feature possible this device without using JTAG feature. disable controller without interfering with normal operation device, should tied (VSS) prevent clocking device. internally pulled unconnected. They alternately pulled through resistor. should left unconnected. Upon power-up device will come reset state which will interfere with operation device.
Test Data (OUTPUT) output used serially clock data-out from registers. output that active depending state state machine (refer Figure Controller State Diagram). Output changes response falling edge TCK. This output side serial registers placed between TDO. connected Least Significant (LSB) register (see Figure Performing Reset circuitry does have reset (TRST, which optional IEEE 1149.1 specification). RESET performed controller forcing HIGH (VCC) five rising edges pre-loads instruction register with IDCODE command. This type reset does affect operation system logic. reset affects test logic only. power-up, reset internally ensure that High-Z state.
Test Access Port (TAP) Registers
Overview various registers selected (one time) sequences ones zeros input strobed. Each TAPs registers serial shift registers that capture serial input data rising edge push serial data subsequent falling edge TCK. When register selected, connected between pins. Instruction Register instruction register holds instructions that executed controller when moved into test/idle various data register states. instructions three bits long. register loaded when placed between pins. parallel outputs instruction register automatically preloaded with IDCODE instruction upon power-up whenever controller placed test-logic reset state. When controller Capture-IR state, least significant bits serial instruction register loaded with binary "01" pattern allow fault isolation board-level serial test data path. Bypass Register bypass register single-bit register that placed between TDO. allows serial test data passed through device another device scan chain with minimum delay. bypass register when BYPASS instruction executed.
Test Access Port (TAP)
Test Clock (INPUT) Clocks events. inputs captured rising edge outputs propagate from falling edge TCK. Test Mode Select (INPUT) input sampled rising edge TCK. This command input controller state machine. allowable leave this unconnected used. pulled internally, resulting logic HIGH level. Test Data (INPUT) input sampled rising edge TCK. This input side serial registers placed between TDO. register placed between determined state controller state machine instruction that currently loaded instruction register Figure allowable leave this unconnected used application. pulled internally, resulting logic HIGH level. connected Most Significant (MSB) register (see Figure
Note: product, There only BWb.
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Boundary Scan Register Boundary Scan register connected input bidirectional pins (not counting pins) device. This also includes number pins that reserved future needs. There total bits device bits device. boundary scan register, under control controller, loaded with contents device ring when controller Capture-DR state then placed between pins when controller moved Shift-DR state. EXTEST, SAMPLE/PRELOAD SAMPLE-Z instructions used capture contents ring. Boundary Scan Order table describes order which bits connected. first column defines bit's position boundary scan register. register connected TDI, connected TDO. second column signal name, third column TQFP number, fourth column bump number. Identification (ID) Register Register 32-bit register that loaded with device vendor specific 32-bit code when controller Capture-DR state with IDCODE command loaded instruction register. register then placed between pins when controller moved into Shift-DR state. register first reach when shifting begins. code loaded from 32-bit on-chip ROM. describes various attributes device described Identification Register Definitions table. controller does recognize all-0 instruction. When EXTEST instruction loaded into instruction register, device responds SAMPLE/PRELOAD instruction been loaded. There difference between instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places device outputs High-Z state. IDCODE IDCODE instruction causes vendor-specific, 32-bit code loaded into register when controller Capture-DR mode places register between pins Shift-DR mode. IDCODE instruction default instruction loaded instruction upon power-up time controller placed test-logic reset state. SAMPLE-Z High-Z instruction loaded instruction register, output pins forced High-Z state boundary scan register connected between pins when controller Shift-DR state. SAMPLE/PRELOAD SAMPLE/PRELOAD IEEE 1149.1 mandatory instruction. PRELOAD portion command implemented this device, device controller fully IEEE 1149.1-compliant. When SAMPLE/PRELOAD instruction loaded instruction register controller Capture-DR state, snap shot data device's input buffers loaded into boundary scan register. Because device system clock(s) independent from clock (TCK), possible attempt capture input ring contents while buffers transition (i.e., metastable state). Although allowing sample metastable inputs will harm device, repeatable results expected. guarantee that boundary scan register will capture correct value signal, device input signals must stabilized long enough meet controller's capture plus hold time (tCS plus tCH). device clock input(s) need paused other operation except capturing input ring contents into boundary scan register. Moving controller Shift-DR state then places boundary scan register between pins. Because PRELOAD portion command implemented this device, moving controller Update-DR state with SAMPLE/PRELOAD instruction loaded instruction register same effect Pause-DR command. BYPASS When BYPASS instruction loaded instruction register controller Shift-DR state, bypass register placed between TDO. This allows board level scan path shortened facilitate testing other devices scan path. Reserved these instructions. They reserved future use.
Controller Instruction
Overview There classes instructions defined IEEE Standard 1149.1-1990; standard (public) instructions device specific (private) instructions. Some public instructions mandatory IEEE 1149.1 compliance. Optional public instructions must implemented prescribed ways. Although controller this device follows IEEE 1149.1 conventions, IEEE 1149.1 compliant because some mandatory instructions fully implemented. this device used monitor input pads, used load address, data, control signals into device preload buffers. other words, device will perform IEEE 1149.1 EXTEST, INTEST, preload portion SAMPLE/PRELOAD command. When controller placed Capture-IR state, least significant bits instruction register loaded with When controller moved Shift-IR state instruction serially loaded through input (while previous contents shifted TDO). instructions, executes newly loaded instructions only when controller moved Update-IR state. instruction sets this device listed following tables. EXTEST EXTEST IEEE 1149.1 mandatory public instruction. executed whenever instruction register loaded with EXTEST implemented this device.
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
TEST-LOGIC RESET SELECT IR-SCAN CAPTURE-DR SHIFT-DR EXIT1-DR PAUSE-DR EXIT2-DR UPDATE-DR EXIT2-IR UPDATE-IR CAPTURE-IR SHIFT-IR EXIT1-IR PAUSE-IR
REUN-TEST/ IDLE
SELECT DR-SCAN
Figure Controller State Diagram [11]
Note: next each state represents value rising edge TCK.
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Bypass Register Selection Circuitry Selection Circuitry
Instruction Register
Identification Register
Boundary Scan Register [12]
Controller
Figure Controller Block Diagram
Electrical Characteristics Over Operating Range
Parameter VOLC VOHC VOLT VOHT Description Input High (Logic Voltage Input (Logic Voltage Input Leakage Current Input Leakage Current Output Leakage Current LVCMOS Output Voltage[13, LVCMOS Output High Voltage LVTTL Output Voltage
[13] [13] [13, [13, [13,
Test Conditions
Min. -0.3
Max.
Unit
Output disabled, VCCQ IOLC IOHC IOLT IOHT
-5.0 -5.0
LVTTL Output High Voltage
Notes: configuration; configuration. Voltage referenced (GND). Overshoot: VIH(AC)<VCC+1.5V KHKH/2, Undershoot: (AC)<-0.5V t<tKHKH/2, Power-up: VIH<3.6V VCC<3.135V VCCQ<1.4V t<200 During normal operation, VCCQ must exceed VCC. Control input signals (such R/W, ADV/LD, etc.) have pulse widths less than tKHKL (min.). This parameter sampled.
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Switching Characteristics Over Operating Range [16,
Parameter Clock tTHTH tTHTL tTLTH Output Times tTLQX tTLQV tDVTH tTHDX Set-up Times tMVTH Hold Times tTHMX Hold Capture Hold Set-up Capture Set-up Unknown Valid Valid HIGH HIGH Invalid Clock Cycle Time Clock Frequency Clock HIGH Time Clock Time Description Min. Unit
Notes: refer set-up hold time requirements latching data from boundary scan register. Test conditions specified using load Test Conditions.
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Timing Test Conditions
1.5V
INPUT PULSES 3.0V 1.5V
THTL
TLTH
TEST CLOCK (TCK)
TEST MODE SELECT (TMS)
TEST DATA (TDI)
TEST DATA (TDO)
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Identification Register Definitions
Instruction Field REVISION NUMBER (31:28) DEVICE DEPTH (27:23) DEVICE WIDTH (22:18) RESERVED (17:12) CYPRESS JEDEC CODE (11:1) Register Presence Indicator 256K XXXX 00110 00100 XXXXXX 00011100100 512K XXXX 00111 00011 XXXXXX 00011100100 Description Reserved revision number. Defines depth 256K 512K words. Defines width bits. Reserved future use. Allows unique identification DEVICE vendor. Indicates presence register.
Scan Register Sizes
Register Name Instruction Bypass Boundary Scan Size (x36) Size (x18)
Instruction Codes
Instruction EXTEST Code Description Captures ring contents. Places boundary scan register between TDO. Forces device outputs High-Z state. This instruction IEEE 1149.1-compliant. Preloads register with vendor code places between TDO. This instruction does affect device operations. Captures ring contents. Places boundary scan register between TDO. Forces device outputs High-Z state. these instructions; they reserved future use. Captures ring contents. Places boundary scan register between TDO. This instruction does affect device operations. This instruction does implement IEEE 1149.1 PRELOAD function therefore 1149.1-compliant. these instructions; they reserved future use. these instructions; they reserved future use. Places bypass register between TDO. This instruction does affect device operations.
IDCODE SAMPLE-Z RESERVED SAMPLE/PRELOAD
RESERVED RESERVED BYPASS
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Boundary Scan Order (256K
Bit# Signal Name ADSP ADSC TQFP Bump
Boundary Scan Order (256K (continued)
Bit# Signal Name MODE TQFP Bump
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Boundary Scan Order (512K
Bit# Signal Name ADSP ADSC TQFP Bump
Boundary Scan Order (512K (continued)
Bit# Signal Name MODE TQFP Bump
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Voltage Supply Relative -0.5V +4.6V .-0.5V VCC+0.5V Storage Temperature (plastic) .-55°C +150° Junction Temperature .+150° Com'l Power Dissipation 1.0W Short Circuit Output Current.
Operating Range
Range Ambient Temperature[18] +70°C 3.3V -5%/+10%
Electrical Characteristics Over Operating Range
Parameter VIHD VCCQ VCCQ Input (Logic Voltage Input Leakage Current MODE Input Leakage Current Output Leakage Current Output High Voltage[13] Output Voltage[13] Supply Voltage
[13] [13] [13] [20] [13,
Description Input High (Logic Voltage
[13,
Test Conditions Data Inputs (DQx) Other Inputs Output(s) disabled, VOUT -5.0
Min. -0.5
Max. VCC+0.3
Unit
3.135 3.135 2.375 -4.4 -6.7
Supply Voltage (3.3V) Supply Voltage (2.5V)
Parameter
Description Power Supply Current: Operating[21, CMOS Standby[22,
Conditions Device selected; inputs VIH; cycle time min.; Max.; outputs open Device deselected; Max.; inputs >VCC 0.2; inputs static; frequency Device deselected; inputs VIH; inputs static; MAX; frequency Device deselected; inputs VIH; Max. cycle time Min.
Typ.
Unit
ISB2
ISB3
Standby[22,
ISB4
Clock Running[22,
Capacitance[15]
Parameter Description Input Capacitance Input/Output Capacitance (DQ) Test Conditions 25°C, MHz, 3.3V Typ. Max. Unit
Notes: case temperature. Overshoot: +6.0V Undershoot:VIL -2.0V Output loading specified with CL=5 Test Loads. given with output current. increases with greater output loading faster cycle times. "Device Deselected" means device Power-Down mode defined truth table. "Device Selected" means device active. Typical values measured 3.3V, 25°C, cycle time.
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Thermal Resistance
Description Test Conditions Symbol TQFP Typ. Unit °C/W °C/W Thermal Resistance (Junction Ambient) Still Air, soldered 4.25 1.125 inch, 4-layer Thermal Resistance (Junction Case)
Test Loads Waveforms 3.3V
1.5V 3.3V INPUT PULSES 3.0V
Test Loads Waveforms 2.5V
2.5V 1.25V INPUT PULSES
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Switching Characteristics Over Operating Range[24]
-4.4 Parameter Clock tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ Hold Times Address, Controls, Data In[28]
Min.
Min.
-6.7 Min.
Description Clock Cycle Time Clock HIGH Time Clock Time Clock Output Valid Clock Output Invalid Clock Output Low-Z Output Valid
[27] [15,
Min.
Max.
Max.
Max.
Max.
Unit
Output Times VCCQ 3.3V VCCQ 2.5V
1.25 1.25 1.25 1.25 1.25 1.25 1.25 1.25
Clock Output High-Z [15, VCCQ 3.3V VCCQ 2.5V Output Low-Z
[15, [15,
Output High-Z
Set-up Times Address, Controls, Data In[28]
Typical Output Buffer Characteristics
Output High Voltage -0.5 1.25 Pull-Up Current (mA) Min. (mA) Max. -105 -105 -105 Output Voltage -0.5 1.25 Pull-Down Current (mA) Min. (mA) Max.
Notes: Test conditions specified with output loading shown part Test Loads unless otherwise noted. Output loading specified with CL=5 part Test Loads. given temperature voltage condition, tKQHZ less than tKQLZ tOEHZ less than OELZ. "Don't Care" when byte write enable sampled LOW. This synchronous device. synchronous inputs must meet specified setup hold time, except "Don't Care" defined truth table.
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Switching Waveforms
Read Timing[29,
ADSP#
ADSC#
ADDRESS BWa#, BWb#, BWc#, BWd# BWE#,
ADV#
tKQLZ tOELZ
Q(A1)
tOEQ
Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1)
SINGLE READ
BURST READ
Notes: active this timing diagram means that chip enables CE2, active. only available package version. product, there only byte write control.
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Switching Waveforms (continued)
Write Timing[29,
ADSP#
ADSC#
ADDRESS BWa#, BWb#, BWc#, BWd#, BWE#
ADV#
tKQX tOEHZ
D(A1) D(A2) D(A2+1) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2)
SINGLE WRITE
BURST WRITE
BURST WRITE
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Switching Waveforms (continued)
Read/Write Timing[29,
ADSP#
ADSC#
ADDRESS BWa#, BWb#, BWc#, BWd#, BWE#,
ADV#
Q(A1) Single Reads
Q(A2)
D(A3) Single Write
Q(A4)
Q(A4+1) Burst Read
Q(A4+2)
D(A5)
D(A5+1)
Burst Write
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Ordering Information
Speed (MHz) Ordering Code CY7C1366A-225AJC/ GVT71256C36T-4.4 CY7C1366A-225AC/ GVT71256C36TA-4.4 CY7C1366A-225BGC/ GVT71256C36B-4.4 CY7C1366A-200AJC/ GVT71256C36T-5 CY7C1366A-200AC/ GVT71256C36TA-5 CY7C1366A-200BGC/ GVT71256C36B-5 CY7C1366A-166AJC/ GVT71256C36T-6 CY7C1366A-166AC/ GVT71256C36TA-6 CY7C1366A-166BGC/ GVT71256C36B-6 CY7C1366A-150AJC/ GVT71256C36T-6.7 CY7C1366A-150AC/ GVT71256C36TA-6.7 CY7C1366A-150BGC/ GVT71256C36B-6.7 Package Name A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 Package Type 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 119-Lead 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 119-Lead 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 119-Lead 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 119-Lead Operating Range Commercial
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Ordering Information (continued)
Speed (MHz) Ordering Code CY7C1367A-225AJC/ GVT71512C18T-4.4 CY7C1367A-225AC/ GVT71512C18TA-4.4 CY7C1367A-225BGC/ GVT71512C18B-4.4 CY7C1367A-200AJC/ GVT71512C18T-5 CY7C1367A-200AC/ GVT71512C18TA-5 CY7C1367A-200BGC/ GVT715152C18B-5 CY7C1367A-166AJC/ GVT715152C18T-6 CY7C1367A-166AC/ GVT71512C18TA-6 CY7C1367A-166BGC/ GVT71512C18B-6 CY7C1367A-150AJC/ GVT71512C18T-6.7 CY7C1367A-150AC/ GVT71512C18TA-6.7 CY7C1367A-150BGC/ GVT71512C18B-6.7 Package Name A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 A101 A101 BG119 Package Type 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 119-Lead 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 119-Lead 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 119-Lead 100-Lead Thin Quad Flat Pack 100-Lead Thin Quad Flat Pack 119-Lead Operating Range Commercial
Document 38-01011-*B
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Package Diagrams
100-Pin Thin Plastic Quad Flatpack A101
51-85050-A
CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18
Package Diagrams (continued)
119-Lead BG119
51-85115
Cypress Semiconductor Corporation, 2001. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

GVT71512C18

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