GF9330 GF9331
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GF9330 High Performance HDTV/SDTV Deinterlacer
GF9330 Data Sheet Features
10/8-bit progressive scan output 1080p60 support multiplexed non-mutiplexed video multi-directional edge detection processing adaptive inter-field motion detection seamless interface Gennum's GF9331 motion coprocessor fully configurable support custom video modes film mode operation HDTV/SDTV inputs programmable noise reduction detail enhancement de-interlace, pass-through film rate down conversion modes operation seamless interface popular ADCs NTSC/PAL decoders ability extract information from embedded selectable rounding clipping output data selectable blanking active video lines output signals with programmable output video cropping serial/parallel host interface 3.3V supply device 2.5V core logic tolerant inputs
Device Overview
GF9330 10-bit high performance VDSP engine that performs high quality motion adaptive de-interlacing interlaced digital video signals. GF9330 supports standard definition (SDTV) high definition (HDTV) signal formats clock rates 1080p60 with support arbitrary display modes. GF9330 uses multi-directional adaptive filters edge processing, adaptive vertical motion filter adaptive inter-field motion filter. GF9330 features detail enhancement noise reduction capabilities. GF9330 also supports pull-down, static/freeze-frame detection compensation film rate conversions. GF9330 operate stand-alone de-interlacer used with GF9331 Motion Co-processor enable higher quality de-interlacing with edge vertical motion detection. devices configured tandem such that GF9331 sends edge detection vertical motion filter control information GF9330. These control signals adaptively switch GF9330's internal filters pixel-by-pixel basis. GF9330 integrates required line delays seamlessly interfaces chip SDRAMs that form required field delays. device also operate by-pass mode should processing input signal desired.
Applications
HDTV Up/Down Converters Production Equipment Video Walls Projection Systems Plasma Displays Home Theatre Systems Players
Ordering Information
Part Number
GF9330-CBP
Package
Temp. Range
70oC
Control from GF9331
Timing Generator
Pulldown Detector Edge Adaptive Interpolator
Input Processing
Noise Reducer Detail Enhancer
Vertical Motion Adaptive Interpolator Selector Inter-field Motion Adaptive Interpolator Output Processing Processed
Field Merging Host Interface Inter-field Motion Detector External Memory Interface
Block Diagram
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GF9330 Data Sheet
Contents
Contents Descriptions Electrical Characteristics Tolerant Inputs Tolerance 3.3V Supply Device 2.5V Core Logic Detailed Device Description Supported Input Video Formats Input Synchronization Seamless Interface GF9331 Motion Co-processor Directional Filter Control Seamless Interface External SDRAMs Host Interface Closed Caption Blanking Programmable Noise Reduction Detail Enhancement RESET Modes Operation 3.10 Output Data Formats 3.11 Sequence Detection Package Dimensions Revision History
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GF9330 Data Sheet
Descriptions
RESET
S2_DAT0
S2_DAT2
S2_DAT4
S2_DAT8
S2_DAT12
S2_DAT16
S2_DAT20
S2_DAT25
S2_DAT29
S2_DAT36
S2_CLK
S2_DAT44
S2_ADDR0
S2_ADDR4
S2_ADDR8
S2_ADDR12
S2_CS
S2_WE
VCLK_OUT
Y_IN9 S2_DAT1 S2_DAT3 S2_DAT5 S2_DAT9 S2_DAT13 S2_DAT17 S2_DAT21 S2_DAT26 S2_DAT30 S2_DAT35 S2_DAT39 S2_DAT43 S2_DAT47 S2_ADDR3 S2_ADDR7 S2_ADDR11 S2_CAS S2_RAS LOCK_32
Y_IN8 Y_IN7 Y_IN6 S2_DAT6 S2_DAT10 S2_DAT14 S2_DAT18 S2_DAT22 S2_DAT27 S2_DAT31 S2_DAT34 S2_DAT38 S2_DAT42 S2_DAT46 S2_ADDR2 S2_ADDR6 S2_ADDR10 S2_ADDR13 XSEQ1 XSEQ0
Y_IN5 Y_IN4 Y_IN3 S2_DAT7 S2_DAT11 S2_DAT15 S2_DAT19 S2_DAT23 S2_DAT28 S2_DAT32 S2_DAT33 S2_DAT37 S2_DAT41 S2_DAT45 S2_ADDR1 S2_ADDR5 S2_ADDR9 Y1_OUT11 XSEQ3 XSEQ2
Y_IN2 Y_IN1 Y_IN0 HOST_EN VDD_INT VDD_IO S2_DAT24 VDD_IO VDD_INT S2_DAT40 VDD_IO Y1_OUT8 Y1_OUT9 Y1_OUT10
VCLK_IN MODE2 MODE1 MODE0 VDD_CLKD VDD_INT VDD_IO VDD_IO VDD_INT Y1_OUT4 Y1_OUT5 Y1_OUT6 Y1_OUT7
SER_MD STD4 STD3 STD2 VSS_CLKD VDD_INT
VIEW GF9330
TGND TGND TGND TGND
VDD_INT
Y1_OUT0
Y1_OUT1
Y1_OUT2
Y1_OUT3
MEMCLK_IN STD1 STD0 XVOCLK_SL
Y2_OUT8
Y2_OUT9
Y2_OUT10
Y2_OUT11
XVOCLK_IN LOCK_22 C_IN9 C_IN8 VDD_IO
VDD_IO
Y2_OUT4
Y2_OUT5
Y2_OUT6
Y2_OUT7
C_IN7 C_IN6 C_IN5 C_IN4 TGND TGND TGND TGND Y2_OUT1 Y2_OUT2 Y2_OUT3
C_IN0 C_IN1 C_IN2 C_IN3 VDD_INT TGND TGND TGND TGND Y2_OUT0 C1_OUT11 C1_OUT10
FIL_SEL0 FIL_SEL1 FIL_SEL2 FIL_SEL3 TGND TGND TGND TGND VDD_IO C1_OUT9 C1_OUT8 C1_OUT7 C1_OUT6
FVH_EN F_IN V_IN H_IN VDD_IO C1_OUT5 C1_OUT4 C1_OUT3 C1_OUT2
FF_EN VDD_INT C1_OUT1 C1_OUT0 C2_OUT11 C2_OUT10
DAT_IO4 DAT_IO5 DAT_IO6 DAT_IO7 VDD_INT VDD_IO VDD_IO VDD_INT C2_OUT9 C2_OUT8 C2_OUT7 C2_OUT6
DAT_IO0 DAT_IO1 DAT_IO2 DAT_IO3 VDD_INT VDD_IO S1_DAT41 VDD_IO VDD_INT S1_DAT25 VDD_IO C2_OUT5 C2_OUT4 C2_OUT3
S1_ADDR6 S1_ADDR2 S1_DAT46 S1_DAT42 S1_DAT37 S1_DAT34 S1_DAT33 S1_DAT29 S1_DAT24 S1_DAT20 S1_DAT16 S1_DAT12 S1_DAT8 C2_OUT2 C2_OUT1 C2_OUT0
TCLK S1_ADDR13 S1_ADDR10 S1_ADDR7 S1_ADDR3 S1_DAT47 S1_DAT43 S1_DAT38 S1_DAT35 S1_DAT32 S1_DAT28 S1_DAT23 S1_DAT19 S1_DAT15 S1_DAT11 S1_DAT7 S1_DAT4 F_OUT H_OUT
S1_RAS S1_CAS S1_ADDR11 S1_ADDR8 S1_ADDR4 S1_ADDR0 S1_DAT44 S1_DAT39 S1_DAT36 S1_DAT31 S1_DAT27 S1_DAT22 S1_DAT18 S1_DAT14 S1_DAT10 S1_DAT6 S1_DAT3 S1_DAT1 V_OUT
S1_WE S1_CS S1_ADDR12 S1_ADDR9 S1_ADDR5 S1_ADDR1 S1_DAT45 S1_DAT40 S1_CLK S1_DAT30 S1_DAT26 S1_DAT21 S1_DAT17 S1_DAT13 S1_DAT9 S1_DAT5 S1_DAT2 S1_DAT0
GND/TGND: VDD_IO: +3.3V VDD_INT: +2.5V Connection
Figure 1-1: View
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GF9330 Data Sheet
Table 1-1: Descriptions Symbol
RESET VCLK_IN
Grid
Type
Description
Active low, asynchronous RESET. Resets internal logic default conditions. Should applied power Video input clock. When input SDTV input clock will 72MHz. When input format HDTV, input clock will 74.25 74.25/ 1.001MHz. Memory clock SDRAM operation support modes, 90MHz input (supplied off-chip crystal oscillator). External video output clock. This input used instead internal VCLK_IN clock doubler supply video output clock VCLK_OUT. Control signal input. When HIGH, selects XVOCLK_IN; when LOW, selects internal VCLK_IN clock doubler generation video output VCLK_OUT signal. 10/8-bit input separate luminance multiplexed luminance colour difference video data. When supplying 8-bit data GF9330, Y_IN[1:0] will 8-bit data supplied Y_IN[9:2]. 10/8-bit input colour difference video data. When supplying 8-bit data GF9330, C_IN[1:0] will 8-bit data supplied C_IN[9:2]. Filter selection control bus. FIL_SEL[3:0] used switch GF9330's internal directional filters pixel pixel basis. FIL_SEL[3:0] supplied GF9331. Video timing control. F_IN identifies EVEN fields incoming video signal. F_IN will Field HIGH Field Video timing control. V_IN represents vertical blanking signal associated with incoming video signal. V_IN HIGH during vertical blanking interval during active video. Video timing control. H_IN represents horizontal blanking signal associated with incoming video signal. H_IN HIGH during horizontal blanking during active video. Control signal input. When HIGH, F_IN, V_IN, H_IN input pins will used video data signalling. When LOW, embedded TRS's will detected video data timing. Control signal input. When HIGH, FF_EN enables GF9330's internal freeze frame compensation. 3.11.4 Static Freeze Frame Detection/ Compensation. Control signal input. pull-down compensation, LOCK_22 will used identify presence sequence input video stream. Video format definition. Defines video standard when operating without host interface. Table 3-1: Encoding STD[4:0] Selecting Input Data Format. Operating mode selection. Defines mode operation when operating without host interface. Modes Operation.
MEMCLK_IN XVOCLK_IN XVOCLK_SL
Y_IN[9:0]
C_IN[9:0]
FIL_SEL[3:0]
F_IN V_IN
H_IN
FVH_EN
FF_EN
LOCK_22 STD[4:0]
MODE[2:0]
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GF9330 Data Sheet
Table 1-1: Descriptions (Continued) Symbol
HOST_EN
Grid
Type
Description
Host interface enable. When HIGH, GF9330 will configured through host interface. high transition HOST_EN GF9330 will replace register settings host interface with values present external pins device including: STD[4:0], MODE[2:0], FVH_EN, FF_EN XVOCLK_SL. Host interface mode selection. Enables serial mode operation when HIGH. Enables parallel mode operation when LOW. Functions active chip select input host interface parallel mode operation. Functions serial clock input host interface serial mode operation. Host interface bi-directional data parallel mode. serial mode, DAT[7] serves serial data output DAT[0] serves serial data input pin. Host interface Read/Write control parallel mode. read cycle defined when HIGH, write cycle defined when LOW. Host interface Address/Data control parallel mode. data contains address when HIGH, data word when LOW. serial mode, this serves chip select (active low). Video output clock. Output frequency based selected output standard. Modes Operation. Output data separate luminance multiplexed luminance colour difference video data. 3.10.2 12-bits Output Resolution. Output data luminance video data during dual pixel mode operation. 3.10.2 12-bits Output Resolution. Output data colour difference video data. 3.10.2 12-bits Output Resolution.
SER_MD
DAT_IO[7:0]
VCLK_OUT Y1_OUT[11:0]
D18, E20, E19, E18, F20, F19, F18, F17, G20, G19, G18, H20, H19, H18, H17, J20, J19, J18, J17, K20, K19, K18, L19, L20, M17, M18, M19, M20, N17, N18, N19, N20, P17, P19, P20, R17, R18, R19, R20, T18, T19, T20, U18, U19,
Y2_OUT[11:0]
C1_OUT[11:0]
C2_OUT[11:0]
Output data colour difference video data during dual pixel mode operation. 3.10.2 12-bits Output Resolution. Control signal output. When GF9330's internal algorithm detects sequence video stream LOCK_32 signal HIGH. Otherwise, LOCK_32 LOW. Control signal input/output. external sequence detection, XSEQ[3:0] pins will used provide sequence information. internal detection XSEQ[3:0] pins output detected sequence information. Figure 3-12: Sequence Detection Input Signals. Output control signal. H_OUT HIGH during horizontal blanking. Output control signal. F_OUT during field HIGH during field Output control signal. V_OUT HIGH during vertical blanking. SDRAM bank clock. Active SDRAM chip select Field Buffer
LOCK_32
XSEQ[3:0]
D19, D20, C19,
H_OUT F_OUT V_OUT S1_CLK S1_CS
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GF9330 Data Sheet
Table 1-1: Descriptions (Continued) Symbol
S1_RAS S1_CAS S1_WE S1_ADDR[13:0]
Grid
W10, V10, U10, U11, V11, W11, Y11, U12, V12, W12, Y12, T13, U13, V13, W13, Y13, U14, V14, W14, Y14, U15, V15, W15, Y15, U16, V16, W16, Y16, U17, V17, W17, Y17, V18, W18, Y18, W19, C18, A17, B17, C17, D17, A16, B16, C16, D16, A15, B15, C15, D15, B14, C14, D14, A13, B13, C13, D13, E13, B12, C12, D12, A11, B11, C11, D11, D10, C10, B10, A10, E10, E15, F15, J16, M16, R15, T10,
Type
Description
Active SDRAM address strobe Field Buffer Active SDRAM column address strobe Field Buffer Active SDRAM write enable Field Buffer SDRAM address Field Buffer
S1_DAT[47:0]
SDRAM data Field Buffer
S2_CLK S2_CS S2_RAS S2_CAS S2_WE S2_ADDR[13:0]
SDRAM bank clock. Active SDRAM chip select Field Buffer Active SDRAM address strobe Field Buffer Active SDRAM column address strobe Field Buffer Active SDRAM write enable Field Buffer SDRAM address Field Buffer
S2_DAT[47:0]
SDRAM data Field Buffer
TCLK VDD_CLKD VSS_CLKD VDD_IO
JTAG data input; connect used. JTAG mode select; connect used. JTAG test clock; connect used. JTAG data output. 2.5V supply internal clock doubler. Ground connection internal clock doubler. 3.3V supply.
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GF9330 Data Sheet
Table 1-1: Descriptions (Continued) Symbol
VDD_INT
Grid
E12, F16, G16, P16, R16, E11, E14, E16, F14, G15, H16, K16, L16, N16, P15, T11, T14, T16, J10, J11, J12, K10, K11, K12, L10, L11, L12, M10, M11, M12, E17, K17, L17,
Type
2.5V supply.
Description
TGND
Device ground Thermal ground (electrically equivalent).
connection.
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GF9330 Data Sheet
Electrical Characteristics
Tolerant Inputs
Input cells used design able withstand 3.3V CMOS input signals without degrading performance long-term reliability well compatible inputs.
Tolerance
GF9330 protection. testing done accordance with Gennum's standard testing procedure.
3.3V Supply Device 2.5V Core Logic
GF9330 operates from single +3.3V supply device I/O, single +2.5V supply core logic.
Table 2-1: Absolute Maximum Ratings Parameter
Device Supply Voltage Device Core Supply Voltage Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering seconds) 70oC -40oC 125oC 260oC
Symbol
VDDIO VDDCORE
Value
-0.5 -0.5 -0.5 +4.6V
Table 2-2: Electrical Characteristics VDDIO 3.6V, VDDCORE 2.25 2.75V, 70oC, unless otherwise shown. Parameter
Device Supply Voltage Device Core Supply Voltage Device Supply Current Device Core Supply Current Input Leakage Current VDDIO=3.3V VDDCORE=2.5V IIN=0V IIN=VDD
Conditions
Symbol
VDDIO VDDCORE IDDIO IDDCORE ILEAK
+3.0 +2.25
+3.3 +2.5
+3.6 +2.75
Units
Notes
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GF9330 Data Sheet
Table 2-2: Electrical Characteristics (Continued) VDDIO 3.6V, VDDCORE 2.25 2.75V, 70oC, unless otherwise shown. Parameter
Tristate Leakage Current Input Logic Voltage Input Logic HIGH Voltage Output Logic Voltage Output Logic HIGH Voltage IOL= IOH= -4mA
Conditions
Symbol
ITRILEAK
Units
Notes
Production, test performed room temperature.
Table 2-3: Electrical Characteristics Video Interfaces Video Interface signals include: VCLK, Y_IN[9:0}, C_IN[9:0}, FIL_SEL[3:0], F_IN, V_IN, H_IN, FVH_EN, FF_EN, LOCK_22, Y1_OUT[11:0], Y2_OUT[11:0], C1_OUT[11:0], C2_OUT[11:0], LOCK_32, XSEQ[3:0], H_OUT, F_OUT V_OUT. VDDIO 3.6V, VDDCORE 2.25 2.75V, 70oC, unless otherwise shown. Parameter
Clock Input Frequency Input Data Setup Time Input Data Hold Time Input Clock Duty Cycle Output Data Delay Time VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load
Conditions
Symbol
FHSCI
74.25
10.0
Units
Notes
Output Data Hold Time
Output Enable Time
tOEN
Output Disable Time
tODIS
Output Data Rise/Fall Time
tODRF
a.Based simulation results, verified during device characterization process. b.Also supports 74.25/1.001MHz. c.50% levels. d.20% levels.
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GF9330 Data Sheet
Table 2-4: Electrical Characteristics SDRAM Interfaces SDRAM Interface signals include S1_CLK, S1_CS, S1_RAS, S1_CAS, S1_WE, S1_ADDR[13:0] S1_DAT[47:0]. SDRAM Interface signals include S2_CLK, S2_CS, S2_RAS, S2_CAS, S2_WE, S2_ADDR[13:0] S2_DAT[47:0]. VDDIO 3.6V, VDDCORE 2.25 2.75V, 70oC, unless otherwise shown. Parameter
Clock Input Frequency Input Data Setup Time Input Data Hold Time Input Clock Duty Cycle Output Data Delay Time VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load tOD_SD
Conditions
Symbol
FHSCI_SD tSU_SD tIH_SD
Units
Notes
Output Data Hold Time
tOH_SD
Output Enable Time
tOEN_SD
Output Disable Time
tODIS_SD
Output Data Rise/Fall Time
tODRF_SD
a.Based simulation results, verified during device characterization process. b.50% levels. c.Two clock cycles allocated data turnaround. d.20% levels.
Table 2-5: Electrical Characteristics Host Interfaces Host Interface signals include HOST_EN, SER_MD, DAT_IO[7:0], A_D. VDDIO 3.6V, VDDCORE 2.25 2.75V, 70oC, unless otherwise shown. Parameter
Clock Input Frequency Input Data Setup Time Input Data Hold Time Input Clock Duty Cycle Output Data Delay Time VDDIO=3.6V, CL=15pF load tOD_HI
Conditions
Symbol
FHSCI_HI tSU_HI tIH_HI
10.0
Units
Notes
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GF9330 Data Sheet
Table 2-5: Electrical Characteristics Host Interfaces (Continued) Host Interface signals include HOST_EN, SER_MD, DAT_IO[7:0], A_D. VDDIO 3.6V, VDDCORE 2.25 2.75V, 70oC, unless otherwise shown. Parameter
Output Data Hold Time
Conditions
VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load VDDIO=3.6V, CL=15pF load
Symbol
tOH_HI
Units
Notes
Output Enable Time
tOEN_HI
Output Disable Time
tODIS_HI
Output Data Rise/Fall Time
tODRF_HI
a.Based simulation results, verified during device characterization process. b.50% levels. c.20% levels.
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GF9330 Data Sheet
Detailed Device Description
Supported Input Video Formats
GF9330 supports multiple input data formats with multiplexed separate channels. Data supplied GF9330 through Y_IN[9:0] C_IN[9:0] busses. Table 3-1: Encoding STD[4:0] Selecting Input Data Format outlines data formats that supported according setting control register bits STD[4:0] NOTE: progressive video standards GF9330 must manually bypass mode (MODE[2:0] 111). Host Interface details.
Table 3-1: Encoding STD[4:0] Selecting Input Data Format
STD[4:0]
00000
Description
525i (30/1.001) component SMPTE 125M. Multiplexed YCbCr data applied Y_IN. C_IN LOW. NOTE: Input clock 27MHz.
00001 00010
Reserved 525i (30/1.001) component 16x9 SMPTE 267M. Multiplexed YCbCr data applied Y_IN. C_IN LOW. NOTE: Input clock 36MHz.
00011 00100
Reserved 625i (25Hz) component tech. 3267E. Multiplexed YCbCr data applied Y_IN. C_IN LOW. NOTE: Input clock 27MHz.
00101 00110
Reserved 625i (25Hz) component 16x9 ITU-R BT.601-5 Part Multiplexed YCbCr data applied Y_IN. C_IN LOW. NOTE: Input clock 36MHz.
00111 01000
Reserved 525p (60/1.001Hz) SMPTE 293M. YCbCr data stream applied Y_IN. C_IN LOW. NOTE: Input clock 54MHz.
01001 01010 01011 01100
Reserved Reserved Reserved 625p (50Hz) ITU-R BT.1358. YCbCr data stream applied Y_IN. C_IN LOW. NOTE: Input clock 54MHz.
01101
625p (50Hz) with 18MHz sampling. YCbCr data stream applied Y_IN. C_IN LOW. NOTE: Input clock 72MHz.
01110
Generic input data format with 4:1:1 sampling. YCbCr data applied both Y_IN C_IN. Externally supplied F_IN, V_IN H_IN signals used synchronize input data stream. NOTE: Input clock 27MHz.
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GF9330 Data Sheet
Table 3-1: Encoding STD[4:0] Selecting Input Data Format (Continued)
STD[4:0]
01111
Description
Generic input data format with 4:2:2 sampling single multiplexed YCbCr input format. YCbCr data applied Y_IN. C_IN LOW. Externally supplied F_IN, V_IN H_IN signals used synchronize input data stream. NOTE: Input clock 36MHz.
10000
720p 60/1.001Hz) SMPTE 296M-2001. Data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25 74.25/1.001MHz.
10001
720p 30/1.001Hz) SMPTE 296M-2001. Data applied Y_IN. data applied C_IN. NOTE: Input clock 74.2 74.2/1.001MHz.
10010
1080p 30/1.001Hz) SMPTE 274M. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
10011
720p (50Hz) SMPTE 296M-2001. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
10100
1080p (25Hz) SMPTE 274M. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
10101
720p (25Hz) SMPTE 296M-2001. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
10110
1080p 24/1.001Hz) SMPTE 274M. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
10111
720p 24/1.001Hz) SMPTE 296M-2001. Data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
11000
1080i 30/1.001Hz) SMPTE 274M. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
11001
1080p 30/1.001Hz Segmented Frame Format) SMPTE RP211-2000. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
11010
1080i (25Hz) SMPTE 274. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
11011
1080p Segmented Frame Format) SMPTE RP211-2000. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
11100
1080i (25Hz) SMPTE 295M. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
11101
1080p 24/1.001Hz Segmented Frame Format) SMPTE RP211-2000. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
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GF9330 Data Sheet
Table 3-1: Encoding STD[4:0] Selecting Input Data Format (Continued)
STD[4:0]
11110
Description
1035i (30Hz) SMPTE 260M. data applied Y_IN. data applied C_IN. NOTE: Input clock 74.25MHz.
11111
Generic input data format with 4:2:2 sampling separate format. data applied Y_IN. data applied C_IN. Externally supplied F_IN, V_IN H_IN signals used synchronize input data stream. NOTE: Input clock 74.25MHz 74.25/1.001MHz.
Input Synchronization
GF9330 obtains relevant timing information from either embedded information externally supplied H_IN, V_IN F_IN signals. When FVH_EN HIGH, using either host interface external pin, GF9330 relies externally supplied H_IN, V_IN F_IN signals timing information. When FVH_EN LOW, GF9330 will extract embedded timing information from video data stream will ignore timing information present F_IN, V_IN H_IN pins.
3.2.1 Support Both 8-bit 10-bit Input Data
GF9330 supports 10-bit input data. When operating with 8-bit input data, LSBs GF9330's 10-bit input should input data applied MSBs input bus.
3.2.2 Generic Input Format Signalling
GF9330 supports generic input data formats with either 4:1:1 4:2:2 sampling structures handling 2046 active samples line with total maximum line width 4096 (active blanking) samples. addition, there limit 2048 lines interlaced frame. following host interface parameters used describe generic input data format relative F_IN, V_IN H_IN signals. Figure 3-1: Generic Input Format Definition.
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GF9330 Data Sheet
OUTPUT H_BLANK_SIZE EVEN FIELD V_BLANK_SIZE_EVEN FIELD
FIELD
F_OFFSET_ODD V_OFFSET_ODD FIELD V_BLANK_SIZE_ODD EVEN FIELD
EVEN FIELD
F_OFFSET_EVEN V_OFFSET_EVEN EVEN FIELD FIELD
Figure 3-1: Generic Input Format Definition
3.2.2.1 OUTPUT H_BLANK_SIZE This parameter defines number samples that comprise horizontal blanking region. This parameter maximum value 4095 less than total line width (active blanking) sample size. Twelve bits within host interface dedicated this parameter. GF9330 only stores processes active video samples only (i.e. H_IN=0). 3.2.2.2 V_BLANK_SIZE_ODD This parameter defines number lines that comprise vertical blanking interval that follows field. This parameter maximum value 255. Eight bits within host interface dedicated this parameter. GF9330 only stores processes active video samples (i.e. V_IN=0). Figure 3-1: Generic Input Format Definition. 3.2.2.3 V_BLANK_SIZE_EVEN This parameter defines number lines that comprise vertical blanking interval that follows even field. This parameter maximum value 255. Eight bits within host interface dedicated this parameter. GF9330 only stores processes active video samples (i.e. V_IN=0). Figure 3-1: Generic Input Format Definition.
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GF9330 Data Sheet 3.2.2.4 V_OFFSET_ODD This defines number lines from V_IN transition active video field region. This parameter maximum value 255. Eight bits within host interface dedicated this parameter. This parameter been added accommodate video decoders which that output non-standard timing V_IN signal. Figure 3-2: Vertical Offset Definition.
Last active line H_IN Vertical Blanking Region
V_IN
V_OFFSET_ODD/EVEN
Figure 3-2: Vertical Offset Definition
3.2.2.5 V_OFFSET_EVEN This parameter defines number lines from V_IN transition even active video field region. This parameter maximum value 255. Eight bits within host interface dedicated this parameter. This parameter been added accommodate video decoders that output nonstandard timing V_IN signal. Figure 3-2: Vertical Offset Definition. 3.2.2.6 F_OFFSET_ODD This defines number lines from F_IN transition vertical blanking interval following field. This parameter maximum value 255. Eight bits within host interface dedicated this parameter. This parameter been added accommodate video decoders that output nonstandard timing F_IN signal. Figure 3-1: Generic Input Format Definition. 3.2.2.7 F_OFFSET_EVEN This register defines number lines from F_IN transition vertical blanking interval following even field. This parameter maximum value 255. Eight bits within host interface dedicated this parameter. This parameter been added accommodate video decoders which output non-standard timing F_IN signal. Figure 3-1: Generic Input Format Definition. 3.2.2.8 H_POLARITY This register defines polarity H_IN pin. With H_POLARITY LOW, falling transition H_IN indicates active video. With H_POLARITY HIGH, rising transition H_IN indicates active video. within host interface dedicated this parameter.
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GF9330 Data Sheet 3.2.2.9 F_POLARITY This register defines polarity F_IN pin. Refer Table 3-2: F_POLARITY F_POLARITY encoding. within host interface dedicated this parameter.
Table 3-2: F_POLARITY F_POLARITY Register
F_IN
F_IN Function
Even Field Field Field Even Field
3.2.2.10 V_POLARITY This register defines polarity V_IN pin. With V_POLARITY LOW, falling transition V_IN indicates active video. With V_POLARITY HIGH, rising transition V_IN indicates active video. within host interface dedicated this parameter.
Seamless Interface GF9331 Motion Co-processor Directional Filter Control
GF9330 operate stand-alone motion adaptive de-interlacer operate conjunction with GF9331 Motion Co-processor. GF9331 contains adaptive multi-directional edge detection vertical motion detection. Control signals back directly GF9330. These control signals adaptively switch GF9330's internal edge vertical motion de-interlacing filters pixel pixel basis. These control signals GF9330 GF9331 over FIL_SEL[3:0] control bus. When GF9330 being used with GF9331, FIL_SEL[3:0] inputs should LOW. NOTE: When using GF9331, Y_IN[9:0] GF9330 must connected Y_OUT[9:0] GF9331 C_IN[9:0] GF9330 must connected C_OUT[9:0] GF9331. FIL_SEL[3:0] GF9330 must also connected FIL_SEL[3:0] GF9331. timing information from GF9331 provided exclusively through F_OUT, H_OUT V_OUT pins which must connected F_IN, H_IN V_IN pins GF9330.
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GF9330 Data Sheet
Seamless Interface External SDRAMs
video formats, GF9330 requires 24-bit (min.) SDRAM field buffers. pass video formats bypass mode, GF9330 requires field buffers, each implemented with 48-bit (min.) SDRAM configuration. deinterlace formats, memory requirements increase 48-bit (min) SDRAM configuration.
Table 3-3: SDRAM Configuration Format Bypass Configuration Banka Total ADDR BANKb SDRAM properties (per bank) Min. Freq. (MHz)
Recomended
Min. Access Time (ns)
Latency
1(1Mx24) 1(1Mx24 1(1Mx48) 1(1Mx48)
Micron: MT48LC4M16A2, MT48LC8M16A2
a.There b.This assuming 8-column structure.
Host Interface
GF9330 provides both serial parallel host interface control port configuration internal parameters. GF9330 also able operate standalone mode, with host interface control. stand-alone mode, video standard (STD[4:0]) mode operation (MODE[2:0]) using dedicated pins device. These values loaded into device falling transition HOST_EN after setting RESET LOW. Both serial parallel interfaces share common pins described Table Host Interface Common Pins.
Table 3-4: Host Interface Common Pins GF9330 NAME
DAT_IO[0] DAT_IO[1] DAT_IO[2] DAT_IO[3] DAT_IO[4]
PARALLEL MODE
CHIP select Data/address (bit Data/address (bit Data/address (bit Data/address (bit Data/address (bit
SERIAL MODE
SCLK Serial Clock Serial data (not used) (not used) (not used) (not used)
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GF9330 Data Sheet
Table 3-4: Host Interface Common Pins (Continued) GF9330 NAME
DAT_IO[5] DAT_IO[6] DAT_IO[7] HOST_EN SER_MD
PARALLEL MODE
Data/address (bit Data/address (bit Data/address (bit Address/data select Read/write select Host Interface enable Parallel mode enable
SERIAL MODE
(not used) (not used) Serial data Serial chip select (not used) Host Interface enable HIGH Serial mode enable
3.5.1 Host Interface Serial Mode
Gennum Serial Peripheral Interface (GSPI) wire interface comprised serial data (SDI), serial data (SDO), active serial chip select (SCS) clock (SCLK). interface operates master/slave configuration, where master provides SCLK, SDI, signals slave slaves. master uC_SDO drives slave(s) input. tristate output that allows multiple devices drive master uC_SDI. Serial mode operation supports both continuous clock burst clock configuration. serial mode interface illustrated Figure 3-3: Host Interface Serial Mode.
MASTER (uC) SLAVE (GF9330)
uC_SCLK
SCLK (CS)
uC_SDO
DAT_IO[0]
uC_SDI
DAT_IO[7]
uC_SCS
(A_D) ASIC Name
Figure 3-3: Host Interface Serial Mode
3.5.1.1 Serial Command Word Description command word consists 16-bit word transmitted first contains read/write bit, Auto-Configure control bit, nine reserved bits 5-bit address. shown Figure 3-4: Serial Command Word Representation.
Figure 3-4: Serial Command Word Representation
indicates Read command HIGH, write command when LOW.
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GF9330 Data Sheet 3.5.1.2 Auto-Configure Auto-Configure feature will executed when Auto-Configure control set. Auto-Configure registers will updated their appropriate settings based current video standard operational mode. When setting Auto-Configure bit, command word should with only remaining bits should complete Auto-Configuration additional bits must loaded into device. state these bits either HIGH LOW. Before Auto-Configuring device, standard mode must using either host interface (HOST_EN external pins (with falling transition HOST_EN). This simplifies configuration while allowing customization many features format parameters. 3.5.1.3 Serial Data Word Description serial data word consists 16-bit word shown Figure 3-5: Serial Data Word Representation. Serial data transmitted received first.
Figure 3-5: Serial Data Word Representation
Both command data words clocked into GF9330 rising edge serial clock (SCLK), which operate either continuous burst fashion. first (MSB) serial output (SDO) available following last falling SCLK edge "read" command word. remaining bits clocked falling edges SCLK. 3.5.1.4 Serial Write Operation write cycles consist command word followed data word, both transmitted GF9330 SDI. first 16-bit word transmitted following falling transition command word. Several write cycles performed while LOW. Figure 3-6: Write Cycle.
tSU_HI
SCLK
tIH_HI tSU_HI
Figure 3-6: Write Cycle
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GF9330 Data Sheet 3.5.1.5 Serial Read Operation read cycles consist command word transmitted GF9330 followed data word transmitted from GF9330 SDO. first 16-bit word transmitted following falling transition command word. Several read cycles performed while LOW. Figure 3-7: Read Cycle.
OEN_HI
SCLK
tOD_HI tODIS_HI
Figure 3-7: Read Cycle
3.5.2 Host Interface Parallel Mode
Gennum Parallel Peripheral Interface (GPPI) consists 8-bit multiplexed address/data (DAT_IO[7:0]), chip select (CS), read/write (R_W), address/data (A_D) shown Figure 3-8: Parallel Peripheral Interface.
MASTER (uC) SLAVE (GF9330)
uC_CS
uc_ADDR/DAT
DAT_IO[7:0]
uC_R/W
uC_A/D
ASIC Name
Figure 3-8: Parallel Peripheral Interface
Data strobed in/out parallel interface falling edge GF9330 drives DAT_IO[7:0] when HIGH LOW, otherwise this port high impedance state.
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GF9330 Data Sheet 3.5.2.1 Parallel Address Word Description 8-bit address word loads address accessed allows AutoConfigure set. Auto-Configure bit, followed reserved bits 5-bit address shown Figure 3-9: Parallel Address Word Representation.
Figure 3-9: Parallel Address Word Representation
3.5.2.2 Parallel Write Operation write cycle parallel interface shown Figure 3-10: Write Cycle Parallel Interface. First 8-bit address word provided DAT_IO asserting HIGH. address word contains auto-update flag, which allows automatic configuration predefined registers. LSB's address word contain address location read write operation. remaining address bits DAT_IO[6:5] reserved. address word registered falling edge Following this, driven data words sent upper byte (UB) word first each clocked falling edge 8-bit data words must follow each address word occupy each 16-bit parameter, which defined Figure 3-11: Host Interface Register Allocation.
tOEN_HI
DAT_IO[7:0]
ADDRESS
(UB) DATA_IN
(LB) DATA_IN
ADDRESS
(UB) DATA_OUT
(LB) DATA_OUT
tSU_HI
tIH_HI
tODIS_HI
Figure 3-10: Write Cycle Parallel Interface
3.5.2.3 Parallel Read Operation read cycle begins with address write asserting HIGH. address clocked falling edge Following address, must driven HIGH driven allow upper byte data clocked first falling edge followed lower byte second falling edge
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GF9330 Data Sheet
CLK_X1_SEL
VOCLK_X1_SEL
START_OPERATION EXT_MEMCLK_SEL
Address
ADD_LINES_TOP_F2 ADD_LINES_BOTTOM_F1 ADD_LINES_BOTTOM_F2 V_FIELD1_LASTLINE(11:0) V_BLANK1_LASTLINE(11:0) OUTPUT_H_BLANK_SIZE(11:0) OUTPUT_H_LINE_SIZE(12:0) OM_MODE(2:0) FDC_MODE(1:0) ACTIVE_PIXEL_LINE(10:0) ACTIVE_LINE_FIELD(10:0) V_BLANK_SIZE_ODD(7:0) V_BLANK_SIZE_EVEN(7:0) NO_LINE_DELAYS(9:0)
FIELD2_HAS_TOP_LINE PROGRESSIVE_INPUT H_BLANK_SIZE_1HALF
CMD_RESET
Address
V_FIELD2_LASTLINE(11:0) V_BLANK2_LASTLINE(11:0)
Address
Address
F_VBI1_OFFSET(3:0) F_VBI2_OFFSET(3:0)
Address
FRAME_REGEN
ID_MODE(1:0) FORMAT_SD V_BLANK_OFFSET
ODD_FIELD_ONE_MORE EVEN_FIELD_ONE_MORE
DIFF3T(15:0)
DIFF3T(18:16)
MSF(15:0)
MSF(18:16)
M32(15:0) CROP_V_CROP_SIZE(11:0) CROP_V_FRAME_SIZE(11:0) CROP_H_CROP_SIZE(11:0) CROP_H_LINE_SIZE(11:0) DETAIL_ENH(9:0) TV32(7:0) CC_BLANK_START_LINE(7:0) TVSF(7:0) MD_THRESHOLD V_OFFSET_ODD(7:0) F_OFFSET_ODD(7:0) V_POLARITY CL_RND(2:0) SEQUENCE(3:0) LOCK_32 FF_DETECT F_POLARITY FVH_EN_BIT CROP_EN CC_BLANK_EN MODE_32 MODE(2:0) SOBEL_THRESHOLD(3:0)
M32(18:16)
Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address
FREEZE_FRAME_THRESHOLD CC_BLANK_END_LINE(7:0) THSF(7:0) NOISE_RED(7:0) V_OFFESET_EVEN(7:0) F_OFFESET_EVEN(7:0) MD_MODE(1:0) FF_EN_BIT STD(4:0) FF_MODE(1:0)
H_POLARITY
Address Address Address Address Address Address Address Address Address
Figure 3-11: Host Interface Register Allocation
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GF9330 Data Sheet
3.5.3 Control Register Definitions
host interface internal registers divided into three classes: User Configurable (UC), Auto-Configurable (AC), Read-Only (RO). Address locations through contain parameters which configured user. Locations through automatically configured based STD[4:0] MODE[2:0] registers, user configured desired. Address contains three status registers LOCK_32, FF_DETECT, SEQUENCE[3:0] which only read. Writing read-only registers will have effect their contents.
Table 3-5: Control Register Definitions Address
Location
Register Name
STD[4:0] MODE[2:0]
Class
Description
Defines video standard described Supported Input Video Formats. Defines GF9330 operating mode: 000: Interlaced Progressive Mode 001: Field Merging Mode 010: Film Rate Down Conversion Mode 011: Film Rate Down Conversion (Progressive Segmented Frame) Mode 111: Bypass Mode (Video Pass Through Mode)
Default
00000
11:8
SEQUENCE[3:0] FF_DETECT LOCK_32
Provides detected field sequence number from detection circuit. video freeze frame been detected. video sequence been detected.
Calculated Calculated Calculated
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GF9330 Data Sheet
Table 3-5: Control Register Definitions (Continued) Address
Location
Register Name
FF_MODE[1:0]
Class
Description
Defines freeze frame operating mode: Manual freeze frame detection/compensation Automatic freeze frame detection/compensation (default value) Disabled Reserved
Default
FF_EN_BIT
Enables disables freeze frame detection compensation when manual freeze frame mode, i.e. FF_MODE Defines motion detection compensation mode: Disabled Automatic Reserved Reserved
MD_MODE[1:0]
MODE_32
Selects internal sequence detection when otherwise uses external sequence from input pins, XSEQ[3:0]. Enables blanking close captioned video region. Defines clipping rounding output format: 000: 12-bit output with 10.2 (.25 lsb) resolution 001: 10-bit output clipped/rounded from 1023 010: 10-bit output clipped/rounded from 4-1019 011: 10-bit output clipped/rounded from 940, Cr/Cb clipped/rounded from 100: Reserved 101: 8-bit output clipped/rounded from 110: 8-bit output rounded/clipped from 111: 8-bit output clipped/rounded from 235, Cr/Cb clipped/rounded from
10:8
CC_BLANK_EN CL_RND[2:0]
CROP_EN
Enables output video cropping based CROP_V_CROP_SIZE, CROP_V_FRAME_SIZE, CROP_H_CROP_SIZE CROP_H_LINE_SIZE parameters. Enables GF9330 external control place embedded TRS. Defines polarity F_IN pin. When '1', follows normal convention where F_IN field 1(odd) field (even). Defines polarity V_IN pin. When '1', V_IN follows normal convention where V_IN vertical blanking region. Defines polarity H_IN pin. When '1', H_IN follows normal convention where horizontal blanking region.
FVH_EN_BIT F_POLARITY
V_POLARITY
H_POLARITY
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GF9330 Data Sheet
Table 3-5: Control Register Definitions (Continued) Address
Location
Register Name
F_OFFSET_EVEN[7:0]
Class
Description
Defines number lines from F_IN transition vertical blanking interval following even field. This parameter maximum value 255. Defines number lines from F_IN transition vertical blanking interval following field. This parameter maximum value 255. Defines number lines from V_IN transition even active video field region. This parameter maximum value 255. Defines number lines from V_IN transition active video field region. This parameter maximum value 255. upper five bits this parameter adjust noise reduction level applied video image, resolution adjustment defined lower 3-bits: Noise Reduction NOISE_RED[7:3] NOISE_RED[2:0] X=1|2|4 higher value represents more noise reduction with greater resolution.
Default
00000000
15:8
F_OFFSET_ODD[7:0]
00000000
V_OFFSET_EVEN[7:0]
00000000
15:8
V_OFFSET_ODD[7:0]
00000000
NOISE_RED[7:0]
00100001
15:8
STANDARD CONFIGURATION REGISTERS FF_DET_HV[15:0]
Must default value.
01000100
15:0
Freeze frame detection setting. 3.11.4 Static Freeze Frame Detection/Compensation
IE32H
CC_BLANK_END_ LINE[7:0]
Defines last line number which closed captioned blanking. this parameter, line defined first active line field/frame. Defines first line number which start closed captioned blanking. this parameter, line defined first active line field/frame. Defines freeze frame detection threshold, value causes noise have larger impact freeze frame detection. Defines threshold detection vertical motion between consecutive fields. higher value will increase sensitivity.
0000000
15:8
CC_BLANK_START_ LINE[7:0] FREEZE_FRAME_ THRESHOLD[4:0]
00000000
10000 decimal) 00101000 decimal)
15:9
TV32[7:0]
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GF9330 Data Sheet
Table 3-5: Control Register Definitions (Continued) Address
Location
Register Name
STANDARD CONFIGURATION REGISTERS DETAIL_ENH[9:0]
Class
Description
Must default value.
Default
100100
15:6
Defines detail enhancement configuration. upper five bits this word adjust high frequency detail image. lower 5-bits control resolution granularity. higher value represents more detail with higher granularity. Detail Enhancement DETAIL_ENH[9:5] DETAIL_ENH[4:0]
00000000
11:0 11:0 11:0
CROP_H_LINE_SIZE [11:0]
CROP_H_CROP_SIZE [11:0]
Specifies length line output, following cropped pixels left side line. Specifies number active pixels blank beginning each line. Specifies number lines output, following cropped lines frame field). Specifies number active lines blank beginning each frame. Must default value.
00000000 0000 00000000 0000 00000000 0000 00000000 0000 00080H (128 decimal) Calculated
CROP_V_FRAME_ SIZE[11:0]
11:0
CROP_V_CROP_ SIZE[11:0]
14,13
2:0, 15:0
STANDARD CONFIGURATION REGISTERS MSF[18:0]
16,15
2:0, 15:0
Represents number pixels smallest active field divided scaling factor required estimate same frame detection. higher value also means vertical edges will have more effect detection same frames. equation follows:
2:0, 15:0
DIFF3T[18:0]
Represents number active pixels smallest field divided factor required estimate even pattern detection. equation follows: DIFF3T
Calculated
V_BLANK_SIZE_ EVEN[7:0]
Defines number lines that comprise vertical blanking interval that follows even input field. This parameter maximum value 255. Defines number lines that comprise vertical blanking interval that follows input field. This parameter maximum value 255. Defines number active lines smallest input field.
Auto
15:8
V_BLANK_SIZE_ ODD[7:0]
Auto
10:0
ACTIVE_LINE_ FIELD[10:0]
Auto
15:12
V_BLANK_OFFSET [3:0]
pull-down compensation, this parameter must provide difference any) number input active lines frame number output active lines frame.
Auto
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GF9330 Data Sheet
Table 3-5: Control Register Definitions (Continued) Address
Location
10:0
Register Name
ACTIVE_PIXEL_ LINE[10:0]
Class
Description
Defines number active pixels video input line.
Default
Auto
FORMAT_SD
Used configure GF9330 SDRAM controller. when 24-bit mode. This auto-configured based standard mode selection. When `1', configures GF9330 accept progressive video format. This auto-configured based standard mode selection. Defines type video sequence input video demultiplexing. When "00" input represents 4:2:2 sequence, "01" represents 4:1:1 sequence, "10" represents format. This word auto-configured based video standard mode. Defines number horizontal blanked input words line which corresponds times number blanking pixels line 4:2:2 modes equal number pixels line formats. This value auto-configured. Reserved output video formats requiring equivalent pixel line size resolution. This occurs MODE only. when field line first line video frame (SMPTE 260M). video standards that have even number lines frame (SMPTE 295M). video standards that have even number lines frame (SMPTE 295M).
Auto
PROGRESSIVE_ INPUT
Auto
15:14
ID_MODE[1:0]
Auto
11:0
INPUT_H_BLANK_ WORDS_PER_LINE [11:0]
Auto
H_BLANK_SIZE_ 1HALF
Auto
FIELD2_HAS_TOP_ LINE
Auto
EVEN_FIELD_ONE_ MORE ODD_FIELD_ONE_ MORE
Auto Auto
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GF9330 Data Sheet
Table 3-5: Control Register Definitions (Continued) Address
Location
Register Name
NO_LINE_DELAYS [9:0]
Class
Description
Defines number line delays implement within external field delay. This value auto-configured based standard mode. calculation No_line_delays (Total number lines frame
Default
Auto
11:10
FDC_MODE[1:0]
Defines field delay controller mode output video formatting: mode 24PsF
Auto
15:13
FRAME_REGEN OM_MODE[2:0]
Defines frame timing regeneration. This occurs 30i-24p 30i-24PsF modes. Defines GF9330 video output mode: 000: bypass 001: field merging 010: 011: 100: bypass 101: field merging 110: 111: This value auto-configured based standard mode.
Auto Auto
12:0
OUTPUT_H_LINE_ SIZE[11:0]
Represents total number pixels (Active plus blanking) output line. Defines number blanking pixels line output. Defines number lines wait before rising transition vertical blanking interval output. Defines last line first blanking interval, where line first blank line vertical blanking interval that precedes field first frame. Defines number lines wait before falling transition vertical blanking interval output. Defines last line first active video field.
Auto
11:0 15:12
OUTPUT_H_BLANK _SIZE[11:0]
F_VBI2_OFFSET[3:0]
Auto Auto Auto
11:0
V_BLANK1_LASTLINE [11:0]
15:12 11:10
F_VBI1_OFFSET[3:0]
Auto Auto
V_FIELD1_LASTLINE [11:0]
14:12 11:10 14:12
ADD_LINES_BOTTOM V_BLANK2_LASTLINE [11:0]
Defines number lines bottom field (not used). Defines last line second blanking interval. Defines number lines bottom field (not used).
Auto Auto Auto
ADD_LINES_BOTTOM
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GF9330 Data Sheet
Table 3-5: Control Register Definitions (Continued) Address
Location
11:0
Register Name
V_FIELD2_LASTLINE [11:0]
Class
Description
Defines last line second active video field.
Default
Auto
14:12
ADD_LINES_TOP_F2 EXT_MEMCLK_SEL
Defines number lines field (not used). Controls selection SDRAM clock source. VCLK_IN frequency less than MHz, internal clock doubler used, other modes external source required (MEMCLK_IN). Normally modes where output video clock equal input video clock frequency cases where output video clock double video input clock frequency. Normally modes other cases. Using external F_IN, V_IN H_IN signals, this parameter must following completion programming F_IN, V_IN H_IN offsets. Forces GF9330 enter reset state. This commanded reset remains effect until this parameter cleared with subsequent command.
Auto Auto
VOCLK_X1_SEL
Auto
CLK_X1_SE START_OPERATION
Auto
CMD_RESET
Closed Caption Blanking
GF9330 provides blanking function selected input video lines. Consecutive lines within each input field blanked when this function enabled, beginning with CC_BLANK_START_LINE ending with CC_BLANK_END_LINE. blanking applied prior processing video data. blanking function enabled with CC_BLANK_EN bit. BLANK_START_LINE BLANK_END_LINE each allocated 8-bits within host interface.
Programmable Noise Reduction Detail Enhancement
GF9330 performs efficient technique high frequency noise reduction detail enhancement. There levels control provided NOISE_RED[7:0] bits within host interface. High frequency details that detected with two-dimensional high pass filter enhanced using non-linear function mapping between input output signal. There levels control provided DETAIL_ENH[9:0] bits within host interface.
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GF9330 Data Sheet
RESET
RESET will reset internal logic it's default conditions when LOW. power recommended reset device ensure internal registers their default state. When applying reset, GF9330 will load STD[4:0] MODE[2:0] settings from external pins. further configuration done, these settings will used operation device.
Modes Operation
GF9330 supports stand-alone, co-processor enabled, pass-through film rate down conversion modes operation. Table 3-6: Modes Operation: MODE[2:0] shows basic operating modes GF9330 selected using MODE[2:0] control bits through host interface using MODE[2:0] register, Address [0][7:5].
Table 3-6: Modes Operation: MODE[2:0] Mode
Description
Motion adaptive de-interlacing input video signal. De-interlacing input video signal with pull-down compensation. Film rate down conversion mode (60Hz 24Hz). Film rate down conversion mode (60Hz 24Hz Segmented Frame) Reserved Video pass through mode.
3.9.1 De-Interlacing Mode (MODE=000)
When operate de-interlacer GF9330 operate "stand-alone" device performing motion adaptive processing. enable multi-directional edge vertical motion detection GF9330 must connected GF9331 described Seamless Interface GF9331 Motion Co-processor Directional Filter Control. Segmented frame progressive frame conversion also supported this mode. This function performed when progressive segmented frame input video format selected either external pins host interface register STD[4:0].
3.9.2 De-interlacing Mode with Pull-down Compensation (MODE=001)
When operate this mode, GF9330 operate "stand-alone" device performing motion adaptive processing with added pull-down compensation. enable multi-directional edge vertical motion detection GF9330 must connected GF9331 described Seamless Interface GF9331 Motion Co-processor Directional Filter Control.
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GF9330 Data Sheet GF9330 will provide sequence compensation (field merging) film source material. When using internal sequence detection, GF9330 will perform "field-merging" sequences, will revert processing when sequence identified. sequence internally detected (host interface bit, MODE_32 supplied external sequence pins (XSEQ[3:0]) MODE_32 HIGH. With external sequence selected, device will revert back processing external sequence pins have invalid code (i.e. XSEQ[3:0] value should changed during sixth blank line each vertical blanking interval.
Original Film Material (24p)
GF9330 Video Input (30i) SEQUENCE (XSEQ[3:0])
Figure 3-12: Sequence Detection Input Signals
3.9.3 Film Rate Down Conversion Mode (MODE= 010)
When configured operate Film Rate Down Converter, GF9330 removes sequences from input video stream outputs 24Hz progressive scan video. filtering signal performed this mode operation. external sequence pins (XSEQ[3:0]) used this mode, setting MODE_32 effect. NOTE: this mode, compensation remains effect times.
3.9.4 Film Rate Down Conversion Mode, Segmented Frame Output (MODE= 011)
This mode operates same manner Film Rate Down Converter mode, outputs progressive scan video segmented frame format.
3.9.5 Video Pass Through Mode (MODE=111)
GF9330, operating Pass-through Mode, will pass through only active portion input video signal. other ancillary data will lost from input data stream. video channel maintained bypass mode, however, processing takes place. Therefore, field buffers still chip must known programmed state.
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3.10 Output Data Formats
GF9330 supports multiple output data formats. output data format depends input format selected well defined operating mode. Table 3-7: Output Formats specifies available output formats GF9330.
Table 3-7: Output Formats Input Format De-interlacing I-to-P Convert mode=000
525i (30/1.001) SMPTE 125M 525p (60/1.001) SMPTE 293M Note: Reserved 525i (30/1.001) SMPTE 267M 16x9 Reserved 625i (25) Tech 3267 625p (50) ITU-R BT.1358 Note:
Film Rate Down-Conversion I-to-P Convert mode=010
525p (24/1.001 Note:
Bypass mode=111
Field Merging mode=001
525p (60/1.001) SMPTE 293M Note: 525p (60/1.001) 16x9 Note:
I-to-PsF Convert mode=011
525p (24/1.001) Note:
Note:
525p (60/1.001) 16x9 Note:
525p (24/1.001) 16x9 Note:
525PsF (24/1.001) 16x9 Note: Note:
625p (50) ITU-R BT.1358 (2:2 Pulldown Comp.) Note:
625p (25) (2:2 Pulldown Comp.) Note:
625PsF (25) (2:2 Pulldown Comp.) Note:
Note:
Reserved 625i (25) ITU-R BT.601 Part 625p (50) Note:
625p (50) Note:
625p (25) Note:
625PsF Note:
Note:
Reserved 525p (60/1.001) SMPTE 293M Note:
Reserved Reserved Reserved 625p (50) ITU-R BT-1358 Note:
625p (50) 16x9 Generic 4:1:1 Generic 4:2:2
Note: Note: Note:
Refer 3.2.2 Generic Input Format Signalling Refer 3.2.2 Generic Input Format Signalling
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GF9330 Data Sheet
Table 3-7: Output Formats Input Format
(Continued)
De-interlacing I-to-P Convert mode=000 Field Merging mode=001
Film Rate Down-Conversion I-to-P Convert mode=010
Bypass mode=111
I-to-PsF Convert mode=011
720p 1.001) SMPTE 296M2001
Note:
720p 1.001) SMPTE 296M2001
Note:
1080p 1.001) SMPTE 274M
Note:
720p (50) SMPTE 296M2001
Note:
1080p (25) SMPTE 274M
Note:
720p (25) SMPTE 296M2001
Note:
1080p 1.001) SMPTE 274M
Note:
720p 1.001) SMPTE 296M2001
Note:
1080i 1.001) SMPTE 274M
1080p 1.001) SMPTE 274M (System Note:
1080p 1.001) SMPTE 274M (System Note:
1080p 24/1.001) SMPTE 274M Note:
1080PsF 1.001) Draft Note:
Note:
1080PsF 30/1.001) SMPTE RP2112000
1080p 1.001) SMPTE 274M Note:
Note:
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GF9330 Data Sheet
Table 3-7: Output Formats Input Format
(Continued)
De-interlacing I-to-P Convert mode=000 Field Merging mode=001
1080p (50) SMPTE 274M (System (2:2 Pulldown Comp.) Note:
Film Rate Down-Conversion I-to-P Convert mode=010
1080p (25) SMPTE 274M (System (2:2 Pulldown Comp.) Note:
Bypass mode=111
I-to-PsF Convert mode=011
1080i (25) SMPTE 274M
1080p (50) SMPTE 274M (System Note:
Note:
1080PsF (25) SMPTE RP2112000
1080p (25) SMPTE 274M (System (PsF Note:
Note:
1080i (25) SMPTE 295M
1080p (50) SMPTE 295M (System Note:
1080p (50) SMPTE 295M (System (2:2 Pulldown Comp.) Note:
1080p (25) SMPTE 274M (System (2:2 Pulldown Comp.) Note:
Note:
1080PsF 24/1.001) SMPTE RP2112000
1080p 1.001) SMPTE 274M (System #11) (PsF Note:
Note:
1035i 1.001) SMPTE 260M
1035p (60&60/ 1.001) Note:
1035p (60&60/ 1.001) Note:
1035p (24&24/1.001) Note:
1035p (24&24/1.001) Note:
Note:
Generic 4:2:2
Refer 3.2.2 Generic Input Format Signalling
Note:
a.Y/C output multiplexed Y1_OUT[11:0]. Output Y1_OUT[11:0] Output C1_OUT[11:0]. c.Odd (first) pixel data Y1_OUT[11:0], Even (second) pixel data Y2_OUT[11:0], (first) pixel data C1_OUT[11:0], Even (second) pixel data C2_OUT[11:0]. d.These standards cannot used stand alone mode. OM_MODE[2:0] register within host interface must configured "110" order achieve output port operation described
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GF9330 Data Sheet
3.10.1 Output Video Frame Cropping
GF9330 provides programmable output video cropping both horizontal vertical directions. rectangular window within full output active frame field) selectable output, with video data outside this rectangular window cropped (set blanking level). H_OUT, V_OUT, F_OUT signals generated provide timing cropped video frame. embedded TRSs remain original positions. Output video cropping enabled with CROP_EN within host interface. Cropping horizontal direction implemented based settings CROP_H_CROP_SIZE CROP_H_LINE_SIZE. CROP_H_CROP_SIZE parameter specifies number active pixels blank beginning each line. CROP_H_LINE_SIZE parameter specifies length line output, following cropped pixels left side line. CROP_H_CROP_SIZE CROP_H_LINE_SIZE each allocated 12-bits within host interface. Cropping vertical direction implemented based settings CROP_V_CROP_SIZE CROP_V_FRAME_SIZE. CROP_V_CROP_SIZE parameter specifies number active lines blank beginning each frame. CROP_V_FRAME_SIZE parameter specifies number lines output, following cropped lines frame field). CROP_V_CROP_SIZE CROP_V_FRAME_SIZE each allocated 12-bits within host interface. Valid H_OUT, V_OUT F_OUT always present even when output signals contain embedded signals. When outputting standards with embedded TRSs, H_OUT, V_OUT F_OUT synchronized with GF9330's output data stream (V_OUT F_OUT transition sequences). Refer Figure 3-13: Output Video Cropping pictorial representation cropping function.
V_OUT VERTICAL BLANKING REGION CROP_V_CROP_SIZE HORIZONTAL BLANKING REGION
CROP_V_FRAME_SIZE
CROPPED VIDEO FRAME
AVAILABLE OUTPUT VIDEO FRAME
H_OUT CROP_H_LINE_SIZE CROP_H_CROP_SIZE
Figure 3-13: Output Video Cropping
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GF9330 Data Sheet
3.10.2 12-bits Output Resolution
output data busses 12-bits total resolution. Output data always unsigned data format. Output always offset binary data format. Relative input data stream 12-bits outputs formatted 10.2 extensions).
3.10.3 Controllable Rounding Clipping Output Data
GF9330 provides wide range round/clipping options based setting CL_RND[2:0] bits within host interface shown Table 3-8: CL_RND[2:0].
Table 3-8: CL_RND[2:0] CL_RND[2]
CL_RND[1]
CL_RND[0]
12-bit Output.
Description
channels rounded 10.2 output resolution. 10-bit Output Data clipped/rounded 1023. 10-bit Output Data clipped/rounded 1019. 10-bit Output data clipped/rounded 940. Cr/Cb clipped/rounded 960. Reserved 8-bit Output Data clipped/rounded 255. 8-bit Output Data clipped/rounded 254. 8-bit Output data clipped/rounded 235. Cr/Cb clipped/rounded 240.
3.11 Sequence Detection
GF9330 supports modes operating with respect sequence detection (internal external modes) described Table 3-9: Mode Select. host interface reserved MODE_32 bit.
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GF9330 Data Sheet
Table 3-9: Mode Select MODE_32
Internal. sequence automatically detected input data stream. GF9330 reports lock sequence information host interface registers called LOCK_32 SEQUENCE[3:0]. GF9330 also reports this information XSEQ[3:0] pins when configured outputs. External. GF9330 accepts sequence from XSEQ[3:0] pins configured inputs.
Description
3.11.1 Internal Detection
When operate internal detect mode, GF9330 automatically detect pull-down sequence incoming video data stream. sequence detected, GF9330 sets LOCK_32 control host interface `1'. LOCK_32 also asserted HIGH once sequence been detected. actual sequence information reported SEQUENCE[3:0] register within host interface XSEQ[3:0] pins. Refer Figure 3-12: Sequence Detection Input Signals pictorial representation sequence reporting.
3.11.2 External Detection
When operate external mode, user will supply sequence information XSEQ[3:0] pins. GF9330 uses this information properly deinterlace input signal perform 60Hz 24Hz conversion depending state MODE[2:0] register host interface MODE[2:0] pins. When operating this mode input sequence information relates input data stream. sequence information requires updating during first blank line vertical blanking interval, identifying sequence number following field.
3.11.3 Sequence Detection Compensation
GF9330 supports external sequence detection. LOCK_22 provided indicate presence sequence. sequence information inherently embedded interlaced video input data, identified with F_IN signal (either derived from embedded TRSs supplied from external pin). LOCK_22 signal will updated during first line each vertical blanking interval.
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GF9330 Data Sheet
3.11.4 Static Freeze Frame Detection/Compensation
GF9330 operates either disabled, automatic manual mode detection compensation freeze frame conditions within video input stream. When operate disabled mode (host interface bits, FF_MODE=10), GF9330 disables internal freeze frame detection compensation circuitry also ignores information presented FF_EN host interface bit, FF_EN_BIT. When operate automatic mode (FF_MODE[2:0]=01) GF9330 internally detects compensates freeze frame situations. When freeze frame situation detected, GF9330 reports this FF_DETECT status found host interface. This updated beginning field remains valid remainder field. When operate manual mode (FF_MODE=00) GF9330 monitors FF_EN host interface bit, FF_EN_BIT enable disable freeze frame compensation. Static freeze frame detection compensation further described Table 3-10: FF_MODE[1:0]. order manually force freeze frame detector GF9330 into freeze static freeze motion, following parameters must follows: Freeze Static: Uses temporal filter only.
7FFFh FF_DET_HV 0000h FF_EN_BIT
Freeze motion: Uses both vertical temporal filter.
0000h FF_DET_HV FFFFh FF_EN_BIT
NOTE: When using freeze motion settings when image static, there will vertical ringing along horizontal edges.
Table 3-10: FF_MODE[1:0] Host Interface FF_MODE[1:0] Register
External FF_EN
Host Interface FF_EN_BIT
Description
Manual: freeze frame detection compensation disabled Manual: perform freeze frame compensation
Automatic freeze frame detection/compensation Freeze frame detection compensation disabled Reserved
3.11.5 Motion Detection Compensation
GF9330 operates disabled automatic mode motion detection compensation. When operate disable mode (host interface bits,
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GF9330 Data Sheet MD_MODE=00), GF9330 does perform internal motion detection compensation. When operate automatic mode (MD_MODE=01) GF9330 internally detects compensates motion. Motion detection compensation control further described Table 3-11: MD_MODE[1:0].
Table 3-11: MD_MODE[1:0] Host Interface MD_MODE[1:0] Register
Description
Disabled Mode Automatic Mode Reserved Reserved
3.11.6 Processing Latency
de-interlacing mode (with exception progressive segmented frame progressive format conversion), GF9330 processing latency constant regardless input output format selection. other modes, (including progressive segmented frame progressive format conversion Film Rate Down Conversion) GF9330 processing latency unique constant regardless input output format selection. standard de-interlacing delay will field lines pixels. detection compensation both 24psf delay will frame lines pixels. bypass mode delay always lines.
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GF9330 Data Sheet
Package Dimensions
1213 151617
1.00 (3X) REF.
0.75 0.15 (X328)
24.00 REF.
27.00 0.20
4.00, (4X) 24.00 REF. 24.13 27.00 0.20
24.13
1.27
1.27
Figure 4-1: Package Dimensions
0.60 0.10
2.33 0.13
1.17 REF.
0.56 REF.
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GF9330 Data Sheet
Revision History
Version
133231
Date
June 2004 October 2002
Changes Modifications
Correction text bypass mode memories used. Changed document template. Update document information figures.
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
OPEN PACKAGES HANDLE EXCEPT STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
DATA SHEET product development phase specifications subject change without notice. Gennum reserves right remove product time. Listing product does constitute offer sale.
GENNUM CORPORATION Mailing Address: P.O. 489, Stn. Burlington, Ontario, Canada Tel. (905) 632-2996 Fax. (905) 632-5946 Shipping Address: Fraser Drive, Burlington, Ontario, Canada GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. (03) 3349-5501, Fax. (03) 3349-5505 GENNUM LIMITED Long Garden Walk, Farnham, Surrey, England TEL. (0)1252 (0)1252 Gennum Corporation assumes responsibility circuits described herein makes representations that they free from patent infringement. Copyright June 2001 Gennum Corporation. rights reserved. Printed Canada www.gennum.com
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