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FRL234R4


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P-channel 200V mos fet - P-channel 200V mos fet  
FRL234R4 - FRL234R4  

JANSR2N7278
Formerly FRL234R4
250V, 0.700 Ohm, Hard, N-Channel Power MOSFET
Description
Intersil Corporation designed series SECOND GENERATION hardened power MOSFETs both N-Channel P-Channel enhancement types with ratings from 100V 500V, 60A, resistance Total dose hardness offered 100K (Si) 1000K (Si) with neutron hardness ranging from 1E13 500V product 1E14 100V product. Dose rate hardness (GAMMA DOT) exists rates without current limiting 2E12 with current limiting. This MOSFET enhancement-mode silicon-gate power field effect transistor vertical DMOS (VDMOS) structure. specially designed processed exhibit minimal characteristic changes total dose (GAMMA) neutron (no) exposures. Design processing efforts also directed enhance survival dose rate (GAMMA DOT) exposure. Also available other radiation screening levels. web, Intersil's home page: http://www.intersil.com. Contact your local Intersil Sales Office additional information.
/Title (JANS R2N72 /Subject (4A, 250V, 0.700 Ohm, Hard, NChannel Power MOSFET) /Autho /Keywords (Intersil Corporation, Semiconductor, 250V, 0.700 Ohm, Hard, NChannel Power
Features
250V, rDS(ON) 0.700 Total Dose Meets Pre-RAD Specifications 100K (Si) Dose Rate Typically Survives (Si)/s BVDSS Typically Survives 2E12 Current Limited Photo Current Per-RAD(Si)/s Typically Neutron Maintain Pre-RAD Specifications 1E13 Neutrons/cm2 Usable 1E14 Neutrons/cm2
Ordering Information
PART NUMBER JANSR2N7278 PACKAGE TO-205AF BRAND JANSR2N7278
family TA17633. MIL-PRF-19500/604.
Symbol
Packaging
TO-205AF
©2001 Fairchild Semiconductor Corporation
JANSR2N7278 Rev.
JANSR2N7278
Absolute Maximum Ratings
25oC, Unless Otherwise Specified JANSR2N7278 0.20 UNITS W/oC
Drain Source Voltage .VDS Drain Gate Voltage (RGS 20k) VDGR Continuous Drain Current 25oC 100oC Pulsed Drain Current Gate Source Voltage. .VGS Maximum Power Dissipation 25oC 100oC Linear Derating Factor Single Pulsed Avalanche Current, 100µH, (See Test Figure). Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Operating Storage Temperature TSTG Lead Temperature (During Soldering) (Distance >0.063in (1.6mm) from Case, Max) Weight (Typical)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
Electrical Specifications
PARAMETER
25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) TEST CONDITIONS 1mA, VDS, -55oC 25oC 125oC 25oC 125oC 125V, 2.94 0.700 1.68 UNITS
oC/W oC/W
Drain Source Breakdown Voltage Gate Threshold Voltage
Zero Gate Voltage Drain Current
IDSS
200V, ±20V
25oC 125oC 25oC 125oC
Gate Source Leakage Current
IGSS
Drain Source On-State Voltage Drain Source Resistance
VDS(ON) rDS(ON)
10V,
Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Not Slash Sheet) Gate Charge Threshold Gate Charge (Not Slash Sheet) Gate Charge Source Gate Charge Drain Thermal Resistance Junction Case Thermal Resistance Junction Ambient
td(ON) td(OFF) Qg(TOT) Qg(10) Qg(TH)
125V, 31.3, 10V,
©2001 Fairchild Semiconductor Corporation
JANSR2N7278 Rev.
JANSR2N7278
Source Drain Diode Specifications
PARAMETER Forward Voltage Reverse Recovery Time SYMBOL dISD/dt 100A/µs 25oC, Unless Otherwise Specified SYMBOL (Note (Note (Notes (Note (Notes (Notes BVDSS VGS(TH) IGSS IDSS VDS(ON) rDS(ON) TEST CONDITIONS VDS, ±20V, 200V 10V, 10V, 2.94 0.700 UNITS TEST CONDITIONS UNITS
Electrical Specifications 100K
PARAMETER Drain Source Breakdown Volts Gate Source Threshold Volts Gate Body Leakage Zero Gate Leakage Drain Source On-State Volts Drain Source Resistance
NOTES: Pulse test, 300µs Max. Absolute value. Insitu Gamma bias must sampled both 10V, BVDSS
Typical Performance Curves
Unless Otherwise Specified
25oC DRAIN CURRENT
DRAIN
100µs
OPERATION THIS AREA LIMITED rDS(ON) DRAIN SOURCE VOLTAGE 10ms 100ms
CASE TEMPERATURE (oC)
FIGURE MAXIMUM CONTINUOUS DRAIN CURRENT CASE TEMPERATURE
FIGURE FORWARD BIAS SAFE OPERATING AREA
NORMALIZED THERMAL IMPEDANCE (ZJC)
0.05 0.02 0.01
SINGLE PULSE NOTES: DUTY FACTOR: t1/t2 PEAK
0.01
0.001 10-5
10-4
10-3
10-2
10-1
RECTANGULAR PULSE DURATION
FIGURE NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
©2001 Fairchild Semiconductor Corporation JANSR2N7278 Rev.
JANSR2N7278 Test Circuits Waveforms
ELECTRONIC SWITCH OPENS WHEN REACHED CURRENT TRANSFORMER BVDSS
VARY OBTAIN REQUIRED PEAK
50V-150V
FIGURE UNCLAMPED ENERGY TEST CIRCUIT
FIGURE UNCLAMPED ENERGY WAVEFORMS
td(ON)
tOFF td(OFF)
PULSE WIDTH
FIGURE RESISTIVE SWITCHING TEST CIRCUIT
FIGURE RESISTIVE SWITCHING WAVEFORMS
CHARGE
FIGURE BASIC GATE CHARGE WAVEFORM
©2001 Fairchild Semiconductor Corporation
JANSR2N7278 Rev.
JANSR2N7278 Screening Information
Screening performed accordance with latest revision effect MIL-S-19500, (Screening Information Table).
Delta Tests Limits (JANS) 25oC, Unless Otherwise Specified
PARAMETER Gate Source Leakage Current Zero Gate Voltage Drain Current Drain Source Resistance Gate Threshold Voltage NOTES: 100% Initial Reading (whichever greater). Initial Reading. SYMBOL IGSS IDSS rDS(ON) VGS(TH) TEST CONDITIONS ±20V Rated Value 25oC Rated 1.0mA (Note (Note ±20% (Note ±20% (Note UNITS
Screening Information
TEST Gate Stress Pind Burn-In Tests (Note Steady State Gate Bias (Gate Stress) 30V, 250µs Required MIL-S-19500 Group Subgroup (All Static Tests 25oC) MIL-STD-750, Method 1042, Condition Rated Value, 150oC, Time hours Delta Parameters Listed Delta Tests Limits Table MIL-STD-750, Method 1042, Condition Rated Value, 150oC, Time hours MIL-S-19500, Group Subgroups JANS
Interim Electrical Tests (Note Steady State Reverse Bias (Drain Stress)
Final Electrical Tests (Note
NOTE: Test limits identical post burn-in.
Additional Screening Tests
PARAMETER Safe Operating Area Unclamped Inductive Switching Thermal Response Thermal Impedance SYMBOL TEST CONDITIONS 200V, 10ms VGS(PEAK) 15V, 0.1mH 10ms; 25V; 500ms; 25V; 0.50 UNITS
©2001 Fairchild Semiconductor Corporation
JANSR2N7278 Rev.
JANSR2N7278 Hard Data Packages Intersil Power Transistors
JANS Hard Standard Data Package Certificate Compliance Serialization Records Assembly Flow Chart Photos Report Preconditioning Attributes Data Sheet Hi-Rel Traveler HTRB Temp Gate Stress Post Reverse Bias Data Delta Data HTRB Temp Drain Stress Post Reverse Bias Delta Data Group Group Group Group Attributes Data Sheet Attributes Data Sheet Attributes Data Sheet Attributes Data Sheet
JANS Hard Optional Data Package Certificate Compliance Serialization Records Assembly Flow Chart Photos Report Preconditioning Attributes Data Sheet Hi-Rel Traveler HTRB Temp Gate Stress Post Reverse Bias Data Delta Data HTRB Temp Drain Stress Post Reverse Bias Delta Data X-Ray X-Ray Report Group Attributes Data Sheet Hi-Rel Traveler Subgroups Data Attributes Data Sheet Hi-Rel Traveler Subgroups Data Attributes Data Sheet Hi-Rel Traveler Subgroups Data Attributes Data Sheet Hi-Rel Traveler Post Radiation Data
Group
Group
Group
©2001 Fairchild Semiconductor Corporation
JANSR2N7278 Rev.
JANSR2N7278 TO-205AF
LEAD JEDEC TO-205AF HERMETIC METAL PACKAGE
INCHES SYMBOL 0.160 0.016 0.350 0.315 0.095 0.190 0.095 0.010 0.028 0.029 0.500 0.075 0.180 0.021 0.370 0.335 0.105 0.210 0.105 0.020 0.034 0.045 0.560
MILLIMETERS 4.07 0.41 8.89 8.01 2.42 4.83 2.42 0.26 0.72 0.74 12.70 1.91 4.57 0.53 9.39 8.50 2.66 5.33 2.66 0.50 0.86 1.14 14.22 NOTES
SEATING PLANE
NOTES: These dimensions within allowable dimensions Rev. JEDEC TO-205AF outline dated 11-82. Lead dimension (without solder). Solder coating vary along lead length, typically 0.002 inches (0.05mm) solder coating. Position lead measured 0.100 inches (2.54mm) from bottom seating plane. This zone controlled automatic handling. variation actual diameter within this zone shall exceed 0.010 inches (0.254mm). Lead butt welded stem base. Controlling dimension: Inch. Revision dated 6-94.
©2001 Fairchild Semiconductor Corporation
JANSR2N7278 Rev.
TRADEMARKS
following registered unregistered trademarks Fairchild Semiconductor owns authorized intended exhaustive list such trademarks.
Quiet SeriesDISCLAIMER
FAST
PACMANPOPPowerTrench QFETQSQT OptoelectronicsQuiet SeriesSILENT SWITCHER SMART STARTStar* PowerStealth
SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTinyLogicUHCUltraFET VCX
FAIRCHILD SEMICONDUCTOR RESERVES RIGHT MAKE CHANGES WITHOUT FURTHER NOTICE PRODUCTS HEREIN IMPROVE RELIABILITY, FUNCTION DESIGN. FAIRCHILD DOES ASSUME LIABILITY ARISING APPLICATION PRODUCT CIRCUIT DESCRIBED HEREIN; NEITHER DOES CONVEY LICENSE UNDER PATENT RIGHTS, RIGHTS OTHERS.
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices critical component component life support device system whose failure perform systems which, intended surgical implant into reasonably expected cause failure life body, support sustain life, whose support device system, affect safety failure perform when properly used accordance with instructions provided labeling, effectiveness. reasonably expected result significant injury user. PRODUCT STATUS DEFINITIONS Definition Terms Datasheet Identification Advance Information Product Status Formative Design Definition This datasheet contains design specifications product development. Specifications change manner without notice. This datasheet contains preliminary data, supplementary data will published later date. Fairchild Semiconductor reserves right make changes time without notice order improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves right make changes time without notice order improve design.
Preliminary
First Production
Identification Needed
Full Production
Obsolete
Production
This datasheet contains specifications product that been discontinued Fairchild semiconductor. datasheet printed reference information only.
Rev.

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