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MC6805* - MC6805*
"Ferroelectric RAM" - "Ferroelectric RAM"
FM25160 - FM25160
FM25160 FRAM Serial Memory
16Kbit Nonvolatile Ferroelectric Organized 2,048 Power CMOS Technology 10µA Standby Over Industrial Temperature Range Standby Over Commercial Temperature Range Reliable Thin Film Ferroelectric Technology Billion (1010) Cycle Read/Write Endurance Year Data Retention High Performance Write Delay Unlimited Sequential Write
Simple Three Wire Compatible (CPOL CPHA 2.1MHz Maximum Clock Rate Multiple Levels Write Protection Hardware Write Protect Internal Write Enable Latch Block Protect Bits Voltage Lockout Protection Greater Than 2,000V Pins True Only Operation 8-Pin Mini Packages -40° +85°C Operating Range
Ramtron's FM25160 ferroelectric random access memory, FRAM® memory provides nonvolatile data integrity compact package. three wire serial interface provides access byte within memory while reducing cost processor interface compared parallel access memories). FM25160 useful wide variety applications storage configuration information, user programmable data/features, calibration data. With Ramtron's ferroelectric technology, writes nonvolatile, eliminating long delays, extra page mode control, high voltage pins. technology designed highly reliable operation, offering extended endurance year data retention. FM25160 uses industry standard three wire protocol serial chip communication. available mini-DIP packages.
Instruction Decode Clock Generator Control Logic Write Protect
Chip Select Serial Data Write Protect Ground Serial Data Serial Clock Hold Input Supply Voltage
Address Register Counter
Data In/Out Register
Nonvolatile Status Register
Ramtron reserves right change discontinue this product without notice.
1994 Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, 80921 Telephone (800) 545-FRAM, (719) 481-7000 (719) 488-9095 R1.9 June 1994
Absolute Maximum Ratings
Ambient Storage Operating Temperature Guarantee Nonvolatility Stored Data Voltage with Respect Ground D.C. Output Current Lead Temperature (Soldering, Seconds)
-40°C +85°C -1.0 +7.0V 300°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. -40°C +85°C, 5.0V 10%, Unless Otherwise Specified
Power Supply Voltage Supply Current Supply Current Standby Current 70°C Standby Current 85°C Input Leakage Current Output Leakage Current Input Voltage Input High Voltage Output Voltage Output High Voltage Input Hysteresis
2.1MHz, Read Write CMOS Levels, Other Inputs 0.3V 1.0MHz, Read Write CMOS Levels, Other Inputs 0.3V Other Inputs Other Inputs
Typical values 25°C, 5.0V. This paramter periodically sampled 100% tested.
Power Read Operation Power Write Operation
Endurance Data Retention
Endurance Data Retention
tPUR tPUW delays required from time stable until specified operation initiated. These parameters periodically sampled 100% tested.
Input Pulse Levels Input Rise Fall Times Input Output Timing Levels
Equivalent Load Circuit
OUT(2) IN(2) Output Capacitance Input Capacitance
This paramter periodically sampled 100% tested.
Hold (/HOLD) /HOLD used pause sequence must Serial Output (SO) process some other event middle operation. While /HOLD This active only during read operation. high low, FM25160 will ignore transitions impedance other times when /HOLD low. During read pins. When /HOLD high, operations will proceed normally. operation, this line driven high depending current Transitions /HOLD must occur while low. data output bit. Data clocked FM25160 falling edge serial clock. Device Operation Serial Input (SI) Data clocked into FM25160 this rising edge serial clock signal. Beyond setup hold times around this clock edge, state this ignored. However, this should driven valid logic level times prevent excessive power dissipation.
FM25160 serial ferroelectric memory designed interface easily with Serial Peripheral Interface (SPI) port common many MC6805 MC68HC11 processors. communications channel uses three wires (clock, serial data serial data out) that shared among number devices. Additionally, fourth (chip select) selects device time multiplexed that should respond access request. Serial Clock (SCK) typical system configuration shown Figure Information clocked into FM25160 using this Data transferred from FM25160 bytes eight when /HOLD high. Input values latched bits each, governed edges signal. Data transferred rising edge, while data output changes occur after falling with most significant (MSB) first. operation first edge this signal. maximum clock rate 2.1MHz. FM25160 byte transferred operation code (opcode) which completely static design, clocking interrupted determines what performed memory. There point time, clock rate arbitrarily slow. operations that performed FM25160. Table lists operation with corresponding opcode. Chip Select (/CS) When this signal low, FM25160 will respond Table Opcode Commands transitions signal. When high, inputs ignored, outputs placed high impedance state, FM25160 Opcode Description Name goes into power standby mode. high transition 0000 0110 Write Enable Latch WREN required this before each opcode.
Write Protect (/WP) This provides hardware write protect status register. When WPEN high low, then writes status register disabled. Note that operation this differs from function FM25040. FM25040, provides write protection status register FRAM memory array. function enabled WPEN status register. Figure Typical System Configuration
0000 0100 0000 0101 0000 0001 00AA A011 00AA A010
Write Disable Read Status Register Write Status Register Read Data Write Data
WRDI RDSR WRSR READ WRITE
HOLD1 HOLD2 Master Acronym Definitions MOSI: Master Slave MISO: Master Slave Slave Select
Status Register Table shows organization status register. register read using RDSR instruction. Bits through unused. When read, they return value status register transmitted directly after RDSR opcode. Executing RDSR instruction effect status register bits. (This unlike WRSR instruction which clears Write Enable Latch [WEL] bit.) WEL. function write protect status register FRAM memory array. When set, writes take place part. When reset, writes will ignored. Bits nonvolatile block protect bits (BP0 BP1). These bits provide further protection portions array specified Table Note that bytes within blocks that protected with will still only written write enable latch set. Writing status register step process: must enable write. This done using WREN instruction. WRSR instruction then used change block protect bits WPEN bit. Note that execution WRSR instruction clears bit. write protect enable latch bit. WPEN enables hardware write protect feature provided pin. When WPEN high low, then status register write protected. internal write enable latch FM25160 prevents writes data within part while cleared. /WEL protects nonvolatile memory array status register bits. automatically cleared power whenever power Table Status Register Organization
Table Memory Block Protect Bits
Protected Address Range (Hex)
(upper array) (upper array) (all array)
supply falls below 3.5V (typical). also cleared after write operations (including WRSR). user reset transmitting corresponding opcode FM25160 (WREN WRDI, respectively). address data bytes follow opcode. Note that following write enable latch instruction (WREN), chip select must rise again before write sequence started. FM25160 will ignore bits transmitted after opcode before rise /CS. Write Protection write protection features FM25160 extensive. features summarized Table lines through write protection status register disabled since WPEN low. status does matter, controls write protection unprotected blocks FRAM array together. lines same situation occurs this time fact that high. lines status register protected being WPEN being high. Line provides semi-permanent write protect feature. With low, taking WPEN high prevents further writes protected blocks status register. This only unlocked taking high. Read Write Sequences read write operation, address byte must transmitted FM25160 after opcode. Bits opcode address bits A10, respectively. Following address byte, data bytes should transferred first. number bytes read written sequential order starting with specified address, wrapping around address after byte address (hex) accessed. read write sequence continues until brought high. Note that FRAM device, number bytes written with single write sequence, while EEPROM based 25160 devices limited through four bytes only. accommodate this feature, actual write nonvolatile array takes place after eighth each byte transmitted. rises during write operation, only byte that been completely transmitted will ignored. Voltage Protection When powering FM25160 will automatically perform internal reset await high transition from master. master should wait TPUR TPUW after reaches 4.5V before selecting part. Additionally, whenever falls below 3.5V (typical), part goes into voltage protection mode. this mode, accesses part inhibited part performs internal reset. access progress when power supply fails, will automatically aborted FM25160.
Protected Unprotected Protected Unprotected Protected Unprotected Protected Unprotected
Table Write Protection
Protected Protected Protected Protected Protected Protected Protected Protected
Protected Unprotected Protected Unprotected Protected Protected Protected Unprotected
Serial Data Output Timing
Serial output timing shown Figure Data placed FM25160 serial output (SO) tODV seconds after falling edge SCK. clock frequency arbitrary with maximum clock rate 2.1MHz. This timing sequence that applies reading status register bits nonvolatile memory.
Serial Data Output Timing Parameters (4,5)
Clock Frequency Clock High Time Clock Time Chip Select Time Output Disable Time Output Data Valid Time Output Hold Time
-40°C +85°C, 5.0V ±10%, Unless Otherwise Specified Switching Times Measured from Unless Otherwise Specified
Figure Serial Data Output Timing Diagram
Serial Data Input Timing
Serial input timing shown Figure Input data latched rising edge SCL. data must valid seconds before this rising edge. addition, data must held tHLD seconds after this rising edge. This timing sequence that applies clocking opcodes, addresses, data written status register memory.
Serial Data Input Timing Parameters
tF(6) tHLD tR(6)
Deselect Time Data Fall Time Data Hold Time Chip Select Lead Time Data Rise Time Data Setup Time
-40°C +85°C, 5.0V ±10%, Unless Otherwise Specified Rise Fall Times Measured Between Points Waveform
Figure Serial Data Input Timing Diagram
Hold timing shown Figure Hold used pause timing sequence allow processor service higher priority task. Note that must during transitions /HOLD signal.
Hold Timing Parameters
Hold Hold Time Hold Setup Time HOLD High HOLD High
-40°C +85°C, 5.0V ±10%, Unless Otherwise Specified
Figure Hold Timing Diagram
detailed read protocol shown Figure sequence follows: master initiates sequence pulling low. very next rising edge begins input clocking opcode into FM25160. iii) eight opcode clocked into FM25160. Note that bits address bits A10, respectively. byte address through follows immediately. data shifted FM25160 immediately following byte address using falling edge SCK. Data continuously shifted FM25160 continually supplying clock pulses. When highest byte address read, address counter wraps zero reading continues. vii) master terminates read taking high.
Figure Read Sequence
Read Opcode Byte Address Data
detailed write protocol shown Figures sequence follows: master must enable writes FM25160 issuing WREN instruction shown Figure Note that must taken high after WREN instruction transmitted from master FM25160. master writes write opcode, byte address, number sequential bytes FM25160 shown Figure Again, operation must terminated taking high after last byte.
Figure WREN Instruction
Figure Write Sequence
Write Opcode Byte Address Data
0.41 (10.36) 0.36 (9.10)
0.30 (7.62) 0.24 (6.10)
0.065 (1.65) 0.055 (1.40) 0.310 (7.87) 0.290 (7.37) 0.17 (4.45) 0.10 (2.54) 0.20 (5.08) 0.13 (3.30) 0.165 (4.19) 0.125 (3.18) 0.100 (2.54) 0.023 (0.58) 0.015 (0.38) 0-8° 0.395 (9.37) 0.300 (7.62)
0.014 (0.36) 0.010 (0.25)
0.189 (4.80) 0.210 (5.33) 0.009 (0.23) 0.019 (0.48) 0.007 (0.18) 0.009 (0.23) 0-8°
0.149 (3.78) 0.177 (4.50) 0.053 (1.35) 0.068 (1.73)
0.013 (0.33) 0.020 (0.51)
0.004 (0.10) 0.010 (0.25) 0.228 (5.80) 0.244 (6.20) 0.016 (0.40) 0.050 (1.27)
Package Type (8-Pin) Serial FRAM Memory Ramtron Ferroelectric Memory
Ramtron International Corporation assumes responsibility circuitry other than circuitry embodied Ramtron product, does convey imply license under patent other rights. FRAM Registered Trademark Ramtron International Corporation. Copyright 1994 Ramtron International Corporation.
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