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EP220 EP224


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EP220 EP224 Classic EPLDs
1995, ver.
Features
High-performance, low-power Erasable Programmable Logic Devices (EPLDs) with macrocells Combinatorial speeds Counter frequencies Pipelined data rates Maximum 5.5-ns Clock-to-output time; minimum 4.5-ns setup time Replacement upgrade 16V8/20V8 devices inputs dedicated inputs) EP220, inputs dedicated inputs) EP224; outputs both EP220 EP224 Macrocells independently programmable both registered combinatorial logic Programmable inversion control supporting active-high activelow outputs power consumption Typical (for speed grades) Quarter-power mode (ICC Programmable zero-power mode with typical (for -10A speed grades) Programmable Security total protection proprietary designs output skew Clock driver applications 100% generically tested provide 100% programming yield Software programming support from Altera wide range third-party tools Available windowed ceramic one-time-programmable (OTP) plastic packages 20-pin plastic J-lead package (PLCC) 20-pin ceramic plastic dual in-line packages (CerDIP PDIP) 24-pin PDIP 28-pin PLCC
General Description
EPROM-based EP220 EP224 devices feature flexible architecture implement usable (300 available) gates custom user logic functions. EP220 EP224 devices used upgrades high-speed bipolar programmable logic devices (PLDs) 74-series CMOS (SSI MSI) logic devices high-performance microcomputer systems.
Altera Corporation
A-ds-220/224-01
EP220 EP224 Classic EPLDs
Compared bipolar devices equivalent speed, EP220 EP224 offer lower power consumption, faster input-to-nonregistered-output delay (tPD) combinatorial mode, higher counter frequencies registered applications. This added performance supports faster state machine designs compared bipolar devices, provides additional timing margin existing designs. EP220 EP224 ideal high-volume manufacturing high-performance systems. These devices improve performance decrease system noise, power consumption, heat generation.
Functional Description
Figure shows block diagrams EP220 EP224 device architectures. EP220 dedicated inputs pins; EP224 dedicated inputs pins.
Altera Corporation
EP220 EP224 Classic EPLDs
Figure EP220 EP224 Block Diagram
Numbers parentheses refer pin-out number.
EP220
Global Clock
INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell (19) (18) (17) (16) (15) (14) (13) (12)
Global
INPUT (11)
EP224
Global Clock
INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell (22) (21) (20) (19) (18) (17) (16) (15)
Global
INPUT (10) INPUT (11) INPUT (13) INPUT (14) INPUT (23)
EP220 EP224 architecture based sum-of-products, programmable-AND/fixed-OR structure. Each macrocell individually programmed combinatorial registered output. inversion option allows each output configured active-high active-low operation. Each programmed function input, output, bidirectional pin. EP220 EP224 device architecture offers following features:
Macrocells High-frequency, low-skew global Clock
Altera Corporation
EP220 EP224 Classic EPLDs
Macrocells
Each macrocell includes product-term block with product terms feeding gate. product term dedicated Output Enable (OE) control tri-state buffer. global logic array allows each product term connect true complement each input-36 inputs EP220, inputs EP224-and feedback signal. Figure
Figure EP220 EP224 Macrocell
Output Enable
Inversion Control Programmable Register
Feedback Logic Array Pin, I/O, Macrocell Feedback
Feedback Select
Macrocells individually configured registered combinatorial operation, providing mixed-mode operation available fixedarchitecture devices. When registered output selected, feedback from register logic array bypasses output buffer. When combinatorial output selected, feedback comes from through output buffer, used bidirectional I/O. Unlike devices, eight outputs EP220 EP224 allow combinatorial feedback signal from feed logic array. Data clocked into macrocell's register rising edge global Clock.
Altera Corporation
EP220 EP224 Classic EPLDs
gate implement active-high active-low logic, DeMorgan's inversion reduce number product terms needed implement function. EP220 EP224 register outputs require signal, internal product term hold output enabled state; global signal required, input dedicated task, eight product terms programmed accordingly.
High-Frequency, Low-Skew Global Clock
EP220 EP224 devices have extremely output-pin skew: registered output skew (tOCR) typically less than combinatorial output skew (tOSC) typically less than This output-skew rate makes EP220 EP224 devices ideal high-frequency system Clock applications, including Intel Pentium microprocessors, 486-based PCs, designs.
Compatibility
EP220 EP224 devices logical superset most high-speed, 24-pin PAL/GAL devices. Industry-standard JEDEC Files from compatible devices programmed into EP220 EP224 devices. Table summarizes some devices that replaced upgraded with EP220 EP224 devices.
Table EP220- EP224-Compatible Devices (Part
PAL/GAL Vendor
Advanced Micro Devices
PAL/GAL Device
PAL16L8 PAL16R8 PALCE16V8 PAL20L8 PAL20R8 PALCE20V8 PAL16L8 PAL16R8 PALCE16V8 PAL20L8 PAL20R8 PALCE20V8
Altera Replacement Device
EP220-7
Speed Grade
EP224-7
EP220-10
EP224-10
Altera Corporation
EP220 EP224 Classic EPLDs
Table EP220- EP224-Compatible Devices (Part
PAL/GAL Vendor
Advanced Micro Devices (continued)
PAL/GAL Device
PAL16L8D PAL16R8D PAL16R8-7 PALCE16V8 PAL20L8-10 PAL20R8-10 PAL20R8-7 PALCE20V8 PAL16L8 PAL16R8 PALCE16V8 PAL20L8 PAL20R8 PALCE20V8
Altera Replacement Device
EP220-10A
Speed Grade
-10A
EP224-10A
EP220-12
EP224-12
Lattice Semiconductor Corp.
GAL16V8B GAL20V8B GAL16V8A GAL16V8B GAL20V8A GAL20V8B
EP220-7 EP224-7 EP220-10 EP224-10 EP220-7 EP220-10
National Semiconductor
PAL16L8 PAL16R8 PAL16L8 PAL16R8 GAL16V8A PAL20L8 PAL20R8 GAL20V8A PAL16L8D PAL16R8D GAL16V8A PAL20L8D PAL20R8D GAL20V8A
EP224-10
EP220-10A
-10A
EP224-10A
Altera Corporation
EP220 EP224 Classic EPLDs
Table EP220- EP224-Compatible Devices (Part
PAL/GAL Vendor
National Semiconductor (continued)
PAL/GAL Device
PAL16L8 PAL16R8 GAL16V8A PAL20L8 PAL20R8 GAL20V8A
Altera Replacement Device
EP220-12
Speed Grade
EP224-12
Philips Semiconductor
PLUS16L8 PLUS16R8 PLUS20L8 PLUS20R8 PLUS16L8 PLUS16R8 PLUS20L8 PLUS20R8 PLUS16L8D PLUS16R8D PLUS16R8-7 PLUS20L8-10 PLUS20R8-10 PLUS20R8-7 PLUS16L8 PLUS16R8 PLUS20L8 PLUS20R8-
EP220-7 EP224-7 EP220-10 EP224-10 EP220-10A
-10A
EP224-10A
EP220-12 EP224-12 EP220-7 EP224-7 EP220-10 EP224-10 EP220-10A
Texas Instruments, Inc.
TIBPAL16L8 TIBPAL20L8 TIBPAL16L8 TIBPAL20L8 TIBPAL16L8-10 TIBPAL16R8-10 TIBPAL16R8-7 TIBPAL20L8-10 TIBPAL20R8-10 TIBPAL20R8-7
-10A
EP224-10A
Altera Corporation
EP220 EP224 Classic EPLDs
Table EP220- EP224-Compatible Devices (Part
PAL/GAL Vendor
Texas Instruments, Inc. (continued)
PAL/GAL Device
TIBPAL16L8 TIBPAL16R6 TIBPAL16R8 TIBPAL20L8 TIBPAL20R6 TIBPAL20R8
Altera Replacement Device
EP220-12
Speed Grade
EP224-12
Power-On Characteristics Design Security
EP220 EP224 inputs outputs respond maximum after power-up (VCC 4.75 after power-loss/power-up sequence. macrocells that programmed registers logic power-up. EP220 EP224 devices contain programmable Security that controls access data programmed into device. When this turned proprietary design implemented device cannot copied retrieved. This feature provides high level design security, because programmed data within EPROM cells invisible. Security that controls this function, well other program data, reset when device erased. -10A speed grades EP220 EP224 devices contain programmable Turbo control automatic power-down feature that enables low-standby-power mode CC). When Turbo turned low-standby-power mode disabled. values tested with Turbo turned When device operating with Turbo turned (non-turbo mode), non-turbo adder must added appropriate parameter determine worst-case timing. non-turbo adder specified Operating Conditions" tables this data sheet. EP220 EP224 devices fully functionally tested guaranteed. Complete testing each programmable EPROM configuration element internal logic elements ensures 100% programming yield. Figure shows test conditions.
Turbo
Generic Testing
Altera Corporation
EP220 EP224 Classic EPLDs
Figure EP220 EP224 Test Circuits
Power-supply transients affect measurements. Simultaneous transitions multiple outputs should avoided accurate measurement. Threshold tests must performed under conditions. Large-amplitude, fast groundcurrent transients normally occur device outputs discharge load capacitances. When these transients flow through parasitic inductance between device ground test-system ground, significant reductions observable noise immunity result. Numbers parentheses EP224 device.
(330 Device Output Test System
(200
(includes capacitance)
Test programs used then erased during early stages device production flow. EPROM-based devices one-timeprogrammable, windowless packages also contain on-board logic test circuitry allow verification function specifications during production flow.
Software Programming Support
EP220 supported Altera MAX+PLUS development software, Altera programming hardware, third-party hardware. Both EP220 EP224 supported Altera PLDshell Plus design software, third-party logic compilers (e.g., ABEL, CUPL, PLDesigner, LOG/IC, iPLS II), third-party programming hardware (e.g., Data I/O). more information software support with PLDshell Plus, PLDshell Plus/PLDasm User's Guide (available from Altera Literature Department). more information MAX+PLUS MAX+PLUS Programmable Logic Development System Software Data Sheet Altera 1995 Data Book refer MAX+PLUS Help. Programming Hardware Data Sheet Programming Hardware Manufacturers Data Sheet Altera 1995 Data Book information Altera third-party programming hardware support.
Altera Corporation
EP220 EP224 Classic EPLDs
Figure shows typical supply current (ICC) versus frequency EP220 EP224 devices.
Figure EP220 EP224 Frequency
Active (mA) Typ.
Speed Grade
Turbo -10A Speed Grades Non-Turbo
Frequency (MHz)
Figure shows output drive characteristics EP220 EP224 pins.
Figure EP220 EP224 Output Drive Characteristics
Output Current (mA)
Output Voltage
Altera Corporation
EP220 EP224 Classic EPLDs
Absolute Maximum Ratings
Symbol
TSTG TAMB
Note
Conditions
Note Notes (2), Note
Parameter
Supply voltage input voltage Storage temperature Ambient temperature
-2.0 -0.5
Unit
Recommended Operating Conditions
Symbol
Input voltage Output voltage Operating temperature Operating temperature Input rise time Input fall time commercial industrial
Parameter
Supply voltage
Conditions
5.0-V operation
4.75
5.25
Unit
Operating Conditions
Symbol
Note
Conditions
Note Note
-4.0 Min. -7A, -10: Min. -10A, -12: Min. Max., Max., VOUT Max., VOUT Note
Parameter
High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input leakage current Tri-state output leakage current Output short-circuit current
-0.3
0.45
Unit
Capacitance
Symbol
COUT CCLK CVPP
Notes (5),
Parameter Conditions
VOUT VOUT (EP220) (EP224),
Unit
Input capacitance capacitance Clock capacitance capacitance
Altera Corporation
EP220 EP224 Classic EPLDs
Supply Current: EP220-7A EP224-7A
Symbol
ICC3
Note
Conditions
MHz, Note MHz, Note
Parameter
supply current
Unit
Supply Current: EP220-10A, EP224-10A, EP220-12 EP224-12
Symbol
ICC1 ICC2 ICC3
Note
Parameter
supply current (non-turbo) supply current (non-turbo) supply current (turbo, active)
Conditions
Standby mode, Note Max., GND, load, MHz, Notes (9), (10) MHz, Note MHz, Note
Unit
Supply Current: EP220-7, EP224-7, EP220-10 EP224-10
Symbol
ICC1 ICC3
Note
Parameter
supply current (standby) supply current (active)
Conditions
MHz, Note MHz, Note MHz, Note MHz, Note
Unit
Notes tables:
Operating Requirements Altera Devices Altera 1995 Data Book. Voltage with respect ground. Minimum input -0.5 During transitions, inputs undershoot -2.0 overshoot periods less than under no-load conditions. Under bias. Extended temperature versions also available. Operating conditions: commercial use. -40° industrial use. Absolute values with respect device GND; over- undershoots system tester noise included. -7A, -10A, speed grades EP220 EP224 devices: maximum (all outputs) speed grades EP220 EP224 devices: test output time; test duration should exceed These values measured during initial characterization. Max., GND. Measured with device programmed 8-bit counter. (10) When Turbo (non-turbo mode), EP220 EP224 device enters standby mode logic transitions occur approximately after last transition.
Altera Corporation
EP220 EP224 Classic EPLDs
Operating Conditions: -7A, -10A, Speed Grades Combinatorial Mode
Symbol
tPD1 tPD2 tPZX tPXZ tOSR tOSC
Note
EP220-10A EP224-10A EP220-12 EP224-12 Non-Turbo Adder
EP220-7A EP224-7A
Parameter
Input non-registered output, Note non-registered output, Note Input output enable, Note Input output disable, Note Register-mode output output skew Combinatorial-mode output output skew
Note Units
Synchronous Clock Mode
Symbol
fMAX fCNT1 fCNT2 tSU1 tCO1 tCO2 tCNT
EP220-7A EP224-7A
EP220-10A EP224-10A
EP220-12 EP224-12
Non-Turbo Adder
Parameter
Maximum frequency (pipelined), feedback, Note Maximum counter frequency, external feedback, Note Maximum counter frequency, internal feedback, Note Input setup time global clock Input hold time from global clock Global clock output delay, Note Global clock output delay through combinatorial macrocell Minimum global clock period, Note Clock time Clock high time Clock period
Note
90.9 83.3
Units
Notes tables:
Operating conditions: commercial use. -40° industrial use. device enters standby mode remains inactive approximately increase time amount shown. EP220-10A, EP220-12, EP224-10A, EP224-12 devices only. Measured with outputs switching. tPZX tPXZ parameters measured from steady-state voltage that driven specified output load. tPXZ parameter measured with with eight outputs switching.
Altera Corporation
EP220 EP224 Classic EPLDs
Operating Conditions: Speed Grades Combinatorial Mode
Symbol
tPD1 tPD2 tPZX tPXZ tOSR tOSC
Note
EP220-7 EP224-7 EP220-10 EP224-10
Parameter
Input non-registered output, inversion Note Input non-registered output, inversion off, Note Input output enable, Note Input output disable, Note Register mode output-to-output skew Combinatorial mode output-to-output skew
Units
Synchronous Clock Mode
Symbol
fMAX fCNT1 fCNT2 tSU1 tCO1 tCO2 tCNT
EP220-7 EP224-7
EP220-10 EP224-10
Parameter
Maximum frequency (pipelined), feedback, Note Maximum counter frequency, external feedback, Note Maximum counter frequency, internal feedback, Note Input setup time global clock Input hold time from global clock Global clock output delay, Note Global clock output delay through combinatorial macrocell Minimum global clock period, Note Clock time Clock high time Clock period
62.5 58.8 60.6
Units
16.5
Notes tables:
Operating conditions: commercial use. Measured with three outputs switching. tPZX tPXZ parameters measured from steady-state voltage that driven specified output load. tPXZ parameter measured with with eight outputs switching.
Altera Corporation
EP220 EP224 Classic EPLDs
Figure shows package pin-outs EP220 EP224 devices.
Figure EP220 EP224 Package Pin-Outs
Package outlines drawn scale. Windows ceramic packages only.
INPUT/CLK
INPUT
INPUT
INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
INPUT
INPUT INPUT INPUT INPUT INPUT INPUT
EP220
INPUT VCC/NC
20-Pin
20-Pin J-Lead
INPUT/CLK
INPUT
INPUT
INPUT
INPUT/CLK INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT INPUT
INPUT
INPUT INPUT INPUT INPUT INPUT INPUT INPUT
INPUT
INPUT
INPUT INPUT
24-Pin
28-Pin J-Lead
Package Outlines
Refer "Altera Device Package Outlines" Altera 1995 Data Book detailed information package outlines.
Altera Corporation
INPUT
EP220 EP224
EP224
EP220 EP224 Classic EPLDs
Product Availability
Table summarizes availability EP220 EP224 devices. Altera will accept Intel ordering codes Intel devices until June 1995. After that date, only Altera ordering codes will accepted.
Table EP220 EP224 Availability
Device
EP220
Temperature Grade
Commercial temperature
Speed Grade
-10A -10A -10A -10A -10A
Package
20-pin CerDIP 20-pin PDIP 20-pin PDIP 20-pin PDIP 20-pin PDIP 20-pin PLCC 20-pin PLCC 20-pin PLCC 20-pin PLCC 20-pin PLCC 20-pin PLCC 24-pin PDIP 24-pin PDIP 24-pin PDIP 24-pin PDIP 28-pin PLCC 28-pin PLCC 28-pin PLCC 28-pin PLCC 28-pin PLCC
Altera Ordering Code
EP220DC-10A EP220PC-7 EP220PC-10 EP220PC-10A EP220PC-12 EP220LC-7A EP220LC-10A EP220LC-12 EP220LC-7 EP220LC-10 EP220LI-12 EP224PC-7 EP224PC-10 EP224PC-10A EP224PC-12 EP224LC-7A EP224LC-10A EP224LC-12 EP224LC-7 EP224LC-10
Intel Ordering Code
D85C220-80 P85C220-7 P85C220-10 P85C220-80 P85C220-66 N85C220-100 N85C220-80 N85C220-66 N85C220-7 N85C220-10 TN85C220-66 P85C224-7 P85C224-10 P85C224-80 P85C224-66 N85C224-100 N85C224-80 N85C224-66 N85C224-7 N85C224-10
Industrial temperature (-40° EP224 Commercial temperature
2610 Orchard Parkway Jose, 95134-2020 (408) 894-7000 Applications Hotline: (800) 800-EPLD Customer Marketing: (408) 894-7104 Literature Services: (408) 894-7144
Printed Recycled Paper.
Altera, MAX, MAX+PLUS, FLEX registered trademarks Altera Corporation. following trademarks Altera Corporation: MAX+PLUS AHDL, FLEX 10K. Altera acknowledges trademarks other organizations their respective products services mentioned this document, specifically: Verilog Verilog-XL registered trademarks Cadence Design Systems, Inc. Mentor Graphics registered trademark Mentor Graphics Corporation. Synopsys registered trademark Synopsys, Inc. Viewlogic registered trademark Viewlogic Systems, Inc. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services. Copyright 1996 Altera Corporation. rights reserved.
Altera Corporation

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