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DS90C383A DS90CF383A


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DS90C383A/DS90CF383A 3.3V LVDS 24-Bit Flat Panel Display (FPD) Link-65MHz 3.3V LVDS 24-Bit Flat Panel Display (FPD) Link-65MHz
2003 3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 DS90CF383A DS90C383A 3.3V LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65
DS90C383A/DS90CF383A
3.3V LVDS 24-Bit Flat Panel Display (FPD) Link-65MHz 3.3V LVDS 24-Bit Flat Panel Display (FPD) Link-65MHz
DS90C383A/DS90CF383A CMOS/ LVDS (Low Voltage Differential Signaling) LVDS 65MHz (FPLINEFPFRAMEDRDYCNTL) LVDS 455Mbps 227MB/s DS90C383A DS90CF383A (DS90CF384
65MHz (TJCC) (65MHz 225ps 130mW (65MHzGrayscale) BiCMOS (max) (HBM)500V (EIAJ) VGASVGAXGA SXGA 1.8Gbps 227MB/s 345mV TIA/EIA-644 LVDS TSSOP SN75LVDS83 DS90C383A SN75LVDS81 DS90CF383A
DS90C383A/DS90CF383A
Order Number DS90C383AMTD DS90CF383AMTD Package Number MTD56
TRI-STATE®
National Semiconductor Corporation DS100100-06-JP
DS90C383A/DS90CF383A
(Note
(VCC) 0.3V CMOS/TTL 0.3V (VCC 0.3V) LVDS 0.3V (VCC 0.3V) LVDS MTD56 (TSSOP) DS90C383A/DS90CF383A 1.63
DS90C383A/DS90CF383A (HBM1.5k100pF) (EIAJ0200pF)
12.5mW/
500V
(VCC) (TA) (VCC) TxCLKIN mVPP
Symbol Parameter CMOS/TTL SPECIFICATIONS High Level Input Voltage Level Input Voltage Input Clamp Voltage Input Current 0.4V, 2.5V LVDS SPECIFICATIONS Differential Output Voltage Change between complimentary output states Offset Voltage (Note Change between complimentary output states Output Short Circuit Current Output TRI-STATE® Current Conditions 0.79 1.125 1.25 1.375 VOUT Power Down VOUT 100, Worst Case Pattern (Figures 100, Grayscale Pattern (Figures 32.5 37.5 32.5 37.5 Units
TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case
ICCTG
Transmitter Supply Current Grayscale
ICCTZ
Transmitter Supply Current Power Down
Power Down Driver Outputs TRI-STATE under Power Down Mode
Note Note Note Note
(Typ) 3.3VTA
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DS90C383A/DS90CF383A
Symbol TCIT TCIP TCIH TCIL TxCLK Period (Figure TxCLK High Time (Figure TxCLK Time (Figure Parameter TxCLK Transition Time (Figure 14.7 0.35T 0.35T 0.5T 0.5T 55.6 0.65T 0.65T Units
Symbol LLHT LHLT TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TPPos0 TPPos1 TPPos2 TPPos3 TPPos4 TPPos5 TPPos6 TSTC THTC TCCD TJCC Parameter LVDS Low-to-High Transition Time (Figure LVDS High-to-Low Transition Time (Figure Transmitter Output Pulse Position (Figure (Note Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position (Figure (Note Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position (Figure 11)(Note Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position Transmitter Output Pulse Position TxIN Setup TxCLK (Figure TxIN Hold TxCLK (Figure TxCLK TxCLK Delay (Figure ,VCC 3.3V TxCLK TxCLK Delay (Figure Transmitter Jitter Cycle-to-Cycle (Figures 13)(Note 32.5 TPLLS TPDD
Note Note
0.75 0.75
0.20 2.40 4.60 6.80 9.00 11.20 13.40 0.35 3.92 7.49 11.06 14.63 18.21 21.78 0.40 4.80 9.20 13.60 18.00 22.40 26.80
Units
0.30 1.90 4.10 6.30 8.50 10.70 12.90
2.20 4.40 6.60 8.80 11.00 13.20 3.57 7.14 10.71 14.28 17.86 21.43 4.40 8.80 13.20 17.60 22.00 26.40
0.35 3.22 6.79 10.36 13.93 17.51 21.08
32.5
0.40 4.00 8.40 12.80 17.20 21.60 26.00
Transmitter Phase Lock Loop (Figure Transmitter Power Down Delay (Figure
(RSKM) Figure12 13AN-1059
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DS90C383A/DS90CF383A
FIGURE
"Worst Case"Test Pattern
FIGURE
Note Note Note
Grayscale"Test Pattern (Note
LVDS Figure (TxCLK IN/RxCLK OUT)
Note
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DS90C383A/DS90CF383A
FIGURE DS90C383A/DS90CF383A (Transmitter) LVDS Output Load
FIGURE DS90C383A/DS90CF383A (Transmitter) LVDS Transition Times
FIGURE DS90C383A/DS90CF383A (Transmitter) Input Clock Transition Time
FIGURE DS90C383A/DS90CF383A (Transmitter) Setup/Hold High/Low Times (Falling Edge Strobe)
FIGURE DS90C383A/DS90CF383A (Transmitter) Clock Clock Delay (Falling Edge Strobe)
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DS90C383A/DS90CF383A
FIGURE DS90C383A/DS90CF383A (Transmitter) Phase Lock Loop Time
FIGURE Parallel Data Inputs Mapped LVDS Outputs
FIGURE Transmitter Power Down Delay
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DS90C383A/DS90CF383A
FIGURE Transmitter LVDS Output Pulse Position Measurement
FIGURE TJCC Test Setup
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DS90C383A/DS90CF383A
FIGURE Timing Diagram Input cycle-to-cycle clock jitter
DS90C383A
TxIN Red8 Green8 Blue FPLINEFPFRAMEDRDY (HSYNCVSYNCData Enable) LVDS LVDS TXCLK (Table LVDS LVDS TRI-STATE LVDS LVDS
TxOUT TxOUT FPSHIFT R_FB TxCLK TxCLK DOWN LVDS LVDS
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DS90C383A/DS90CF383A
DS90CF383A
TxIN Red8 Green8 Blue FPLINEFPFRAMEDRDY (HSYNCVSYNCData Enable) LVDS LVDS TxCLK LVDS LVDS TRI-STATE LVDS LVDS
TxOUT TxOUT FPSHIFT TxCLK TxCLK DOWN LVDS LVDS
DS90C383A/DS90CF383A DS90C383/DS90CF383 DS90C383A/DS90CF383A DS90C383A/DS90CF383A TCCD (AN-1084 TCCD 65MHz 250ps DS90CF583 (5V65MHz) DS90CF581 (5V40MHz) 3.3V (VCCLVDS VCCPLL VCC) DS90C383A 3.3VTTL/CMOS DS90C383A R_FB Figure1213 (Txin0 High (TxCLKIN) High1 Low) (PWR DOWN High) DOWN DOWN "Low" TRI-STATE DOWN 1.5V 10ms DOWN Low) (typ) Link (RxOUT) LVDS Link High (High) High
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DS90C383A/DS90CF383A
DS90C383A DS90CF383A
Typical Application
TABLE Programmable Transmitter (DS90C383A)
R_FB R_FB R_FB R_FB Condition Strobe Status Rising edge strobe Falling edge strobe
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DS90C383A/DS90CF383A 3.3V LVDS 24-Bit Flat Panel Display (FPD) Link-65MHz 3.3V LVDS 24-Bit Flat Panel Display (FPD) Link-65MHz
millimeters
56-Lead Molded Thin Shrink Small Outline Package, JEDEC Order Number DS90C383AMTD, DS90CF383AMTD Package Number MTD56
135-0042 2-17-16 TEL.(03)5639-7300
www.national.com/JPN/
0120-666-116

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