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Thin Film Transistor (TFT) Controller (v2.00a)
DS695 September 2009
Product Specification
Introduction
Thin Film Transistor (TFT) controller hardware display controller core capable displaying 256k colors. controller connects master V4.6 (Processor Local with Xilinx simplification) reads video pixel data from attached video memory. This core also connects slave (Device Control Register) register access. This core capable configuring Chrontel CH-7301 Transmitter Chip through interface.
LogiCOREFacts
Core Specifics Virtex-4®, Virtex-4Q, Virtex-4QV, Virtex-5, Virtex-5FX, Virtex-6, Virtex-6CX, Spartan®-3E, Automotive Spartan-3E, Spartan-3, Automotive Spartan-3, Spartan-3A, Automotive Spartan-3A, Spartan-3A DSP, Automotive Spartan-3A DSP, Spartan-6 xps_tft Resources Used SLICES LUTs Block RAMs Special Features Provided with Core Documentation Design File Formats Constraints File Verification Instantiation Template Product Specification Mixed Design Tool Requirements Xilinx Implementation Tools Verification Simulation Synthesis ISE® 11.3 later Mentor Graphics ModelSim v6.4b later Mentor Graphics ModelSim v6.4b later 11.3or later Support Provided Xilinx, Inc. Refer Table Table Table Table v2.00a
Supported Device Family
Version core
Features
Connects 64-bit master V4.6 bits data width Connects 32-bit Slave V2.9 V4.6 bits data width Supports daisy chain protocol Parameterizable interface 18-bit 24-bit Supports clock display resolution 640x480 pixels refresh rate Supports configuration external Chrontel Transmitter Chip through interface Supports separate clock domain interface interface Supports Vsync Interrupt Status
2008-2009 Xilinx, Inc. XILINX, Xilinx logo, Virtex, Spartan, other designated brands included herein trademarks Xilinx United States other countries. PowerPC name logo registered trademarks Corp. used under license. other trademarks property their respective owners.
DS695 September 2009 Product Specification
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Thin Film Transistor (TFT) Controller (v2.00a)
Functional Description
controller hardware display controller 640x480 resolution display screen. This core capable displaying 256K colors through interface. design contains master interface that reads video data from attached memory device displays data onto screen. design also contains parameterizable slave interface. parameter C_DCR_SPLB_SLAVE_IF controller configured using slave interface, else configured through slave interface. This controller also provide interface configure Chrontel CH7301C video encoder chip when interface selected. controller block diagram shown Figure
Figure x-ref
Controller Controller
Slave Interface Module Slave Register Logic Register Access Control
Interface Signals TFT_DPS TFT_DE TFT_VSYNC Interface Logic TFT_HSYNC TFT_VGA_CLK TFT_VGA_R Control Logic HSYNC VSYNC Control TFT_VGA_G TFT_VGA_B TFT_DVI_CLK_P TFT_DVI_CLK_N TFT_DVI_DATA TFT_IIC_SCL TFT_IIC_SDA
DCR_Clk DCR_Rst
Slave Interface Module
Master Interface Module
Line Buffer
IP2INTC_Irpt
Interface Chrontel Ch7301 Configuration
SYS_TFT_Clk
Clock Domain
Clock Domain
Note: Slave Interface included design parameter C_DCR_SPLB_SLAVE_IF slave interface part Slave Regiter Logic included design parameter C_DCR_SPLB_SLAVE_IF interface included design parameter C_TFT_INTERFACE interface included design parameter C_TFT_INTERFACE This logic included design _TFT_INTERFACE
DS695_01_020509
Figure Controller Block Diagram
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DS695 September 2009 Product Specification
Thin Film Transistor (TFT) Controller (v2.00a)
major modules controller described subsequent sections. These modules are: Master Interface Module Slave Interface Module Slave Register Logic Control Logic Line Buffer HSYNC VSYNC Control Interface Logic Master Interface Module Master Interface Module provides master interface between controller PLB. controller reads pixel data from external memory device through Master Interface Module. This module takes care interface signals, protocol other interface issues. master interface native data width fixed 64-bits. C_MPLB_SMALLEST_SLAVE size should same attached memory data width. Slave Interface Module Slave Interface Module provides interface between Slave Register Logic bus.This interface included design parameter C_DCR_SPLB_SLAVE_IF controller registers accessed through using this interface. controller core only supports clock ratio SPLB MPLB clocks. Slave Register Logic Slave Register Logic module consists Address Register (AR), Control Register (CR) logic provide access these registers using either interface. slave interface logic included design parameter C_DCR_SPLB_SLAVE_IF Address Register allows user change base address video memory read from. This allows video frames fetched from other memory locations without being seen display. user change video memory base address display different frame when ready. Control Register allows display rotated degrees turned configuring control bits. Control Logic Control Logic module generates read request Master Interface Module pixel data from external memory device. This module synchronizes signals crossing different clock domains. control logic generates master read request, address video memory reads pixel data each display line using series 16-double word burst transactions. pixel data stored internal line buffer then sent display with necessary timing correctly display image. This process repeats continuously over every line frame displayed 640x480 screen. data flow diagram from shown Figure When display turned clearing display enable Control Register, controller issues reset counters stops requesting data from video memory applying reset Master Interface Module. reset state, controller sets Hsync Vsync their default value causing display enter sleep mode.
DS695 September 2009 Product Specification
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Thin Film Transistor (TFT) Controller (v2.00a)
Figure x-ref
Clock Domain
Clock Domain
Control Logic Column Addr Master Data Interface Module Green Data Blue Data
Line
Video Memory
Column Addr Data Line Buffer Green Data Blue Data Interface Logic
Video Signal Display
DS695_02_020509
Figure Data Flow Diagram
Line Buffer controller allows clock video clock asynchronous each other. line buffer module includes synchronization logic allow control signals passed between asynchronous clock domains. This module consists dual port BRAM size which used line buffer pass video data between clock domains. 64-bit data, 36-bit data gets written BRAM. HSYNC/VSYNC Control This module generates necessary timing video synchronization signals including back porch front porch timing Hsync Vsync. Video TimingVideo Timing section more information. Interface Logic interface logic driving display operates same clock domain video clock. reads pixel data from dual port line buffer transmits TFT. This module consists logic transmit pixel data either format based parameter C_TFT_INTERFACE logic configure Chrontel CH-7301 video encoder chip. Hsync, Vsync signals common both interfaces. VGA, Chrontel interfaces described below.
Interface
interface logic included design parameter C_TFT_INTERFACE 18-bit pixel data transmitted ports logic transmitted ports.
Interface
interface logic included design parameter C_TFT_INTERFACE 18-bit data converted into 24-bit pixel data padding zeros between data. This 24-bit pixel data transmitted 12-bit data port clocking data both edges using
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DS695 September 2009 Product Specification
Thin Film Transistor (TFT) Controller (v2.00a)
double data rate registers shown Figure 18-bit pixel data translation 24-bit data shown Table
Figure x-ref
Clock TFT_DE Data (17:0)
TFT_DVI_Data(11:0)
DS695_03_020509
Figure data Table data conversion
Data
TFT_DVI_DATA[0] TFT_DVI_DATA[1] TFT_DVI_DATA[2] TFT_DVI_DATA[3] TFT_DVI_DATA[4] TFT_DVI_DATA[5] TFT_DVI_DATA[6] TFT_DVI_DATA[7] TFT_DVI_DATA[8] TFT_DVI_DATA[9] TFT_DVI_DATA[10] TFT_DVI_DATA[11]
Data
G[2] G[3] G[4] G[5] R[0] R[1] R[2] R[3] R[4] R[5]
Data
B[0] B[1] B[2] B[3] B[4] B[5] G[0] G[1]
DS695 September 2009 Product Specification
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Thin Film Transistor (TFT) Controller (v2.00a)
Chrontel Interface
Chrontel interface logic included design parameter C_TFT_INTERFACE This module consists logic configure Chrontel CH-7301 video encoder chip. configuration sequence logic hard coded this module data sent over interface. This core configures only basic registers CH-7301 chip interface. controller remains reset state till controller completes configuration Chrontel chip. description these registers address configuration data shown Table user wants different configuration Chrontel chip, then user must configure Chrontel chip externally. more information Chrontel transmitter, please refer Chrontel CH7301 Transmitter Device Specification.
Table Chrontel CH-7301 Configuration Register Description
Register Address (hex)
Register Name
TPCP
Configuration Data (hex)
Access
Write Write Write Write Write
Description
Power Management Register Control Register Charge Pump Control Register Divider Register Filter Register
Video Timing
signal timings 640x480 display using pixel clock shown Table controller takes 16.8 display each 640x480 display frame refresh rate TFT. Hence, display complete frame TFT, user should update video memory start address (AR) before this time frame.
Table 640x480 Mode Display Timing
Vertical Sync Symbol
TPULSE TDisp
Horizontal Sync Lines
Parameter Time
Sync pulse time Display time Pulse width time Back porch time Front porch time 16.8 15.4
Clocks
420000 384000 1600 24800
Time
25.6 3.84 1.92
Clocks
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DS695 September 2009 Product Specification
Thin Film Transistor (TFT) Controller (v2.00a)
Hsync Timing Hsync active signal complete time period Hsync clocks. clock period, active pixel data qualified active high signal clocks. Hsync pulse period clocks. time period between Hsync pulse start active data called back porch which clocks. time period between active data start Hsync pulse called front porch which clocks. Hsync timing with respect clock shown Figure
Figure x-ref
Hsynch
(Fixed)
data
Invalid
(639,
Invalid
Pulse Width Clocks Back Porch Clocks Pixel Time Clocks Front Porch Clocks Hsync Pulse TFTClocks
Figure Horizontal Data
DS695_04_020509
Vsync Timing Vsync active signal complete time period Vsync h_syncs. h_syncs, Vsync pulse period h_syncs, active display period h_syncs, back porch period h_syncs front porch period h_syncs. Vsync timing with respect Hsync shown Figure
DS695 September 2009 Product Specification
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Thin Film Transistor (TFT) Controller (v2.00a)
Figure x-ref
Vsynch
(Fixed)
Hsyncs
thpb
data
Invalid
data
479)
Invalid
Invalid
(639,
Invalid
Pulse Width h_syncs Back Porch h_syncs Pixel Time Clocks Front Porch h_syncs Vsync Pusle h_sync thpb Back Porch Valid Data Hsync Front Porch Display period h_syncs
Figure Vertical Data
DS695_05_020509
Video Memory
important design system that there sufficient bandwidth available between controller memory device meet video bandwidth requirements TFT. Furthermore, there must enough bandwidth available rest system. bandwidth requirement rest system more, clock frequency reduced. However, reducing clock frequency also lowers refresh rate screen. This lead noticeable flicker screen clock slow. master interface logic ability skip reading line data fails finish reading data from previous line because shortage bandwidth. This prevents controller losing synchronization between interface logic. Note that extreme shortage available bandwidth controller cause screen appear unstable stale lines video data displayed screen. video memory expected arranged that each pixel represented 32-bit word memory. video memory should stored region memory consisting 1024 data
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DS695 September 2009 Product Specification
Thin Film Transistor (TFT) Controller (v2.00a)
words word bits) line lines frame. this 1024 memory space, only first columns rows displayed screen. given 479) column 639), pixel color information encoded shown Table
Table Pixel Color Encoding
Pixel Address
Bits
[0:7] [8:13] [14:15] Undefined
Description
Pixel Data: 000000 darkest 111111 brightest Undefined Green Pixel Data: 000000 darkest 111111 brightest Undefined Blue Pixel Data: 000000 darkest 111111 brightest Undefined
Base Address (4096 row) column)
[16:21] [22:23] [24:29] [30:31]
Controller Signals
controller signals listed described Table
Table Controller Signal Description
Port
Signal Name
Interface
Initial State
Description
System Signals MPLB_Clk MPLB_Rst SPLB_Clk(1) SPLB_Rst MD_error IP2INTC_Irpt System System System System System System master clock master reset slave clock slave reset Master error detection indicator (active high) Vysnc Pulse Interrupt
Master Interface Signals M_request M_priority M_buslock M_RNW M_BE(0:[C_MPLB_DWIDTH/8]1) M_Msize(0:1) Master request Master request priority Master lock Master read write Master byte enables Master data size
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Thin Film Transistor (TFT) Controller (v2.00a)
Table Controller Signal Description (Cont.)
Port
Signal Name
M_size(0:3) M_type(0:2) M_ABus(0:31) M_wrBurst M_rdBurst M_wrDBus(0:C_MPLB_DWIDT H-1) PLB_MSize(0:1) PLB_MaddrAck PLB_Mrearbitrate PLB_MTimeout PLB_MRdErr PLB_MWrErr PLB_MRdDBus(0:C_MPLB_D WIDTH-1) PLB_MRdDAck PLB_MWrDAck PLB_RdBTerm PLB_MWrBTerm
Interface
Initial State
Description
Master transfer size Master transfer type Master address Master burst write transfer indicator Master read write transfer indicator Master write data master slave data port width master address acknowledge master rearbitrate indicator master time master slave read error indicator master slave write error indicator master read data master read data acknowledge master write data acknowledge master terminate read burst indicator master terminate write burst indicator
Unused Master Interface Signals M_TAttribute(0 M_lockerr M_abort M_UABus(0:31)) PLB_MBusy PLB_MIRQ PLB_RdWdAddr(0:3) Master transfer attribute Master lock error indicator Master abort request indicator Master upper address master busy signal master interrupt indicator master read word address
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DS695 September 2009 Product Specification
Thin Film Transistor (TFT) Controller (v2.00a)
Table Controller Signal Description (Cont.)
Port
Signal Name
Interface
Initial State
Description
Slave Interface Signals PLB_ABus[0: C_SPLB_AWIDTH PLB_PAValid PLB_masterID[0: C_SPLB_MID_WIDTH PLB_RNW PLB_BE[0: (C_SPLB_DWIDTH/8) PLB_size[0:3] PLB_type[0:2] PLB_wrDBus[0: C_SPLB_DWIDTH Sl_addrAck Sl_SSize[0:1] Sl_wait Sl_rearbitrate Sl_wrDAck Sl_wrComp Sl_rdDBus[0: C_SPLB_DWIDTH Sl_rdDAck Sl_rdComp Sl_MBusy[0: C_SPLB_NUM_MASTERS Sl_MWrErr[0: C_SPLB_NUM_MASTERS Sl_MRdErr[0: C_SPLB_NUM_MASTERS address primary address valid current master identifier read write byte enables size requested transfer transfer type write data Slave address acknowledge Slave data size Slave wait Slave rearbitrate Slave write data acknowledge Slave write transfer complete Slave read data Slave read data acknowledge Slave read transfer complete Slave busy Slave write error Slave read error
Unused Slave Interface Signals PLB_UABus[0: PLB_SAValid PLB_rdPrim PLB_wrPrim PLB_abort upper address bits secondary address valid secondary primary read request indicator secondary primary write request indicator abort request
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Thin Film Transistor (TFT) Controller (v2.00a)
Table Controller Signal Description (Cont.)
Port
Signal Name
PLB_busLock PLB_MSize PLB_lockErr PLB_wrBurst PLB_rdBurst PLB_wrPendReq PLB_rdPendReq PLB_wrPendPri[0:1] PLB_rdPendPri[0:1] PLB_reqPri[0:1] PLB_TAttribute[0:15] Sl_wrBTerm Sl_rdWdAddr[0:3] Sl_rdBTerm Sl_MIRQ[0: C_SPLB_NUM_MASTERS
Interface
Initial State
Description
lock data width indicator lock error burst write transfer burst read transfer pending write request pending read request pending write request priority pending read request priority current request priority transfer attribute Slave terminate write burst transfer Slave read word address Slave terminate read burst transfer Master interrupt request
Slave Interface Signals DCR_Clk(1) DCR_Rst DCR_Read DCR_Write DCR_ABus[0 C_SDCR_AWIDTH-1] DCR_Sl_DBus[0 C_SDCR_DWIDTH-1] Sl_DCR_DBusout[0 C_SDCR_DWIDTH-1] clock reset read request from master write request from master address from master slave data from master Slave data Slave acknowledge
Sl_dcrAck
Interface Signals SYS_TFT_Clk TFT_HSYNC clock input Horizontal Sync (Active Low)
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DS695 September 2009 Product Specification
Thin Film Transistor (TFT) Controller (v2.00a)
Table Controller Signal Description (Cont.)
Port
P100 P101 P102
Signal Name
TFT_VSYNC TFT_DE TFT_DPS TFT_VGA_CLK TFT_VGA_R[5:0] TFT_VGA_G[5:0] TFT_VGA_B[5:0] TFT_DVI_CLK_P TFT_DVI_CLK_N TFT_DVI_DATA[11:0] TFT_IIC_SCL_O TFT_IIC_SCL_I TFT_IIC_SCL_T TFT_IIC_SDA_O TFT_IIC_SDA_I TFT_IIC_SDA_T
Interface
TFT-VGA TFT-VGA TFT-VGA TFT-VGA TFT-DVI TFT-DVI TFT-DVI TFT-DVI TFT-DVI TFT-DVI TFT-DVI TFT-DVI TFT-DVI
Initial State
Description
Vertical Sync (Active Low) Data enable Display scan clock(2) pixel data(2) Green pixel data(2) Blue pixel data(2) Differential clock(3) Differential clock(3) data(3) output clock Chrontel chip(4) input clock from Chrontel chip(4) 3-state control clock(4) output data Chrontel chip(4) input data from Chrontel chip(4) 3-state control data(4)
Notes: This controller supports clock ratio only slave interface clock(SPLB_Clk/DCR_Clk) master interface clock(MPLB_Clk). interface signals. interface signals. signals used configure Chrontel Video Encoder chip. These ports active when interface selected.
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Thin Film Transistor (TFT) Controller (v2.00a)
Controller Design Parameters
allow user create controller that uniquely tailored user's system, certain features parameterizable controller design. This allows user have design that utilizes only resources required system runs best possible performance. features that parameterizable controller core shown Table
Table Controller Design Parameters
Generic
Feature/Descripti
Parameter Name
Allowable Values
Default Value
VHDL Type
Controller Parameter spartan3a, aspartan3a, spartan3, aspartan3, spartan3e, aspartan3e, spartan3adsp, aspartan3adsp, spartan6, virtex4, qvirtex4, qrvirtex4, virtex5, virtex5fx, virtex6, virtex6cx valid address slave interface slave interface interface interface Valid slave address
Target FPGA family
C_FAMILY
virtex4
string
Base address attached Video memory Controller Register access interface
C_DEFAULT_TFT_ BASE_ADDR(1)
0xF000000
std_logic_vector
C_DCR_SPLB_SL AVE_IF
integer
interface selection Slave address external Chrontel transmitter
C_TFT_INTERFAC C_I2C_SLAVE_AD
integer
"1110110"
std_logic_vector
Interface Parameters Slave Base Address Slave High Address C_DCR_BASEAD C_DCR_HIGHADD Valid Address Valid Address Valid 10-bit address Valid 10-bit address std_logic_vector std_logic_vector
Master Interface Parameters Address width Data width C_MPLB_AWIDTH C_MPLB_DWIDTH integer integer
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DS695 September 2009 Product Specification
Thin Film Transistor (TFT) Controller (v2.00a)
Table Controller Design Parameters (Cont.)
Generic
Feature/Descripti
Data width attached video memory Internal native data width master interface
Parameter Name
C_MPLB_SMALLE ST_SLAVE C_MPLB_NATIVE_ DWIDTH
Allowable Values
Default Value
VHDL Type
integer
integer
Slave Interface Parameters controller Base Address controller High Address slave interface address width slave interface data width Selects point-to-point shared topology Master width Number Masters Width internal slave data C_SPLB_BASEAD C_SPLB_HIGHAD C_SPLB_AWIDTH C_SPLB_DWIDTH Valid Address(3) Valid Address(3) Shared Topology log2(C_SPLB_ NUM_MASTERS with minimum value None(2) None(2) std_logic_vector std_logic_vector integer integer
C_SPLB_P2P
integer
C_SPLB_MID_WI C_SPLB_NUM_M ASTERS C_SPLB_NATIVE_ DWIDTH
integer
integer integer
Notes: C_DEFAULT_TFT_BASE_ADDR specifies base address attached video memory. This base address video memory must aligned boundary (i.e. only upper bits valid, remaining address bits must always '0'). controller will only this base address read data from video memory. default value will specified insure that actual value set, i.e., value set, compiler error will generated. C_SPLB_BASEADDR must multiple range size, where range size C_SPLB_HIGHADDR C_SPLB_BASEADDR must power two. range size must large enough accommodate registers.
Allowable Parameter Combinations
address-range size specified C_SPLB_BASEADDR C_SPLB_HIGHADDR must power must least 0x10. address specified C_DEFAULT_TFT_BASE_ADDR must aligned boundary. Only bits should have valid address, remaining address bits must always '0'. slave interface only included design C_DCR_SPLB_SLAVE_IF When C_DCR_SPLB_SLAVE_IF slave interface included design ports unused.
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Thin Film Transistor (TFT) Controller (v2.00a)
Optimal System Settings
recommended have separate buses video memory access from core rest system. This will have sufficient bandwidth available between controller memory device. native data width controller fixed 64-bits. Optimal performance will achieved when video memory interface width greater than equal native data width master interface (C_MPLB_SMALLEST_SLAVE C_MPLB_NATIVE_DWIDTH).
Controller Parameter Port Dependencies
dependencies between controller core design parameters signals described Table addition, when certain features parameterized design, related logic will longer part design. unused input signals related output signals specified value.
Table Controller Design Parameter Port Dependencies
Generic Port
Name
Affects
Depends
Relationship Description
Design Parameters Affect DCR/PLB interface ports. C_DCR_SPLB_SLAVE_IF ports inactive. C_DCR_SPLB_SLAVE_IF ports inactive. Affects interface ports. C_TFT_INTERFACE ports tied '0'. C_TFT_INTERFACE ports tied '0'. Depends C_TFT_INTERFACE. Required only when interface selected.
C_DCR_SPLB_SLAVE_IF
C_TFT_INTERFACE
P101
C_I2C_SLAVE_ADDR
P10, P17, P40, P43,
C_MPLB_DWIDTH C_SPLB_AWIDTH C_SPLB_DWIDTH
Affects number bits master data
Affects number bits address Affects number bits slave data Affects width current master identifier signals depends log2(C_SPLB_NUM_MASTERS) with minimum value Affects width busy error signals
C_SPLB_MID_WIDTH
C_SPLB_NUM_MASTERS
P53, P54, P55, Signals
M_BE[0: (C_MPLB_DWIDTH/8) M_wrDBus[0: C_MPLB_DWIDTH
Width varies with size master data Width varies with size master data
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DS695 September 2009 Product Specification
Thin Film Transistor (TFT) Controller (v2.00a)
Table Controller Design Parameter Port Dependencies (Cont.)
Generic Port
Name
PLB_MRdDBus[0: C_MPLB_DWIDTH PLB_ABus[0: C_SPLB_AWIDTH PLB_masterID[0: C_SPLB_MID_WIDTH PLB_BE[0: (C_SPLB_DWIDTH/8)-1] PLB_wrDBus[0: C_SPLB_DWIDTH Sl_rdDBus[0: C_SPLB_DWIDTH Sl_MBusy[0: C_SPLB_NUM_MASTERS Sl_MWrErr[0: C_SPLB_NUM_MASTERS Sl_MRdErr[0: C_SPLB_NUM_MASTERS Sl_MIRQ[0: C_SPLB_NUM_MASTERS Slave Interface ports Interface ports TFT_VGA_CLK TFT_VGA_R TFT_VGA_G TFT_VGA_B TFT_DVI_CLK_P TFT_DVI_CLK_N TFT_DVI_DATA
Affects
Depends
Relationship Description
Width varies with size master data Width varies with size address Width varies with size master identifier Width varies with size slave data Width varies with size slave data Width varies with size slave data Width varies with number masters Width varies with number masters Width varies with number masters Width varies with number masters Ports unused when C_DCR_SPLB_SLAVE_IF Ports unused when C_DCR_SPLB_SLAVE_IF Port tied when C_TFT_INTERFACE Ports tied when C_TFT_INTERFACE Ports tied when C_TFT_INTERFACE Ports tied when C_TFT_INTERFACE Port tied when C_TFT_INTERFACE Port tied when C_TFT_INTERFACE Ports tied when C_TFT_INTERFACE
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Thin Film Transistor (TFT) Controller (v2.00a)
Table Controller Design Parameter Port Dependencies (Cont.)
Generic Port
Name
TFT_IIC_SCL_O TFT_IIC_SCL_I TFT_IIC_SCL_T TFT_IIC_SDA_O TFT_IIC_SDA_I TFT_IIC_SDA_T
Affects
Depends
Relationship Description
Port tied when C_TFT_INTERFACE Port un-used when C_TFT_INTERFACE Port tied when C_TFT_INTERFACE Port tied when C_TFT_INTERFACE Port un-used when C_TFT_INTERFACE Port tied when C_TFT_INTERFACE
Controller Register Description
There four internal registers available controller design. These registers accessed through either slave interface slave interface based parameter setting C_DCR_SPLB_SLAVE_IF. memory controller design determined setting C_SPLB_BASEADDR/C_DCR_BASEADDR parameter. internal registers controller fixed offset from base address 32-bit boundary. Writing into reserved registers effect. Reading from reserved registers returns zero. registers defined 32-bit access only. When slave interface selected, partial word write access (byte, half-word) effect registers partial word read access (byte, half-word) returns zero. partial access core register returns error. controller internal registers their offset interface interface listed Table Table
Table Controller Internal Registers access through
Base Address Offset (hex)
Register Name
Access
Default Value (hex)
Description
address register which specifies base address video memory from which controller fetches data control register Vsync interrupt enable status register. Reserved future
C_SPLB_BASEADDR
Read/Write
C_DEFAULT_TFT_ BASE_ADDR
C_SPLB_BASEADDR C_SPLB_BASEADDR C_SPLB_BASEADDR
IESR Reserved
Read/Write Read/Write
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DS695 September 2009 Product Specification
Thin Film Transistor (TFT) Controller (v2.00a)
Table Controller Internal Registers access through Base Address Offset (hex) Register Name Access Default Value (hex) Description
address register which specifies base address video memory from which controller fetches data control register Vsync interrupt enable status register. Reserved future
C_DCR_BASEADDR
Read/Write
C_DEFAULT_TFT_ BASE_ADDR
C_DCR_BASEADDR C_DCR_BASEADDR C_DCR_BASEADDR
IESR Reserved
Read/Write Read/Write
Address Register (AR) Base Address Register specifies upper 11-bits base address video memory. This address accessible memory device that acts video memory. This address must aligned boundary (i.e. only upper bits writable, remaining address bits always '0') shown Figure described Table
Figure x-ref
Video Memory address
Reserved
DS695_06_020509
Figure Address Register Table Address Register Description
Bits
Name
base address Reserved
Core Access
Reset Value
C_DEFAULT_TFT_BASE_ ADDR[0:10]
Description
Specifies base address video memory from which controller fetched data Reserved
[0:10] [11:31]
Control Register (CR) Control Register contains control bits configure controller scanning mode display on/off. Writing display enable resets controller. reset state, controller stops requesting data from video memory applying reset Master Interface
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Thin Film Transistor (TFT) Controller (v2.00a)
Module Hsync Vsync their default value causing display enter sleep mode. assignment control register shown Figure described Table
Figure x-ref
Reserved
DS695_07_020509
Figure Control Register Table Control Register description
Bits
[0:29]
Name
Reserved
Core Access
Reset Value
Reserved
Description
[30]
Display Scan Control output This sets display normal scan direction. output This sets display reverse scan direction (rotates screen degrees). Display Enable Disable display. This resets controller stops Vsync/Hsync signals causing display sleep mode. Enable display. This causes controller operate normally.
[31]
Interrupt Enable Status Register (IESR) Interrupt Enable Status register 32-bit read/write register. This register contains Vsync interrupt enable status bit. Vsync interrupt enabled, core generates interrupt Vsyn pulse every frame. every rising edge Vsync pulse, core status indicate that core displayed current frame completely accepted address from This status gets cleared every write access assignment IESR shown Figure described Table
Figure x-ref
Reserved
Interrupt Enable
Status(S)
DS695_15_020509
Figure Interrupt Enable Status Register
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Thin Film Transistor (TFT) Controller (v2.00a)
Table Interrupt Enable Status Register description
Bits
[0:27] [28] [29:30]
Name
Reserved Interrupt Enable Reserved
Core Access
Reset Value
Reserved
Description
Vsync Interrupt Enable Disable Vsync pulse interrupt. Enable Vsync pulse interrupt. Reserved Vsync address latch status Core displaying current frame. Vsync pulse active. Also indicate that previous frame displayed completely core accepted address from
[31]
Status
Controller Timing Diagrams
Master Burst Read attached Memory
burst read transaction shown Figure
Figure x-ref
Cycles 111213 1415 1718 1920 2122 2526 282930 3233 353637 MPLB_Clk M_request M_RNW M_BE[0:7] M_size[0:3] M_Abus[0:31] M_rdBurst PLB_MAddrAck PLB_MRdDBus[0:63] PLB_MRdDAck
DS695_08_020509
A0+8
Figure Burst Read Transaction
Register Read/Write through slave interface
Figure shows controller register access through slave interface.
Figure x-ref
Cycles SPLB_Clk PLB_Abus[0:31] PLB_PAValid PLB_RNW PLB_BE[0:3] PLB_wrDBus[0:31] Sl_AddrAck Sl_rdDAck Sl_wrDAck Sl_rdDBus[0:31]
DDS695_09_020509
Figure Register Read/Write Through Slave Interface
DS695 September 2009 Product Specification
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Thin Film Transistor (TFT) Controller (v2.00a)
Register Read/Write through slave interface
Figure shows controller register access through slave interface.
Figure x-ref
Cycles DCR_Clk DCR_Abus[0:9] DCR_Sl_DBus[0:31] DCR_Read DCR_Write Sl_DCRAck Sl_DCRDBus[0:31]
DDS695_10_020509
Figure Register Read/Write Through Slave Interface
Cases
controller system build different cases based processor interface core slave interface. Following uses cases controller. Standard PowerPC® processor system with slave interface (Figure Standard PowerPC processor system with slave interface (Figure Microblazeprocessor system with slave interface (Figure PowerPC processor system with separate master slave interface (Figure 15).
Figure x-ref
DPLB0 IPLB0
PLBv46 Memory MPMC
Master Interface Controller Slave Interface
DS695_11_020509
Figure PowerPC Processor System with Slave Interface
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DS695 September 2009 Product Specification
Thin Film Transistor (TFT) Controller (v2.00a)
Figure x-ref
DPLB0 IPLB
PLBv46 Memory MPMC
Master Interface Controller Slave Interface
DS695_12_020509
Figure PowerPC Processor System with Slave Interface
Figure x-ref
DPLB0 Microblaze IPLB
PLBv46 Memory MPMC
PLBv46 Bridge
Master Interface Controller Slave Interface
DS695_13_020509
Figure Microblaze System with Slave Interface
DS695 September 2009 Product Specification
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Thin Film Transistor (TFT) Controller (v2.00a)
Figure x-ref
PLBv46 DPLB0 IPLBPLB_0 PLB_1
MPMC PLBv46
Memory
Master Interface Controller Slave Interface
Slave
Slave
DS695_14_020509
Figure PowerPC Processor System with Separate Buses Master Slave Interface
Design Implementation
Target Technology
target technology FPGA listed Supported Device Family field LogiCORE Facts Table.
Device Utilization Performance Benchmarks
Since controller core will used with other design modules FPGA, utilization timing numbers reported this section estimates only. When controller core combined with other designs system, utilization FPGA resources timing controller design will vary from results reported here. controller resource utilization various parameter combinations measured with Virtex-4 FPGA target device detailed Table
Table Performance Resource Utilization Benchmarks Virtex-4 FPGA (xc4vlx25-ff668-10)
Parameter Values
C_DCR_SPLB_SLAVE_IF C_TFT_INTERFACE
Device Resources
Slices Slice Flip-Flops LUTs
Performance
FMAX (MHz)
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DS695 September 2009 Product Specification
Thin Film Transistor (TFT) Controller (v2.00a)
controller resource utilization various parameter combinations measured with Virtex-5 target device detailed Table
Table Performance Resource Utilization Benchmarks Virtex-5 FPGA (xc5vfx70-ff1136-1)
Parameter Values
C_DCR_SPLB_SLAVE_IF C_TFT_INTERFACE
Device Resources
Slices Slice Flip-Flops LUTs
Performance
FMAX (MHz)
controller resource utilization various parameter combinations measured with Spartan-3 FPGA target device detailed Table
Table Performance Resource Utilization Benchmarks Spartan-3 FPGA (xc3sd1800a-fg676-4)
Parameter Values
C_DCR_SPLB_SLAVE_IF C_TFT_INTERFACE
Device Resources
Slices Slice Flip-Flops LUTs
Performance
FMAX (MHz)
controller resource utilization various parameter combinations measured with Virtex-6 FPGA target device detailed Table
Table Performance Resource Utilization Benchmarks Virtex-6 FPGA (xc6vlx75ft-ff784-1)
Parameter Values
C_DCR_SPLB_SLAVE_IF C_TFT_INTERFACE
Device Resources
Slices Slice Flip-Flops LUTs
Performance
FMAX (MHz)
DS695 September 2009 Product Specification
www.xilinx.com
Thin Film Transistor (TFT) Controller (v2.00a)
controller resource utilization various parameter combinations measured with Spartan-6 FPGA target device detailed Table
Table Performance Resource Utilization Benchmarks Spartan-6 FPGA (xc6slx16-csg324-2)
Parameter Values
C_DCR_SPLB_SLAVE_IF C_TFT_INTERFACE
Device Resources
Slices Slice Flip-Flops LUTs
Performance
FMAX (MHz)
Specification Exceptions
This core capable configuring Chrontel CH-7301 chip only. system video encoder chip other than Chrontel CH-7301, user must take care configuring chip.
Support
Xilinx provides technical support this LogiCORE product when used described product documentation. Xilinx cannot guarantee timing, functionality, support product implemented devices that defined documentation, customized beyond that allowed product documentation, changes made section design labeled MODIFY.
Reference Documents
DS402 Xilinx Device Control Register Design Specification DS561 Xilinx PLBV46 Slave Single Design Specification DS565 Xilinx PLBV46 Master Burst Design Specification CoreConnect 128-Bit Processor Local Bus, Architectural Specification (v4.6) CoreConnect 32-Bit Device Control Register Bus: Architecture Specification, Chrontel CH-7301C Transmitter Specification, 1.32 specification
Revision History
Date
07/07/08 7/21/08 4/24/09 9/16/09
Version
Initial Xilinx release.
Revision
Added QPro Virtex-4 Hi-Rel QPro Virtex-4 Tolerant support. Replaced references supported device families tool name(s) with hyperlink file. Updated v2.00.a; added Performance Resource Utilization table Virtex-6 Spartan-6; updated images.
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DS695 September 2009 Product Specification
Thin Film Transistor (TFT) Controller (v2.00a)
Notice Disclaimer
Xilinx providing this product documentation, hereinafter "Information," with warranty kind, express implied. Xilinx makes representation that Information, particular implementation thereof, free from claims infringement. responsible obtaining rights require implementation based Information. specifications subject change without notice. XILINX EXPRESSLY DISCLAIMS WARRANTY WHATSOEVER WITH RESPECT ADEQUACY INFORMATION IMPLEMENTATION BASED THEREON, INCLUDING LIMITED WARRANTIES REPRESENTATIONS THAT THIS IMPLEMENTATION FREE FROM CLAIMS INFRINGEMENT IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Except stated herein, none Information copied, reproduced, distributed, republished, downloaded, displayed, posted, transmitted form means including, limited electronic, mechanical, photocopying, recording, otherwise, without prior written consent Xilinx.
DS695 September 2009 Product Specification
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