DP83916EB-AT AT9010 AT9010B DP83950EB-AT DP8392
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DP83916EB-AT High Performance Compatible Master Ethernet Adapter Card
DP83916EB-AT High Performance Compatible Master Ethernet Adapter Card
INTRODUCTION DP83916EB-AT board high performance 16-bit Ethernet adapter card designed PC-AT compatible computer systems employs unique master architecture which transfers packet data rates Megabytes second from PC-AT's system memory during Ethernet reception transmission Featuring National Semiconductor DP83916 Systems-Oriented Network Interface Controller (SONIC-16) AT9010 board functions master adapter card implementing Ethernet nodes design includes interface which enables PC-AT managed-hub applications Furthermore supports three types media functionality IEEE networks using DP83916 SONIC-16 DP83916EB-AT board maximizes master performance over existing adapter cards First SONIC-16's highly integrated design eliminates need mapped dual port adapter designs Second SONIC-16's master architecture facilitates writing reading network data directly from main system memory This architecture supported SONIC-16's latency tolerance link-list buffer management scheme 24-bit memory addressing capability AT9010 AT9010B provides compact inexpensive high performance interface DP83916EB-AT adapter card integrates much SONIC-16 signal decoding control logic Because most options selected software drivers jumpers reduced DP83916EB-AT offers management interface logic implement managed when board coupled with DP83950EB-AT RICKIT This interface allows SONIC-16 emulate Inter-RICManagement hence SONIC-16 receive packets containing network data collision information also transmit packets over this using management DP83916EB-AT makes network statistics available manager located anywhere network Finally adapter card offers multiple IEEE cable media options DP8392 Coaxial Transceiver Interface Thin Ethernet connector Thick Ethernet Twisted-Pair
National Semiconductor Application Note Denise Troutman November 1992
DP83916EB-AT adapter card provides cost 15-chip master Ethernet node that supports three media options IEEE networks SONIC-16 management included addition only five chips DP83950EB-AT RICKIT FEATURES Efficient DP83916 Systems-Oriented Network Interface Controller (SONIC-16) Highly integrated AT9010 PC-AT master interface Inter-RIC Management interface optional connection DP83950EB-AT RICKIT Selectable media interfaces Thin Ethernet Twisted-Pair Thick Ethernet Optional EPROM remote system boot Four programmable master data transfer speeds including Megabytes second Selectable interrupt lines request channels adapter card addresses EPROM memory addresses
HARDWARE OVERVIEW block diagram DP83916EB-AT board shown Figure design broken into four sections slave logic master logic management media interface slave logic facilitates AT's accessing SONIC-16's registers AT9010's registers Ethernet Address PROM network Boot EPROM (socket) Much slave circuitry decode (chip selects) control logic implemented AT9010 slave devices accessed memory space master logic assists SONIC-16 transferring data directly from AT's system memory includes signal translation control logic required access large portion which integrated AT9010 SONIC-16 uses controller arbitrate between requestors control additional buffers address data buses
AN-855
TRI-STATE registered trademark National Semiconductor Corporation SONICRICInter-RICare trademarks National Semiconductor Corporation Ethernet registered trademark Xerox Corporation registered trademark Lattice Semiconductor Corporation PC-AT registered trademarks Corporation trademark used under license from Advanced Micro Devices C1995 National Semiconductor Corporation
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RRD-B30M75 Printed
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FIGURE DP83916EB-AT Board Block Diagram management logic interfaces Inter-RIC Management SONIC-16 enables SONICto gather network statistics packets transmitted from DP83950EB-AT evaluation board receive control packets from remote nodes (managers) transmit packets network logic includes turbo transceivers (BTLs) driving signals arbitration signals flip-flop which provides transmit clock media interface connects adapter card three network media choices Coax 10BASE2 (Thin Ethernet) 10BASE5 (Thick Ethernet) 10BASE-T (Twisted-Pair) Connection requirements each choice will described later DP83916EB-AT supports versions interface chip SONIC-16 PC-AT platform original AT9010 AT9010B board populated with AT9010 (U11) required bugs AT9010 chip bugs corrected AT9010B adapter cards containing this version chip should have placed socket (Note subsequent references this application note ``AT9010'' apply both versions chip unless specified otherwise Since populated when AT9010B populated signals driven from AT9010B into will have effect appendices this application note provide following information Appendix equations Appendix Bill Materials (BOM) Appendix AT9010 AT9010B Register Descriptions Appendix Signal Descriptions Appendix DP83916EB-AT Card Layout Appendix Test Layout Appendix Design Change Recommendation Appendix VIII Compatibility Testing addition detailed schematic DP83916EB-AT adapter card also located this application note SLAVE LOGIC SECTION During slave cycles AT's accesses four slave devices card SONIC-16's internal registers Ethernet address PROM AT9010's five internal registers boot EPROM Slave mode also includes card initialization AT9010 provides chip select control signal conversion logic configuration registers specify address mapping SONIC-16 register select information EPROM memory address decoding interrupt line specification
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FIGURE Slave Logic Block Diagram MAPPING SONIC-16 registers AT9010 registers Ethernet address PROM reside PC-AT's space AT9010 offers choice seven 32-byte blocks (shown Table place card within space user board into these blocks selecting unused portion space positioning jumpers JP1- accordingly shorted jumper corresponds open jumper corresponds values these jumpers enabled onto data during power subsequently initialize AT9010's Configuration Register bits TABLE Space Mapping actual mapping SONIC-16 registers AT9010 registers PROM SONIC-16 paging register into 32-byte blocks space shown Figure Bytes AT9010's Configuration Registers bytes Ethernet address PROM byte AT9010's Configuration Register bytes SONIC-16's registers other bytes reserved
SONIC-16 REGISTERS locations) AT9010 CONFIGURATION REGISTERS RESERVED
FIGURE Card 32-Byte Space
Bits
Address (Hex) 100-11F 120-13F 140-15F 160-17F 300-31F 320-33F 340-35F 340-35F
AT9010 CONFIG RESERVED ETHERNET ADDRESS PROM bytes) RESERVED
DP83916EB-AT default setting short (jumper open (jumper off)
SONIC-16 AT9010 REGISTER ACCESS limited PC-AT space only eight SONIC-16's registers accessible time DP83916EB-AT accommodates this partitioning SONIC-16's registers into eight pages eight registers (16-bit locations) access registers must drive 6-bit register address First sets page number executing 8-bit write cycle AT9010's Configuration Register bitsk5 These data bits drive three most significant SONIC-16 register address bits RAk5 Then executes 16-bit read write cycle using PC-AT's lower address lines SAk3 drive SONIC-16's address bits RAk2 which select appropriate register This completes SONIC-16 register access Note most SONIC-16 register accesses actually require only cycle because SONIC-16 registers which accessed most often located Page AT9010 configuration registers bits wide read written through standard 8-bit cycles PROM EPROM MEMORY MAPPING PROM 32-byte register which holds unique 6-byte Ethernet Address offset locations 08H-0DH read 8-bit read cycles optional boot EPROM (socket) which resides PC's BIOS memory space also 8-bit device used EPROM programmed with instructions that scanned power-up enable diskless workstation boot remotely from network then access server boot EPROM memory mapped above 640k within first megabyte memory Specifically AT9010 places EPROM section memory within 0C0000H 0DFFFFH address range shown Figure upper address decode bits LAk23 predetermined AT9010 complete base address decode bits SAk16 must programmed user Configuration Register AT9010 configured EPROM During EPROM memory accesses address lines LAk23 decoded notify AT9010 EPROM activity This decode accomplished comparator shown Figure DP83916EB-AT design supports EPROM (socket) hence memory base address options sections memory Table shows decode EPROM Note SA13 driven directly into EPROM therefore Configuration Register don't care EPROM used Configuration Register bits must enable EPROM select EPROM EPROM used these bits must disable EPROM
TABLE EPROM Memory Base Address Bitsk5 bit5 bit4 bit3 bit2 Base Address EPROM (Hex) 0C0000 0C4000 0C8000 0CC000 0D0000 0D4000 0D8000 0DC000
INTERRUPT LINE SELECTION SONIC-16 transmits receives packets from network generates interrupts (via IRQx line from AT9010) This results several slave cycles which read SONIC-16's Interrupt Status Register service interrupt When original AT9010 chip asserts interrupt sets non-latched interrupt indicator Configuration Register that cleared when IRQx cleared AT9010B interrupt indicator latched hence maintained even IRQx deasserts cleared writing CR15 DP83916EB-AT user select four interrupt lines programming AT9010's Configuration Register Table presents IRQx choices (lines indicates necessary bits select appropriate line addition choosing IRQx line user must also program Configuration Register mask unmask chosen interrupt upon assertion from SONIC-16 TABLE Interrupt Line Selection
Bits
Reference
IRQx Signal
Comparator Decode LA23 LA22 LA21 LA20 LA19 LA18 LA17
Configuration Register SA16 bit5 SA15 bit4 SA14 bit3 SA13 bit2
FIGURE EPROM Address Specification
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FIGURE Write Cycle SONIC-16 Registers SLAVE CYCLES following section presents basic description timing diagrams signals generated AT9010 SONIC-16 when DP83916EB-AT slave mode detailed description relevant signals associated with cycles adapter card memory accesses EPROM located Appendix this application note DP83916EB-AT adapter card designed that power-up POSCS3 will enable address adapter card onto data This address latched into bitsk7 Configuration Register locates card space Software drivers must subsequently program registers with correct data operation initiates cycle driving address onto asserting BALE high generating -IORD -IOWR AT9010 then generates chip select appropriate slave device SONIC-16 registers which located space written read Because they bits wide special signal lOCSl6 driven duration SONIC-16 access AT9010 drives IOCHRDY (not ready) after address lORD lOWR signals asserted (and MEMR MEMW active) (Note this document IOCHRDY will broken down into IOCHRDYBUS IOCHRDYAT order give clear explanation signal IOCHRDY's purpose explanation these signals refer signal descriptions equations appendices schematic this application note When SONIC-16 latched write data driven valid read data generates RDYo terminate cycle this time AT9010 asserts IOCHRDY high example signal timing write cycle SONIC-16 registers shown Figure Most devices (like DP83916EB-AT during slave mode) drive IOCHRDY after address command signal asserted However some compatible machines chip sets (from Chips Technologies VLSI Technologies) with modified timing characteristics whereby during 16-bit cycles PC's controller samples IOCHRDY before lORD IOWR driven This problem detailed document ``PC-AT Design Considerations DP83902EB-AT'' accommodate this early sampling problem AT9010B programmed drive IOCHRDY immediately upon SONIC-16 register address decode AT9010B then uses gating signal maintain IOCHRDY cycle cycle stop asserting IOCHRDY cycle memory cycle Specifically AT9010B Configuration Register IOCHRDY will driven early based address decode SONIC-16 register then qualified with gating signal IOCHRDY will follow standard address decode SONIC-16 register IORD IOWR inactive MEM-R MEMW early IOCHRDY feature should used cycles functioning properly Furthermore supported original AT9010 chip
AT9010's registers written read 32-byte PROM however only read either device read cycles finished once data been enabled onto read write cycle AT9010 register completed once data been latched AT9010 IOCHRDY driven during 8-bit cycles either these devices initiates boot EPROM cycle driving address onto asserting BALE high generating MEMR Once AT9010 chip selected EPROM data enabled onto data memory cycle complete EPROM read cycle illustrated Figure IOCHRDY driven during EPROM cycles DP83916EB-AT REGISTER INITIALIZATION Upon power-up DP83916EB-AT card pulses card's address into Configuration Register Subsequently software initializes Configuration Registers operation original AT9010 enabled setting Configuration Register this original AT9010 will respond host access except hard reset AT9010B card enabled regardless state this AT9010B supports software reset Configuration Register AT9010B will reset
chip's functions default condition except Configuration Registers bits Configuration Register software must subsequently write clear this reserved original AT9010 card lost space only recovered hard reset
Note AT9010B corrects bugs AT9010 offers additional features DP83916EB-AT card demonstration software support both versions interface chip Appendix provides details regarding specific programming Configuration Registers
MASTER LOGIC SECTION During master mode AT's allows SONIC-16 take over system access main memory directly SONIC-16 uses controller assist arbitration process addition utilizes AT9010's interface logic requesting generating compatible read write signals block diagram showing master logic presented Figure CONTROLLER CHANNEL SELECTION data transfer PC-ATs utilize 8237A controllers with four channels each Controller contains channels which support byte transfers typically reserved diskette SDLC cascaded with Controller which contains channels support word transfers While channel used cascade Controller channels usually spare
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FIGURE Memory Read Cycle Boot EPROM
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FIGURE Master Logic Block Diagram user must select spare channels programming AT9010's bits Configuration Register user select request line shown Table This will route request (DRQx) acknowledge (-DACKx) signals from appropriate controller channel TABLE Channel Selection Bitsk1 Reference Channel TABLE Controller Programming
Register COMMAND DRQx Active High DACKx Active Rotating Priority Enable Channel MODE Cascade Channel Write Single Mask Unmask Channel
Addr
Data
Channel
example adapter card configuration shown Figure Controller cascaded with Controller Hence channel Controller must programmed cascade mode that whenever Controller requests Controller will arbitrate without executing memory cycles software driver must also program channel used SONIC-16 cascade mode This done writing commands shown Table registers appropriate Controller These commands define sense DROx DACKx lines arbitration priority algorithm (fixed rotating) enable cascade particular channel unmask channel
MASTER CYCLES following section presents basic description AT9010 SONIC-16 signals generated when DP83916EB-AT becomes master illustrates timing diagram presents basic description relevant
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FIGURE Example Controller Configuration signals associated with SONIC-16's read write cycles system memory more detailed description signals associated with master cycles located Appendix this application note DP83916EB-AT transmits receives packets accesses system memory read write packet data descriptor information SONIC-16 requires these operations hence drives HOLD AT9010 which translates this request into active DRQx line Once available controller responds AT9010 chosen DACKx line Subsequently AT9010 asserts MASTER relays DACKx SONIC-16 asserting HLDA This handshake shown Figure Once SONIC-16 gained ownership generates multiple read write cycles AT's system memory begin cycle SONIC-16 drives MW-R AT9010 Then AT9010 drives HAOE enable address buffers HDOE0 HDOE1 enable data buffers HDDIR high (memory write) (memory read) establish direction flow data through data buffers beginning each transfer cycle SONIC-16 drives address into address buffers asserts address strobe AT9010 latches address onto rest transfer depends whether SONIC-16 writing data reading data from system memory SONIC-16 writing data AT9010 will strobe MEMW each transfer SONIC-16 will source data which valid after falling edge first BSCK each cycle Once system asserts IOCHRDY high AT9010 will drive RDYi SONIC-16 complete write cycle timing diagram master write cycle shown Figure SONIC-16 reading data AT9010 will pulse MEMR each read transfer system memory will source data which latched SONIC-16 rising edge first BSCK after RDYi asserted Again when asserts IOCHRDY high AT9010 will drive RDYi SONIC-16 complete read cycle DP83916EB-AT CYCLE CONFIGURATION There timers which govern SONIC-16's activity during master mode first hold timer which activated ensure SONIC-16 cannot begins when AT9010 receives DACKx from expires after depending whether AT9010 Configuration Register
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FIGURE Master Write Cycle this point AT9010 pre-empts SONIC deasserting HLDA original AT9010 chip does follow proper timing requirements pre-empting SONIC-16 this been corrected both (U11) AT9010B certain with slow memory cycles pre-emption causes FIFO underruns overruns during loopback diagnostics SONIC16's heavy during this mode Because these compatibility issues pre-emption disabled enable disable) AT9010 Configuration Register This drives signal PRE-EMPT high low) (U11) enable disable) pre-emption AT9010B program second timer timer purpose shorten SONIC-16's acquisition time when SONIC-16 control then deasserts HOLD re-asserts HOLD before expired original AT9010 these conditions satisfied timer expired original AT9010 will maintain DRQx However conditions satisfied timer expired SONIC will lose once
deasserts HOLD This true regardless state signal PRE-EMPT AT9010B timer independent timer timer disabled AT9010B's timer enabled disabled) setting both versions AT9010 timer active expired timer active then SONIC-16 deasserts HOLD then re-asserts HOLD before expired HLDA follows HOLD DRQx maintained high AT9010 offers option different master transfer cycle speeds These speeds define widths MEMR MEMW pulses each cycle They selected Configuration Register outlined Table TABLE Master Transfer Cycle Speeds
DP83916EB-AT several DP83950EB-ATs this configuration SONIC-16 gathers buffers network statistics packets sent from RICs DP83950EB-ATs SONIC-16 also transmits over allowing management statistics accessed node network block diagram adapter card portion managed shown Figure comprehensive list management signals presented Appendix this note RECEIVED PACKET FORMAT Packets sent RICs DP83950EB-ATs SONIC-16 over Management portion format these packets differs from format standard Ethernet packets First preamble start frame delimiter packets 5-bit sequence 01011 rather than standard eight bytes 10101 1011 Second packets have Return Zero (NRZ) format because they sent over rather than through physical layer Third seven bytes status information appended RICs after cyclical redundancy check (CRC) sequence packet This information contains statistics regarding packet's transmission over network Because status field appended packet SONIC-16 interprets last four bytes status flags error even though there legitimate error this reason SONIC-16's Receive Control Register (RCR) must programmed accept packets with errors
Bits
Megabytes
MANAGEMENT DP83916EB-AT incorporates interface InterRIC Management DP83950EB-AT This interface implements managed connecting
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FIGURE Management Interface
Finally packet's destination specify SONIC-16 node packet contains management commands intended SONIC-16 another node packet sent SONIC-16 purpose saving status information Hence SONIC-16's must configured accept packets including runt packets address type packets addition accepting errored packets described above) packet that sent over management format shown Figure detailed description information contained seven bytes management statistics located DP83950 Repeater Interface Controller (RIC) Data Sheet PACKET RECEPTION SIGNALS signals MCRS MRXD MRXC sent over management management carrier sense management data management clock which specify packets sent SONIC-16 They buffered through inverting turbo transceivers (BTLs) BTLs drive signals with same characteristics signals DP83950EB-AT card features include high density backplane capabilities minimum delay fast voltage switching characteristics however BTLs required applications described above packets format hence buffered signals driven SONIC-16 signals These signals connected directly SONIC-16 SONIC-16 programmed (USER PIN3 AT9010 Configuration Register external ENDEC mode With above configuration SONIC-16 will buffer every packet received from however programmed save memory space ``compressing'' packets whose data intended reception SONIC-16 With this feature SONIC-16 buffer status information portion data status entire packet This accomplished SONIC-16 control signal called PCOMP PCOMP asserted management receive clock signal MRXC will inhibited during transmission packet data enabled during transmission packet's seven bytes status information This causes packet ``compressed'' only destination address status data buffered memory
order packet compression SONIC-16's DCR2 register must programmed assert PCOMP upon (Content Addressable Memory) register match mismatch managed DCR2 must programmed assert PCOMP upon mismatch Then SONIC-16's programmed with Ethernet address packets with destination addresses equal SONIC16's address will buffered other packets will compressed managed bridge DCR2 register must programmed assert PCOMP upon register match this case SONIC-16's programmed with addresses RICs from which packet being transmitted Then only packets intended SONIC-16 nodes other side bridge link will buffered packets which merely repeated connected SONIC-16 then forwarded SONIC-16 over Management will compressed save status information only addition programming SONIC-16's DCR2 Packet Compress Decode (PCD) Register must initialized with number bytes after including seven bytes status information transferred SONIC-16 asserts PCOMP According DP83950 Data Sheet value this register must less than equal bytes actual value however must between bytes because SONIC-16 requires bytes destination address five bits address compare time order determine whether assert PCOMP user enters value less than seven bytes driver software should change value seven that PCOMP will operate properly this scenario bytes destination address byte source address will buffered along with seven bytes status information example PCOMP effect MRXC shown Figure this example RIC's transmits packet counts bytes from beginning destination address Because SONIC-16 asserts PCOMP inhibits MRXC bytes after beginning packet enables MRXC last seven bytes status data
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FIGURE Packet Reception Over Management
PACKET RECEPTION When SONIC-16 begins receiving packet compares destination address packet with addresses content addressable memory (CAM) register SONIC-16 configured managed there match entire packet along with seven bytes status information buffered memory where waits processed upper-level management software there match SONIC-16 asserts PCOMP Management Depending value sending packet will inhibit receive clock signal MRXC during portion packet data enable during seven bytes status Hence only destination address portion source address data status information buffered memory where waits processed upper-level management software TRANSMITTED PACKET FORMAT Packets sent SONIC-16 RICs DP83950EB-ATs over Inter-RIC portion These packets have format standard Ethernet packets PACKET TRANSMISSION SIGNALS SONIC-16 transmits over Inter-RIC using transmit enable (TXE) transmit data (TXD) transmit clock (TXC) specify packets driven signal from flip-flop which divides external oscillator clock transmit signals connected SONIC-16's transmit pins have format They driven through inverting turbo transceiver (BTL) become Inter-RIC enable (IRE) Inter-RIC data (IRD) Inter-RIC clock (IRC) which connect directly Inter-RIC Because SONIC-16's interface Inter-RIC Management appears another rest network Hence SONIC-16 participates RICs' serial arbitration scheme transmission uses same handshake signals This arbitration scheme contained described following paragraphs actual equations located this application note RICs SONIC-16 connected serial arbitration scheme signals ACKi ACKo ACKo above SONIC-16 connects ACKi SONIC-16 ACKo SONIC-16 connects ACKi below SONIC-16 RICs pass permission transmit down chain driving ACKo high ACKi next chip chain Regardless whether SONIC-16 permission transmit does whenever management quiet there data send Hence when SONIC-16 wants transmit drives high SONIC-16 permission transmit ACKi high) activates ACTNd high notify RICs SONIC-16's transmit activity Inter-RIC SONIC-16 does have permission transmit ACKi low) activates ANYXNd high which notifies RICs SONIC-16 transmit collision
SONIC-16's collision (COL) driven when SONIC-16 transmitting either transmit collision occurs network lnter-RIC receive collision occurs RIC's port SONIC-16 transmitting collision occurs SONIC-16 sends pattern then backs Inter-RIC same time RICs send pattern then become idle After some time SONIC-16 attempts retransmit SONIC-16 transmitting collision occurs network RICs send their ports Management Interface Configuration (MIFCON) RIC's Interrupt Management Configuration Register determines outcome this collision event MIFCON collision occurs before packet's start frame delimiter whose packet collided will send 01011 followed seven bytes status (which reflect collision) SONIC-16 MIFCON collision occurs before neither packet status data transmitted over Management SONIC-16 Finally MIFCON collision occurs after packet's appends status information sends packet SONIC-16 drives transmit enable signal transmit which enables only when SONIC-16 configured external ENDEC permission transmit wants transmit This prevents from driving unless SONIC-16's transmission valid DP83916EB-AT CONFIGURATION MANAGEMENT adapter card must configured differently hub-management option First card cannot connected Inter-RIC Management physical layer interface same time Jumper must disconnected Second AT9010's USER PIN3 (bit Configuration Register must configure SONIC-16 external ENDEC mode Third AT9010's USERPIN2 (bit Configuration Register must enable receiving MEDIA INTERFACE network interface DP83916EB-AT card offers three media interface options addition Inter-RIC Management interface) Thin Ethernet Thick Ethernet Twisted-Pair Only three interfaces used given time cabling requirements specified following section physical layer block diagram given Figure Coaxial Interface features DP8392C Coaxial Transceiver Interface (CTI) coaxial cable line driver receiver connected between SONIC-16 connector Thin Ethernet coaxial cable transmission converts signals single-ended 10BASE2 signals reception converts single-ended 10BASE2 signals signals isolation between SONIC-16 required IEEE satisfied signal lines transformer Power isolation performed converter which supplies with power supply operation adapter card Thin Ethernet environment necessary short which supplies with
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FIGURE Media Interface Block Diagram Interface option allows DP83916EB-AT with several alternative cable media Possible choices include Thick Ethernet cable 10BASE2 networks Twisted-Pair cable 10BASE-T networks on-board transformers required isolation because connector medium attachment unit (MAU) which houses transformer converter However capacitors used isolation fault tolerance interface open disable power interface options jumper settings summarized Table imperative note that only network interface option cable used time Multiple cables wiII result network errors TABLE Jumper Selection Media Interface Management Short Open Open
DP83916EB-AT default setting
Network Interface Thin Ethernet Thick Ethernet Twisted-Pair HUB-Management
HARDWARE CONFIGURATION There versions interface chip AT9010 AT9010B DP83916EB-AT design supports both chips with following component placement considerations original AT9010 used (U11) containing AT9010 fixes must populated addition resistors must populated AT9010B used (U11) must left open resistors must populated above considerations determined time board assembly Hence they should concern card user user must determine address card jumpers optional boot EPROM used must inserted adapter card DP83916EB-AT's media interface user must select interface options including Thin Coax (10BASE2) (with BASE5 10BASE-T) configure according Media Interface Section management user must install DP83950E-B-AT RICKIT disconnect DP83916EB-AT media interface connections open above hardware settings must considered prior inserting board into slot SOFTWARE CONFIGURATION DP83916EB-AT features many user options which selected programming configuration registers AT9010 following summarizes software options available references AT9010 given (Configuration Register Number Applicable Bits) complete listing AT9010 Configuration Registers demonstration software defaults refer Appendix
DP83916EB-AT CONFIGURATION order maximize utility options DP83916EB-AT adapter card imperative that board configured correctly following section highlights hardware software configuration issues which must considered prior installation card first time
Card enable (CR0 Bit0) enables disables original AT9010 Once disabled original AT9010 only re-enabled with hard reset AT9010B always enabled regardless state this Selectable interrupt lines (CR0 Bitsk2 four must chosen IRQ3 IRQ4 IRQ5 IRQ9 Interrupt unmask (CR0 unmasks masks IRQx signal when driven SONIC-16 timer (CR0 enables disables timer AT9010B This timer always enabled original AT9010 Maximum hold time after detection DACKx (CR0 original AT9010 this timer enabled disabled) setting AT9010B enabled disabled) setting USER PIN1 PRE-EMPT (CR1 enables disables SONIC-16 pre-emption original AT9010 USER PIN2 (CR1 Bit2) drives receive enable management interface This must when using management USER PIN3 (CRl Bit3) drives internal SONIC-16 ENDEC when using physical interface external ENDEC when using management interface address card (CR1 Bits seven choices must made these outlined Slave Logic Section Note address programmed AT9010's must match address selected JP1-JP3
EPROM memory size disable (CR2 Bits selects EPROM EPROM EPROM disable disable EPROM memory address (CR2 Bits this address must specified using EPROM Details given Slave Logic Section Selectable lines (CR3 Bits four must chosen DMA7 MEMW cycle extension (CR3 when this option will extend -MEMW cycle allow additional address set-up time IOCHRDY assert (CR3 selects IOCHRDY normal assert early assert AT9010B only Slave Logic Section details Master data transfer cycle (CR3 Bits four speeds must chosen Channel check enable (CR3 used DP83916EB-AT This should disable AT9010 check output Software reset (CR15 supported AT9010B When this AT9010B resets chip's functions their default conditions except CR15 bits This cleared writing CR15 clear original AT9010 setting this causes card lost space only recovered hard reset ADDITIONAL INFORMATION Additional information AT9010 Master Interface Chip available through Technology Clyde Avenue Mountain View 94043 (415) 960-0448 (415) 960-0479
APPENDIX (U16) (U11) EQUATIONS This appendix provides equations (U16) (U11) contains arbitration equations management contains fixes bugs original AT9010 chip DP83916EB-AT Inter-RIC Management Interface (U16)
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DP83916EB-AT Original AT9010 Fixes (U11)
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APPENDIX BILL MATERIALS (BOM) DP83916EB-AT This appendix provides list components placed DP83916EB-AT original AT9010 populated (U11) must also populated resistors should left open AT9010B populated (U11) should left open should populated
Capacitors (58) Monolithic Monolithic Ceramic Disk Spark Monolithic Tantalum Monolithic Tantalum Tantalum Tantalum Monolithic
Resistors (46) unless otherwise specified)
populate original AT9010 populate AT9010B)
Integrated Circuits (17) DM74AS245 DM74S288 NMC27CP128 DM74ALS244A DM74ALS541 DM74ALS521 PLXAT9010 GAL20V8A-15 DP83916B 74F74 DS3893A PAL16L8A DP8392V
(not supplied board)
(populate original AT9010 populate AT9010B)
Connectors Magnetics Jumpers Test Pins (35) TP35 Sockets 24-pin Dual in-line socket (U11) 20-pin Dual in-line socket (U16) 16-pin Dual in-line socket PROM (U3) 28-pin Dual in-line socket EPROM (U4) 132-pin Socket SONIC-16 (U12) Housing Sub-Assembly Cover (AMP Cover (AMP Single post pins Single Jumpers Shunt Block with spacing PE64103 (Pulse Engineering) LT6003 (Valor) PM7102 (Valor) DC-DC Converter Connector socket 15-Pin Connector socket (AMP 227161-2) (AMP 9020A 747845-4)
821949-5) 821942-1)
Others Bracket Slide Latch Oscillator 40%-60% Duty 001% Tolerance MMBD1203 Diode Face plate 15-pin D-Connector (J5) (AMP 745583-5)
Note (EPROM) marked ``not supplied board'' component socket left open
APPENDIX AT9010 AT9010B CONFIGURATION REGISTERS This appendix describes features programming original AT9010 AT9010B Configuration Registers assumed that bits have same function both chips unless otherwise noted demonstration software ``sonicpla exe'' defaults also provided CONFIGURATION REGISTER default
Short Name Default
reserved hold time AT9010 reserved
AT9010B enable timer enable disable)
unmask interrupt unmask mask) interrupt select IRQ3 IRQ4 IRQ5 IRQ9) AT9010 card enable
AT9010B reserved CONFIGURATION REGISTER default
Short Name Default
base address (000 AT9010 reserved
AT9010B disable hold timer disable enable)
external ENDEC Inter-RIC Management internal external) enable receive Inter-RIC Management enable disable) pre-empt enable enable disable SONIC pre-emption AT9010) User (not used)
CONFIGURATION REGISTER default
Short Name Default
PROM select size disable disable) PROM base address (for EPROM 000X C0000 001X C4000
010X C8000H 011X CC000 100X D0000 101X D4000H 110X D8000 111X DC000 reserved
CONFIGURATION REGISTER default
Short Name Default
channel check (output) assert (not used) mask channel check (not used) master data transfer cycle speed sec) AT9010 reserved
AT9010B IOCHRDY signal assert normal early IOCHRDY signal)
extra time extended normal -MEMW cycle) channel select DMA3
CONFIGURATION REGISTER default
Short Name Default
AT9010 reserved
AT9010B software reset soft reset non-soft reset mode)
channel check (input) indicator (not used) SONIC register page select interrupt indicator reserved
APPENDIX DP83916EB-AT SIGNALS This appendix presents detailed description adapter card control signals specific timing slave cycles initialization master cycles management They presented form SIGNAL (ORIGIN DESTINATION) SIGNAL (ORIGIN DESTINATION ORIGIN DESTINATION) CLOCK SIGNALS clock signals provided synchronous operations AT9010 SONIC-16 optional interface They described detail below AT9010 SONIC-16 Flip-flop) oscillator signal which drives synchronous operations AT9010 provides clock SONIC16's ENDEC also provides signal flip-flop divide circuit which drives transmit BSCK (AT9010 GAL) provides timing SONIC-16 logic (Flip-flop SONIC-16 BTL) provides timing transmission packets when using hub-management interface SLAVE CYCLE SIGNALS following control signals provide interrupt reset status functions (SONIC-16 AT9010) active when SONIC-16 asserts interrupt request IRQx (AT9010 bus) asserted AT9010 when SONIC-16 asserts interrupt request line four lines IRQ9 IRQ5 IRQ4 IRQ3 selected interrupt programming bits AT9010's Configuration Register AT9010) provides hard reset AT9010 This signal initializes logic internal AT9010 LRESET -RESET (AT9010 SONIC-16) provides hardware reset SONIC-16 asserted deasserted synchronous BSCK AT9010B this signal inverted inside chip driven directly SONIC-16 (SONIC-16 AT9010) SONIC-16 status lines which indicate current SONIC-16 operation USER PIN3 (AT9010 SONIC-16 PAL) drives input SONIC-16 enable SONIC16's internal ENDEC (when using media interface) high disable ENDEC (for managed-hub applications) level this signal AT9010's Configuration Register USER PIN2 (AT9010 BTL) drives receive enable signal turbo-transceivers (BTL) when using SONIC-16 hub-management interface POSCS3 (AT9010 A-buffer) enables address buffer load address adapter card into AT9010 Configuration Register bits after hard reset other POSCS pins connected because registers loaded software rather than hardware following signals utilized during slave mode both cycles EPROM cycles BALE AT9010) driven high slave cycles DP83916EB-AT
HDDIR (AT9010 D-Buffers) input data buffers which identifies direction data transfer drives high data transfers during EPROM read cycle drives data transfers adapter card during write cycle IOCHRDYAT IOCHRDYBUS (AT9010 bus) input output signals both AT9010 original AT9010 translates AT9010's IOCHRDYAT into IOCHRDYBUS drives this signal complete 16-bit cycle SONIC-16's registers AT9010B IOCHRDY driven from AT9010B directly early IOCHRDY signal driven AT9010B This detailed Slave Logic Section During cycles following signals generated AT9010 GAL) signal asserted high ports during cycles prevent resources that have active DACKx from responding controller cycles AT9010 uses level qualify accesses registers space IORD AT9010 GAL) indicates that system reading data from register IOWR AT9010 GAL) indicates that system writing data register (AT9010 SONIC-16) chip select SONIC-16 IOCS16 (AT9010 bus) driven when SONIC-16 registers accessed indicates 16-bit slave device PROMID (AT9010 PROM) chip enable PROM (AT9010 SONIC-16) asserted AT9010 SONIC-16 During register write cycle this signal indicates valid address During register read cycle indicates SONIC-16 begin sourcing data SW-R (AT9010 SONIC-16) driven SONIC-16 identify whether current register access read write cycle RDYo (SONIC-16 AT9010) driven after system accessed SONIC-16's registers SONIC-16 completed cycle SONIC-16 this signal insert wait states cycle following signals driven during memory cycles boot EPROM EPROMRD (AT9010 EPROM) chip enable boot EPROM HAENB (Comp AT9010) signal which indicates when BIOS EPROM being accessed output comparator which uses base address EPROM bitsk5 LAk23 inputs address decode MEMR AT9010) input AT9010 indicate memory read cycle during EPROM memory access MASTER CYCLE SIGNALS description master signals generated while requesting during memory read write cycles given below Again format followed SIGNAL (ORIGIN DESTINATION) HOLD (SONIC-16 AT9010 GAL) SONIC-16's request signal that notifies AT9010 that SONIC-16 requesting
DRQx (AT9010 bus) conversion HOLD driven AT9010 through controller DACKx AT9010) acknowledgment signal which grants controller ownership MASTER (AT9010 bus) asserted when DACKx received disables buffers HLDAAT HLDASONIC (AT9010 SONIC-16) generated AT9010 when been granted ownership bugs original AT9010 HLDAAT extended clock before being driven SONIC-16 HLDASONIC AT9010B problem corrected HLDA driven directly SONIC-16 USER PIN1 PRE-EMPT (AT9010 GAL) drives enable disable) SONIC pre-emption This original AT9010 only following signals driven during memory read write cycles master mode operation BALE AT9010) high duration master mode (SONIC-16 AT9010) address strobe driven SONIC-16 which notifies AT9010 valid address HAOE (AT9010 A-buffers) enable address buffers which gate address from adapter card MW-R (SONIC-16 AT9010) input AT9010 SONIC-16 indicate read operation (signal low) write operation (signal high) MEMR (AT9010 bus) AT9010 conversion signal indicates SONIC-16 read cycle system memory MEMW (AT9010 bus) AT9010 conversion signal MW-R indicates SONIC-16 write cycle system memory SBHE (AT9010 bus) 9010) denotes data most significant byte Dk15 data notifies system during SONIC-16 memory write notifies AT9010 during SONIC-16 memory read HDDIR (AT9010 D-Buffers) input data buffers which identifies direction data transfer drives high data transfers during memory write cycle drives data transfers adapter card during memory read cycle HDOE1 (AT9010 D-buffer) enables data buffer upper byte data Dk15 HDOE0 (AT9010 D-buffer) enables data buffer lower byte data IOCHRDYBUS IOCHRDYAT AT9010) input output signals both AT9010 original AT9010 translates bus's IOCHRDYBUS into IOCHRDYAT drives this signal AT9010 insert wait states complete memory access AT9010B drives IOCHRDY directly AT9010B
RDYi (AT9010 SONIC-16) indicates SONIC-16 that memory cycle completed SONIC-16 will wait this signal before re-asserting begin another cycle MANAGEMENT SIGNALS following signals generated during management interface signals presented format SIGNAL (ORIGIN DESTINATION) SIGNAL (ORIGIN DESTINATION ORlGIN DESTINATION) MCRS SONIC-16) management carrier sense which indicates data SONIC-16's receive lines MRXD SONIC-16) management receive data MRXC SONIC-16) management receive clock PCOMP (SONIC-16 bus) SONIC-16's packet compression output which causes transmitting inhibit MRXC clock upon mismatch packet's destination address with SONIC-16's when SONIC-16 managed-hub mode (SONIC-16 bus) SONIC-16's transmit enable signal (SONIC-16 bus) SONIC-16's transmit data (Flip-flop SONIC-16 bus) transmit clock signal ACKI PAL) passes permission (ACKI denial (ACKI SONIC-16 from above arbitration chain (This transmission arbitration ACKO (PAL bus) passes permission (ACKO transmit over Inter-RIC below SONIC-16 SONIC-16 permission transmit does want transmit ACKO passes denial (ACKO SONIC-16 does have permission (ACKI SONIC-16 wants transmit (ACKI (PAL BTL) transmit drive enable asserted when SONIC-16 transmits (TXE permission transmit (ACKI configured external ENDEC (EXT ACTNd (PAL BTL) notifies RICs that SONIC-16 wants transmit asserted when SONIC-16 transmits (TXE permission transmit (ACKI ANYXNd (PAL BTL) asserted when SONIC-16 transmits (TXE does have permission transmit (ACKI ANYXNd indicates collision Inter-RIC ANYXNs (BTL PAL) senses transmit collisions InterRIC network (PAL SONIC-16) driven when there transmit collision Inter-RIC (ANYXN there receive collision network (COLN during either event SONIC-16 transmitting (TXE COLN PAL) indicates receive collisions network
APPENDIX DP83916EB-AT CARD COMPONENT PLACEMENT This appendix illustrates placement DP83916EB-AT components Special layout considerations DP8392 (Coaxial Transceiver Interface) identified (Details regarding these considerations found data sheet DP8392 silk line illustrates place board which power ground planes Inter-RIC Management signals non-overlapping hence full card into half card along this line located adapter card shown test pins provided card test signals defined Appendix DP83916EB-AT Layout
11707
APPENDIX TEST LAYOUT test pins their associated signals presented below Most other signals probed extender card
11707
APPENDIX DP83916EB-AT DESIGN CHANGE RECOMMENDATION This appendix outlines design change recommendation future designs which implement both management alternative media same card There signal which driven from flip flop (U14) (pin SONIC-16 (U12) Inter-RIC Management transmit (U17) This signal intended provide transmit clock SONIC-16's when SONIC configured management hence external ENDEC mode current design DP83916EB-AT however provides whether SONIC-16 internal ENDEC mode stand-alone node) external ENDEC mode manager) When SONIC-16 internal ENDEC mode drives signal (from ENDEC) chip Because flip flop also driving this node problem could arise clocks become phase Although problems have arisen testing recommended that following changes made future designs implementing same functionality DP83916EB-AT these changes will implemented next version this adapter card Place jumper between flip-flop output SONIC-16's Populate jumper during management mode only Jumper Solution
11707
Place TRI-STATE buffer (74AS241A) between flip-flop SONIC-16's USER PIN3 from AT9010 buffer enable When internal ENDEC buffer will disabled When external ENDEC buffer will enabled signal will drive into SONIC-16's transmit TRI-STATE Buffer Solution
11707
Delete flip-flop (U14) replace (U11) with registered (GAL16V8) Input clock into GAL's clock (pin Define assignment (pin Change device declaration ``P16V8R'' Include equations following equations signal will only drive when external ENDEC mode When will TRI-STATE
Note defines that equation clocked rising edge signal Since equations asynchronous except equation there should only colon before equal sign equation
This solution reduces overall chip count places management signals However because signals traversing half length card radiation noise increased Inter-RIC Management Solution
11707
Additional Equations
APPENDIX VIII COMPATIBILITY TESTING This appendix describes basic compatibility testing results DP83916EB-AT DP83916EB-AT been tested various PC-AT Compatible EISA machines original AT9010 chip used SONIC-16 pre-emption disabled master data transfer rate following basic tests were used Initialization loopback load Ethernet address PROM read EPROM enable read Simultaneous transmission reception two-node network Continuous manual loopback (set FE00h CTDA link field CTDA register current address
DP83916EB-AT passed basic tests following PC-AT Compatible EISA machines
Machine 386DX Clone Clone 386SX Clone Clone Compaq Compaq 486DX Dell Dell 486SX Dell 486DX Everex 386SX Everex Zeos EISA 386DX EISA Compaq EISA Compaq EISA 486SX Compaq EISA 486DX Dell EISA Dell EISA 486DX EISA EISA
Fastest Master Transfer Speed
EISA
11707
Interface
11707
Note original AT9010 install leave open AT9010B install leave open
Interface (Continued)
11707
SONIC Inter-RIC Management Interface
11707
SONIC Inter-RIC Management Interface (Continued)
11707
Media Interface
DP83916EB-AT High Performance Compatible Master Ethernet Adapter Card
Note configured transmit mode collision detection
11707
Note Unless otherwise specified resistors
Media Interface (Continued)
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION used herein Life support devices systems devices systems which intended surgical implant into body support sustain life whose failure perform when properly used accordance with instructions provided labeling reasonably expected result significant injury user
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