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Design Note DN506
Usage
Siri Namtvedt
CC1100 CC1101 CC1150 CC2500 CC2550 RXFIFO_OVERFLOW TXFIFO_UNDERFLOW
Introduction
useful controlling radio. GDO1 same interface, thus output programmed this will only valid when high. important notice that CC1150 CC2550 only have digital output pins; GDO0 GDO1.
CC1100, CC1101, CC2500 have three digital output pins, GDO0, GDO1, GDO2, which general control pins configured using IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG, IOCFG2.GDO2_CFG respectively. There several different signals that monitored pins hence
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Design Note DN506
Table Contents
KEYWORDS. INTRODUCTION. ABBREVIATIONS. IOCFGX 0X06 WHEN IOCFGX 0X06 3.1.1 Error Free (IOCFGx 0x06) 3.1.2 TXFIFO_UNDERFLOW (IOCFGx 0x06).3 WHEN IOCFGX 0X06 3.2.1 Error Free (IOCFGx 0x06) 3.2.2 RXFIFO_OVERFLOW (IOCFGx 0x06).4 3.2.3 Address Filtering (IOCFGx 0x06).5 3.2.4 Maximum Length Filtering (IOCFGx 0x06).5 IOCFGX 0X00 IOCFGX 0X01 IOCFGX 0X02 IOCFGX 0X03 IOCFGX 0X07 REFERENCES. GENERAL INFORMATION 10.1 DOCUMENT HISTORY.
Abbreviations
Cyclic Redundancy Check First-In-First-Out Interrupt Service Routine Micro Controller Unit Serial Peripheral Interface
FIFO
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IOCFGx 0x06
This signal probably most useful signal related packet handler engine. GDOx asserted when sync word been sent received, de-asserted packet. will de-assert when address filtering maximum length filtering leads packet being discarded FIFO overflows. will de-assert FIFO underflows. 3.1.1 when IOCFGx 0x06 Error Free (IOCFGx 0x06)
Assume transmitting following packet: 0x06, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06. radio configured variable packet length mode (PKTCTRL0.LENGTH_CONFIG insertion enabled (PKTCTRL0.CRC_EN data rate kbps. After sync word transmitted (1), more bytes sent: length byte payload bytes bytes. This takes 250000) [us]. Figure GDOx signal high about difference between theoretical value measure value internal delays signal path. radio will state determined MCSM1.TXOFF_MODE after GDOx de-asserted (2).
Figure Error Free (IOCFGx 0x06) 3.1.2 TXFIFO_UNDERFLOW (IOCFGx 0x06)
Assume transmitting following packet: 0x03, 0x01, 0x02. radio configured described 3.1.1. Since variable packet length mode used, transmitting this packet will make radio enter TXFIFO_UNDERFLOW state (the length byte there only bytes payload; 0x01 0x02). This means that GDOx signal will de-asserted after 250000) [us] ((1) shows sync transmitted). only TXFIFO_UNDERFLOW state issue SFTX strobe. This will radio back IDLE state, regardless MCSM1.TXOFF_MODE setting.
Figure TXFIFO_UNDERFLOW (IOCFGx 0x06)
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3.2.1 when IOCFGx 0x06 Error Free (IOCFGx 0x06)
Assume receiving packet transmitted 3.1.1. seen Figure GDOx signal receiver (SYNC RECEIVED PACKET RECEIVED) asserted de-asserted just after GDOx signal transmitter (SYNC SENT PACKET SENT) asserted de-asserted (2). radio will state determined MCSM1.RXOFF_MODE after GDOx de-asserted.
Figure Error Free (IOCFGx 0x06) 3.2.2 RXFIFO_OVERFLOW (IOCFGx 0x06)
transmitted packet still same 3.1.1, receiver been configured fixed packet length mode (PKTCTRL0.LENGTH_CONFIG packet length (PKTLEN 0x46). Sync word received immediately after sync word been transmitted (1). However, when packet sent (2), receiver continues state since configured receive bytes. After 2.15 radio enters RXFIFO_OVERFLOW state (4). only takes 250000) 2.048 [ms] fill FIFO, some internal buffering, takes some additional time before RXFIFO_OVERFLOW state entered. only RXFIFO_UNDERFLOW state issue SFRX strobe. This will radio back IDLE state, regardless MCSM1.RXOFF_MODE setting. Please Errata Note description related RXFIFO_OVERFLOW state.
Figure RXFIFO_OVERFLOW (IOCFGx 0x06)
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3.2.3 Address Filtering (IOCFGx 0x06) Assume transmitting following packet: 0x0A, 0x07, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A (the radio settings same 3.1.1). receiver have same radio settings transmitter, addition configured address filtering (PKTCTRL1.ADR_CHK ADDR 0x06). When address filtering enabled, receiver will interpret second byte received after sync word address fixed packet length mode where used (PKTCTRL0.LENGTH_CONFIG would interpret first byte after sync address byte, since packet would have length byte).
Figure Address Filtering (IOCFGx 0x06) Since receiver address 0x06 (ADDR 0x06) second byte received after sync 0x07, packet will discarded GDOx will de-assert (2). Figure shows that GDOx de-asserted after bytes must received before address checked; 250000) [us] ((1) shows sync received). After GDOx de-asserted, radio will back state, regardless MCSM1.RXOFF_MODE setting. 3.2.4 Maximum Length Filtering (IOCFGx 0x06)
using maximum length filtering (PKTCTRL0.LENGTH_CONFIG PKTLEN maximum packet length radio should accept) GDOx signal will behave same described 3.2.3. However, GDOx will de-asserted after (and since only length byte received before filtering take place. After GDOx signal been de-asserted, radio will also this case back state, regardless MCSM1.RXOFF_MODE setting. Figure ((1) sync received), transmitted packet same described 3.2.3. receiver, PKTLEN 0x09 (with PKTLEN 0x0A, packet would received properly).
Figure Maximum Length Filtering (IOCFGx 0x06)
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IOCFGx 0x00
This signal associated with FIFO asserted when FIFO filled above FIFO threshold de-asserted when FIFO drained below same threshold. This signal valid CC1150 CC2550. Assume same packet being transmitted 3.2.3. receiver, FIFOTHR.FIFO_THR bytes FIFO) append status enabled (PKTCTRL1.APPEND_STATUS This means that total bytes FIFO length byte data bytes status bytes). takes 250000) [us] after sync word received until GDOx indicated that there bytes FIFO (2). When bytes been read from FIFO (and there bytes left), GDOx de-asserted (3).
Figure IOCFGx 0x00
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IOCFGx 0x01
This signal associated with FIFO asserted when FIFO filled above FIFO threshold packet reached. de-asserts when FIFO empty. This signal valid CC1150 CC2550. Assume transmitting packet described 3.2.3. After sync word received takes 250000) [us] before FIFO threshold reached (see Figure
Figure IOCFGx 0x01 FIFO Filled Above Threshold) transmission showed Figure FIFO threshold changed (FIFOTHR.FIFO_THR Since only bytes received FIFO, GDOx asserted before whole packet been received (same time packet received signal de-asserted (2)).
Figure IOCFGx 0x01 (End Packet Reached) GDOx de-asserted when FIFO empty (3). important remember that related FIFO should never empty FIFO before last byte packet been received (See Errata Notes CC1100 [1], CC1101 [2], CC2500 [3]).
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IOCFGx 0x02
This signal associated with FIFO; asserted when FIFO filled above FIFO threshold de-asserted when FIFO below same threshold. Assume writing bytes FIFO. FIFOTHR.FIFO_THR meaning that there will five bytes FIFO when signal asserted (1). signal deasserted when number bytes FIFO goes below five. illustrate this, TXBYTES register read just after signal de-asserted shows that there four bytes FIFO (3).
Figure IOCFGx 0x02
IOCFGx 0x03
This signal associated with FIFO; asserts when FIFO full de-asserts when FIFO drained below FIFO threshold. FIFOTHR.FIFO_THR FIFO threshold bytes) bytes written FIFO, GDOx signal will behave shown Figure asserts after bytes have been written FIFO de-asserts when there less than bytes left (2). Reading TXBYTES register after GDOx de-asserted shows that there bytes left FIFO (3).
Figure IOCFGx 0x03
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IOCFGx 0x07
This signal asserted when packet been received with de-asserted when first byte read from FIFO. signal valid CC1150 CC2550. Note that CC2500, this signal only valid when PKTCTRL0.CC2400_EN Figure shows bytes long packet being transmitted. shows sync sent shows packet sent. GDOx signal asserted when packet been received de-asserted after first byte read from FIFO (5).
Figure IOCFGx 0x07 Assume following scenario: GDOx used generate interrupt when packet with been received. This means that faulty packet being received, interrupt generated hence faulty packet will FIFO, potentially causing FIFO overflow. solution would auto flush function (PKTCTRL1.CRC_AUTOFLUSH which will flush entire FIFO check fails. problem that filtering work, PKTCTRL0.CC2400_EN must This means that using this approach will only work CC1100 where this GDOx signal valid both PKTCTRL0.CC2400_EN PKTCTRL0.CC2400_EN however, still possible signal CC2500, should used single source interrupt MCU. using this signal sync received packet received (IOCFGx 0x06) generate interrupt falling edge then, ISR, check GDOx pin, indicating asserted not. GDOx asserted, received packet faulty FIFO should flushed issuing SFRX strobe. Remember that SFRX strobe should only issued when radio RXFIFO_OVERFLOW state when IDLE state.
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References
CC1100 Single-Chip Cost Power RF-Transceiver, Data sheet (cc1100.pdf) CC1101 Single-Chip Cost Power RF-Transceiver, Data sheet (cc1101.pdf) CC2500 Single-Chip Cost Power RF-Transceiver, Data sheet (cc2500.pdf)
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General Information
10.1 Document History
Revision SWRA121A SWRA121 Date 2007.10.22 2006.12.18 Description/Changes Added reference table. Removed logo from header. Added CC1101 Initial release.
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