DAC8412 DAC8413

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Quad, 12-Bit Voltage Output with Readback DAC8412/DAC8413
operation Unipolar bipolar operation True voltage output Double-buffered inputs Reset minimum (DAC8413) center scale (DAC8412) Fast access time Readback
DATA
FUNCTIONAL BLOCK DIAGRAM
VLOGIC PORT INPUT INPUT INPUT INPUT OUTPUT OUTPUT OUTPUT OUTPUT VREFH
VOUTA
DGND CONTROL LOGIC
VOUTB
VOUTC
VOUTD
APPLICATIONS
Automatic test equipment Digitally controlled calibration Servo controls Process control equipment
VREFL
Figure
GENERAL DESCRIPTION
DAC8412/DAC8413 quad, 12-bit voltage output DACs with readback capability. Built using complementary BiCMOS process, these monolithic DACs offer user very high package density. Output voltage swing reference inputs VREFH VREFL. setting VREFL input VREFH positive voltage, provides unipolar positive output range. similar configuration with VREFH VREFL negative voltage provides unipolar negative output range. Bipolar outputs configured connecting both VREFH VREFL nonzero voltages. This method setting output voltage range advantages over other bipolar offsetting methods because dependent internal external resistors with different temperature coefficients. Digital controls allow user load read back data from DAC, load DAC, transfer data DACs time. active RESET loads output registers midscale DAC8412 zero scale DAC8413. DAC8412/DAC8413 available 28-lead plastic DIP, 28-lead ceramic DIP, 28-lead PLCC, 28-lead packages. They operated from wide variety supply reference voltages with supplies ranging from single references from +2.5 Power dissipation less than with supplies only with supply. MIL-STD-883 applications, contact your local Analog Devices, Inc. sales office DAC8412/DAC8413/883 data sheet, which specifies operation over -55°C +125°C temperature range. parts also available Standard Military Drawings 5962-91 76401MXA through 76404M3A.
0.500 0.375
LINEARITY ERROR (LSB)
+125°C +25°C
0.250 0.125
-55°C -0.125 -0.250 -0.375 -0.500 1024 1536 2046 2548 2560 DIGITAL INPUT CODE (Decimal) 3072 4096 +15V -15V VREFH +10V VREFL -10V -55°C, +25°C, +125°C
00274-002
Figure Code Over Temperature
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007 Analog Devices, Inc. rights reserved.
00274-001
RESET LDAC
DAC8412/DAC8413 TABLE CONTENTS
Features Applications. Functional Block Diagram General Description Revision History Specifications. Electrical Characteristics. Absolute Maximum Ratings. Thermal Resistance Caution. Configuration Function Descriptions. Typical Performance Characteristics Theory Operation Introduction. DACs Glitch. Reference Inputs Digital Coding RESET Supplies. Amplifiers. Reference Configurations. Single Supply Operation Outline Dimensions Ordering Guide
REVISION HISTORY
6/07-Rev. Rev. Updated Format.Universal Added CERDIP Package.Universal Changes Specifications Section. Changes Absolute Maximum Ratings Section. Updated Outline Dimensions Changes Ordering Guide 3/00-Rev. Rev.
Rev. Page
DAC8412/DAC8413 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
+15.0 -15.0 VLOGIC +5.0 VREFH +10.0 VREFL -10.0 V,-40°C +85°C, unless otherwise noted. Table
Parameter ACCURACY Integral Nonlinearity Error Differential Nonlinearity Error Min-Scale Error Full-Scale Error Min-Scale Temperature Coefficient Full-Scale Temperature Coefficient Linearity Matching REFERENCE Positive Reference Input Voltage Range Negative Reference Input Voltage Range2 Reference High Input Current Reference Input Current Large Signal Bandwidth AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate Analog Crosstalk LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Voltage Logic Output High Voltage Logic Output Voltage Logic Input Current Input Capacitance Digital Feedthrough LOGIC TIMING CHARACTERISTICS3, Chip Select Write Pulse Width Write Setup Write Hold Address Setup Address Hold Load Setup Load Hold Write Data Setup Write Data Hold Load Data Pulse Width Reset Pulse Width Chip Select Read Pulse Width Read Data Hold Read Data Setup Data High-Z Chip Select Data Symbol VZSE VFSE TCVZSE TCVFSE Conditions grade grade Monotonic over temperature Adjacent Matching ±0.25 VREFL -2.75 VREFH 0.01%, step, VREFH +2.75 2.75 ±0.5 Unit ppm/°C ppm/°C nV-sec
IREFH IREFL IOUT
+1.5
VINH VINL
25°C 25°C -1.6
VREFH VREFL tWCS tWDS tWDH tLDW tRESET tRCS tRDH tRDS tCSD
tWCS tWCS
tWCS tWCS
tRCS tRCS
Rev. Page
DAC8412/DAC8413
Parameter SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation
Symbol PDISS
Conditions 14.25 15.75 VREFH
Unit ppm/V
-6.5
supplies varied ±5%, operation guaranteed. Device tested with nominal supplies. Operation guaranteed over this reference range, linearity neither tested guaranteed. parameters guaranteed design. input control signals specified with (10% timed from voltage level
VLOGIC +5.0 VREFH +2.5 VREFL -5.0 VREFL -2.5 -40°C +85°C, unless otherwise noted. Table
Parameter ACCURACY Integral Nonlinearity Error Symbol Conditions grade grade grade grade2 Monotonic over temperature -5.0 -5.0 ±0.5 VREFL -2.5 -1.0 -1.25 0.45 +1.25 VREFH VREFH +1.0 Units ppm/°C ppm/°C
Differential Nonlinearity Error Min-Scale Error Full-Scale Error Min-Scale Error Full-Scale Error Min-Scale Temperature Coefficient Full-Scale Temperature Coefficient Linearity Matching REFERENCE Positive Reference Input Voltage Range Negative Reference Input Voltage Range Reference High Input Current Large Signal Bandwidth AMPLIFIER CHARACTERISTICS Output Current Settling Time Slew Rate LOGIC CHARACTERISTICS Logic Input High Voltage Logic Input Voltage Logic Output High Voltage Logic Output Voltage Logic Input Current Input Capacitance LOGIC TIMING CHARACTERISTICS Chip Select Write Pulse Width Write Setup Write Hold Address Setup Address Hold Load Setup Load Hold
VZSE VFSE VZSE VFSE TCVZSE TCVFSE
Adjacent matching
IREFH IOUT VINH VINL tWCS
-5.0 Code 0x000 VREFH 0.01%, step, 25°C 25°C -1.6
tWCS tWCS
Rev. Page
DAC8412/DAC8413
Parameter Write Data Setup Write Data Hold Load Data Pulse Width Reset Pulse Width Chip Select Read Pulse Width Read Data Hold Read Data Setup Data High-Z Chip Select Data SUPPLY CHARACTERISTICS Power Supply Sensitivity Positive Supply Current Negative Supply Current Power Dissipation Symbol tWDS tWDH tLDW tRESET tRCS tRDH tRDS tCSD PDISS Conditions tWCS tWCS Units ppm/V
tRCS tRCS
-5.0 -5.0
supplies varied ±5%, operation guaranteed. Device tested with 4.75 single-supply operation only (VREFL internal offset errors, measured beginning 0x005. Operation guaranteed over this reference range, linearity neither tested guaranteed. parameters guaranteed design. input control signals specified with (10% timed from voltage level
tWCS
tRDS
A0/A1
tRCS
tRDH
LDAC
tLDW
A0/A1
tWDS
DATA
tWDH
00274-003
tCSD
RESET
Figure Data Output (Read Timing)
Figure Data Write (Input Output Registers) Timing
Rev. Page
00274-004
DATA
HIGH-Z
DATA VALID
HIGH-Z
tRESET
DAC8412/DAC8413
80ns
80ns
ADDRESS ADDRESS ADDRESS ADDRESS THREE ADDRESS FOUR
ADDRESS ADDRESS ADDRESS ADDRESS THREE ADDRESS FOUR
LDAC
LDAC
00274-005
tWDS
DATA DATA1 VALID DATA2 VALID DATA3 VALID DATA4 VALID
tWDH
DATA
DATA1 VALID
DATA2 VALID
DATA3 VALID
DATA4 VALID
Figure Single-Buffer Mode
Figure Double-Buffer Mode
VREFH VREFL
VREFH VOUTB VOUTA DGND RESET LDAC
VREFL VOUTC VOUTD VLOGIC DB11 DB10 ONCE PORT
DGND
+15V, -15V, VREFH +10V, VREFL 100, 10k, 100k, LCC, 4.7µF (ONCE PORT), 0.01µF (EACH DEVICE) 1N4001 EQUIVALENT (ONCE PORT) CONNECT
Figure Burn-In Diagram
Rev. Page
00274-007
00274-006
tWDS
tLDW
tWDH
DAC8412/DAC8413 ABSOLUTE MAXIMUM RATINGS
+25°C, unless otherwise noted. Table
Parameter VLOGIC VLOGIC DGND VREFL VREFH VREFH VREFL Current into Digital Input Voltage DGND Digital Output Voltage DGND Operating Temperature Range Junction Temperature Storage Temperature Range Power Dissipation Package Lead Temperature Soldering Rating -0.3 +33.0 -0.3 +33.0 -0.3 +7.0 -0.3 +VSS +2.0 +33.0 +2.0 -0.3 VLOGIC -0.3 +7.0 -40°C +85°C -55°C +125°C 150°C -65°C +150°C 1000 JEDEC Industry Standard J-STD-020
THERMAL RESISTANCE
specified worst-case mounting conditions, that device socket. Table Thermal Resistance
Package Type 28-Lead Plastic (PDIP) 28-Terminal Ceramic Leadless Chip Carrier (LLC) 28-Lead Plastic Leaded Chip Carrier (PLLC) 28-Lead Ceramic Dual In-Line Package (CERDIP) Unit °C/W °C/W °C/W °C/W
CAUTION
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
Rev. Page
DAC8412/DAC8413 CONFIGURATION FUNCTION DESCRIPTIONS
VOUTA VOUTB VOUTC
VOUTA VOUTB VOUTC VOUTD VREFH VREFL
VOUTB VOUTA DGND RESET LDAC
VOUTC VOUTD VLOGIC
DGND RESET LDAC (LSB)
VREFH
VREFL
VLOGIC
DAC8412/ DAC8413
INDENTFIER
DGND RESET LDAC (LSB)
VOUTD
VLOGIC DB11 (MSB)
VREFH
VIEW (LSB) (Not Scale)
DAC8412/ DAC8413
VIEW (Not Scale)
DB11 (MSB)
00274-009
DAC8412/ DAC8413
VIEW (Not Scale)
DB11 (MSB) DB10
00274-008
Figure PDIP/CERDIP
Figure PLCC
DB10
Figure
Table Function Descriptions
Number Mnemonic VREFH VOUTB VOUTA DGND RESET LDAC DB10 DB11 VLOGIC VOUTD VOUTC VREFL Description High-Side Reference Input. Output. Output. Lower Rail Power Supply. Digital Ground. Reset Input Output Registers Enabled Active Low. Load Data DAC, Enabled Active Low. Data LSB. Data Data Data Data Data Data Data Data Data Data Data MSB. Active Write Data DAC. Active high readback previous data data pins with VLOGIC connected Address Address Chip Select, Enabled Active Low. Voltage Supply Readback Function. open circuit used. Upper Rail Power Supply. Output. Output. Low-Side Reference Input.
Rev. Page
DB10
00274-010
VREFL
DAC8412/DAC8413 TYPICAL PERFORMANCE CHARACTERISTICS
+15V -15V VREFL -10V 25°C
VREFL 25°C
MAXIMUM LINEARITY ERROR (LSB)
MAXIMUM LINEARITY ERROR (LSB)
00274-011
VREFH
VREFH
Figure VREFH
Figure VREFH
MAXIMUM LINEARITY ERROR (LSB)
MAXIMUM LINEARITY ERROR (LSB)
VREFL 25°C
+15V -15V VREFL 25°C
00274-014
VREFH
VREFH
Figure VREFH
Figure vs.VREFH
FULL-SCALE ERROR (LSB)
ZERO-SCALE ERROR (LSB)
+15V -15V VREFH +10V VREFL -10V
-0.1
-0.2 -0.4 -0.6
00274-015
-0.3
-0.5
+15V -15V VREFH +10V VREFL -10V
00274-016
-0.7
HOURS OPERATION 125°C
1000
HOURS OPERATION 125°C
1000
Figure Full-Scale Error Time Accelerated Burn-in
Figure Zero-Scale Error Time Accelerated Burn-In
Rev. Page
00274-013
00274-012
DAC8412/DAC8413
1.00
FULL-SCALE ERROR (LSB)
LINEARITY ERROR (LSB)
+15V -15V VREFH +10V VREFL -10V
0.75 0.50 0.25 -0.25 -0.50 -0.75
00274-017
VREFH 2.5V 25°C
-0.2
-0.4
TEMPERATURE (°C)
1024 1536 2048 2560 3072 DIGITAL INPUT CODE (Decimal)
3584
4096
Figure Full-Scale Error Temperature
+15V -15V VREFH +10V VREFL -10V
Figure Channel-to-Channel Matching (VSUPPLY V/GND)
+15V -15V VREFL -10V
ZERO-SCALE ERROR (LSB)
-0.2 -0.4
(mA)
00274-018
TEMPERATURE (°C)
VREFH
Figure Zero-Scale Error Temperature
0.37500 0.26125 0.18750 0.08375 -0.09375 -0.18750 -0.23125
00274-019
Figure VREFH (All DACs High)
0.500
VREFH VREFL 25°C
LINEARITY ERROR (LSB)
0.375 0.250 0.125 -0.125 -0.250 -0.375 -0.500 +15V -15V VREFH +10V VREFL -10V -55°C, +25°C, +125°C
LINEARITY ERROR (LSB)
1024 1536 2048 2560 3072 DIGITAL INPUT CODE (Decimal)
3584
4096
1024 1536 2048 2560 3072 DIGITAL INPUT CODE (Decimal)
3584
4096
Figure Channel-to-Channel Matching (VSUPPLY
Figure Code
Rev. Page
00274-022
-0.37500
00274-021
-0.6
00274-020
-0.6
-1.00
DAC8412/DAC8413
1V/DIV
1V/DIV
TRIG'D
+15V -15V VREFH +10V VREFL -10V 25°C
TRIG'D
+15V -15V VREFH +10V VREFL -10V 25°C
00274-026
-580ns
1µs/DIV
9.42µs
-580ns
1µs/DIV
9.42µs
Figure Positive Slew Rate
15.5mV INPUT
Figure Negative Slew Rate
+15V -15V VREFH +10V VREFL -10V 25°C
+15V -15V VREFH +10V VREFL -10V 25°C
IVREFH (mA)
2mV/DIV
5V/DIV
TRIG'D
00274-025
2µs/DIV
18.04µs
1023 1535 2047 2559 3071 DIGITAL INPUT CODE (Decimal)
3583
4095
Figure Settling Time (Negative)
32.5mV INPUT
Figure IVREFH Code
+15V -15V VREFH +10V VREFL -10V 25°C
(LSB)
5mV/DIV
ERROR BAND
5V/DIV
TRIG'D
2µs/DIV
18.04µs
LOAD RESISTANCE
Figure Settling Time (Positive)
Figure Load Resistance
Rev. Page
00274-028
-17.5mV -1.96µs
00274-024
+15V -15V VREFH +10V VREFL -10V 25°C
-0.2 0.01
00274-023
-4.5mV -1.96µs
-0.5
00274-027
DAC8412/DAC8413
POWER SUPPLY REJECTION RATIO (dB)
+15V -15V VREFH +10V VREFL -10V 25°C
FULL-SCALE VOLTAGE
+PSRR -PSRR
+PSRR: +15V ±1Vp -15V -PSRR: +15V -15V VREFH +10V DATA FREQUENCY (Hz) 100k
00274-032
LOAD RESISTANCE
Figure Output Swing Load Resistance
00274-029
0.01
Figure PSRR Frequency
GAIN (dB)
NOISE DENSITY (µV)
+15V -15V VREFH +10V VREFL -10V 25°C
0.10
+15V -15V VREFH ±100mV VREFL -10V DATA BITS 200mV
00274-030
0.01
FREQUENCY (Hz)
100k
NOISE FREQUENCY (Hz)
Figure Small Signal Response
POWER SUPPLY CURRENT (mA)
Figure Noise Density Noise Frequency
+15V -15V
IOUT (mA)
+15V -15V VREFH +10V VREFL -10V 25°C DATA 0x000
+ISC
-ISC
00274-031
TEMPERATURE (°C)
VOUT
Figure Power Supply Current Temperature
Figure IOUT VOUT
Rev. Page
00274-034
00274-033
0.001
DAC8412/DAC8413
10µs
MEAN 66.19µV
GLITCH OUTPUT
+15V -15V VREFH +10V VREFL -10V 25°C
20µV/DIV 200µs 12.9mV
DEGLITCHER OUTPUT
00274-035 00274-037
1.86V
Figure Broadband Noise
IOUT (mA)
Figure Glitch Deglitched Results
+15V VREFH +10V VREFL 25°C DATA 0x800
+ISC
VOUT
00274-036
-ISC
Figure IOUT VOUT
Rev. Page
DAC8412/DAC8413 THEORY OPERATION
INTRODUCTION
DAC8412/DAC8413 quad, voltage output, 12-bit parallel input DACs featuring 12-bit data with readback capability. only differences between DAC8412/DAC8413 reset functions. DAC8412 resets midscale (Code 0x800), DAC8413 resets minimum scale (Code 0x000). ability operate from single supply unique feature these DACs. Operation DAC8412/DAC8413 viewed dividing system into three separate functional groups: digital logic, digital-to-analog converters, output amplifiers.
REFERENCE INPUTS
four DACs share common reference high (VREFH) reference (VREFL) inputs. voltages applied these reference inputs output high voltage limits four DACs. Each reference input voltage restrictions with respect other reference power supplies. VREFL voltage between VREFH VREFH value between +VDD VREFL Note that because these restrictions, DAC8412 references cannot inverted (that VREFL cannot greater than VREFH). important note that DAC8412 VREFH input both sinks sources current. addition, input current both VREFH VREFL code-dependent. Many references have limited current-sinking capability must buffered with amplifier drive VREFH. VREFL such special requirements. recommended that reference inputs bypassed with capacitors when operating with references. This limits reference bandwidth.
DACS
Each voltage switched, high impedance R-2R ladder configuration. Each resistor driven pair switches that connect resistor either VREFH VREFL.
GLITCH
Worst-case glitch occurs transition between Half-Scale Digital Code 1000 0000 0000 half-scale minus LSB, 0111 1111 1111. measured about (see Figure 37). demanding applications such waveform generation precision instrumentation control, deglitcher circuit implemented with standard sample-and-hold circuit (see Figure 38). When enabled synchronizing hold period longer than glitch tradition, output voltage smoothed with minimum disturbance. quad sample-and-hold amplifier, SMP04, been used illustrate deglitching result (see Figure 37).
DACOUT DACOUT
DIGITAL
Table digital control logic truth table. Digital consists 12-bit bidirectional data bus, registers select inputs, input, RESET input, chip select (CS), load (LDAC) input. Control DACs direction determined these inputs shown Table Digital data bits labeled with defined Data Data digital pins TTL/CMOS compatible. Figure simplified logic diagram. register select inputs select individual registers (Binary Code through (Binary Code 11). Decoding registers enabled input. When high, decoding takes place, neither writing reading input registers enabled. loading second bank registers controlled asynchronous LDAC input. taking LDAC while enabled, output registers updated simultaneously. Note that tLDW required pulse width updating DACs minimum input, when enabled controls writing reading from input register.
DACOUT
DACOUT
00274-038
CODING
Both DAC8412/DAC8413 binary coding. output voltage calculated
Figure Data Output (Read Timing)
VOUT VREFL
(VREFH VREFL 4096
where digital code decimal.
Rev. Page
DAC8412/DAC8413
RESET
RESET function used either power-up time during operation. RESET function independent This active sets output registers either center code DAC8412, zero code DAC8413. reset-to-center code most useful when configured bipolar references output after reset desired. VLOGIC digital output supply voltage readback function. normally connected This logic reference input only. does supply current device. readback function being used, VLOGIC left opencircuit. While VLOGIC does supply current DAC8412, does supply currents digital outputs when readback used.
AMPLIFIERS
Unlike many voltage output DACs, DAC8412 features buffered voltage outputs. Each output capable both sourcing sinking eliminating need external amplifiers when driving smaller capacitive load most applications. These amplifiers short-circuit protected.
SUPPLIES
Supplies required VSS, VDD, VLOGIC. supply between positive supply; operating range between
Table DAC8412/DAC8413 Logic Table
LDAC
Input Register Output Register Write Write Write Write Write Write Write Write Write Hold Write Hold Write Hold Write Hold Read Hold Read Hold Read Hold Read Hold Hold Update output registers Hold Hold registers reset midscale/zero-scale registers latched midscale/zero-scale1
Mode Transparent Transparent Transparent Transparent Write input Write input Write input Write input Read input Read input Read input Read input Hold
DAC8412 resets midscale, DAC8413 resets zero scale. logic low; logic high; don't care. Input output registers transparent when asserted.
Rev. Page
DAC8412/DAC8413
VREFH RDDACA WRDB0 WRDB1 WRDACA RDDACB WRDB2 WRDB3 WRDB4 WRDACB WRDB5 INPUT OUTPUT REGISTER WRDB6 REGISTER RDDACC WRDB7 WRDACC RDDACD WRDACD DB11.DB0 VLOGIC WRDB8 WRDB9 WRDB10 WRDB11 VOUTD VREFL LDAC RESET READOUTBAR READBACKDATAIN_DB11 READBACK DATAOUT_DB11 READOUT
00274-039
VOUTA
VOUTB
VOUTC
READBACKDATAIN_DB10
DGND
Figure Simplified Logic Diagram
Careful attention grounding important accurate operation DAC8412. This because DAC8412 more sensitive than other 12-bit DACs, because with four outputs references, there greater potential ground loops. Because DAC8412 analog ground, ground must specified with respect reference.
+15V +15V
BALANCE 100k
0.2µF
VREFH
REFERENCE CONFIGURATIONS
Output voltage ranges configured either unipolar bipolar, within these choices, wide variety options exists. unipolar configuration either positive negative voltage output, bipolar configuration either symmetrical nonsymmetrical.
+15V INPUT +15V
GAIN 100k
AD688 ±10V AD588
0.2µF
DAC8412 DAC8413
VREFL
0.1µF //10µF
-15V ±10V OPERATION
Figure Symmetrical Bipolar Operation
OUTPUT
OP400
VREFH 0.2µF
REF10
DAC8412
TRIM
VREFL +10V OPERATION
DAC8413
0.1µF //10µF
-15V
Figure Unipolar Operation
Figure (symmetrical bipolar operation) shows DAC8412 configured operation. AD688 data sheet full explanation reference operation. Adjustments required many applications since AD688 very high accuracy reference. However, additional adjustments required, adjust DAC8412 full scale first. Begin loading digital full-scale code (0xFFF), then adjust gain adjust potentiometer attain output voltage 9.9976 Then, adjust balance adjust center-scale output voltage 0.000
Rev. Page
00274-040
00274-041
DAC8412/DAC8413
bypass capacitors shown reference inputs Figure should used whenever references used. Applications with single references references require bypassing. resistor series with output reference amplifier keeps amplifier from oscillating with capacitive load. This resistor been found large enough stabilize this circuit. Larger resistor values acceptable, provided that drop across resistor does exceed VBE. Assuming minimum maximum current 2.75 then resistor should under loading single DAC8412. Using separate references recommended. Having references cause different drifts with time temperature; whereas with single reference, most drifts track. Unipolar positive full-scale operation usually with reference with correct output voltage. This preferable using reference dividing down required value. full-scale output, circuit configured shown Figure this configuration, full-scale value first adjusting resistor full-scale output 9.9976
TRIM VREFH OUTPUT 0.2µF 0.01µF 10µF
00274-042
Figure shows DAC8412 configured operation. REF08 with output connected directly VREFL reference voltage.
SINGLE SUPPLY OPERATION
operation with supply, reference voltage should between optimum linearity. Figure shows REF43 used supply reference voltage. headroom reference both sufficient support supply with tolerance. VLOGIC should connected same supply. Separate bypassing each should also used.
10µF INPUT OUTPUT
0.01µF
VREFH 0.2µF VREFL
REF43
TRIM
DAC8412
0.1µF //10µF
DAC8413
00274-043
ZERO 2.5V OPERATION SINGLE SUPPLY
0.1µF //10µF
REF08
DAC8412
VREFL
Figure Single-Supply Operation
DAC8413
ZERO -10V OPERATION -15V
Figure Unipolar Operation
Rev. Page
DAC8412/DAC8413 OUTLINE DIMENSIONS
0.100 (2.54) 0.064 (1.63) 0.075 (1.91)
0.300 (7.62) 0.020 (0.51)
0.458 (11.63) 0.442 (11.23)
0.458 (11.63)
0.05 (1.27)
BOTTON VIEW
0.028 (0.71) 0.022 (0.56)
022106-A
0.075 (1.91) 0.055 (1.40) 0.045 (1.14)
0.15 (3.81)
0.088 (2.24) 0.054 (1.37)
0.095 (2.41) 0.075 (1.90)
CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN
Figure 28-Terminal Ceramic Leadless Chip Carrier [LCC] (E-28-1) Dimensions shown inches (millimeters)
1.565 (39.75) 1.380 (35.05)
0.580 (14.73) 0.485 (12.31)
0.100 (2.54) 0.250 (6.35) 0.200 (5.08) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE 0.015 (0.38) SEATING PLANE 0.022 (0.56) 0.014 (0.36) 0.070 (1.78) 0.050 (1.27) 0.005 (0.13)
0.625 (15.88) 0.600 (15.24) 0.195 (4.95) 0.125 (3.17)
0.700 (17.78)
0.015 (0.38) 0.008 (0.20)
COMPLIANT JEDEC STANDARDS MS-011 CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN. CORNER LEADS CONFIGURED WHOLE LEADS.
022106-A
Figure 28-Lead Plastic Dual In-Line Package [PDIP] Wide Body (N-28-2) Dimensions shown inches (millimeters)
Rev. Page
071006-A
DAC8412/DAC8413
0.048 (1.22) 0.042 (1.07)
IDENTIFIER
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) 0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66)
0.048 (1.22) 0.042 (1.07)
PVIEW
(PINS DOWN)
0.050 (1.27)
0.430 (10.92) 0.390 (9.91)
BOTTOM VIEW (PINS
0.456 (11.582) 0.450 (11.430) 0.495 (12.57) 0.485 (12.32)
0.120 (3.04) 0.090 (2.29)
0.045 (1.14) 0.025 (0.64)
COMPLIANT JEDEC STANDARDS MO-047-AB CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN.
Figure 28-Lead Plastic Leaded Chip Carrier [PLCC] (P-28) Dimensions shown inches (millimeters)
0.005 (0.13)
0.100 (2.54)
0.610 (15.49) 0.500 (12.70)
0.225(5.72) 1.490 (37.85) 0.015 (0.38) 0.150 (3.81) 0.200 (5.08) 0.125 (3.18) 0.026 (0.66) 0.014 (0.36) 0.620 (15.75) 0.590 (14.99)
0.018 (0.46) 0.008 (0.20)
0.100 (2.54)
0.070 (1.78) SEATING 0.030 (0.76) PLANE
CONTROLLING DIMENSIONS INCHES; MILLIMETER DIMENSIONS PARENTHESES) ROUNDED-OFF INCH EQUIVALENTS REFERENCE ONLY APPROPRIATE DESIGN.
Figure 28-Lead Ceramic Dual In-Line Package [CERDIP] (Q-28-2) Dimensions shown inches (millimeters)
Rev. Page
030106-A
DAC8412/DAC8413
ORDERING GUIDE
Model DAC8412AT/883C DAC8412BT/883C DAC8412BTC/883C DAC8412EP DAC8412EPZ1, DAC8412FP1 DAC8412FPC1 DAC8412FPC-REEL1 DAC8412FPCZ1, DAC8412FPCZ-REEL1, DAC8412FPZ1, DAC8413AT/883C DAC8413BT/883C DAC8413BTC/883C DAC8413EP1 DAC8413EPZ1, DAC8413FP1 DAC8413FPC1 DAC8413FPC-REEL1 DAC8413FPCZ1, DAC8413FPC-REEL1 DAC8413FPZ1,
Temperature Range -55°C +125°C -55°C +125°C -55°C +125°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -55°C +125°C -55°C +125°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
±1.5 ±1.5 ±1.5 ±0.5 ±0.5 ±1.5 ±1.5 ±1.5 ±0.5 ±0.5
Package Description 28-Lead Ceramic Dual In-Line Package [CERDIP] 28-Lead Ceramic Dual In-Line Package [CERDIP] 28-Terminal Ceramic Leadless Chip Carrier [LCC] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Ceramic Dual In-Line Package [CERDIP] 28-Lead Ceramic Dual In-Line Package [CERDIP] 28-Terminal Ceramic Leadless Chip Carrier [LCC] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Leaded Chip Carrier [PLCC] 28-Lead Plastic Dual In-Line Package [PDIP] 28-Lead Plastic Dual In-Line Package [PDIP]
Package Option Q-28-2 Q-28-2 E-28-1 N-28-2 N-28-2 N-28-2 P-28 P-28 P-28 P-28 N-28-2 Q-28-2 Q-28-2 E-28-1 N-28-2 N-28-2 N-28-2 P-28 P-28 P-28 N-28-2 N-28-2
burn-in required, these models available CERDIP. Contact sales. RoHS Compliant Part.
©2007 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D00274-0-6/07(E)
Rev. Page

DAC8412 DAC8413

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