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PSoC® Programmable System-on-Chip
XRES Support In-System Serial Programming (ISSP) External Reset Control CY8C24894 Powerful Harvard Architecture Processor Processor Speeds Multiply, 32-Bit Accumulate Power High Speed 5.25V Operating Voltage Industrial Temperature Range: -40°C +85°C Temperature Range: -10°C +85°C Advanced Peripherals (PSoC® Blocks) Rail-to-Rail Analog PSoC Blocks Provide: 14-Bit ADCs 9-Bit DACs Programmable Gain Amplifiers Programmable Filters Comparators Four Digital PSoC Blocks Provide: 32-Bit Timers, Counters, PWMs Modules Full-Duplex UART Multiple SPIMasters Slaves Connectable GPI/O Pins Complex Peripherals Combining Blocks Capacitive Sensing Application Capability
Full Speed Mbps) Four Uni-Directional Endpoints Bi-Directional Control Endpoint Compliant Dedicated Byte Buffer External Crystal Required Flexible On-Chip Memory Flash Program Storage 50,000 Erase Write Cycles SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation Flash Programmable Configurations Sink, Source GPIO Pull Pull Down, High Strong, Open Drain Drive Modes GPI/O Analog Inputs GPI/O Analog Outputs GPI/O Configurable Interrupt GPI/O Precision, Programmable Clocking Internal Oscillator Internal Oscillator Watchdog Sleep 0.25% Accuracy with External Components Additional System Resources Slave, Master, Multi-Master Watchdog Sleep Timers User Configurable Voltage Detection
Logic Block Diagram
System
PSoC
SYSTEM
Type
Cypress Semiconductor Corporation Document Number: 38-12018 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised March 2010
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Contents
Features Logic Block Diagram Contents PSoC Functional Overview PSoC Core Digital System Analog System Additional System Resources PSoC Device Characteristics Getting Started Application Notes Development Kits Training CyPros Consultants Solutions Library Technical Support Development Tools PSoC Designer Software Subsystems In-Circuit Emulator Designing with PSoC Designer Select Components Configure Components Organize Connect Generate, Verify, Debug Document Conventions Acronyms Used Units Measure Numeric Naming Information 56-Pin Part Pinout 56-Pin Part Pinout (with XRES) 68-Pin Part Pinout 68-Pin Part Pinout (On-Chip Debug) 100-Ball VFBGA Part Pinout 100-Ball VFBGA Part Pinout (On-Chip Debug) 100-Pin Part Pinout (On-Chip Debug) Register Reference Register Conventions Register Mapping Tables Register Bank Table: User Space Register Bank Table: Configuration Space Electrical Specifications Absolute Maximum Ratings Operating Temperature Electrical Characteristics Electrical Characteristics Packaging Dimensions Thermal Impedance Solder Reflow Peak Temperature Development Tool Selection Software Development Kits Evaluation Tools Device Programmers Accessories (Emulation Programming) Ordering Information Ordering Code Definitions Document History Page Sales, Solutions, Legal Information
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PSoC Functional Overview
PSoC family consists many programmable system-on-chips with On-Chip Controller devices. PSoC family devices designed replace traditional MCUs, system ICs, numerous discrete components that surround them. PSoC CY8C24x94 devices unique members PSoC family because includes full featured, full speed Mbps) port. Configurable analog, digital, interconnect circuitry enable high level integration host industrial, consumer, communication applications. This architecture enables user create customized peripheral configurations that match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts packages. PSoC architecture, illustrated left, comprised four main areas: PSoC Core, Digital System, Analog System, System Resources including full speed port. Configurable global busing enables device resources combined into complete custom system. PSoC CY8C24x94 devices have seven ports that connect global digital analog interconnects, providing access digital blocks analog blocks.
Digital System
Digital System composed four digital PSoC blocks. Each block 8-bit resource used alone combined with other blocks form 32-bit peripherals, which called user modules. Figure 3-1. Digital System Block Diagram
Port Port Port Port Port Port Port
Digital Clocks From Core
System
Analog System
DIGITAL SYSTEM
Digital PSoC Block Array
Input Configuration
DBB00 DBB01 DCB02
DCB03
Output Configuration
GIE[7:0] GIO[7:0]
PSoC Core
PSoC Core powerful engine that supports rich feature set. core includes CPU, memory, clocks, configurable GPI/O (General Purpose I/O). core powerful processor with speeds MHz, providing four MIPS 8-bit Harvard architecture microprocessor. uses interrupt controller with vectors, simplify programming real time embedded events. Program execution timed protected using included Sleep Watch Timers (WDT). Memory encompasses Flash program storage, SRAM data storage, EEPROM emulated using Flash. Program Flash uses four protection levels blocks bytes, allowing customized software protection. PSoC device incorporates flexible internal clock generators, including (internal main oscillator) accurate over temperature voltage. also doubled digital system. power (internal speed oscillator) provided Sleep timer WDT. clocks, together with programmable clock dividers System Resource), provide flexibility integrate almost timing requirement into PSoC device. systems, self tunes 0.25% accuracy communication. PSoC GPIOs provide connection CPU, digital analog resources device. Each pin's drive mode selected from eight options, allowing great flexibility external interfacing. Every also capable generating system interrupt high level, level, change from last read.
Global Digital Interconnect
GOE[7:0] GOO[7:0]
Digital peripheral configurations include following:
Full Speed Mbps) PWMs bit) PWMs with Dead band bit) Counters bit) Timers bit) UART with selectable parity master slave slave multi-master Cyclical Redundancy Checker/Generator bit) IrDA Pseudo Random Sequence Generators bit)
digital blocks connected GPI/O through series global buses that route signal pin. buses also enable signal multiplexing performing logic operations. This configurability frees designs from constraints fixed peripheral controller. Digital blocks provided rows four, where number blocks varies PSoC device family. This enables optimum choice system resources your application. Family resources shown Table page
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Analog System
Analog System composed configurable blocks, each comprised opamp circuit allowing creation complex analog signal flows. Analog peripherals very flexible customized support specific application requirements. Some more common PSoC analog functions (most available user modules) follows.
Figure 3-2. Analog System Block Diagram
AGNDIn RefIn Analog
Analog-to-digital converters with 14-bit resolution, selectable Incremental, Delta Sigma, SAR) Filters pole band-pass, low-pass, notch) Amplifiers with selectable gain 48x) Instrumentation amplifiers with selectable gain 93x) Comparators with selectable thresholds) DACs with 9-bit resolution) Multiplying DACs with 9-bit resolution) High current output drivers (two with drive PSoC Core Resource) 1.3V reference System Resource) DTMF Dialer Modulators Correlators Peak Detectors Many other topologies possible
rray
ASD20
AGND andgap
Analog blocks arranged column three, which includes (Continuous Time) (Switched Capacitor) blocks, shown Figure 3-2.
3.3.1 Analog Multiplexer System Analog connect every GPI/O ports 0-5. Pins connected individually combination. also connects analog system analysis with comparators analog-to-digital converters. split into sections simultaneous dual-channel processing. additional analog input multiplexer provides second path bring Port pins analog array. Switch control logic enables selected pins precharge continuously under hardware control. This enables capacitive measurement applications such touch sensing. Other multiplexer applications include:
Track pad, finger sensing. Chip-wide that enables analog input from pins. Crosspoint connection between combinations.
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Additional System Resources
System Resources, provide additional capability useful complete systems. Additional resources include multiplier, decimator, voltage detection, power reset. Brief statements describing merits each resource follow.
Getting Started
quickest understand PSoC silicon read this data sheet then PSoC Designer Integrated Development Environment (IDE). This data sheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. depth information, along with detailed programming information, Technical Reference Manual this PSoC device. up-to-date ordering, packaging, electrical specification information, latest PSoC device data sheets http://www.cypress.com.
Full Speed Mbps) with configurable endpoints bytes RAM. external components required except series resistors. Wider than commercial temperature operation (-10°C +85°C). Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. Additional clocks generated using digital PSoC blocks clock dividers. multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate, assist both general math digital filters. Decimator provides custom hardware filter digital signal processing applications including creation Delta Sigma ADCs. module provides communication over wires. Slave, master, multi-master supported. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal 1.3V reference provides absolute reference analog system, including ADCs DACs. Versatile analog multiplexer system.
Application Notes
Application notes excellent introduction wide variety possible PSoC designs available http://www.cypress.com.
Development Kits
PSoC Development Kits available online from Cypress http://www.cypress.com through growing number regional global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, Newark.
Training
Free PSoC technical training demand, webinars, workshops) available online http://www.cypress.com. training covers wide variety topics skill levels assist your designs.
PSoC Device Characteristics
Depending your PSoC device characteristics, digital analog systems have digital blocks analog blocks. following table lists resources available specific PSoC device groups. device covered this data sheet shown highlighted table Table 3-1. PSoC Device Characteristics
Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital Digital Rows SRAM Size PSoC Part Number CY8C29x66 CY8C27x43 CY8C24x94 CY8C24x23A CY8C21x34 CY8C21x23 CY8C20x34 Flash Size
CyPros Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant http://www.cypress.com refer CYPros Consultants.
Solutions Library
Visit growing library solution focused designs http://www.cypress.com. Here find various application designs that include firmware hardware design files that enable complete your designs quickly.
Bytes Bytes Bytes Bytes Bytes
Technical Support
assistance with technical issues, search KnowledgeBase articles forums http://www.cypress.com. cannot find answer your question, call technical support 1-800-541-4736.
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Development Tools
PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer runs Windows Windows Vista. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, built-in support third-party assemblers compilers. PSoC Designer also supports language compilers developed specifically devices PSoC family. 5.1.4 Code Generation Tools PSoC Designer supports multiple third party compilers assemblers. code generation tools work seamlessly within PSoC Designer interface have been tested with full range debugging tools. choice yours. Assemblers. assemblers allow assembly code merge seamlessly with code. Link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compilers. language compilers available that support PSoC family devices. products allow create complete programs PSoC family devices. optimizing compilers provide features tailored PSoC architecture. They come complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. 5.1.5 Debugger PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing test program physical system while providing internal view PSoC device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. 5.1.6 Online Help System online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
PSoC Designer Software Subsystems
5.1.1 System-Level View drag-and-drop visual embedded system design environment based PSoC Express. system level view create model your system inputs, outputs, communication interfaces. define when output device changes state based upon other system devices. Based upon design, PSoC Designer automatically selects more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates embedded code, then compiles links into programming file specific PSoC device. 5.1.2 Chip-Level View chip-level view more traditional integrated development environment (IDE). Choose base device work with then select different onboard analog digital components called user modules that PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. Configure user modules your chosen application connect them each other proper pins. Then generate your project. This prepopulates your project with APIs libraries that program your application. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration enables changing configurations time. 5.1.3 Hybrid Designs begin system-level view, allow choose configure your user modules, routing, generate code, then switch chip-level view gain complete control over on-chip resources. views project share common code editor, builder, common debug, emulation, programming tools.
In-Circuit Emulator
cost, high functionality In-Circuit Emulator (ICE) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal operates with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
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Designing with PSoC Designer
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PSoC Blocks, have ability implement wide variety user-selectable functions. PSoC development process summarized following four steps: Select components Configure components Organize Connect Generate, Verify, Debug
Organize Connect
build signal chains chip level interconnecting user modules each other pins, connect system level inputs, outputs, communication interfaces each other with valuator functions. system-level view, selecting potentiometer driver control variable speed driver setting valuators control speed based input from selects, places, routes, configures programmable gain amplifier (PGA) buffer input from potentiometer, analog digital converter (ADC) convert potentiometer's output digital signal, control fan. chip-level view, perform selection, configuration, routing that have complete control over on-chip resources.
Select Components
Both system-level chip-level views provide library prebuilt, pretested hardware peripheral components. system-level view, these components called "drivers" correspond inputs thermistor, example), outputs brushless fan, example), communication interfaces (I2C-bus, example), logic control they interact with another (called valuators). chip-level view, components called "user modules". User modules make selecting implementing peripheral devices simple, come analog, digital, mixed signal varieties.
Generate, Verify, Debug
When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides software system. Both system-level chip-level designs generate software based your design. chip-level design provides application programming interfaces (APIs) with high level functions control respond hardware events run-time interrupt service routines that adapt needed. system-level design also generates main() program that completely controls chosen application contains placeholders custom code strategic positions allowing further refine software without disrupting generated code. complete code development environment allows develop customize your applications assembly language, both. last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
Configure Components
Each components select establishes basic register settings that implement selected function. They also provide parameters properties that allow tailor their precise configuration your particular application. example, Pulse Width Modulator (PWM) User Module configures more digital PSoC blocks, each bits resolution. user module parameters permit establish pulse width duty cycle. Configure parameters properties correspond your chosen application. Enter values directly selecting values from drop-down menus. Both system-level drivers chip-level user modules documented data sheets that viewed directly PSoC Designer. These data sheets explain internal operation component provide performance specifications. Each data sheet describes each user module parameter driver property, other information need successfully implement your design.
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Document Conventions
Acronyms Used
following table lists acronyms that used this document. Acronym EEPROM GPI/O IPOR PPOR PSoC® SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose graphical user interface human body model in-circuit emulator internal speed oscillator internal main oscillator input/output imprecise power reset least-significant voltage detect most-significant program counter phase-locked loop power reset precision power reset Programmable System-on-Chippulse width modulator switched capacitor static random access memory
Units Measure
units measure table located Electrical Specifications section. Table 10-1 page lists abbreviations used measure PSoC devices.
Numeric Naming
Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, `01010100b' `01000011b'). Numbers indicated decimal.
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Information
This section describes, lists, illustrates CY8C24x94 PSoC device family pins pinout configuration. CY8C24x94 PSoC devices available following packages, which shown following pages. Every port (labeled with "P") capable Digital I/O. However, Vss, Vdd, XRES capable Digital I/O.
56-Pin Part Pinout
Table 8-1. 56-Pin Part Pinout (QFN[3]) LEGEND details footnotes Table page
Type Figure 8-1. Description Digital Analog Name P2[3] Direct switched capacitor block input. P2[1] Direct switched capacitor block input. P4[7] P4[5] P4[3] P2[3] P4[1] P2[1] P3[7] P4[7] P3[5] P4[5] P3[3] P4[3] P3[1] P4[1] P3[7] P5[7] P3[5] P5[5] P3[3] P5[3] P3[1] P5[1] P5[7] P1[7] Serial Clock (SCL). P5[5] P5[3] P1[5] Serial Data (SDA). P5[1] P1[3] P1[1] Serial Clock (SCL), ISSP SCLK[2]. Power Ground connection. Power Supply voltage. P7[7] P7[0] P1[0] Serial Data (SDA), ISSP SDATA[2]. P1[2] P1[4] Optional External Clock Input (EXTCLK). P1[6] P5[0] Type Name Digital Analog P5[2]
SCL, P1[7] SDA, P1[5]
CY8C24794 56-Pin PSoC Device[1]
P0[5], P0[6], P0[4], P0[2], P0[0], P2[6],M P0[7], P2[4],M
P2[5],M P2[7],M P0[1], P0[3],
(Top
M,P1[3] SCL, P1[1] DVdd P7[7]
P7[0]
Description External Voltage Reference (VREF) input. Analog column input. Analog column input. Analog column input VREF. Analog column input. Supply voltage. Ground connection. Analog column input,. Analog column input column output. Analog column input column output. Analog column input.
P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input.
P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
Power Power I/O, I/O,
Note This part cannot programmed with Reset mode; Power Cycle mode when programming.
Document Number: 38-12018 Rev.
SDA, P1[0] M,P1[2] EXTCLK, M,P1[4] P1[6]
P2[2], P2[0], P4[6], P4[4], P4[2], P4[0], P3[6], P3[4], P3[2], P3[0], P5[6], P5[4], P5[2], P5[0],
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56-Pin Part Pinout (with XRES)
Table 8-2. 56-Pin Part Pinout (QFN[3])
Type Description Digital Analog Name P2[3] Direct switched capacitor block input. P2[1] Direct switched capacitor block input. P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] Serial Clock (SCL). P1[5] Serial Data (SDA). P1[3] P1[1] Serial Clock (SCL), ISSP SCLK[2]. Power Ground connection. Power Supply voltage. P7[7] P7[0] P1[0] Serial Data (SDA), ISSP SDATA[2]. P1[2] P1[4] Optional External Clock Input (EXTCLK). P1[6] Input P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] XRES Active high external reset with internal pull down. P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input.
Figure 8-2. CY8C24894 56-Pin PSoC Device
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1]
Type Digital Analog Name P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
Power Power I/O, I/O,
LEGEND Analog, Input, Output, Analog Input.
Notes These ISSP pins, which High POR. PSoC Technical Reference Manual details. center package should connected ground (Vss) best mechanical, thermal, electrical performance. connected ground, should electrically floated connected other signal.
Document Number: 38-12018 Rev.
P1[7] P1[5] P1[3] P1[1] DVdd P7[7] P7[0] SDA, P1[0] P1[2] EXTCLK, P1[4] P1[6]
SCL, SDA, SCL,
P2[5], P2[7], P0[1], P0[3], P0[5], P0[7], P0[6], P0[4], P0[2], P0[0], P2[6], P2[4],
(Top View)
P2[2], P2[0], P4[6], P4[4], P4[2], P4[0], XRES P3[4], P3[2], P3[0], P5[6], P5[4], P5[2], P5[0],
Description External Voltage Reference (VREF) input. Analog column input. Analog column input. Analog column input VREF. Analog column input. Supply voltage. Ground connection. Analog column input,. Analog column input column output. Analog column input column output. Analog column input.
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68-Pin Part Pinout
following 68-pin part table drawing CY8C24994 PSoC device. Table 8-3. 68-Pin Part Pinout (QFN[3])
Type Digital Analog Power Power Power Name P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] Description
Figure 8-3. CY8C24994 68-Pin PSoC Device
P2[6], Ext. VREF P2[4], Ext. AGND P2[2],
P2[3], P2[5], P2[7],
P0[1], P0[3], P0[5],
P2[1],
P0[7], P0[6], P0[4],
connection. connection. Ground connection.
P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] SCL, P1[7] SDA, P1[5]
P0[2], P0[0],
Serial Clock (SCL). Serial Data (SDA). Serial Clock (SCL) ISSP SCLK[2]. Ground connection.
SCL, P1[1] DVdd
P7[7] P7[6] P7[5] P7[4]
P1[3]
P7[3] P7[2] P7[1] P7[0]
SDA, P1[0] P1[2]
Supply voltage.
Serial Data (SDA), ISSP SDATA[2]. Optional External Clock Input (EXTCLK).
Type Digital Analog Power Power I/O,M I/O,M
Name P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1]
Description Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. External Voltage Reference (VREF) input. Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage. Ground connection. Analog column input, integration input Analog column input column output, integration input Analog column input column output. Analog column input.
Input
connection. connection. Active high reset with internal pull down.
Direct switched capacitor block input. Direct switched capacitor block input.
LEGENDA Analog, Input, Output, Connection, Analog Input.
Document Number: 38-12018 Rev.
EXTCLK, P1[4]
P2[0], P4[6], P4[4], P4[2], P4[0], XRES P3[6], P3[4], P3[2], P3[0], P5[6], P5[4], P5[2], P5[0], P1[6],
(Top View)
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68-Pin Part Pinout (On-Chip Debug)
following 68-pin part table drawing CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part only used in-circuit debugging. available production. Table 8-4. 68-Pin Part Pinout (QFN[3])
Type Digital Analog Power Power Power
P2[6], Ext. VREF P2[4], Ext. AGND P2[2],
Name P4[7] P4[5] P4[3] P4[1] OCDE OCDO P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] HCLK CCLK XRES
Description
Figure 8-4. CY8C24094 68-Pin PSoC Device
P2[3], P2[5], P2[7], P0[1], P0[3], P0[5],
even data I/O. data output. Ground connection.
Serial Clock (SCL). Serial Data (SDA). Serial Clock (SCL), ISSP SCLK[2]. Ground connection.
P4[7] P4[5] P4[3] P4[1] OCDE OCDO P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] SCL, P1[7] SDA, P1[5]
P0[7], P0[6], P0[4], P0[2], P0[0],
P2[1],
P1[3] SCL, P1[1] DVdd
Supply voltage.
SDA, P1[0] P1[2] EXTCLK P1[4]
P7[7] P7[6] P7[5] P7[4]
P7[3] P7[2] P7[1] P7[0]
(Top View)
P2[0], P4[6], P4[4], P4[2], P4[0], XRES CCLK HCLK P3[6], P3[4], P3[2], P3[0], P5[6], P5[4], P5[2], P5[0], P1[6],
Type Digital Analog Serial Data (SDA), ISSP SDATA[2]. Optional External Clock Input (EXTCLK). Power Power I/O,M high speed clock output. clock output. Active high reset with internal pull down. I/O,M
Name P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1]
Description Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. External Voltage Reference (VREF) input. Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage. Ground connection. Analog column input, integration input Analog column input column output, integration input Analog column input column output. Analog column input.
Input
P4[0] P4[2] P4[4] LEGENDA Analog, Input, Output, Analog Input, On-Chip Debugger.
Direct switched capacitor block input. Direct switched capacitor block input.
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100-Ball VFBGA Part Pinout
100-ball VFBGA part CY8C24994 PSoC device. Table 8-5. 100-Ball Part Pinout (VFBGA)
Analog Name Description Ground connection. Ground connection. connection. connection. connection. Supply voltage. connection. connection. Ground connection. Ground connection. Ground connection. Ground connection. Direct switched capacitor block input. Analog column input. Analog column input. Supply voltage. Analog column input. Direct switched capacitor block input. Ground connection. Ground connection. connection. Analog Digital Digital Name P5[7] P3[5] P5[1] P5[0] P3[0] XRES P7[1] P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2] P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3] DVdd P7[7] P7[0] P5[2] P7[6] P7[5] P7[4] connection. Description
Power Power
Power Power Power Power Power P2[1] P0[1] P0[7] Power P0[2] P2[2] Power Power P4[1] P4[7] P2[7] I/O,M P0[5] P0[6] P0[0] P2[0] P4[2] P3[7] P4[5] P2[5] I/O,M P0[3] P0[4] P2[6] P4[6] P4[0] P4[3] P2[3] Power Power P2[4] P4[4] P3[6]
Analog column input column output. Analog column input. Analog column input. Direct switched capacitor block input. connection. connection. Analog column input column output. Analog column input. External Voltage Reference (VREF) input. connection. connection. connection. Direct switched capacitor block input. Ground connection. Ground connection. External Analog Ground (AGND) input. connection.
Power Power
Ground connection. Ground connection.
Active high reset with internal pull down. connection.
Serial Clock (SCL). Serial Clock (SCL), ISSP SCLK[2]. Serial Data (SDA), ISSP SDATA[2].
connection.
Power Power Power Power Power Power Power
Serial Data (SDA).
Optional External Clock Input (EXTCLK).
Ground connection. Ground connection.
Supply voltage.
Power Power Power
Ground connection. Ground connection. Ground connection. Ground connection. connection. connection. Supply voltage.
Ground connection. Ground connection.
LEGENDA Analog, Input, Output, Analog Input, Connection.
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Figure 8-5. CY8C24094 (Not Production)
P4[1] P3[7] P5[7] P5[5] P5[3]
P2[1] P4[7] P4[5] P4[3] P3[5] P3[3] P3[1]
P0[1] P2[7] P2[5] P2[3] P5[1] P1[7] P1[5]
P0[7] P0[5] P0[3] P1[1] P1[3]
P0[6] P0[4] P1[0] P1[2] P7[7] P7[6]
P0[2] P0[0] P2[6] P2[4] P5[0] P1[6] P1[4] P7[0] P7[5]
P2[2] P2[0] P4[6] P4[4] P3[0] P3[4] P3[2] P5[2] P7[4]
P4[2] P4[0] P3[6]
XRES
P7[1] P7[2] P7[3]
P5[6] P5[4]
(Top View)
100-Ball VFBGA Part Pinout (On-Chip Debug)
following 100-pin VFBGA part table drawing CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part only used in-circuit debugging. available production. Table 8-6. 100-Ball Part Pinout (VFBGA)
Analog Name P2[1] P0[1] P0[7] P0[2] P2[2] P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] Description Ground connection. Ground connection. connection. connection. connection. Supply voltage. connection. connection. Ground connection. Ground connection. Ground connection. Ground connection. Direct switched capacitor block input. Analog column input. Analog column input. Supply voltage. Analog column input. Direct switched capacitor block input. Ground connection. Ground connection. connection. Analog Digital Digital Name OCDE P5[7] P3[5] P5[1] P5[0] P3[0] XRES P7[1] OCDO P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2] P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] Description even data I/O.
Power Power
Power
Power Power Power Power Power Power Power I/O,
Analog column input column output. Analog column input. Analog column input.
Power Power
Ground connection. Ground connection.
Active high reset with internal pull down. data output.
Serial Clock (SCL). Serial Clock (SCL), ISSP SCLK[2]. Serial Data (SDA), ISSP SDATA[2].
connection.
Serial Data (SDA).
Optional External Clock Input (EXTCLK).
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Table 8-6. 100-Ball Part Pinout (VFBGA) (continued)
Analog Name P2[0] P4[2] P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0] CCLK P4[3] P2[3] P2[4] P4[4] P3[6] HCLK Description Direct switched capacitor block input. Analog Digital Digital Name P3[2] P5[4] P7[3] DVdd P7[7] P7[0] P5[2] P7[6] P7[5] P7[4] Description
I/O,
connection. connection. Analog column input column output. Analog column input. External Voltage Reference (VREF) input.
Power Power Power Power Power Power Power
Ground connection. Ground connection.
Supply voltage.
clock output. connection. connection. Direct switched capacitor block input. Ground connection. Ground connection. External Analog Ground (AGND) input.
Power Power
high speed clock output.
Power Power Power
Ground connection. Ground connection. Ground connection. Ground connection. connection. connection. Supply voltage.
Ground connection. Ground connection.
LEGENDA Analog, Input, Output, Analog Input, Connection, On-Chip Debugger.
Figure 8-6. CY8C24094 (Not Production)
ocde ocdo
P4[1] P3[7] P5[7] P5[5] P5[3]
P2[1] P4[7] P4[5] P4[3] P3[5] P3[3] P3[1]
P0[1] P2[7] P2[5] P2[3] P5[1] P1[7] P1[5]
P0[7] P0[5] P0[3] P1[1] P1[3]
P0[6] P0[4] P1[0] P1[2] P7[7] P7[6]
P0[2] P0[0] P2[6] P2[4] P5[0] P1[6] P1[4] P7[0] P7[5]
P2[2] P2[0] P4[6] P4[4] P3[0] P3[4] P3[2] P5[2] P7[4]
P4[2] P4[0] P3[6]
XRES
CClk HClk P7[1] P7[2] P7[3]
P5[6] P5[4]
(Top View)
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100-Pin Part Pinout (On-Chip Debug)
100-pin TQFP part CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part only used in-circuit debugging. available production. Table 8-7. 100-Pin Part Pinout (TQFP)
Analog Name Description connection. connection. Analog column input. Optional External Clock Input (EXTCLK). I/O, Analog Digital Digital Name P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] HCLK CCLK XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] Description
P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO Power P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4]
Direct switched capacitor block input. Direct switched capacitor block input.
even data I/O. data output. connection. Ground connection.
Input Power
high speed clock output. clock output. Active high reset with internal pull down.
Ground connection.
Serial Clock (SCL). connection. connection. connection. Serial Data (SDA) Crystal (XTALin), Serial Clock (SCL), ISSP SCLK[2]. connection. Ground connection.
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. connection. External Voltage Reference (VREF) input. connection. Analog column input. connection. connection. Analog column input column output. connection. Analog column input column output. connection. Analog column input. Supply voltage. connection. Ground connection. connection. connection. connection. connection. connection. connection. connection. connection. connection. connection. Analog column input. connection. Analog column input column output. connection. Analog column input column output. connection.
Power Power
Power Power
Supply voltage.
connection. connection. connection. connection. Crystal (XTALout), Serial Data (SDA), ISSP SDATA[2].
I/O,
LEGENDA Analog, Input, Output, Connection, Analog Input, On-Chip Debugger.
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Figure 8-7. CY8C24094 (Not Production)
P0[3], P0[5],
P0[6], P0[4],
SDA, P1[5] P1[3] SCL, P1[1] DVdd
P7[1] P7[0] SDA, P1[0]
P7[7] P7[6] P7[5] P7[4]
P7[3] P7[2]
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P1[2] EXTCLK, P1[4]
P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] SCL, P1[7]
P0[2], P0[0], P2[6], External VREF P2[4], External AGND P2[2], P2[0], P4[6], P4[4], P4[2], P4[0], XRES CCLK HCLK P3[6], P3[4], P3[2], P3[0], P5[6], P5[4], P5[2], P5[0], P1[6],
P0[7],
TQFP
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Register Reference
This section lists registers CY8C24x94 PSoC device family. detailed register information, reference PSoC Technical Reference Manual.
Register Conventions
register conventions specific this section listed following table. Convention Description Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Access specific
Register Mapping Tables
PSoC device total register address space bytes. register space referred space divided into banks. Flag register (CPU_F) determines which bank user currently When user Bank Note following register mapping tables, blank fields Reserved should accessed.
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Register Bank Table: User Space
Addr (0,Hex) Access Name PMA0_DR PMA1_DR PMA2_DR PMA3_DR PMA4_DR PMA5_DR PMA6_DR PMA7_DR USB_SOF0 USB_SOF1 USB_CR0 USBI/O_CR0 USBI/O_CR1 EP1_CNT1 EP1_CNT EP2_CNT1 EP2_CNT EP3_CNT1 EP3_CNT EP4_CNT1 EP4_CNT EP0_CR EP0_CNT EP0_DR0 EP0_DR1 EP0_DR2 EP0_DR3 PRT7DR EP0_DR4 PRT7IE EP0_DR5 PRT7GS EP0_DR6 PRT7DM2 EP0_DR7 DBB00DR0 AMX_IN DBB00DR1 AMUXCFG DBB00DR2 DBB00CR0 ARF_CR DBB01DR0 CMP_CR0 DBB01DR1 ASY_CR DBB01DR2 CMP_CR1 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 TMP_DR0 DCB03DR1 TMP_DR1 DCB03DR2 TMP_DR2 DCB03CR0 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 Blank fields Reserved should accessed. Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) Access Addr (0,Hex) ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access specific. Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Access Name Addr (0,Hex) Access
CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2
CPU_F
DAC_D CPU_SCR1 CPU_SCR0
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Register Bank Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) Access Name PMA0_WA PMA1_WA PMA2_WA PMA3_WA PMA4_WA PMA5_WA PMA6_WA PMA7_WA PMA0_RA PMA1_RA PMA2_RA PMA3_RA PMA4_RA PMA5_RA PMA6_RA PMA7_RA PRT7DM0 PRT7DM1 PRT7IC0 PRT7IC1 DBB00FN CLK_CR0 DBB00IN CLK_CR1 DBB00OU ABF_CR0 AMD_CR0 DBB01FN CMP_GO_EN DBB01IN DBB01OU AMD_CR1 ALT_CR0 DCB02FN DCB02IN DCB02OU DCB03FN TMP_DR0 DCB03IN TMP_DR1 DCB03OU TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 Blank fields Reserved should accessed. Addr (1,Hex) Access Addr (1,Hex) ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access specific. Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Access Name USBI/O_CR2 USB_CR1 Addr (1,Hex) Access
EP1_CR0 EP2_CR0 EP3_CR0 EP4_CR0
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU
MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP
IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5
CPU_F
DAC_CR CPU_SCR1 CPU_SCR0
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Electrical Specifications
This section presents electrical specifications CY8C24x94 PSoC device family. most date electrical specifications, confirm that have most recent data sheet visiting http://www.cypress.com. Specifications valid -40°C 85°C 100°C, except where noted. Specifications devices running greater than valid -40°C 70°C 82°C. Figure 10-1. Voltage versus Frequency
5.25
4.75 Voltage
rati
3.00
Frequency
following table lists units measure that used this chapter. Table 10-1. Units Measure Symbol Kbit Vrms Unit Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol Unit Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts million picosecond samples second sigma: standard deviation volts
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10.1 Absolute Maximum Ratings
Table 10-2. Absolute Maximum Ratings Symbol TSTG Description Storage Temperature +100 Units Notes Higher storage temperatures reduces data retention time. Recommended storage temperature +25oC 25oC. Extended duration storage temperatures above 65oC degrades reliability.
TBAKETEMP Bake Temperature TBAKETIME VI/O VI/O2 IMI/O IMAI/O Bake Time
Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tri-state Maximum Current into Port Maximum Current into Port Configured Analog Driver Electro Static Discharge Voltage Latch-up Current
package label -0.5 2000
package label
Hours
+6.0
Human Body Model ESD.
10.2 Operating Temperature
Table 10-3. Operating Temperature Symbol TAUSB Description Ambient Temperature Ambient Temperature using Junction Temperature +100 Units Notes
temperature rise from ambient junction package specific. Thermal Impedance page user must limit power consumption comply with this requirement.
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10.3 Electrical Characteristics
10.3.1 Chip Level Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-4. Chip-Level Specifications Symbol Description Supply Voltage IDD5 Supply Current, (5V) 5.25 Units Notes specifications, Table 10-14 page Conditions 5.0V, MHz, SYSCLK doubler disabled, MHz, 93.75 kHz, 93.75 kHz, analog power off. Conditions 3.3V, MHz, SYSCLK doubler disabled, MHz, 93.75 kHz, 0.367 kHz, analog power off. Conditions with internal slow speed oscillator, 3.3V, analog power off. Conditions with internal slow speed oscillator, 3.3V, analog power off.
IDD3
Supply Current, (3.3V)
ISBH
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT.[4] Sleep (Mode) Current with POR, LVD, Sleep Timer, high temperature.[4]
10.3.2 General Purpose Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-5. GPI/O Specifications Symbol Description Pull Resistor Pull Down Resistor High Output Level Units Notes
Output Level
0.75
COUT
High Level Source Current Level Sink Current Input Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). maximum combined budget. 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). maximum combined budget. Vdd-1.0V, limitations total current note 0.75V, limitations total current note 5.25. 5.25. Gross tested Package dependent. Temp 25oC. Package dependent. Temp 25oC.
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10.3.3 Full Speed Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -10°C 85°C, 3.0V 3.6V -10°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-6. Full Speed Mbps) Specifications Symbol Description Interface Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance High-Z State Data Line Leakage II/O REXT External Series Resistor VUOH Static Output High, Driven VUOHI VUOL VCRS Static Output High, Idle Static Output Driver Output Impedance D+/D- Crossover Voltage Units Notes (D+) (D-)
3.3V. series with each pin. Ground. Internal pull enabled. Ground. Internal pull enabled. Ground. Internal pull enabled. Including REXT Resistor.
10.3.4 Operational Amplifier Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Operational Amplifier component both Analog Continuous Time PSoC blocks Analog Switched Capacitor PSoC blocks. guaranteed specifications measured Analog Continuous Time PSoC block. Table 10-7. Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High TCVOSOA Average Input Offset Voltage Drift Input Leakage Current (Port Analog Pins) IEBOA Input Capacitance (Port Analog Pins) CINOA Common Mode Voltage Range Common Mode Voltage Range (high power high opamp bias) 35.0 Units V/°C Notes
VCMOA
Gross tested Package dependent. Temp 25oC. common-mode input voltage range measured through analog output buffer. specification includes limitations imposed characteristics analog output buffer.
Note Standby current includes functions (POR, LVD, WDT, Sleep Time) needed reliable system operation. This should compared with devices that have similar functions enabled.
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Table 10-7. Operational Amplifier Specifications (continued) Description Open Loop Gain Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High VOHIGHO High Output Voltage Swing (internal signals) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High VOLOWOA Output Voltage Swing (internal signals) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High ISOA Supply Current (including associated AGND buffer) Power Low, Opamp Bias Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High PSRROA Supply Voltage Rejection Ratio Symbol GOLOA Units Notes
1200 2400 4600
1000 1600 3200 6400
(Vdd 2.25) (Vdd 1.25V) Vdd.
10.3.5 Power Comparator Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table 10-8. Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description power comparator (LPC) reference voltage range supply current voltage offset Units Notes
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10.3.6 Analog Output Buffer Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-9. Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High High Output Voltage Swing (Load ohms Vdd/2) Power Power High Output Voltage Swing (Load ohms Vdd/2) Power Power High Supply Current Including Bias Cell Load) Power Power High Supply Voltage Rejection Ratio Units V/°C Notes
VOLOWOB
ISOB PSRROB
(0.5 1.3) VOUT (Vdd 2.3).
Table 10-10. 3.3V Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High High Output Voltage Swing (Load ohms Vdd/2) Power Power High Output Voltage Swing (Load ohms Vdd/2) Power Power High Supply Current Including Bias Cell Load) Power Power High Supply Voltage Rejection Ratio Units V/°C Notes
VOLOWOB
ISOB PSRROB
(0.5 1.0) VOUT (0.5 0.9).
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10.3.7 Analog Reference Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. guaranteed specifications measured through Analog Continuous Time PSoC blocks. power levels AGND refer power Analog Continuous Time PSoC block. power levels RefHi RefLo refer Analog Reference Control register. limits stated AGND include offset error AGND buffer local Analog Continuous Time PSoC block. Reference control power high. Table 10-11. Analog Reference Specifications Symbol Description Bandgap Voltage Reference 1.28 1.30 1.32 AGND Vdd/2[5, Vdd/2 0.04 Vdd/2 0.01 Vdd/2 0.007 AGND BandGap[5, 0.048 0.030 0.024 AGND P2[4] (P2[4] Vdd/2) P2[4] 0.011 P2[4] P2[4] 0.011 AGND BandGap[5, 0.009 0.008 0.016 AGND BandGap[5, 0.022 0.010 0.018 AGND Block Block Variation (AGND Vdd/2)[5, -0.034 0.000 0.034 RefHi Vdd/2 BandGap Vdd/2 0.10 Vdd/2 Vdd/2 0.10 RefHi BandGap 0.06 0.06 RefHi BandGap P2[6] (P2[6] 1.3V) P2[6] P2[6] P2[6] 0.113 0.018 0.077 RefHi P2[4] BandGap (P2[4] Vdd/2) P2[4] 0.130 P2[4] 0.016 P2[4] 0.098 RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 1.3V) P2[4] P2[6] P2[4] P2[6] P2[4] P2[6]+ 0.133 0.016 0.100 RefHi BandGap 0.112 0.076 RefLo Vdd/2 BandGap Vdd/2 0.04 Vdd/2 0.024 Vdd/2 0.04 RefLo BandGap 0.06 0.06 RefLo BandGap P2[6] (P2[6] 1.3V) P2[6] P2[6] P2[6] 0.084 0.025 0.134 RefLo P2[4] BandGap (P2[4] Vdd/2) P2[4] 0.056 P2[4] 0.026 P2[4] 0.107 RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 1.3V) P2[4] P2[6] P2[4] P2[6] P2[4] P2[6] 0.057 0.026 0.110 Units
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Table 10-12. 3.3V Analog Reference Specifications Symbol Description Bandgap Voltage Reference AGND Vdd/2[5, AGND BandGap[5, AGND P2[4] (P2[4] Vdd/2) AGND BandGap[5, AGND BandGap[5, AGND Column Column Variation (AGND Vdd/2)[5, RefHi Vdd/2 BandGap RefHi BandGap RefHi BandGap P2[6] (P2[6] 0.5V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 0.5V) 1.28 Vdd/2 0.03 P2[4] 0.008 0.009 0.027 -0.034 1.30 1.32 Vdd/2 0.01 Vdd/2 0.005 Allowed P2[4] 0.001 P2[4] 0.009 0.005 0.015 0.010 0.018 0.000 0.034 Allowed Allowed Allowed Allowed P2[4] P2[6] 0.009 Allowed Allowed Allowed Allowed Allowed P2[4]- P2[6] 0.022 Units
P2[4] P2[6] 0.075
P2[4] P2[6] 0.057
RefHi BandGap RefLo Vdd/2 BandGap RefLo BandGap RefLo BandGap P2[6] (P2[6] 0.5V) RefLo P2[4] BandGap (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 0.5V) P2[4] P2[6] 0.048
P2[4] P2[6] 0.092
10.3.8 Analog PSoC Block Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-13. Analog PSoC Block Specifications Symbol Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switched Capacitor) 12.2 Units Notes
Note AGND tolerance includes offsets local buffer PSoC block. Bandgap voltage 1.3V 0.02V. Avoid using P2[4] digital signaling when using analog resource that depends Analog Reference. Some coupling digital signal appear AGND.
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10.3.9 Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Note bits PORLEV following table refer bits VLT_CR register. PSoC Technical Reference Manual more information VLT_CR register. Table 10-14. Specifications Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Value PPOR Trip (positive ramp) PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value PPOR Trip (negative ramp) PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] PPOR Hysteresis PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b 2.91 4.39 4.55 2.82 4.39 4.55 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 Units Notes
2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72
2.98[7] 3.08 3.20 4.08 4.57 4.74[8] 4.82 4.91
Notes Always greater than above PPOR (PORLEV falling supply. Always greater than above PPOR (PORLEV falling supply.
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10.3.10 Programming Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-15. Programming Specifications Description Supply Current During Programming Verify Input Voltage During Programming Verify VIHP Input High Voltage During Programming Verify IILP Input Current when Applying Vilp P1[0] P1[1] During Programming Verify IIHP Input Current when Applying Vihp P1[0] P1[1] During Programming Verify VOLV Output Voltage During Programming Verify VOHV Output High Voltage During Programming Verify FlashENPB Flash Endurance (per block)[9] FlashENT FlashDR Flash Endurance (total)[10] Flash Data Retention Symbol IDDP VILP 50,000 1,800,000 0.75 Units Years Erase/write cycles block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor. Notes
Note 50,000 cycle flash endurance block will only guaranteed flash operating within voltage range. Voltage ranges 3.0V 3.6V 4.75V 5.25V. maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles). full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information.
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10.4 Electrical Characteristics
10.4.1 Chip-Level Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-16. Chip-Level Specifications
Symbol FIMO245V FIMO243V FIMOUSB5V Description Internal Main Oscillator Frequency (5V) Internal Main Oscillator Frequency (3.3V) Internal Main Oscillator Frequency with (5V) Frequency locking enabled traffic present. Internal Main Oscillator Frequency with (3.3V) Frequency locking enabled traffic present. Internal Main Oscillator Frequency 23.04 22.08 23.94 24.96[11,12] 25.92[12,13] 24.06[12] Units Notes Trimmed operation using factory trim values. Trimmed 3.3V operation using factory trim values. -10°C 85°Cn 4.35 5.15 -0°C 70°C 3.15 3.45 Trimmed 3.3V operation using factory trim values. figure page SLIMO Mode
FIMOUSB3V
23.94
24.06[12]
FIMO6
6.5[11,12,13]
FCPU1 FCPU2 FBLK5 FBLK3 F32K1 F32K_U
Frequency Nominal) Frequency (3.3V Nominal) Digital PSoC Block Frequency Nominal) Digital PSoC Block Frequency (3.3V Nominal) Internal Speed Oscillator Frequency Internal Speed Oscillator (ILO) Untrimmed Frequency
0.090 0.086
24.96[11,12] 12.96[12,13] 49.92[11,12,14] 25.92[12,14]
Refer Digital Block Specifications.
After reset before starts run, trimmed. System Resets section PSoC Technical Reference Manual details timing this
Jitter32k TXRST DC24M DCILO Step24M Fout48M Jitter24M1 FMAX
Period Jitter External Reset Pulse Width Duty Cycle Internal Speed Oscillator Duty Cycle Trim Step Size Output Frequency
46.08
48.0
49.92[11,13]
V/ms
Trimmed. Utilizing factory trim values.
Period Jitter (IMO) Peak-to-Peak Maximum frequency signal input output. SRPOWER_UP Power Supply Slew Rate TPOWERUP Time from executing code
12.96
slew rate during power Power from System Resets section PSoC Technical Reference Manual.
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Figure 10-2. Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
10.4.2 General Purpose Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-17. GPI/O Specifications Symbol FGPI/O TRiseF TFallF TRiseS TFallS Description GPI/O Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload Units Notes Normal Strong Mode 5.25V, 5.25V, 5.25V, 5.25V,
Figure 10-3. GPI/O Timing Diagram
utput Voltage
TRiseF TRiseS
TFallF TFallS
10.4.3 Full Speed Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -10°C 85°C, 3.0V 3.6V -10°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-18. Full Speed Mbps) Specifications Symbol TRFS TFSS TRFMFS TDRATEFS Description Transition Rise Time Transition Fall Time Rise/Fall Time Matching: (TR/TF) Full Speed Data Rate 0.25% 0.25% Units Mbps Notes load. load. load.
Notes 4.75V 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim range. 3.0V 3.6V. Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V. individual user module data sheets information maximum frequencies user modules
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10.4.4 Operational Amplifier Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Settling times, slew rates, gain bandwidth based Analog Continuous Time PSoC block. Power High Opamp Bias High supported 3.3V. Table 10-19. Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Rising Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Falling Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Noise (Power Medium, Opamp Bias High) Units
0.72 0.62
TSOA
0.15
0.92 0.72
SRROA
SRFOA
0.01
BWOA
ENOA Symbol TROA
0.75
nV/rt-Hz
Table 10-20. 3.3V Operational Amplifier Specifications Description Rising Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Rising Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Falling Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High Noise (Power Medium, Opamp Bias High) Units
3.92 0.72
TSOA
0.31
5.41 0.72
SRROA
SRFOA
0.24
BWOA ENOA
0.67
nV/rt-Hz
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When bypassed capacitor P2[4], noise analog ground signal distributed each block reduced factor dB). This frequencies above corner frequency defined on-chip 8.1k resistance external capacitor. Figure 10-4. Typical AGND Noise with P2[4] Bypass
dBV/rtHz 10000
0.01
1000
0.001
0.01
Freq (kHz)
frequencies, opamp noise proportional 1/f, power independent, determined device geometry. high frequencies, increased power level reduces noise spectrum level. Figure 10-5. Typical Opamp Noise
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
0.001
0.01
Freq (kHz)
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10.4.5 Power Comparator Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table 10-21. Power Comparator Specifications Symbol TRLPC Description response time Units Notes overdrive comparator reference within VREFLPC.
10.4.6 Digital Block Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-22. Digital Block Specifications Function Timer Description Capture Pulse Width Maximum Frequency, Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency Width Negated Between Transmissions Maximum Input Clock Frequency Maximum Input Clock Frequency 50[15] 50[15] 49.92 49.92 4.75V 5.25V. 4.75V 5.25V. 50[15] 50[15] 49.92 25.92 49.92 25.92 Units 4.75V 5.25V. 4.75V 5.25V. Notes
24.6
50[15]
24.6 24.6
Maximum data rate over clocking.
Maximum data rate 3.08 over clocking. Maximum data rate 3.08 over clocking.
Note minimum input pulse width based input synchronizers running nominal period).
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10.4.7 External Clock Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-23. External Clock Specifications Symbol Duty Cycle Power Switch Description 23.94 24.06 Units Notes FOSCEXT Frequency Applications
10.4.8 Analog Output Buffer Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-24. Analog Output Buffer Specifications Symbol Description TROB Rising Settling Time 0.1%, Step, 100pF Load Power Power High TSOB Falling Settling Time 0.1%, Step, 100pF Load Power Power High SRROB Rising Slew Rate (20% 80%), Step, Load Power Power High SRFOB Falling Slew Rate (80% 20%), Step, Load Power Power High BWOBSS Small Signal Bandwidth, 20mVpp, Load Power Power High BWOBLS Large Signal Bandwidth, 1Vpp, Load Power Power High Table 10-25. 3.3V Analog Output Buffer Specifications
Symbol TROB TSOB SRROB SRFOB BWOBSS BWOBLS Description Rising Settling Time 0.1%, Step, Load Power Power High Falling Settling Time 0.1%, Step, Load Power Power High Rising Slew Rate (20% 80%), Step, Load Power Power High Falling Slew Rate (80% 20%), Step, Load Power Power High Small Signal Bandwidth, 20mVpp, Load Power Power High Large Signal Bandwidth, 1Vpp, Load Power Power High Units Notes
0.65 0.65 0.65 0.65
Units
Notes
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10.4.9 Programming Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-26. Programming Specifications
Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TERASEALL Description Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Flash Erase Time (Bulk) 100[16] 200[16] Units Notes
TPROGRAM_HOT Flash Block Erase Flash Block Write Time TPROGRAM_COLD Flash Block Erase Flash Block Write Time
Erase Blocks protection fields once 100°C -40°C
Note full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information.
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10.4.10 Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 10-27. Characteristics Pins Symbol Description Standard Mode Fast Mode 100[17] Units Notes
Clock Frequency FSCLI2C THDSTAI2C Hold Time (repeated) START Condition. After this period, first clock pulse generated. TLOWI2C Period Clock HIGH Period Clock THIGHI2C TSUSTAI2C Setup Time Repeated START Condition THDDATI2C Data Hold Time TSUDATI2C Data Setup Time TSUSTOI2C Setup Time STOP Condition Free Time Between STOP START TBUFI2C Condition TSPI2C Pulse Width spikes suppressed input filter.
Figure 10-6. Definition Timing Fast/Standard Mode
TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Note Fast-Mode I2C-bus device used Standard-Mode I2C-bus system, requirement tSU;DAT must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSU;DAT 1000 1250 (according Standard-Mode I2C-bus specification) before line released.
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Packaging Dimensions
This section illustrates package specification CY8C24x94 PSoC devices, along with thermal impedance package solder reflow peak temperatures. Important Note Emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer Emulator Dimension drawings http://www.cypress.com. Figure 11-1. 56-Pin (7x7x0.6
001-58740
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Figure 11-2. 56-Pin (8x8
VIEW SIDE VIEW
0.08[0.003] 7.90[0.311] 8.10[0.319] 7.70[0.303] 7.80[0.307] 0.80[0.031] DIA. 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.18[0.007] 0.28[0.011] 0.45[0.018] PIN1 0.20[0.008]
BOTTOM VIEW
7.70[0.303] 7.80[0.307]
7.90[0.311] 8.10[0.319]
0°-12°
SEATING PLANE
0.30[0.012] 0.50[0.020] 6.45[0.254] 6.55[0.258]
0.50[0.020]
0.24[0.009] 0.60[0.024]
(4X)
NOTES: HATCH AREA SOLDERABLE EXPOSED METAL. REFERENCE JEDEC#: MO-220 PACKAGE WEIGHT: 0.162g DIMENSIONS [MIN/MAX] PACKAGE CODE PART LF56A LY56A DESCRIPTION STANDARD PB-FREE
001-12921
Figure 11-3. 56-Pin Sawn
001-53450
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6.45[0.254] 6.55[0.258]
SOLDERABLE EXPOSED
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Figure 11-4. 68-Pin (8x8 0.89
VIEW
7.90[0.311] 8.10[0.319] 7.70[0.303] 7.80[0.307] 0.70[0.028] 0.2[0.008] 0.9[0.035] 0.05[0.002] 0.18[0.007] 0.28[0.011] PIN1 0.20
SIDE VIEW
0.08
BOTTOM VIEW
5.69
SOLDERABLE EXPOSED
7.90[0.311]
7.70[0.303]
7.80[0.307]
8.10[0.319]
5.69
0°-12° 0.24[0.009] 0.60[0.023]
NOTES: HATCH SOLDERABLE EXPOSED PAD. REFERENCE JEDEC#: MO-220 PACKAGE WEIGHT: 0.17g DIMENSIONS [MIN/MAX] PACKAGE CODE PART LF68 LY68 DESCRIPTION STANDARD PB-FREE
SEATING PLANE
B.S.C. 6.50[0.255]
NOTE: EXPOSED DIMENSION VARIES LEADFRAME CAVITY (PADDLE) SIZE
51-85214
Important Note
information preferred dimensions mounting packages, refer Application Note, "Application Notes Surface Mount Assembly Amkor's MicroLeadFrame (MLF) Packages" available http://www.amkor.com. Pinned vias thermal conduction required low-power PSoC device.
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Figure 11-5. 68-Pin Sawn (8X8 0.90
VIEW
SIDE VIEW
BOTTOM VIEW
0.900±0.100 8.000±0.100 0.200 5.7±0.10 0.400 PITCH PIN1 0.20
8.000±0.100
5.7±0.10
0.20±0.05
0.05
SEATING PLANE
0.400±0.1005
6.40
NOTES: HATCH AREA SOLDERABLE EXPOSED METAL.
REFERENCE JEDEC#: MO-220 PACKAGE WEIGHT: 0.17g DIMENSIONS MILLIMETERS
0.08
001-09618
Figure 11-6. 100-Ball (6x6 VFBGA
VIEW BOTTOM VIEW CORNER CORNER
6.00±0.10
6.00±0.10
4.50
0.50
2.25
6.00±0.10
2.25 0.50 4.50 6.00±0.10
0.45 REF.
0.10
0.21±0.05
0.08
0.15(4X)
SEATING PLANE 0.21 REF. 1.00
REFERENCE JEDEC MO-195C PKG. WEIGHT: (NEW PKG.)
51-85209
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6.40
LASER MARK
SOLDERABLE EXPOSED
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Figure 11-7. 100-Pin (14x14 TQFP
51-85048
11.1 Thermal Impedance
Package QFN[19] QFN[19] VFBGA TQFP Typical [18] 12.93 °C/W 13.05 °C/W °C/W °C/W
11.2 Solder Reflow Peak Temperature
Following minimum solder reflow peak temperature achieve good solderability. Package VFBGA TQFP Minimum Peak Temperature[20] 240°C 240°C 240°C 240°C Maximum Peak Temperature 260°C 260°C 260°C 260°C
Notes POWER achieve thermal impedance specified package,refer "Application Notes Surface Mount Assembly Amkor's MicroLeadFrame (MLF) Packages" available http://www.amkor.com. Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications
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Development Tool Selection
12.1 Software
12.1.1 PSoC Designer core PSoC development software suite PSoC Designer, used generate PSoC firmware applications. PSoC Designer available free charge http://www.cypress.com includes free compiler. 12.1.2 PSoC Programmer Flexible enough used bench development, suitable factory programming, PSoC Programmer works either standalone programming application operate directly from PSoC Designer. PSoC Programmer software compatible with both PSoC ICE-Cube In-Circuit Emulator PSoC MiniProg. PSoC programmer available free charge http://www.cypress.com.
12.3 Evaluation Tools
evaluation tools purchased from Cypress Online Store. 12.3.1 CY3210-MiniProg1 CY3210-MiniProg1 enables user program PSoC devices MiniProg1 programming unit. MiniProg small, compact prototyping programmer that connects provided cable. includes:
MiniProg Programming Unit MiniEval Socket Programming Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
12.2 Development Kits
development kits purchased from Cypress Online Store. 12.2.1 CY3215-DK Basic Development CY3215-DK prototyping development with PSoC Designer. This supports in-circuit emulation software interface enables users run, halt, single step processor view content specific memory locations. Advance emulation features also supported through PSoC Designer. includes:
12.3.2 CY3210-PSoCEval1 CY3210-PSoCEval1 features evaluation board MiniProg1 programming unit. evaluation board includes module, potentiometer, LEDs, plenty breadboarding space meet your evaluation needs. includes:
PSoC Designer Software ICE-Cube In-Circuit Emulator Flex-Pod CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 240V Power Supply, Euro-Plug Adapter iMAGEcraft Compiler (Registration Required) ISSP Cable Cable Blue Cat-5 Cable CY8C29466-24PXI 28-PDIP Chip Samples
Evaluation Board with Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
12.3.3 CY3214-PSoCEvalUSB CY3214-PSoCEvalUSB evaluation features development board CY8C24794-24LFXI PSoC device. Special features board include both capacitive sensing development debugging support. This evaluation board also includes module, potentiometer, LEDs, enunciator plenty bread boarding space meet your evaluation needs. includes:
PSoCEvalUSB Board Module MIniProg Programming Unit Mini Cable PSoC Designer Example Projects Getting Started Guide Wire Pack
Document Number: 38-12018 Rev.
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
12.4 Device Programmers
device programmers purchased from Cypress Online Store. 12.4.1 CY3216 Modular Programmer CY3216 Modular Programmer features modular programmer MiniProg1 programming unit. modular programmer includes three programming module cards supports multiple Cypress products. includes:
12.4.2 CY3207ISSP In-System Serial Programmer (ISSP) CY3207ISSP production programmer. includes protection circuitry industrial case that more robust than MiniProg production-programming environment. Note: CY3207ISSP needs special software compatible with PSoC Programmer. includes:
CY3207 Programmer Unit PSoC ISSP Software 240V Power Supply, Euro-Plug Adapter Cable
Modular Programmer Base Programming Module Cards MiniProg Programming Unit PSoC Designer Software Getting Started Guide Cable
12.5 Accessories (Emulation Programming)
Table 12-1. Emulation Programming Accessories Part CY8C24794-24LFXI CY8C24894-24LFXI CY8C24794-24LQXI Package Flex-Pod Kit[21] CY3250-24X94QFN CY3250-24X94QFN CY3250-24X94QFN Foot Kit[22] CY3250-56QFN-FK CY3250-56QFN-FK None Adapter[23] Adapters found http://www.emulation.com.
Notes Flex-Pod includes practice flex-pod practice PCB, addition flex-pods. Foot includes surface mount feet that soldered target PCB. Programming adapter converts non-DIP package footprint. Specific details ordering information each adapters found http://www.emulation.com.
Document Number: 38-12018 Rev.
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Ordering Information
Table 13-1. CY8C24x94 PSoC Device's Features Ordering Information Analog Outputs Digital Pins Analog Blocks Analog Inputs Digital Blocks Temperature Range
TQFP[24] 100-Ball (6x6 VFBGA[24] 68-Pin (Sawn) 68-Pin (Sawn) (Tape Reel) 56-Pin (8x8 56-Pin (8x8 (Tape Reel) 56-Pin (8x8 (Sawn) 56-Pin (8x8 (Sawn) (Tape Reel) 56-Pin (8x8 56-Pin (8x8 (Tape Reel) 56-Pin (8x8 (Sawn) 56-Pin (8x8 (Sawn) (Tape Reel) 100-Ball (6x6 VFBGA 68-Pin (Sawn) 68-Pin (Sawn) (Tape Reel)
CY8C24094-24AXI CY8C24094-24BVXI CY8C24094-24LTXI CY8C24094-24LTXIT CY8C24794-24LFXI CY8C24794-24LFXIT CY8C24794-24LTXI CY8C24794-24LTXIT CY8C24894-24LFXI CY8C24894-24LFXIT CY8C24894-24LTXI CY8C24894-24LTXIT CY8C24994-24BVXI CY8C24994-24LTXI CY8C24994-24LTXIT
-40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Note sales information, contact local Cypress sales office Field Applications Engineer (FAE).
Notes This part used in-circuit debugging. available production
Document Number: 38-12018 Rev.
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XRES
Ordering Code
Package
Flash (Bytes)
SRAM (Bytes)
CY8C24094, CY8C24794 CY8C24894, CY8C24994
13.1 Ordering Code Definitions
XXX- Package Type: PDIP Pb-Free SOIC Pb-Free SSOP Pb-Free LFX/LKX/LQX/LTX Pb-Free TQFP Pb-Free VFBGA Pb-Free Speed: Part Number Family Code Technology Code: CMOS Marketing Code: PSoC Company Cypress Thermal Rating: Commercial Industrial Extended
Document Number: 38-12018 Rev.
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
Document History Page
Document Title: CY8C24094, CY8C24794, CY8C24894, CY8C24994 PSoC® Programmable System-on-Chip Document Number: 38-12018 Rev. Submission Date 133189 251672 289742 01.27.2004 Orig. Change Description Change silicon document Advance Data Sheet. First Preliminary Data Sheet. Changed title encompass only CY8C24794 because CY8C24494 CY8C24694 being offered Cypress. standard items from memo. Analog Input pinouts. MACs. Change bytes SRAM dimension package. Remove HAPI. Update diagrams, registers specs. logo. Update copyright. Update CY.com URLs. Re-add ISSP programming pinout notation. Reflow Temp. table. Update features (MAC, Oscillator, voltage range), registers (INT_CLR2/MSK2, second MAC), specs. (Rext, IMO, analog output buffer.). color logo. Expand analog arch. diagram. Update Electrical Specifications. temperature specifications. Make data sheet Final. Remove logo. preferred dimensions mounting packages. device, CY8C24894 56-pin with XRES pin. Fimousb3v char. specs. Upgrade Perform logo update corporate address copyright. ISSP note pinout tables. Update typical recommended Storage Temperature industrial specs. Update Output Level maximum I/OL budget. FLS_PR1 Register Bank users specify which Flash bank should used SROM operations. devices 68-pin 100-ball VFBGA under RPNs: CY8C24094 CY8C24994. packages 68-pin QFN. non-production pinouts package diagrams. Update branding convention. Dev. Tool section. Update copyright trademarks. Power Comparator (LPC) AC/DC electrical spec. tables. CY8C20x34 PSoC Device Characteristics table. detailed dimensions 56-pin package diagram update revision. Secure package diagram/manufacturing QFN. Update emulation pod/feet part numbers. pinout type-o TestTrack. CapSense requirement reference. Update figure standards. Update Technical Training paragraphs. package clarifications dimensions. Update ECN-ed Amkor dimensioned package diagram revisions. Reword reference. 56-pin spec. footnote AGND descriptions avoid using P2[4] digital signaling noise AGND. Remove reference CMP_GO_EN1 Bank Table Address this register functionality 24xxx. footnote sales. description 'Optional External Clock Input' P1[4] match description P1[4].
335236
344318 346774 349566 393164 469243
561158
728238
2552459
08/14/08
AZIE/PYRS
2616550
12/05/08
OGNE/PYRS Updated Programmable Configuration detail. Changed title from PSoC® Mixed-Signal Array PSoC® Programmable System-on-ChipDPT/PYRS Added package diagram 001-09618 updated Ordering Information table
2657956
02/11/09
Document Number: 38-12018 Rev.
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
Document Title: CY8C24094, CY8C24794, CY8C24894, CY8C24994 PSoC® Programmable System-on-Chip Document Number: 38-12018 2708135 05/18/2009 Added Note Information section page Removed reference Hi-Tech Lite Compiler section Development Tools Selection page Added 56-Pin (Sawn) package diagram updated ordering information Updated following parameters: DCILO, F32K_U, FIMO6, TPOWERUP, TERASE_ALL, TPROGRAM_HOT, TPROGRAM_COLD. Added SRPOWER_UP parameter specs table. Ordering Information table: Changed XRES value CY8C24894-24LTXI CY8C24894-24LTXIT `Yes'. Ordering Information: Updated CY8C24894-24LTXI CY8C24894-24LTXIT parts Sawn updated Digital Analog values Added Contents page. Updated package diagram (51-85124) Added package diagram 001-58740 updated Development Tools section. Modified Note remove voltage range 2.4V 3.0V Updated Cypress website links Added TXRST, DC24M, TBAKETEMP TBAKETIME parameters Removed reference 2.4V Removed sections `Third Party Tools' `Build PSoC Emulator into your Board' Updated package diagrams Removed inactive parts from ordering information table.
2718162 2762161
06/11/2009 09/10/2009
RLRM
2768530 2817938
09/24/09 11/30/09
RLRM KRIS
2846641 2867363 2901653
1/12/10 01/27/10 03/30/2010
RLRM ANUP
Document Number: 38-12018 Rev.
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
Sales, Solutions, Legal Information
Worldwide Sales Design Support
Cypress maintains worldwide network offices, solution centers, manufacturer's representatives, distributors. find office closest you, visit Cypress Locations.
Products
Automotive Clocks Buffers Interface Lighting Power Control Memory Optical Image Sensing PSoC Touch Sensing Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC PSoC PSoC
Cypress Semiconductor Corporation, 2004-2010. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
Document Number: 38-12018 Rev.
Revised March 2010
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PSoC Designeris trademark PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations.
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