CY8C24094 CY8C24794 CY8C24894 CY8C24994
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Final Data Sheet
CY8C24894 includes XRES support In-System Serial Programming (ISSP) external reset control Powerful Harvard Architecture Processor Processor Speeds Multiply, 32-Bit Accumulate Power High Speed 5.25V Operating Voltage Industrial Temperature Range: -40°C +85°C Temperature Range: -10°C +85°C Advanced Peripherals (PSoC Blocks) Rail-to-Rail Analog PSoC Blocks Provide: 14-Bit ADCs 9-Bit DACs Programmable Gain Amplifiers Programmable Filters Comparators Digital PSoC Blocks Provide: 32-Bit Timers, Counters, PWMs Modules Full-Duplex UART Multiple SPIMasters Slaves Connectable GPIO Pins Complex Peripherals Combining Blocks Capacitive Sensing Application Capability Full-Speed Mbps) Four Uni-Directional Endpoints Bi-Directional Control Endpoint Compliant Dedicated Byte Buffer External Crystal Required Flexible On-Chip Memory Flash Program Storage 50,000 Erase/ Write Cycles SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation Flash Programmable Configurations Sink GPIO Pull Pull down, High Strong, Open Drain Drive Modes GPIO Analog Inputs GPIO Analog Outputs GPIO Configurable Interrupt GPIO Precision, Programmable Clocking Internal 24/48 Oscillator Internal Oscillator Watchdog Sleep .25% Accuracy with External Components Additional System Resources I2CSlave, Master, Multi-Master Watchdog Sleep Timers User-Configurable Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoC DesignerTM) Full-Featured, In-Circuit Emulator Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory
Port
Port
Port
Port
Port
Port
Port
Analog Drivers
PSoC® Functional Overview
PSoC® family consists many Mixed-Signal Array with On-Chip Controller devices. PSoC family devices designed replace traditional MCUs, system ICs, numerous discrete components that surround them. PSoC CY8C24x94 devices unique members PSoC family because includes full-featured, full-speed Mbps) port. Configurable analog, digital, interconnect circuitry enable high level integration host industrial, consumer, communication applications. This architecture allows user create customized peripheral configurations that match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts packages. PSoC architecture, illustrated left, comprised four main areas: PSoC Core, Digital System, Analog System, System Resources including full-speed port. Configurable global busing allows device resources combined into complete custom system. PSoC CY8C24x94 devices have seven ports that connect global digital analog interconnects, providing access digital blocks analog blocks.
System
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM Interrupt Controller SROM Flash Sleep Watchdog
Core (M8C) ClockSources (Includes ILO)
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Ref.
Analog Block Array
Digital Decimator Clocks MACs Type
Internal Voltage System Resets Ref.
Analog Input Muxing
SYSTEM RESOURCES
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PSoC® Overview
PSoC Core
PSoC Core powerful engine that supports rich feature set. core includes CPU, memory, clocks, configurable GPIO (General Purpose IO). core powerful processor with speeds MHz, providing four MIPS 8-bit Harvard architecture microprocessor. utilizes interrupt controller with vectors, simplify programming real time embedded events. Program execution timed protected using included Sleep Watch Timers (WDT). Memory encompasses Flash program storage, SRAM data storage, EEPROM emulated using Flash. Program Flash utilizes four protection levels blocks bytes, allowing customized software protection. PSoC device incorporates flexible internal clock generators, including (internal main oscillator) accurate over temperature voltage. also doubled digital system. power (internal speed oscillator) provided Sleep timer WDT. clocks, together with programmable clock dividers System Resource), provide flexibility integrate almost timing requirement into PSoC device. systems, will self-tune 0.25% accuracy communication. PSoC GPIOs provide connection CPU, digital analog resources device. Each pin's drive mode selected from eight options, allowing great flexibility external interfacing. Every also capability generate system interrupt high level, level, change from last read.
Digital peripheral configurations include those listed below.
Full-Speed Mbps) PWMs bit) PWMs with Dead band bit) Counters bit) Timers bit) UART with selectable parity master slave slave multi-master Cyclical Redundancy Checker/Generator bit) IrDA Pseudo Random Sequence Generators bit)
digital blocks connected GPIO through series global buses that route signal pin. buses also allow signal multiplexing performing logic operations. This configurability frees your designs from constraints fixed peripheral controller. Digital blocks provided rows four, where number blocks varies PSoC device family. This allows optimum choice system resources your application. Family resources shown table titled PSoC Device Characteristics.
Analog System
Analog System composed configurable blocks, each comprised opamp circuit allowing creation complex analog signal flows. Analog peripherals very flexible customized support specific application requirements. Some more common PSoC analog functions (most available user modules) listed below.
Digital System
Digital System composed digital PSoC blocks. Each block 8-bit resource that used alone combined with other blocks form 32-bit peripherals, which called user module references. Digital System Block Diagram
Port Port Port Port Port Port Port
Analog-to-digital converters with 14-bit resolution, selectable Incremental, Delta Sigma, SAR) Filters pole band-pass, low-pass, notch) Amplifiers with selectable gain 48x) Instrumentation amplifiers with selectable gain 93x) Comparators with selectable thresholds) DACs with 9-bit resolution) Multiplying DACs with 9-bit resolution) High current output drivers (two with drive PSoC Core Resource) 1.3V reference System Resource) DTMF Dialer Modulators Correlators Peak Detectors Many other topologies possible
Digital Clocks FromCore
System
ToAnalog System
DIGITAL SYSTEM
Digital PSoC Block Array
Input Configuration
DBB00 DBB01 DCB02
DCB03
Output Configuration
GIE[7:0] GIO[7:0]
GlobalDigital Interconnect
GOE[7:0] GOO[7:0]
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Analog blocks arranged column three, which includes (Continuous Time) (Switched Capacitor) blocks, shown figure below. Analog System Block Diagram
(Except Port P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn Analog P0[6] P0[4] P0[2] P0[0] P2[6]
Analog Multiplexer System
Analog connect every GPIO ports Pins connected individually combination. also connects analog system analysis with comparators analog-to-digital converters. split into sections simultaneous dual-channel processing. additional analog input multiplexer provides second path bring Port pins analog array. Switch control logic enables selected pins precharge continuously under hardware control. This enables capacitive measurement applications such touch sensing. Other multiplexer applications include:
Track pad, finger sensing. Chip-wide that allows analog input from pins. Crosspoint connection between combinations.
P2[3]
P2[4] P2[2] P2[0]
P2[1]
When designing capacitive sensing applications, refer latest signal-to-noise signal level requirements Application Notes, which found under http://www.cypress.com DESIGN RESOURCES Application Notes. general, unless otherwise noted relevant Application Notes, minimum signal-to-noise ratio (SNR) CapSense applications 5:1.
ACI0[1:0] ACI1[1:0]
Array Input Configuration
Additional System Resources
ACB00 ASC10 ASD20 ACB01 ASD11 ASC21
Block Array
System Resources, provide additional capability useful complete systems. Additional resources include multiplier, decimator, voltage detection, power reset. Brief statements describing merits each resource follow.
AnalogReference
Interface Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap
Full-Speed Mbps) with configurable endpoints bytes RAM. external components required except series resistors. Wider than commercial temperature operation (-10°C +85°C). Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. Additional clocks generated using digital PSoC blocks clock dividers. multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate, assist both general math well digital filters. Decimator provides custom hardware filter digital signal processing apps. including creation Delta Sigma ADCs. module provides communication over wires. Slave, master, multi-master supported. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal 1.3V reference provides absolute reference analog system, including ADCs DACs. Versatile analog multiplexer system.
Interface (Address Bus, Data Bus, Etc.)
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PSoC® Overview
PSoC Device Characteristics
Depending your PSoC device characteristics, digital analog systems have digital blocks analog blocks. following table lists resources available specific PSoC device groups. device covered this data sheet shown highlighted table PSoC Device Characteristics
Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital Digital Rows SRAM Size PSoC Part Number Flash Size
Getting Started
quickest path understanding PSoC silicon reading this data sheet using PSoC Designer Integrated Development Environment (IDE). This data sheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. in-depth information, along with detailed programming information, reference PSoC Mixed-Signal Array Technical Reference Manual. up-to-date Ordering, Packaging, Electrical Specification information, reference latest PSoC device data sheets http://www.cypress.com/psoc. determine which PSoC device meets your requirements, navigate through PSoC Decision Tree Application Note AN2209 http://www.cypress.com select Application Notes under Design Resources.
CY8C29x66 CY8C27x43 CY8C24x94 CY8C24x23A CY8C21x34 CY8C21x23 CY8C20x34
Bytes Bytes Bytes Bytes Bytes
Development Kits
Development Kits available from following distributors: Digi-Key, Avnet, Arrow, Future. Cypress Online Store contains development kits, compilers, accessories PSoC development. Cypress Online Store site http://www.cypress.com, click Online Store shopping cart icon bottom page, click PSoC (Programmable System-on-Chip) view current list available items.
Limited analog functionality. analog blocks CapSense.
Technical Training Modules
Free PSoC technical training modules available users PSoC. Training modules cover designing, debugging, advanced analog CapSense. http:// www.cypress.com/techtrain.
Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant http://www.cypress.com, click Design Support located left side page, select CYPros Consultants.
Technical Support
PSoC application engineers take pride fast accurate response. They reached with 4-hour guaranteed response
Application Notes
long list application notes will assist every aspect your design effort. view PSoC application notes, http://www.cypress.com site select Application Notes under Design Resources list located center page. Application notes listed date default.
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Development Tools
PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-onChip (PSoC) devices. PSoC Designer application runs Windows 4.0, Windows 2000, Windows Millennium (Me), Windows (Reference PSoC Designer Functional Flow diagram below.) PSoC Designer helps customer select operating configuration PSoC, write application code that uses PSoC, debug application. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, CYASM macro assembler CPUs. PSoC Designer also supports high-level language compiler developed specifically devices family. PSoC Designer Subsystems
PSoC Designer
Graphical Designer Interface
Context Sensitive Help
Commands
Results
Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Configuration Sheet
PSoC Designer Core Engine
Manufacturing Information File
Emulation
In-Circuit Emulator
Device Programmer
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PSoC Designer Software Subsystems
Device Editor
Device Editor subsystem allows user select different onboard analog digital components called user modules using PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configurations time. PSoC Designer sets power-on initialization tables selected PSoC block configurations creates source code application framework. framework contains software operate selected components and, project uses more than operating configuration, contains routines switch between different sets PSoC block configurations time. PSoC Designer print configuration sheet given project configuration during application programming conjunction with Device Data Sheet. Once framework generated, user application-specific code flesh framework. It's also possible change selected components regenerate framework.
Debugger
PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing designer test program physical system while providing internal view PSoC device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest.
Online Help System
online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
Hardware Tools
In-Circuit Emulator
Design Browser
Design Browser allows users select import preconfigured designs into user's project. Users easily browse catalog preconfigured designs facilitate time-to-design. Examples provided tools include 300-baud modem, master slave, controller, magnetic card reader.
cost, high functionality (In-Circuit Emulator) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal will operate with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
Application Editor
Application Editor edit your language Assembly language source code. also assemble, compile, link, build. Assembler. macro assembler allows assembly code merged seamlessly with code. link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compiler. language compiler available that supports PSoC family devices. Even have never worked language before, product quickly allows create complete programs PSoC family devices. embedded, optimizing compiler provides features tailored PSoC architecture. comes complete with embedded libraries providing port operations, standard keypad display support, extended math functionality.
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PSoC® Overview
Designing with User Modules
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PSoC Blocks, have ability implement wide variety user-selectable functions. Each block several registers that determine function connectivity other blocks, multiplexers, buses pins. Iterative development cycles permit adapt hardware well software. This substantially lowers risk having select different part meet final design requirements. speed development process, PSoC Designer Integrated Development Environment (IDE) provides library pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting implementing peripheral devices simple, come analog, digital, mixed signal varieties. standard User Module library contains over common peripherals such ADCs, DACs Timers, Counters, UARTs, other not-so common peripherals such DTMF Generators Bi-Quad analog filter sections. Each user module establishes basic register settings that implement selected function. also provides parameters that allow tailor precise configuration your particular application. example, Pulse Width Modulator User Module configures more digital PSoC blocks, each bits resolution. user module parameters permit establish pulse width duty cycle. User modules also provide tested software your development time. user module application programming interface (API) provides highlevel functions control respond hardware events run-time. also provides optional interrupt service routines that adapt needed. functions documented user module data sheets that viewed directly PSoC Designer IDE. These data sheets explain internal operation user module provide performance specifications. Each data sheet describes each user module parameter documents setting each register controlled user module. development process starts when open project bring Device Editor, graphical user interface (GUI) configuring hardware. pick user modules need your project them onto PSoC blocks with point-and-click simplicity. Next, build signal chains interconnecting user modules each other pins. this stage, also configure clock source connections enter parameter values directly selecting values from drop-down menus. When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides high-level user module functions.
User Module/Source Code Development Flows
Device Editor
User Module Selection Placement Parameter -ization Source Code Generator
Generate Application
Application Editor
Project Manager Source Code Editor Build Manager
Build
Debugger
Interface Storage Inspector Event Breakpoint Manager
next step write your main program, sub-routines using PSoC Designer's Application Editor subsystem. Application Editor includes Project Manager that allows open project source code files (including generated code files) from hierarchal view. source code editor provides syntax coloring advanced edit features both assembly language. File search capabilities include simple string searches recursive "grep-style" patterns. single mouse click invokes Build Manager. employs professional-strength "makefile" system automatically analyze file dependencies compiler assembler necessary. Project-level options control optimization strategies used compiler linker. Syntax errors displayed console window. Double clicking error message takes directly offending line source code. When correct, linker builds file image suitable programming. last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image In-Circuit Emulator (ICE) where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
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Document Conventions
Acronyms Used
following table lists acronyms that used this document.
Acronym Description
Table Contents
depth discussion more information your PSoC device, obtain PSoC Mixed-Signal Array Technical Reference Manual. This document encompasses organized into following chapters sections.
Information
EEPROM GPIO IPOR PPOR PSoC® SRAM
alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose graphical user interface human body model in-circuit emulator internal speed oscillator internal main oscillator input/output imprecise power reset least-significant voltage detect most-significant program counter phase-locked loop power reset precision power reset Programmable System-on-Chippulse width modulator switched capacitor static random access memory
56-Pin Part Pinout 56-Pin Part Pinout (with XRES) 68-Pin Part Pinout 68-Pin Part Pinout (On-Chip Debug) 100-Ball VFBGA Part Pinout 100-Ball VFBGA Part Pinout (On-Chip Debug) 100-Pin Part Pinout (On-Chip Debug)
Register Reference Register Conventions 2.1.1 Abbreviations Used Register Mapping Tables Electrical Specifications Absolute Maximum Ratings Operating Temperature Electrical Characteristics 3.3.1 Chip-Level Specifications 3.3.2 General Purpose Specifications 3.3.3 Full-Speed Specifications 3.3.4 Operational Amplifier Specifications 3.3.5 Power Comparator Specifications 3.3.6 Analog Output Buffer Specifications 3.3.7 Analog Reference Specifications 3.3.8 Analog PSoC Block Specifications 3.3.9 Specifications 3.3.10 Programming Specifications Electrical Characteristics 3.4.1 Chip-Level Specifications 3.4.2 General Purpose Specifications 3.4.3 Full-Speed Specifications 3.4.4 Operational Amplifier Specifications 3.4.5 Power Comparator Specifications 3.4.6 Digital Block Specifications 3.4.7 External Clock Specifications 3.4.8 Analog Output Buffer Specifications 3.4.9 Programming Specifications 3.4.10 Specifications Packaging Information Packaging Dimensions Thermal Impedance Solder Reflow Peak Temperature Development Tool Selection Software 5.1.1 PSoC Designer 5.1.2 PSoC Express 5.1.3 PSoC Programmer 5.1.4 CY3202-C iMAGEcraft Compiler Development Kits 5.2.1 CY3215-DK Basic Development 5.2.2 CY3210-ExpressDK Development Evaluation Tools 5.3.1 CY3210-MiniProg1 5.3.2 CY3210-PSoCEval1 5.3.3 CY3214-PSoCEvalUSB Device Programmers 5.4.1 CY3216 Modular Programmer 5.4.2 CY3207ISSP In-System Serial Programmer (ISSP) Accessories (Emulation Programming) 3rd-Party Tools Build PSoC Emulator into Your Board Ordering Information Ordering Code Definitions Sales Company Information Revision History Copyrights Code Protection
Units Measure
units measure table located Electrical Specifications section. Table page lists abbreviations used measure PSoC devices.
Numeric Naming
Hexidecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexidecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (e.g., 01010100b' `01000011b'). Numbers indicated decimal.
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Information
This chapter describes, lists, illustrates CY8C24x94 PSoC device family pins pinout configuration. CY8C24x94 PSoC devices available following packages, which shown following pages. Every port (labeled with "P") capable Digital However, Vss, Vdd, XRES capable Digital
56-Pin Part Pinout
Name Description
Table 1-1. 56-Pin Part Pinout (QFN**) LEGEND details footnotes Table page
Type Digital Analog Power Power
CY8C24794 56-Pin PSoC Device
P2[5],M P2[7],M P0[1], P0[3], P0[5], P0[7], P0[6], P0[4], P0[2], P0[0], P2[6],M P2[4],M P2[3] P2[1] M,P4[7] M,P4[5] M,P4[3] M,P4[1] M,P3[7] M,P3[5] M,P3[3] M,P3[1] M,P5[7] M,P5[5] M,P5[3] M,P5[1]
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] DVdd P7[7] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4]
Direct switched capacitor block input. Direct switched capacitor block input.
Serial Clock (SCL). Serial Data (SDA). Serial Clock (SCL), ISSP SCLK*. Ground connection.
Supply voltage.
Serial Data (SDA), ISSP SDATA*.
Type Digital Analog Power Power Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input.
Name
P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
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SCL, P1[7] SDA, P1[5] M,P1[3] SCL, P1[1] DVdd P7[7] P7[0] SDA, P1[0] M,P1[2] M,P1[4] M,P1[6]
(Top View
P2[2], P2[0], P4[6],M P4[4],M P4[2],M P4[0],M P3[6],M P3[4],M P3[2],M P3[0],M P5[6],M P5[4],M P5[2],M P5[0],M
Description
External Voltage Reference (VREF) input. Analog column input. Analog column input. Analog column input VREF. Analog column input. Supply voltage. Ground connection. Analog column input,. Analog column input column output. Analog column input column output. Analog column input.
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56-Pin Part Pinout (with XRES)
Name Description
Table 1-2. 56-Pin Part Pinout (QFN**)
Type Digital Analog Power Power
CY8C24894 56-Pin PSoC Device
P0[5], P0[7], P0[6], P0[4], P0[2], P0[0], P2[6], P2[4],
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] DVdd P7[7] P7[0] P1[0] P1[2] P1[4] P1[6]
Direct switched capacitor block input. Direct switched capacitor block input.
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7]
P2[5], P2[7], P0[1], P0[3],
(Top View)
Serial Clock (SCL). Serial Data (SDA). Serial Clock (SCL), ISSP SCLK*. Ground connection.
P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1]
P2[2], P2[0], P4[6], P4[4], P4[2], P4[0], XRES
P3[4], P3[2], P3[0], P5[6], P5[4], P5[2], P5[0],
P1[3] SCL, P1[1] DVdd P7[7]
SCL, P1[7] SDA, P1[5]
Serial Data (SDA), ISSP SDATA*.
Input
P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4]
Type Digital Analog Active high external reset with internal Power pull down. Power Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input.
Name
Description
P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
External Voltage Reference (VREF) input. Analog column input. Analog column input. Analog column input VREF. Analog column input. Supply voltage. Ground connection. Analog column input,. Analog column input column output. Analog column input column output. Analog column input.
LEGEND Analog, Input, Output, Analog Input.
These ISSP pins, which High POR. PSoC Mixed-Signal Array Technical Reference Manual details. center package should connected ground (Vss) best mechanical, thermal, electrical performance. connected ground, should electrically floated connected other signal.
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SDA,
P7[0] P1[0] P1[2] P1[4] P1[6]
Supply voltage.
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68-Pin Part Pinout
68-pin part table drawing below CY8C24994 PSoC device. Table 1-3. 68-Pin Part Pinout (QFN**)
Type Digital Analog Power Power Power Name Description
CY8C24994 68-Pin PSoC Device
Ext. VREF Ext. AGND
P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] XRES
connection. connection. Ground connection.
P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] SCL, SDA, P5[3] P5[1] P1[7] P1[5]
P0[7], P0[6], P0[4], P0[2], P0[0], P2[6], P2[4], P2[2],
P2[1], P2[3], P2[5], P2[7], P0[1], P0[3], P0[5],
Serial Clock (SCL). Serial Data (SDA). Serial Clock (SCL) ISSP SCLK*. Ground connection.
(Top View)
P2[0], P4[6], P4[4], P4[2], P4[0], XRES P3[6], P3[4], P3[2], P3[0],
P5[6], P5[4], P5[2], P5[0], P1[6],
P1[3] SCL, P1[1] DVdd P7[7] P7[6] P7[5] P7[4]
Supply voltage.
Type Digital Analog Serial Data (SDA), ISSP SDATA*. Optional External Clock Input (EXT53 CLK). Power Power IO,M
Name
P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1]
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. External Voltage Reference (VREF) input. Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage. Ground connection. Analog column input, integration input Analog column input column output, integration input Analog column input column output. Analog column input.
Input
connection. connection. Active high reset with internal pull down.
IO,M
P4[0] P4[2] P4[4]
Direct switched capacitor block input. Direct switched capacitor block input.
LEGENDA Analog, Input, Output, Connection, Analog Input. These ISSP pins, which High POR. PSoC Mixed-Signal Array Technical Reference Manual details.
center package should connected ground (Vss) best mechanical, thermal, electrical performance. connected ground, should electrically floated connected other signal.
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Description
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68-Pin Part Pinout (On-Chip Debug)
68-pin part table drawing below CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part only used in-circuit debugging. available production. Table 1-4. 68-Pin Part Pinout (QFN**)
Type Digital Analog Power Power Power Name Description
CY8C24094 68-Pin PSoC Device
P2[6], Ext. VREF P2[4], Ext. AGND P2[2],
P4[7] P4[5] P4[3] P4[1] OCDE OCDO P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] HCLK CCLK XRES
P2[3], P2[5], P2[7], P0[1], P0[3], P0[5],
P2[1],
Serial Clock (SCL). Serial Data (SDA). Serial Clock (SCL), ISSP SCLK*. Ground connection.
P4[7] P4[5] P4[3] P4[1] OCDE OCDO P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] SCL, P1[7] SDA, P1[5]
even data data output. Ground connection.
P0[7], P0[6], P0[4], P0[2], P0[0],
P1[3] SCL, P1[1] DVdd
Supply voltage.
Type Digital Analog Serial Data (SDA), ISSP SDATA*. Optional External Clock Input (EXT53 CLK). Power Power IO,M
Name
Description
P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1]
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. External Voltage Reference (VREF) input. Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage. Ground connection. Analog column input, integration input Analog column input column output, integration input Analog column input column output. Analog column input.
Input
high-speed clock output. clock output. Active high reset with internal pull down.
IO,M
P4[0] P4[2] P4[4]
Direct switched capacitor block input. Direct switched capacitor block input.
LEGENDA Analog, Input, Output, Analog Input, On-Chip Debugger. These ISSP pins, which High POR. PSoC Mixed-Signal Array Technical Reference Manual details.
center package should connected ground (Vss) best mechanical, thermal, electrical performance. connected ground, should electrically floated connected other signal.
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SDA, P1[0] P1[2] P1[4]
P7[7] P7[6] P7[5] P7[4]
P7[3] P7[2] P7[1] P7[0]
(Top View)
P2[0], P4[6], P4[4], P4[2], P4[0], XRES CCLK HCLK P3[6], P3[4], P3[2], P3[0], P5[6], P5[4], P5[2], P5[0], P1[6],
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Information
100-Ball VFBGA Part Pinout
100-ball VFBGA part CY8C24994 PSoC device. Table 1-5. 100-Ball Part Pinout (VFBGA)
Analog Name Description Analog Digital Digital Name Description
Power Power Power Power Power P2[1] P0[1] P0[7] Power P0[2] P2[2] Power Power P4[1] P4[7] P2[7] IO,M P0[5] P0[6] P0[0] P2[0] P4[2] P3[7] P4[5] P2[5] IO,M P0[3] P0[4] P2[6] P4[6] P4[0] P4[3] P2[3] Power Power P2[4] P4[4] P3[6]
Power Power
Analog column input column output. Analog column input. Analog column input. Direct switched capacitor block input. connection. connection. Analog column input column output. Analog column input. External Voltage Reference (VREF) input. connection. connection. connection. Direct switched capacitor block input. Ground connection. Ground connection. External Analog Ground (AGND) input. connection.
Ground connection. Ground connection. connection. connection. connection. Supply voltage. connection. connection. Ground connection. Ground connection. Ground connection. Ground connection. Direct switched capacitor block input. Analog column input. Analog column input. Supply voltage. Analog column input. Direct switched capacitor block input. Ground connection. Ground connection. connection.
Power Power
Power Power Power Power Power Power Power
Power Power Power
P5[7] P3[5] P5[1] P5[0] P3[0] XRES P7[1] P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2] P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3] DVdd P7[7] P7[0] P5[2] P7[6] P7[5] P7[4]
connection.
Ground connection. Ground connection.
Active high reset with internal pull down. connection.
Serial Clock (SCL). Serial Clock (SCL), ISSP SCLK*. Serial Data (SDA), ISSP SDATA*.
connection.
Serial Data (SDA).
Ground connection. Ground connection.
Supply voltage.
Ground connection. Ground connection. Ground connection. Ground connection. connection. connection. Supply voltage.
Ground connection. Ground connection.
LEGEND Analog, Input, Output, Analog Input, Connection. This ISSP pin, which High POR. PSoC Mixed-Signal Array Technical Reference Manual details.
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CY8C24994
P2[1]
P0[1]
P0[7]
P0[2]
P2[2]
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
P4[3]
P2[3]
P2[4]
P4[4]
P3[6]
P5[7]
P3[5]
P5[1]
P5[0]
P3[0]
XRES
P7[1]
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
P7[7]
P7[0]
P5[2]
P7[6]
P7[5]
P7[4]
(Top View)
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100-Ball VFBGA Part Pinout (On-Chip Debug)
100-pin VFBGA part table drawing below CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part only used in-circuit debugging. available production. Table 1-6. 100-Ball Part Pinout (VFBGA)
Analog Name Description Analog Digital Digital Name Description
Power Power Power Power Power P2[1] P0[1] P0[7] Power P0[2] P2[2] Power Power P4[1] P4[7] P2[7] IO,M P0[5] P0[6] P0[0] P2[0] P4[2] P3[7] P4[5] P2[5] IO,M P0[3] P0[4] P2[6] P4[6] P4[0] CCLK P4[3] P2[3] Power Power P2[4] P4[4] P3[6] HCLK
Power Power
Ground connection. Ground connection. connection. connection. connection. Supply voltage. connection. connection. Ground connection. Ground connection. Ground connection. Ground connection. Direct switched capacitor block input. Analog column input. Analog column input. Supply voltage. Analog column input. Direct switched capacitor block input. Ground connection. Ground connection. connection.
Analog column input column output. Analog column input. Analog column input. Direct switched capacitor block input. connection. connection. Analog column input column output. Analog column input. External Voltage Reference (VREF) input. clock output. connection. connection. Direct switched capacitor block input. Ground connection. Ground connection. External Analog Ground (AGND) input. high-speed clock output.
Power Power
Power Power Power Power Power Power Power
Power Power Power
OCDE P5[7] P3[5] P5[1] P5[0] P3[0] XRES P7[1] OCDO P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2] P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3] DVdd P7[7] P7[0] P5[2] P7[6] P7[5] P7[4]
even data
Ground connection. Ground connection.
Active high reset with internal pull down. data output.
Serial Clock (SCL). Serial Clock (SCL), ISSP SCLK*. Serial Data (SDA), ISSP SDATA*.
connection.
Serial Data (SDA).
Ground connection. Ground connection.
Supply voltage.
Ground connection. Ground connection. Ground connection. Ground connection. connection. connection. Supply voltage.
Ground connection. Ground connection.
LEGEND Analog, Input, Output, Analog Input, Connection, On-Chip Debugger. This ISSP pin, which High POR. PSoC Mixed-Signal Array Technical Reference Manual details.
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CY8C24094
P2[1]
P0[1]
P0[7]
P0[2]
P2[2]
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
CClk
P4[3]
P2[3]
P2[4]
P4[4]
P3[6]
HClk
ocde
P5[7]
P3[5]
P5[1]
P5[0]
P3[0]
XRES
P7[1]
ocdo
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
P7[7]
P7[0]
P5[2]
P7[6]
P7[5]
P7[4]
(Top View)
Production
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100-Pin Part Pinout (On-Chip Debug)
100-pin TQFP part CY8C24094 On-Chip Debug (OCD) PSoC device. Note This part only used in-circuit debugging. available production. Table 1-7. 100-Pin Part Pinout (TQFP)
Analog Name Description Analog Digital Digital Name Description
P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO Power P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] DVdd P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4]
connection. connection. Analog column input.
Direct switched capacitor block input. Direct switched capacitor block input.
even data data output. connection. Ground connection.
Serial Clock (SCL). connection. connection. connection. Serial Data (SDA) Crystal (XTALin), Serial Clock (SCL), ISSP SCLK*. connection. Ground connection.
Input Power
P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] HCLK CCLK XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4]
high-speed clock output. clock output. Active high reset with internal pull down.
Ground connection.
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. connection. External Voltage Reference (VREF) input. connection. Analog column input. connection. connection. Analog column input column output. connection. Analog column input column output. connection. Analog column input. Supply voltage. connection. Ground connection. connection. connection. connection. connection. connection. connection. connection. connection. connection. connection. Analog column input. connection. Analog column input column output. connection. Analog column input column output. connection.
Power Power
Supply voltage.
connection. connection. connection. connection. Crystal (XTALout), Serial Data (SDA), ISSP SDATA*. Optional External Clock Input (EXTCLK).
P0[6] Power Power P0[7] P0[5] P0[3]
LEGEND Analog, Input, Output, Connection, Analog Input, On-Chip Debugger. These ISSP pins, which High POR. PSoC Mixed-Signal Array Technical Reference Manual details.
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CY8C24094
P0[3], P0[5],
P0[7],
P0[6], P0[4],
P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] SCL, P1[7]
M,P1[2] M,P1[4]
P0[2],
P0[0], P2[6], External VREF P2[4], External AGND P2[2], P2[0], P4[6], P4[4], P4[2], P4[0], XRES CCLK HCLK P3[6], P3[4], P3[2], P3[0], P5[6], P5[4], P5[2], P5[0], P1[6],
TQFP
P7[7] P7[6] P7[5] P7[4] P7[3] P7[2]
February 2007
SDA, P1[5] M,P1[3] SCL, P1[1] DVdd
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Register Reference
This chapter lists registers CY8C24x94 PSoC device family. detailed register information, reference PSoC Mixed-Signal Array Technical Reference Manual.
2.1.1
Register Conventions
Abbreviations Used
Register Mapping Tables
register conventions specific this section listed following table.
Convention Description
PSoC device total register address space bytes. register space referred space divided into banks. Flag register (CPU_F) determines which bank user currently When user Bank Note following register mapping tables, blank fields Reserved should accessed.
Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Access specific
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Register Reference
Register Bank Table: User Space
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name
PMA0_DR PMA1_DR PMA2_DR PMA3_DR PMA4_DR PMA5_DR PMA6_DR PMA7_DR USB_SOF0 USB_SOF1 USB_CR0 USBIO_CR0 USBIO_CR1 EP1_CNT1 EP1_CNT EP2_CNT1 EP2_CNT EP3_CNT1 EP3_CNT EP4_CNT1 EP4_CNT EP0_CR EP0_CNT EP0_DR0 EP0_DR1 EP0_DR2 EP0_DR3 EP0_DR4 PRT7DR EP0_DR5 PRT7IE EP0_DR6 PRT7GS EP0_DR7 PRT7DM2 DBB00DR0 AMX_IN DBB00DR1 AMUXCFG DBB00DR2 DBB00CR0 ARF_CR DBB01DR0 CMP_CR0 DBB01DR1 ASY_CR DBB01DR2 CMP_CR1 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 TMP_DR0 DCB03DR1 TMP_DR1 DCB03DR2 TMP_DR2 DCB03CR0 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 Blank fields Reserved should accessed. PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2
ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access specific. ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3
CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2
CPU_F
DAC_D CPU_SCR1 CPU_SCR0
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Register Reference
Register Bank Table: Configuration Space
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name
PMA0_WA PMA1_WA PMA2_WA PMA3_WA PMA4_WA PMA5_WA PMA6_WA PMA7_WA PMA0_RA PMA1_RA PMA2_RA PMA3_RA PMA4_RA PMA5_RA PMA6_RA PMA7_RA PRT7DM0 PRT7DM1 PRT7IC0 PRT7IC1 DBB00FN CLK_CR0 DBB00IN CLK_CR1 DBB00OU ABF_CR0 AMD_CR0 DBB01FN CMP_GO_EN DBB01IN CMP_GO_EN1 DBB01OU AMD_CR1 ALT_CR0 DCB02FN DCB02IN DCB02OU DCB03FN TMP_DR0 DCB03IN TMP_DR1 DCB03OU TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 Blank fields Reserved should accessed. PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1
ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access specific. ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3
USBIO_CR2 USB_CR1
EP1_CR0 EP2_CR0 EP3_CR0 EP4_CR0
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 CPU_F DAC_CR CPU_SCR1 CPU_SCR0
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Electrical Specifications
This chapter presents electrical specifications CY8C24x94 PSoC device family. most date electrical specifications, confirm that have most recent data sheet going http://www.cypress.com/psoc. Specifications valid -40oC 85oC 100oC, except where noted. Specifications devices running greater than valid -40oC 70oC 82oC. Figure 3-1. Voltage versus Frequency
5.25
4.75 Voltage
rati
3.00
CPUFrequency
following table lists units measure that used this chapter. Table 3-1: Units Measure
Symbol
Unit Measure
Symbol
Unit Measure
degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts million picosecond samples second sigma: standard deviation volts
Kbit
µVrms
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Electrical Specifications
Symbol
Absolute Maximum Ratings
Description Units
Table 3-2. Absolute Maximum Ratings
Notes
TSTG
Storage Temperature
+100
Higher storage temperatures will reduce data retention time. Recommended storage temperature +25oC 25oC. Extended duration storage temperatures above 65oC will degrade reliability.
VIO2 IMIO IMAIO
Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tri-state Maximum Current into Port Maximum Current into Port Configured Analog Driver Electro Static Discharge Voltage Latch-up Current
-0.5 2000
+6.0
Human Body Model ESD.
Symbol
Operating Temperature
Description Units
Table 3-3. Operating Temperature
Notes
TAUSB
Ambient Temperature Ambient Temperature using Junction Temperature
+100
temperature rise from ambient junction package specific. "Thermal Impedance" page user must limit power consumption comply with this requirement.
3.3.1
Electrical Characteristics
Chip-Level Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-4. Chip-Level Specifications
Symbol Description Units Notes
IDD5
Supply Voltage Supply Current, (5V)
5.25
specifications, Table page Conditions 5.0V, MHz, SYSCLK doubler disabled, MHz, 93.75 kHz, 93.75 kHz, analog power off. Conditions 3.3V, MHz, SYSCLK doubler disabled, MHz, 93.75 kHz, 0.367 kHz, analog power off. Conditions with internal slow speed oscillator, 3.3V, analog power off. Conditions with internal slow speed oscillator, 3.3V, analog power off.
IDD3
Supply Current, (3.3V)
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT.a Sleep (Mode) Current with POR, LVD, Sleep Timer, high temperature.a
ISBH
Standby current includes functions (POR, LVD, WDT, Sleep Time) needed reliable system operation. This should compared with devices that have similar functions enabled.
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3.3.2
General Purpose Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-5. GPIO Specifications
Symbol Description Units Notes
Pull-Up Resistor Pull-Down Resistor High Output Level
4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). maximum combined budget. 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). maximum combined budget. 5.25. 5.25. Gross tested Package dependent. Temp 25oC. Package dependent. Temp 25oC.
Output Level
0.75
COUT
Input Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
3.3.3
Full-Speed Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -10°C 85°C, 3.0V 3.6V -10°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-6. Full-Speed Mbps) Specifications
Symbol Interface Description Units Notes
REXT VUOH VUOHI VUOL VCRS
Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance High-Z State Data Line Leakage External Series Resistor Static Output High, Driven Static Output High, Idle Static Output Driver Output Impedance D+/D- Crossover Voltage
(D+) (D-)
3.3V. series with each pin. Ground. Internal pull-up enabled. Ground. Internal pull-up enabled. Ground. Internal pull-up enabled. Including REXT Resistor.
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3.3.4
Operational Amplifier Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Operational Amplifier component both Analog Continuous Time PSoC blocks Analog Switched Capacitor PSoC blocks. guaranteed specifications measured Analog Continuous Time PSoC block. Table 3-7. Operational Amplifier Specifications
Symbol Description Units Notes
VOSOA
Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High 35.0
µV/oC
TCVOSOA IEBOA CINOA VCMOA
Average Input Offset Voltage Drift Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Common Mode Voltage Range (high power high opamp bias)
Gross tested Package dependent. Temp 25oC. common-mode input voltage range measured through analog output buffer. specification includes limitations imposed characteristics analog output buffer.
GOLOA
Open Loop Gain Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High
VOHIGHOA
High Output Voltage Swing (internal signals) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High 1200 2400 4600 1000 1600 3200 6400
VOLOWOA
Output Voltage Swing (internal signals) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High
ISOA
Supply Current (including associated AGND buffer) Power Low, Opamp Bias Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High
PSRROA
Supply Voltage Rejection Ratio
(Vdd 2.25) (Vdd 1.25V) Vdd.
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Table 3-8. 3.3V Operational Amplifier Specifications
Symbol Description Units Notes
VOSOA
Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High High Power Volts Only 1.65 1.32 35.0
µV/oC
TCVOSOA IEBOA CINOA VCMOA
Average Input Offset Voltage Drift Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range
Gross tested Package dependent. Temp 25oC. common-mode input voltage range measured through analog output buffer. specification includes limitations imposed characteristics analog output buffer.
GOLOA
Open Loop Gain Power Low, Opamp Bias Power Medium, Opamp Bias Power High, Opamp Bias
VOHIGHOA
High Output Voltage Swing (internal signals) Power Low, Opamp Bias Power Medium, Opamp Bias Power High only 1200 2400 4600 1000 1600 3200 6400
VOLOWOA
Output Voltage Swing (internal signals) Power Low, Opamp Bias Power Medium, Opamp Bias Power High, Opamp Bias
ISOA
Supply Current (including associated AGND buffer) Power Low, Opamp Bias Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High
PSRROA
Supply Voltage Rejection Ratio
(Vdd 2.25) (Vdd 1.25V) Vdd.
3.3.5
Power Comparator Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table 3-9. Power Comparator Specifications
Symbol Description Units Notes
VREFLPC ISLPC VOSLPC
power comparator (LPC) reference voltage range supply current voltage offset
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3.3.6
Analog Output Buffer Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-10. Analog Output Buffer Specifications
Symbol Description Units Notes
VOSOB TCVOSOB VCMOB ROUTOB
Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High
µV/°C
VOHIGHOB
High Output Voltage Swing (Load ohms Vdd/2) Power Power High
VOLOWOB
Output Voltage Swing (Load ohms Vdd/2) Power Power High
ISOB
Supply Current Including Bias Cell Load) Power Power High (0.5 1.3) VOUT (Vdd 2.3).
PSRROB
Supply Voltage Rejection Ratio
Table 3-11. 3.3V Analog Output Buffer Specifications
Symbol Description Units Notes
VOSOB TCVOSOB VCMOB ROUTOB
Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High
µV/°C
VOHIGHOB
High Output Voltage Swing (Load ohms Vdd/2) Power Power High
VOLOWOB
Output Voltage Swing (Load ohms Vdd/2) Power Power High
ISOB
Supply Current Including Bias Cell Load) Power Power High (0.5 1.0) VOUT (0.5 0.9).
PSRROB
Supply Voltage Rejection Ratio
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3.3.7
Analog Reference Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. guaranteed specifications measured through Analog Continuous Time PSoC blocks. power levels AGND refer power Analog Continuous Time PSoC block. power levels RefHi RefLo refer Analog Reference Control register. limits stated AGND include offset error AGND buffer local Analog Continuous Time PSoC block. Reference control power high. Table 3-12. Analog Reference Specifications
Symbol Description Units
Bandgap Voltage Reference AGND Vdd/2a AGND BandGap
1.28 Vdd/2 0.04 0.048
1.30 Vdd/2 0.01 0.030 P2[4] 0.008 0.010 0.000
1.32 Vdd/2 0.007 0.024 P2[4] 0.011 0.016 0.018 0.034
AGND P2[4] (P2[4] AGND BandGapa
Vdd/2)a
P2[4] 0.011 0.009
AGND BandGap
0.022 -0.034
AGND Block Block Variation (AGND Vdd/2) RefHi Vdd/2 BandGap RefHi BandGap RefHi BandGap P2[6] (P2[6] 1.3V) RefHi P2[4] BandGap (P2[4] Vdd/2)
Vdd/2 0.10
0.06 P2[6] 0.113 P2[4] 0.130 P2[4] P2[6] 0.133 0.112
Vdd/2
P2[6] 0.018 P2[4] 0.016 P2[4] P2[6] 0.016
Vdd/2 0.10
0.06 P2[6] 0.077 P2[4] 0.098 P2[4] P2[6]+ 0.100 0.076
RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 1.3V) RefHi BandGap RefLo Vdd/2 BandGap RefLo BandGap RefLo BandGap P2[6] (P2[6] 1.3V) RefLo P2[4] BandGap (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 1.3V)
Vdd/2 0.04
0.06 P2[6] 0.084 P2[4] 0.056 P2[4] P2[6] 0.057
Vdd/2 0.024
P2[6] 0.025 P2[4] 0.026 P2[4] P2[6] 0.026
Vdd/2 0.04
0.06 P2[6] 0.134 P2[4] 0.107 P2[4] P2[6] 0.110
AGND tolerance includes offsets local buffer PSoC block. Bandgap voltage 1.3V 0.02V.
Table 3-13. 3.3V Analog Reference Specifications
Symbol Description Units
Bandgap Voltage Reference AGND Vdd/2a AGND BandGapa AGND P2[4] (P2[4] Vdd/2) AGND BandGapa AGND BandGapa AGND Column Column Variation (AGND Vdd/2) RefHi Vdd/2 BandGap RefHi BandGap RefHi BandGap P2[6] (P2[6] 0.5V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 0.5V) RefHi BandGap RefLo Vdd/2 BandGap RefLo BandGap RefLo BandGap P2[6] (P2[6] 0.5V) RefLo P2[4] BandGap (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 0.5V)
1.28 Vdd/2 0.03 Allowed P2[4] 0.008 0.009 0.027 -0.034 Allowed Allowed Allowed Allowed P2[4] P2[6] 0.075 Allowed Allowed Allowed Allowed Allowed P2[4] P2[6] 0.048
1.30 Vdd/2 0.01
1.32 Vdd/2 0.005
P2[4] 0.001 0.005 0.010 0.000
P2[4] 0.009 0.015 0.018 0.034
P2[4] P2[6] 0.009
P2[4] P2[6] 0.057
P2[4]- P2[6] 0.022
P2[4] P2[6] 0.092
AGND tolerance includes offsets local buffer PSoC block. Bandgap voltage 1.3V 0.02V.
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3.3.8
Analog PSoC Block Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-14. Analog PSoC Block Specifications
Symbol Description Units Notes
Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switched Capacitor)
12.2
3.3.9
Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Note bits PORLEV table below refer bits VLT_CR register. PSoC Mixed-Signal Array Technical Reference Manual more information VLT_CR register. Table 3-15. Specifications
Symbol Description Units Notes
Value PPOR Trip (positive ramp) VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value PPOR Trip (negative ramp) PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] PPOR Hysteresis PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98a 3.08 3.20 4.08 4.57 4.74b 4.82 4.91 2.82 4.39 4.55 2.91 4.39 4.55
Always greater than above PPOR (PORLEV falling supply. Always greater than above PPOR (PORLEV falling supply.
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3.3.10
Programming Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-16. Programming Specifications
Symbol Description Units Notes
IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR
Supply Current During Programming Verify Input Voltage During Programming Verify Input High Voltage During Programming Verify Input Current when Applying Vilp P1[0] P1[1] During Programming Verify Input Current when Applying Vihp P1[0] P1[1] During Programming Verify Output Voltage During Programming Verify Output High Voltage During Programming Verify Flash Endurance (per block) Flash Endurance (total) Flash Data Retention
50,000 1,800,000
0.75
Years Erase/write cycles block. Erase/write cycles. Driving internal pull-down resistor. Driving internal pull-down resistor.
maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles). full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information.
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3.4.1
Electrical Characteristics
Chip-Level Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-17. Chip-Level Specifications
Symbol Description Units Notes
FIMO245V FIMO243V FIMOUSB5V FIMOUSB3V FCPU1 FCPU2 FBLK5 FBLK3 F32K1 Jitter32k Step24M Fout48M Jitter24M1 FMAX TRAMP
Internal Main Oscillator Frequency (5V) Internal Main Oscillator Frequency (3.3V) Internal Main Oscillator Frequency with (5V) Frequency locking enabled traffic present. Internal Main Oscillator Frequency with (3.3V) Frequency locking enabled traffic present. Frequency Nominal) Frequency (3.3V Nominal) Digital PSoC Block Frequency Nominal) Digital PSoC Block Frequency (3.3V Nominal) Internal Speed Oscillator Frequency Period Jitter Trim Step Size Output Frequency Period Jitter (IMO) Peak-to-Peak Maximum frequency signal input output. Supply Ramp Time
23.04 22.08 23.94 23.94 0.93 0.93 46.08
48.0
24.96
Trimmed operation using factory trim values. Trimmed 3.3V operation using factory trim values. -10°C 85°C 4.35 5.15 -0°C 70°C 3.15 3.45
25.92b,c 24.06b 24.06b
24.96a,b 12.96
49.92a,b,d 25.92
Refer Digital Block Specifications.
49.92a,c
Trimmed. Utilizing factory trim values.
12.96
4.75V 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim range. 3.0V 3.6V. Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V. individual user module data sheets information maximum frequencies user modules.
Figure 3-2. Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
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3.4.2
General Purpose Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-18. GPIO Specifications
Symbol Description Units Notes
FGPIO TRiseF TFallF TRiseS TFallS
GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload
Normal Strong Mode 5.25V, 5.25V, 5.25V, 5.25V,
Figure 3-3. GPIO Timing Diagram
GPIO
TFallF
3.4.3
Full-Speed Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -10°C 85°C, 3.0V 3.6V -10°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-19. Full-Speed Mbps) Specifications
Symbol Description Units Notes
TRFS TFSS TRFMFS
Transition Rise Time Transition Fall Time Rise/Fall Time Matching: (TR/TF)
0.25%
load. load. load.
TDRATEFS Full-Speed Data Rate
0.25% Mbps
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3.4.4
Operational Amplifier Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Settling times, slew rates, gain bandwidth based Analog Continuous Time PSoC block. Power High Opamp Bias High supported 3.3V. Table 3-20. Operational Amplifier Specifications
Symbol Description Units Notes
TROA
Rising Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High 0.72 0.62
TSOA
Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High 0.15 0.01 0.75 0.92 0.72
SRROA
Rising Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High V/µs V/µs V/µs V/µs V/µs V/µs nV/rt-Hz
SRFOA
Falling Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High
BWOA
Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High
ENOA
Noise (Power Medium, Opamp Bias High)
Table 3-21. 3.3V Operational Amplifier Specifications
Symbol Description Units Notes
TROA
Rising Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High 3.92 0.72
TSOA
Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High 0.31 0.24 0.67 5.41 0.72
SRROA
Rising Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High V/µs V/µs V/µs V/µs nV/rt-Hz
SRFOA
Falling Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High
BWOA
Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High
ENOA
Noise (Power Medium, Opamp Bias High)
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When bypassed capacitor P2[4], noise analog ground signal distributed each block reduced factor dB). This frequencies above corner frequency defined on-chip 8.1k resistance external capacitor. Figure 3-4. Typical AGND Noise with P2[4] Bypass
dBV/rtHz 10000
0.01
1000
0.001
0.01
Freq (kHz)
frequencies, opamp noise proportional 1/f, power independent, determined device geometry. high frequencies, increased power level reduces noise spectrum level. Figure 3-5. Typical Opamp Noise
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
0.001
0.01
Freq (kHz)
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3.4.5
Power Comparator Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table 3-22. Power Comparator Specifications
Symbol Description Units Notes overdrive comparator reference within VREFLPC.
TRLPC
response time
3.4.6
Digital Block Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-23. Digital Block Specifications
Function Description Units Notes
Timer
Capture Pulse Width Maximum Frequency, Capture Maximum Frequency, With Capture
49.92 25.92 49.92 25.92
4.75V 5.25V. 4.75V 5.25V.
Counter
Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input
Dead Band
Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency
49.92 49.92 24.6 24.6 24.6
Maximum data rate 3.08 over clocking. Maximum data rate 3.08 over clocking. Maximum data rate over clocking. 4.75V 5.25V. 4.75V 5.25V.
CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width Negated Between Transmissions Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency
minimum input pulse width based input synchronizers running nominal period).
3.4.7
External Clock Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-24. External Clock Specifications
Symbol Description Units Notes
FOSCEXT
Frequency Applications Duty Cycle Power Switch
23.94
24.06
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3.4.8
Analog Output Buffer Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-25. Analog Output Buffer Specifications
Symbol Description Units Notes
TROB
Rising Settling Time 0.1%, Step, 100pF Load Power Power High 0.65 0.65 0.65 0.65
TSOB
Falling Settling Time 0.1%, Step, 100pF Load Power Power High
SRROB
Rising Slew Rate (20% 80%), Step, 100pF Load Power Power High V/µs V/µs V/µs V/µs
SRFOB
Falling Slew Rate (80% 20%), Step, 100pF Load Power Power High
BWOBSS
Small Signal Bandwidth, 20mVpp, 100pF Load Power Power High
BWOBLS
Large Signal Bandwidth, 1Vpp, 100pF Load Power Power High
Table 3-26. 3.3V Analog Output Buffer Specifications
Symbol Description Units Notes
TROB
Rising Settling Time 0.1%, Step, 100pF Load Power Power High
TSOB
Falling Settling Time 0.1%, Step, 100pF Load Power Power High
SRROB
Rising Slew Rate (20% 80%), Step, 100pF Load Power Power High V/µs V/µs V/µs V/µs
SRFOB
Falling Slew Rate (80% 20%), Step, 100pF Load Power Power High
BWOBSS
Small Signal Bandwidth, 20mVpp, 100pF Load Power Power High
BWOBLS
Large Signal Bandwidth, 1Vpp, 100pF Load Power Power High
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3.4.9
Programming Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-27. Programming Specifications
Symbol Description Units Notes
TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3
Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK
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3.4.10
Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3-28. Characteristics Pins
Standard Mode Symbol Description Fast Mode Units Notes
FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C
Clock Frequency Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock HIGH Period Clock Set-up Time Repeated START Condition Data Hold Time Data Set-up Time Set-up Time STOP Condition Free Time Between STOP START Condition Pulse Width spikes suppressed input filter.
Fast-Mode I2C-bus device used Standard-Mode I2C-bus system, requirement tSU;DAT must then met. This will automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSU;DAT 1000 1250 (according Standard-Mode I2C-bus specification) before line released.
Figure 3-6. Definition Timing Fast/Standard Mode
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
TSUSTOI2C
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Packaging Information
This chapter illustrates package specification CY8C24x94 PSoC devices, along with thermal impedance package solder reflow peak temperatures. Important Note Emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer document titled PSoC Emulator Dimensions
Packaging Dimensions
Figure 4-1. 56-Lead (8x8
001-12921
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Figure 4-2. 68-Lead (8x8 0.89
51-85214
Important Note information preferred dimensions mounting packages, following Application Note Important Note Pinned vias thermal conduction required low-power PSoC device.
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Figure 4-3. 100-Ball (6x6 VFBGA
51-85209
Figure 4-4. 100-Lead (14x14 TQFP
51-85048
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Thermal Impedance
Package Typical
Table 4-1. Thermal Impedance Package
QFN** QFN** VFBGA POWER
12.93 oC/W 13.05 oC/W oC/W
achieve thermal impedance specified package, center thermal should soldered ground plane.
Solder Reflow Peak Temperature
Following minimum solder reflow peak temperature achieve good solderability. Table 4-2. Solder Reflow Peak Temperature
Package Minimum Peak Temperature* Maximum Peak Temperature
VFBGA
240oC 240oC
260oC 260oC 260oC
*Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
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Development Tool Selection
This chapter presents development tools available current PSoC device families including CY8C24x94 family.
5.1.1
Software
PSoC Designer
Development Kits
development kits purchased from Cypress Online Store.
core PSoC development software suite PSoC Designer. Utilized thousands PSoC developers, this robust software been facilitating PSoC designs half decade. PSoC Designer available free charge http:// www.cypress.com under DESIGN RESOURCES Software Drivers.
5.2.1
CY3215-DK Basic Development
5.1.2
PSoC Express
CY3215-DK prototyping development with PSoC Designer. This supports in-circuit emulation software interface allows users run, halt, single step processor view content specific memory locations. Advance emulation features also supported through PSoC Designer. includes:
PSoC Designer Software ICE-Cube In-Circuit Emulator Flex-Pod CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 240V Power Supply, Euro-Plug Adapter iMAGEcraft Compiler (Registration Required) ISSP Cable Cable Blue Cat-5 Cable CY8C29466-24PXI 28-PDIP Chip Samples
newest addition PSoC development software suite, PSoC Express first visual embedded system design tool that allows user create entire PSoC project generate schematic, BOM, data sheet without writing single line code. Users work directly with application objects such LEDs, switches, sensors, fans. PSoC Express available free charge
5.1.3
PSoC Programmer
Flexible enough used bench development, suitable factory programming, PSoC Programmer works either standalone programming application operate directly from PSoC Designer PSoC Express. PSoC Programmer software compatible with both PSoC ICE-Cube InCircuit Emulator PSoC MiniProg. PSoC programmer available free ofcharge
5.1.4
CY3202-C iMAGEcraft Compiler
CY3202 optional upgrade PSoC Designer that enables iMAGEcraft compiler. purchased from Cypress Online Store. http://www.cypress.com, click Online Store shopping cart icon bottom page, click PSoC (Programmable System-on-Chip) view current list available items.
February 2007
Document 38-12018 Rev.
Feedback
CY8C24094, CY8C24794, CY8C24894, CY8C24994 Final Data Sheet
Development Tool Selection
5.2.2
CY3210-ExpressDK PSoC Express Development
5.3.3
CY3214-PSoCEvalUSB
CY3210-ExpressDK advanced prototyping development with PSoC Express (may used with ICE-Cube In-Circuit Emulator). provides access buses, voltage reference, switches, upgradeable modules more. includes:
PSoC Express Software Express Development Board Modules Proto Modules MiniProg In-System Serial Programmer MiniEval Evaluation Board Jumper Wire Cable Serial Cable (DB9) 240V Power Supply, Euro-Plug Adapter CY8C24423A-24PXI 28-PDIP Chip Samples CY8C27443-24PXI 28-PDIP Chip Samples CY8C29466-24PXI 28-PDIP Chip Samples
CY3214-PSoCEvalUSB evaluation features development board CY8C24794-24LFXI PSoC device. Special features board include both capacitive sensing development debugging support. This evaluation board also includes module, potentiometer, LEDs, enunciator plenty bread boarding space meet your evaluation needs. includes:
PSoCEvalUSB Board Module MIniProg Programming Unit Mini Cable PSoC Designer Example Projects Getting Started Guide Wire Pack
Device Programmers
device programmers purchased from Cypress Online Store.
5.4.1
CY3216 Modular Programmer
Evaluation Tools
evaluation tools purchased from Cypress Online Store.
CY3216 Modular Programmer features modular programmer MiniProg1 programming unit. modular programmer includes three programming module cards supports multiple Cypress products. includes:
Modular Programmer Base Programming Module Cards MiniProg Programming Unit PSoC Designer Software Getting Started Guide Cable
5.3.1
CY3210-MiniProg1
CY3210-MiniProg1 allows user program PSoC devices MiniProg1 programming unit. MiniProg small, compact prototyping programmer that connects provided cable. includes:
MiniProg Programming Unit MiniEval Socket Programming Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
5.4.2
CY3207ISSP In-System Serial Programmer (ISSP)
5.3.2
CY3210-PSoCEval1
CY3207ISSP production programmer. includes protection circuitry industrial case that more robust than MiniProg production-programming environment. Note: CY3207ISSP needs special software compatible with PSoC Programmer. includes:
CY3207 Programmer Unit PSoC ISSP Software 240V Power Supply, Euro-Plug Adapter Cable
CY3210-PSoCEval1 features evaluation board MiniProg1 programming unit. evaluation board includes module, potentiometer, LEDs, plenty breadboarding space meet your evaluation needs. includes:
Evaluation Board with Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
February 2007
Document 38-12018 Rev.
Feedback
CY8C24094, CY8C24794, CY8C24894, CY8C24994 Final Data Sheet
Development Tool Selection
Accessories (Emulation Programming)
Package Flex-Pod Kita Foot Kitb Adapterc
Table 5-1. Emulation Programming Accessories
Part
CY8C24794 -24LFXI CY8C24894 -24LFXI
CY325024X94QFN CY325024X94QFN
CY325056QFN-FK CY325056QFN-FK
AS-56-28 AS-28-28-02SS6ENG-GANG
Flex-Pod includes practice flex-pod practice PCB, addition flex-pods. Foot includes surface mount feet that soldered target PCB. Programming adapter converts non-DIP package footprint. Specific details ordering information each adapters found http://www.emulation.com.
3rd-Party Tools
Several tools have been specially designed following 3rd-party vendors accompany PSoC devices during development production. Specific details each these tools found http://www.cypress.com under DESIGN RESOURCES Evaluation Boards.
Build PSoC Emulator into Your Board
details emulate your circuit before going volume production using on-chip debug (OCD) non-production PSoC device, Application Note "Debugging Build PSoC Emulator into Your Board AN2323" http://www.cypress.com/ an2323.
February 2007
Document 38-12018 Rev.
Feedback
Ordering Information
following table lists CY8C24x94 PSoC device's package features ordering codes. Table 6-1. CY8C24x94 PSoC Device's Features Ordering Information
Analog Outputs Analog Blocks Digital Pins Analog Inputs Digital Blocks Temperature Range
(8x8 (8x8 (Tape Reel) (8x8 (8x8 (Tape Reel) (8x8 QFNa (8x8 (8x8 (Tape Reel) Ball (6x6 VFBGAa Ball (6x6 VFBGA TQFPa
CY8C24794-24LFXI CY8C24794-24LFXIT CY8C24894-24LFXI CY8C24894-24LFXIT CY8C24094-24LFXI CY8C24994-24LFXI CY8C24994-24LFXIT CY8C24094-24BVXI CY8C24994-24BVXI CY8C24094-24AXI
-40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C
This part used in-circuit debugging. available production.
Ordering Code Definitions
Package Type: Thermal Rating: PDIP Pb-Free Commercial SOIC Pb-Free Industrial SSOP Pb-Free Extended LFX/LKX Pb-Free TQFP Pb-Free VFBGA Pb-Free Speed: Part Number Family Code Technology Code: CMOS Marketing Code: Cypress PSoC Company Cypress
xxx-SPxx
February 2007
Document 38-12018 Rev.
XRES
Ordering Code
Package
Flash (Bytes)
SRAM (Bytes)
Feedback
Sales Company Information
obtain information about Cypress Semiconductor PSoC sales technical support, reference following information. Cypress Semiconductor Champion Court Jose, 95134 408.943.2600 Sites: Company Information http://www.cypress.com Sales Technical Support
Revision History
CY8C24094, CY8C24794, CY8C24894 CY8C24994 PSoC® Mixed-Signal Array Final Data Sheet
Table 6-1. CY8C24x94 Data Sheet Revision History
Document Title: Document Number: 38-12018
Revision Issue Date Origin Change Description Change
133189 251672 289742 335236
01.27.2004
silicon document Advance Data Sheet. First Preliminary Data Sheet. Changed title encompass only CY8C24794 because CY8C24494 CY8C24694 being offered Cypress MicroSystems. standard items from memo. Analog Input pinouts. MACs. Change bytes SRAM dimension package. Remove HAPI. Update diagrams, registers specs. logo. Update copyright. Update CY.com URLs. Re-add ISSP programming pinout notation. Reflow Temp. table. Update features (MAC, Oscillator, voltage range), registers (INT_CLR2/MSK2, second MAC), specs. (Rext, IMO, analog output buffer.). color logo. Expand analog arch. diagram. Update Electrical Specifications. temperature specifications. Make data sheet Final. Remove logo. preferred dimensions mounting packages. device, CY8C24894 56-pin with XRES pin. Fimousb3v char. specs. Upgrade Perform logo update corporate address copyright. ISSP note pinout tables. Update typical recommended Storage Temperature industrial specs. Update Output Level maximum budget. FLS_PR1 Register Bank users specify which Flash bank should used SROM operations. devices 68-pin 100-ball VFBGA under RPNs: CY8C24094 CY8C24994. packages 68-pin QFN. non-production pinouts package diagrams. Update branding convention. Dev. Tool section. Update copyright trademarks. Power Comparator (LPC) AC/DC electrical spec. tables. CY8C20x34 PSoC Device Characteristics table. detailed dimensions 56-pin package diagram update revision. Secure package diagram/manufacturing QFN. Update emulation pod/feet part numbers. pinout type-o TestTrack. CapSense requirement reference. Update figure standards. Update Technical Training paragraphs. package clarifications dimensions. Update ECN-ed Amkor dimensioned package diagram revisions. Reword reference. 56-pin spec.
Posting: None
344318 346774 349566 393164 469243
561158
728238
Distribution: External/Public
February 2007
Cypress Semiconductor 2004-2007 Document 38-12018 Rev.
Feedback
CY8C24094, CY8C24794, CY8C24894, CY8C24994 Final Data Sheet
Sales Company Information
Copyrights Code Protection
Cypress Semiconductor Corporation. 2004-2007. rights reserved. PSoC DesignerTM, Programmable System-on-ChipTM, PSoC Expressare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. information contained herein subject change without notice. Cypress Semiconductor assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges. Cypress Semiconductor products warranted intended used medical, life-support, life-saving, critical control safety applications, unless pursuant express written agreement with Cypress Semiconductor. Note following details Flash code protection features Cypress Semiconductor PSoC devices. Cypress Semiconductor products meet specifications contained their particular Cypress Semiconductor Data Sheets. Cypress Semiconductor believes that family products most secure families kind market today, regardless they used. There methods, unknown Cypress Semiconductor, that breach code protection features. these methods, knowledge, would dishonest possibly illegal. Neither Cypress Semiconductor other semiconductor manufacturer guarantee security their code. Code protection does mean that guaranteeing product "unbreakable." Cypress Semiconductor willing work with customer concerned about integrity their code. Code protection constantly evolving. Cypress Semiconductor committed continuously improving code protection features products.
February 2007
Document 38-12018 Rev.
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