CY62128

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CY62128LL-70SI - CY62128LL-70SI
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62128-1 - 62128-1
62128 - 62128
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CY62128 - CY62128

CY62128
128K Static
4.5V 5.5V operation CMOS optimum speed/power active power version) (max.) standby power version) (max.) Automatic power-down when deselected TTL-compatible inputs outputs Easy memory expansion with CE1, CE2, options feature that reduces power consumption more than when deselected. Writing device accomplished taking chip enable (CE1) write enable (WE) inputs chip enable (CE2) input HIGH. Data eight pins (I/O0 through I/O7) then written into location specified address pins through A16). Reading from device accomplished taking chip enable (CE1) output enable (OE) while forcing write enable (WE) chip enable HIGH. Under these conditions, contents memory location specified address pins will appear pins. eight input/output pins (I/O0 through I/O7) placed high-impedance state when device deselected (CE1 HIGH LOW), outputs disabled HIGH), during write operation (CE1 LOW, HIGH, LOW). CY62128 available standard 450-mil-wide SOIC, 32-pin TSOP type STSOP packages.
Functional Description
CY62128 high-performance CMOS static organized 131,072 words bits. Easy memory expansion provided active chip enable active HIGH chip enable (CE2), active output enable (OE), three-state drivers. This device automatic power-down
Logic Block Diagram
Configurations
View SOIC
I/O7 I/O6 I/O5 I/O4 I/O3
INPUT BUFFER
SENSE AMPS
512x 256x ARRAY
I/O0 I/O1 I/O2
DECODER
COLUMN DECODER
POWER DOWN
62128-1
TSOP Reverse Pinout View (not scale)
62128-2
I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7
TSOP STSOP View (not scale)
62128-2
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134 408-943-2600 July 1996 Revised June 1998
CY62128
Selection Guide
CY62128-55 Maximum Access Time (ns) Maximum Operating Current Maximum CMOS Standby Current Commercial Commercial CY62128-70
Maximum Ratings
(Above which useful life impaired. user guidelines, tested.) Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage Relative GND[1] -0.5V +7.0V Voltage Applied Outputs High State[1] .-0.5V 0.5V Input Voltage[1].-0.5V 0.5V
Notes: (min.) -2.0V pulse durations less than "instant case temperature.
Current into Outputs (LOW). Static Discharge Voltage >2001V (per MIL-STD-883, Method 3015) Latch-Up Current. >200
Operating Range
Range Commercial Industrial Ambient Temperature[2] +70°C -40°C +85°C
CY62128
Electrical Characteristics Over Operating Range
62128-55 Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[4] Operating Supply Current VCC, Output Disabled Max., VOUT Max., IOUT fMAX 1/tRC Com'l Ind.'l ISB1 Automatic Power-Down Current -TTL Inputs Max. VCC, VIL, VIL, fMAX Com'l Ind.'l ISB2 Automatic Power-Down Current -CMOS Inputs Max. VCC, 0.3V, 0.3V, 0.3V, 0.3V, Com'l 0.15 0.15 Test Conditions Min., -1.0 Min., 2.1mA -0.3 Min. -300 0.15 0.15 -0.3 Typ[3] Max. Min. -300 62128-70 Typ[3] Max. Unit
Capacitance[5]
Parameter COUT Description Input Capacitance Output Capacitance Test Conditions 25°C, MHz, 5.0V Max. Unit
Notes: Typical values included reference only tested guaranteed. Typical values average distribution across normal production variations measured 5.0V, 25°C, tAA=70ns more than output should shorted time. Duration short circuit should exceed seconds. Tested initially after design process changes that affect these parameters.
CY62128
Test Loads Waveforms
OUTPUT INCLUDING SCOPE Equivalent 1800 1800 OUTPUT INCLUDING SCOPE 3.0V INPUT PULSES
62128-3 62128-4
EQUIVALENT 1.77V OUTPUT
Switching Characteristics[6] Over Operating Range
62128-55 Parameter READ CYCLE tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE WRITE CYCLE tSCE tPWE tLZWE tHZWE Read Cycle Time Address Data Valid Data Hold from Address Change Data Valid, HIGH Data Valid Data Valid HIGH High Z[7,8] HIGH
[7,8]
62128-70 Min. Max. Unit
Description
Min.
Max.
HIGH High High
Power-Up, HIGH Power-Up HIGH Power-Down, Power-Down
Write Cycle Time Write End, HIGH Write Address Set-Up Write Address Hold from Write Address Set-Up Write Start Pulse Width Data Set-Up Write Data Hold from Write HIGH High
Notes: Test conditions assume signal transition time less, timing reference levels 1.5V, input pulse levels 3.0V, output loading specified IOL/IOH 100pF load capacitance. tHZOE, tHZCE, tHZWE specified with load capacitance part Test Loads. Transition measured ±500 from steady-state voltage. given temperature voltage condition, tHZCE less than tLZCE, tHZOE less than tLZOE, tHZWE less than tLZWE given device. internal write time memory defined overlap LOW, HIGH, LOW. must HIGH initiate write, transition these signals terminate write. input data set-up hold timing should referenced leading edge signal that terminates write.
CY62128
Data Retention Characteristics (Over Operating Range "LL" version only)
Parameter ICCDR Description Data Retention Data Retention Current Coml. Indl. tCDR[3] tR[3] Chip Deselect Data Retention Time Operation Recovery Time VCC=VDR=3.0V, 0.3V, 0.3V 0.3V Conditions[10] Min. Typ. Max. Unit
Switching Waveforms
Read Cycle No.1[11,12]
ADDRESS tOHA DATA PREVIOUS DATA VALID
[12,13]
DATA VALID
62128-5
Read Cycle Controlled)
ADDRESS tACE tDOE DATA SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tHZOE tHZCE DATA VALID
62128-6
HIGH IMPEDANCE
Notes: input exceed 0.5V. Device continuously selected. VIL, VIH. HIGH read cycle. Address valid prior coincident with transition transition HIGH.
CY62128
Switching Waveforms (continued)
Write Cycle (CE1 Controlled)[14,15]
ADDRESS tSCE tSCE tPWE DATA DATA VALID
62128-7
Write Cycle Controlled, HIGH During Write)[14,15]
ADDRESS tSCE
tSCE tPWE
DATA NOTE tHZOE
Notes: Data high impedance VIH. goes HIGH goes simultaneously with going HIGH, output remains high-impedance state. During this period I/Os output state input signals should applied.
DATAIN VALID
62128-8
CY62128
Switching Waveforms (continued)
Write Cycle No.3 Controlled, LOW)[14,15]
ADDRESS tSCE
tSCE DATAI/O NOTE tHZWE DATA VALID tLZWE
62128-9
tPWE
Truth Table
I/O7 High High Data Data High Mode Power-Down Power-Down Read Write Selected, Outputs Disabled Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
CY62128
Ordering Information
Speed (ns) Ordering Code CY62128-55SC CY62128-55ZC CY62128-55ZAC CY62128-70SC CY62128-70ZC CY62128-70ZAC CY62128-70ZRC CY62128-70SI CY62128-70ZI CY62128-70ZAI CY62128-70ZRI CY62128L-70SC CY62128L-70ZC CY62128L-70ZAC CY62128L-70ZRC CY62128L-70SI CY62128L-70ZI CY62128L-70ZAI CY62128L-70ZRI CY62128LL-70SC CY62128LL-70ZC CY62128LL-70ZAC CY62128LL-70ZRC CY62128LL-70SI CY62128LL-70ZI CY62128LL-70ZAI CY62128LL-70ZRI Document 38-00524-B Package Name ZA32 ZA32 ZR32 ZA32 ZR32 ZA32 ZR32 ZA32 ZR32 ZA32 ZR32 ZR32 Package Type 32-Lead 450-Mil SOIC 32-Lead TSOP Type 32-Lead STSOP Type 32-Lead 450-Mil SOIC 32-Lead TSOP Type 32-Lead STSOP Type 32-Lead Reverse TSOP Type 32-Lead 450-Mil SOIC 32-Lead TSOP Type 32-Lead STSOP Type 32-Lead Reverse TSOP Type 32-Lead 450-Mil SOIC 32-Lead TSOP Type 32-Lead STSOP Type 32-Lead Reverse TSOP Type 32-Lead 450-Mil SOIC 32-Lead TSOP Type 32-Lead STSOP Type 32-Lead Reverse TSOP Type 32-Lead 450-Mil SOIC 32-Lead TSOP Type 32-Lead STSOP Type 32-Lead Reverse TSOP Type 32-Lead 450-Mil Type 32-Lead TSOP Type 32-Lead STSOP Type 32-Lead Reverse TSOP Type Industrial Commercial Industrial Commercial Industrial Commercial Operating Range Commercial
CY62128
Package Diagrams
32-Lead (450 MIL) Molded SOIC
51-85081-A
32-Lead Thin Small Outline Package
51-85056-B
CY62128
Package Diagrams (continued)
32-Lead Shrunk Thin Small Outline Package ZA32
51-85094
32-Lead Reverse Thin Small Outline Package ZR32
51-85089-A
Cypress Semiconductor Corporation, 1998. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress Semiconductor product. does convey imply license under patent other rights. Cypress Semiconductor does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress Semiconductor products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress Semiconductor against charges.

CY62128

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