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CY3663 Hardware User's Manual
Cypress Semiconductor 3901 North First Street Jose, 95134 Tel.: (800) 858-1810 (toll-free U.S.) (408) 943-2600 www.cypress.com
Warranty Disclaimer Limited Liability
Cypress Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Cypress's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Cypress granted
Company connection with sale Cypress products, expressly implication. Cypress's products authorized critical components life support devices systems. CY16 trademark Cypress Corporation. other product names trademarks registered trademarks their respective owners. CY3663 Hardware User's Manual, Version 1.5. Copyright 2003 Cypress Semiconductor Corporation. rights reserved.
Table Contents
Chapter Introduction
Introduction.
Chapter Cypress StrongARM Single Board Computer
Introduction. System Block Diagram Processor Memory Serial Ports. 2.4.1 Serial Port 2.4.2 Serial Port 2.4.3 Serial Port 2.4.4 Serial Port Expansion Port CPLD. User Interface. 2.7.1 2.7.2 LEDs. 2.7.2.1 Power LEDs 2.7.2.2 General Purpose LEDs 2.7.2.3 Network LEDs 2.7.2.4 Other LEDs 2.7.3 Switches 2.7.4 Pushbuttons. Ethernet. Power 2.10 Miscellaneous Jumpers.
Chapter Cypress EZ-Host Development Board
Introduction. System Block Diagram Processor Memory Asynchronous Serial Ports
(Table Contents)
3.4.1 UART. 3.4.2 High Speed Serial (HSS). Co-processor Connection. CPLD. User Interface. 3.8.1 Seven Segment Display 3.8.2 Switches 3.8.3 LEDs. 3.8.3.1 Power LEDs 3.8.3.2 General Purpose LEDs 3.8.3.3 3.8.4 Pushbuttons. Power 3.10 Ports 3.11 Miscellaneous.
Chapter Cypress EZ-OTG Development Board
Introduction System Block Diagram Processor Memory Asynchronous Serial Ports 4.4.1 UART. 4.4.2 High Speed Serial (HSS). Co-processor Connection. CPLD. User Interface. 4.8.1 Seven Segment Display 4.8.2 Switches 4.8.3 LEDs. 4.8.3.1 Power LEDs 4.8.3.2 General Purpose LEDs 4.8.4 Pushbuttons. Power 4.10 Ports 4.11 Miscellaneous.
Table Contents
(Table Contents) Chapter Developing with EZ-Host EZ-OTG Boards
Standalone Mode Operation 5.1.1 Power-up EEPROM Selection. 5.1.2 Switches 5.1.3 Pushbutton Inputs. 5.1.4 LEDs: ERROR, SESSION ACTIVE, HOST, PERIPHERAL 5.1.5 LEDs: RUN/STOP 5.1.6 Seven Segment Display 5.1.7 Debugging Through UART 5.1.8 CPLD Accesses. Co-processor Mode Operation 5.2.1 Power-up Port Selection. 5.2.2 Switches 5.2.3 Push Button Inputs 5.2.4 LEDs. 5.2.5 Seven Segment Display 5.2.6 CPLD Accesses. 5.2.7 Debugging Through UART Addressing EZ-Host/OTG CPLD. 5.3.1 ADD_Reg 5.3.2 Data_Reg Memory Indirect CPLD Registers. EZ-Host/OTG CPLD Indirect Register Descriptions. 5.5.1 PB_Read 5.5.2 PB_UP_Clr 5.5.3 PB_LEFT_Clr 5.5.4 PB_RIGHT_Clr 5.5.5 PB_DOWN_Clr. 5.5.6 PB_ENTER_Clr 5.5.7 DIP_Read 5.5.8 LED_Write 5.5.9 SSD_Write. 5.5.10 VBUS_Level 5.5.11 VBUS_On_GPIO_30 5-10 5.5.12 Add_Reg_Read 5-10 5.5.13 EEPROM_MFG_CTL 5-10 EZ-Host/OTG Board Pushbutton Switch Definitions 5-11
Table Contents
(Table Contents)
5.6.1 Switch Settings 5-11 5.6.2 Pushbuttons. 5-14 5.6.3 LEDs. 5-14 5.6.4 Display 5-15 Co-processor Mode Hints. 5-15 Recommended GPIO Settings EZ-Host/OTG Boards 5-16 Restoring EZ-Host EZ-OTG Boards Factory Defaults. 5-17
Chapter Developing with Cypress StrongArm
Normal Operation Cypress StrongARM SBC. 6.1.1 Running Design Examples 6.1.2 Operation Linux Muti-port Host Linux Development with Cypress StrongARM 6.2.1 Boot Sequence 6.2.2 Using Ethernet Downloads During Development 6.2.2.1 Updating FLASH contents over Ethernet 6.2.3 Using Serial Downloads During Development. 6.2.3.1 Updating FLASH contents over Serial Restoring Factory Defaults Cypress StrongARM Memory CPLD Register Descriptions 6-10 6.5.1 NETWORK_DECODE. 6-10 6.5.2 DIP_PB_CTL 6-10 6.5.3 LED_CTL. 6-11 6.5.4 LCD_CTL. 6-11 6.5.5 LCD_STATUS_0 6-12 6.5.6 LCD_STATUS_1 6-12 6.5.7 LCD_STATUS_3 6-13 6.5.8 CPLD_VERSION. 6-13 6.5.9 SBC_EXP_RST. 6-14 6.5.10 MEZ_CARD_PRESENT. 6-14 6.5.11 MEZ_CARD_DIP. 6-15
Appendix
Definitions Appendix
Table Contents
List Figures
Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 3-1. Figure 3-2. Figure 3-3. Figure 4-1. Figure 5-1. Cypress StrongARM Single Board Computer Cypress StrongARM Block Diagram Serial Port Location Expansion Port Location CPLD User Interface Cypress EZ-Host Development Board Cypress EZ-Host Development Board Block Diagram EZ-Host User Interface Cypress EZ-OTG Development Board Block Diagram Timing Waveforms
List Figures
Chapter Introduction
Introduction
This manual describes hardware Cypress CY3663 Development (DVK). three individual boards included Cypress StrongARM Single Board Computer (SBC), EZ-Host board, EZ-OTG board. next three chapters provide description hardware circuitry each boards, last chapters give developer details using boards. Please refer needed Appendix definition abbreviations terms used throughout manual. Additional hardware documentation that should used conjunction with this document found "Hardware" subdirectory that installed from This directory contains schematics, layout files, Bill-of-Materials, CPLD source three boards this kit.
Chapter Introduction
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Chapter Cypress StrongARM Single Board Computer
Introduction
Figure 2-1. Cypress StrongARM Single Board Computer Cypress StrongARM Single Board Computer (SBC) versatile development platform that currently supports Linux operation system. Other features include: Intel StrongARM SA-1110 microprocessor Mbytes SDRAM, Mbytes FLASH, Kbytes SRAM User interface including two-line LCD, LEDs, pushbuttons
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High density, flexible in-circuit programmable CPLD Ethernet port Multiple synchronous asynchronous serial ports High signal visibility with quick connect logic analyzer support Robust buffered expansion port
System Block Diagram
following block diagram Cypress StrongARM SBC.
Contrast Knob
Line
CPLD Programming EEPROM
EEPROM Programming Conn Control Mictor Address Analyzer Data Connectors Data Address Control Buffer Address Expansion Data Connectors Control GPIO
Switches Pushbuttons CPLD Control Data Address GPIO
FLASH 16-bit data 128Mbit Address Default Bank 16-bit data FLASH 128Mbit Address Optional Bank
Green LEDs
3.6864MHz 32.768KHz
EEPROM
DB9F
RS232 XCVR
Jumpers sharing w/expansion port
SA-1110
GPIO Address Data Control
DB9F RS232 XCVR
Voltage Supervisor Reset Jack regulated input 3.3v Linear Regulator Pushbutton
16-bit data SDRAM 16Mbyte Address Least Significant bits 16-bit data SDRAM Address 16Mbyte Most Significant bits
Data 10Base-T Address Controller Control
Network Magnetics
RJ45
JTAG Conn
StrongARM Core Voltage
16-bit data SRAM Address 256K
Figure 2-2. Cypress StrongARM Block Diagram
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Processor Memory
Cypress StrongARM uses Intel StrongARM SA-1110 microprocessor running MHz. SA-1110 built-in serial ports, memory management unit, programmable chip select unit, interrupt controller, JTAG interface, instruction cache, data cache, programmable memory controller. Cypress StrongARM following memory: Mbytes SDRAM (two 16-bit parts used make 32-bit bus) Mbytes FLASH (one 16-bit part loaded, second 8Meg 16-bit part unpopulated) Kbytes SRAM (one 256K 16-bit part)
Serial Ports
2.4.1 Serial Port
This asynchronous serial port provides communication with terminal control SBC. does support hardware handshaking. port external DB9F connector labeled silkscreen Serial #1". This port uses on-chip StrongARM SA-1110 Channel UART. default settings 115200 baud, parity, data bits, stop bit. Refer Figure port location.
Figure 2-3. Serial Port Location
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2.4.2 Serial Port
This asynchronous serial port provides communication with host running software application. default, does support hardware handshaking, hardware handshaking configured loading shunts appropriate pins modifying Linux kernel support Note that hardware handshaking signals shared with serial port mutually exclusive with that port. Serial port external DB9F connector labeled silkscreen Serial #2". This port uses on-chip StrongARM SA-1110 Channel UART. Refer Figure port location.
2.4.3 Serial Port
This asynchronous serial port provides communication with serial interface expansion port. default, does support hardware handshaking, hardware handshaking used CTS_3 RTS_3 signals J34. Note that hardware handshaking signals shared with serial port mutually exclusive with that port. port does have external connector serial transceiver directly routed expansion port (signal names GPIO_IR1 receive GPIO_IR2 transmit). This port uses on-chip StrongARM SA-1110 Channel UART.
2.4.4 Serial Port
This synchronous serial port provides communication with synchronous serial interface expansion port. port does have external connector serial transceiver directly routed expansion port (signal names SSP_SFRM, SSP_SCLK, SSP_TXD, SSP_RXD). serial port supports various synchronous serial protocols including SPI. This port uses on-chip StrongARM SA-1110 Channel Synchronous Serial Controller.
Expansion Port
expansion port group connectors (J3, J32, J33, J34, J35) that allows expansion cards connected SBC. EZ-Host board EZ-OTG board examples expansion boards that this form factor. expansion port offers following features: Buffered 16-bit 32-bit data bus, buffered address bus, buffered control, buffered master active reset Interrupt support Direct connection several GPIO pins StrongARM SA-1110 Direct connection UART synchronous serial port SA-1110
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Direct connection separate programmable clocks from SA-1110 Connection expansion port clock SBC's CPLD Direct connection several GPIO signals from CPLD chip selects with programmable wait states. chip select supports variable latency peripherals. volt volt power from SBC. Expansion port connectors 20-pin dual connectors, which compatible with Agilent logic analyzer terminator adapters.
Figure 2-4. Expansion Port Location
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Note: careful when removing expansion boards from expansion port. high number 0.1" spacing dual connectors expansion port creates much static friction that removal expansion cards cause flex possible damage.
CPLD
CPLD Cypress Delta39K series part offering high density, great flexibility, easy in-system programming. configuration CPLD stored U25, which serial EEPROM. power-up, CPLD loads configuration from EEPROM, then allows board come reset. that when configuration finished loading CPLD. CPLD following functions features: controller Chip select decode network controller chip, FLASH, Expansion port buffer control switch, push button, control GPIO controller Expansion port reset control Over resources free custom logic
Figure 2-5. CPLD
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User Interface
Figure shows location some LEDs, LCD, switches, pushbuttons that part User Interface.
Figure 2-6. User Interface
2.7.1
line characters that controlled CPLD used primary on-board display. There contrast dial located right side adjust contrast. jumper located turns backlight shunted.
2.7.2 LEDs
several LEDs on-board allow user feedback about board operation.
2.7.2.1
Power LEDs
Green when volts available Green when volts available Green when 1.55 volts available (used SA-1110 core)
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2.7.2.2
General Purpose LEDs
Green connected GPIO SA-1110 Green connected GPIO SA-1110 Green connected CPLD Green connected CPLD
2.7.2.3
Network LEDs
Green active when network link established Green that blinks during network activity
2.7.2.4
Other LEDs
Green active when CPLD successfully loaded configuration from EEPROM
2.7.3 Switches
bank eight switches configuration. Unless indicated otherwise other documentation, switches should normal operation.
2.7.4 Pushbuttons
pushbuttons board. Pushbutton master hard reset board. Pushing will result entire board being reset. Alternatively, connected GPIO SA-1110 moving shunt J40. Pushbuttons through provide menu navigation interface such menu implemented software; otherwise they provide bank general purpose pushbuttons.
Ethernet
support 10Base-T network connection. network cable connected RJ45 connector located LEDs provide link activity indication.
Power
receives power from volt regulated wall transformer. Power fused board fast acting non-resetable fuse volts distributed around board expansion
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port. volt regulator provides volts board expansion port. 1.55 volt regulator provides voltage SA-1110 core. Several two-pin jumpers sprinkled around board providing convenient ground, volt, volt connection.
2.10 Miscellaneous Jumpers
Other jumpers present follows: Isolation jumper Serial port normal operation, pins should shunted. These Mictor footprints connection logic analyzer supporting Mictor form factor. development with results need logic analyzer connection main memory bus, Mictor connectors soldered these locations analyzer support. J26, J27, These debug headers easy connection Agilent logic analyzer with termination adapter. This header JTAG interface SA-1110. This jumper allows FLASH protected from writes. Note that FLASH file system Linux needs FLASH writable. This header connects in-circuit EEPROM programmer CPLD configuration updates. Unloaded components connections There several unloaded component connector footprints PCB. These future have been tested.
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Chapter Cypress EZ-Host Development Board
Introduction
Cypress EZ-Host development board versatile development platform used demonstrate develop with Cypress EZ-Host host/peripheral controller (CY7C67300).
Figure 3-1. Cypress EZ-Host Development Board Other features include: Cypress CY16 microprocessor Cypress EZ-Host host/peripheral controller (CY7C67300)
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64Kybtes external SRAM (one part, with accessible) 8-bit FLASH footprint (not loaded) User interface including seven segment display, LEDs, pushbuttons In-circuit programmable CPLD Serial port Multiple host peripheral ports On-The-Go (OTG) support Charge pump 10mA five volt power VBUS High signal visibility with quick connect logic analyzer support 40-pin connector User selectable operation either standalone mode co-processor mode Support co-processor mode connection Cypress StrongARM Support power from external wall transformer co-processor
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System Block Diagram
following block diagram Cypress EZ-Host development board containing Cypress EZ-Host host/peripheral controller (CY7C67300).
SRAM RS-232 xcvr
ADDRESS GPIO EEPROM EEPROM EEPROM EEPROM FLASH Loaded
GPIO
xcvr switches
CY7C67300 Controller
DATA CONTROL
GPIO
GPIO
Pushbuttons GPIO GPIO Latch
CPLD TQ44
Latch
Seven Segment Display
LEDs Error, Host, Peripheral, Session Active
nRESET CY7C67300
Voltage Reset
Pushbutton
xcvr xcvr
GPIO
Jack
GPIO
X_NRD, X_NWR, NCS, Data, signals
Ports "A", "B", "OTG Xtra headers SPI, HSS, PWM,
3.3v
signals
xcvrs/latches
Reset from inputs
Expansion Port
Figure 3-2. Cypress EZ-Host Development Board Block Diagram
Processor Memory
Cypress EZ-Host development board centered around Cypress EZ-Host host/ peripheral controller (CY7C67300). This controller several on-chip features listed below: 16-bit RISC Processor Kbytes Internal BIOS Kbytes Internal SRAM UARTs four Full-speed compliant host ports
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Full-speed compliant peripheral ports Full-speed compliant On-The-Go (OTG) port Watch-dog Timer External SRAM DRAM controllers Controller Controller Master/Slave Controller Timers
3.4.1
Asynchronous Serial Ports
UART
This serial port provides debug development interface EZ-Host chip. does support hardware software handshaking. This port external DB9F connector with reference designator labeled silkscreen "DEBUG PORT".
3.4.2
High Speed Serial (HSS)
This serial port provides high speed asynchronous serial interface co-processor. routed expansion connectors (signal names GPIO_16, GPIO_17, GPIO_18, GPIO_26). EZ-Host board connected co-processor Cypress StrongARM operation selected appropriate switch settings, port communicates with serial ports SBC. port supports hardware handshaking. optional connection would load components (and surrounding capacitors), RS232 compliant port. Note that these optional components used, baud rate limited maximum switching frequency serial transceiver U16.
CY7C67300 contains master/slave controller. When EZ-Host board connected Cypress StrongARM operation selected appropriate switch settings, port operates slave mode only buffered before connecting SBC. buffered signals available (SBC_NSSI, SBC_SCK, SBC_MOSI, SBC_MISO). switches configure EZ-Host board operation.
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Co-processor Connection
EZ-Host board group connectors (J24, J25, J26, J29, J30, J31, J32) which allow connection Cypress StrongARM SBC. switches configure EZ-Host board operation three co-processor modes: HPI, SPI, HSS.
Note: careful when removing this board from expansion port Cypress StrongARM SBC. high number 0.1" spacing dual connectors expansion port creates much static friction that removal expansion cards cause flex possible damage.
CPLD
CPLD Cypress series part offering flexibility in-circuit programming. CPLD controls mode CY7C67300 powers reading switch settings driving boot pins (GPIO_30, GPIO_31) appropriately. also controls serial EEPROM selection, buffer control, pushbutton control. header position allows in-circuit programmer update CPLD.
User Interface
Figure shows location LEDs, switches, Pushbuttons, EZ-Host User Interface.
Figure 3-3. EZ-Host User Interface
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3.8.1
Seven Segment Display
Seven Segment Display (SSD) allows digits displayed user. When standalone mode, driven CY7C67300. When co-processor mode, driven Cypress StrongARM SBC.
3.8.2
Switches
bank eight switches controls operation EZ-Host board. Based switch settings, EZ-Host board powers standalone mode with four serial EEPROMs active, three co-processor modes. switches also select several demonstration examples. Refer Chapter "Developing with EZ-Host EZ-OTG Boards" table switch settings their definitions.
3.8.3
LEDs
EZ-Host board several LEDs on-board allow user feedback about board operation.
3.8.3.1
Power LEDs
Green when volts available Green when volts available
3.8.3.2
General Purpose LEDs
when error encountered during design example Green when board operating host position during design example Green when board operating peripheral position during design example Green when board active session during design example general purpose LED. Green general purpose LED.
Note: When stand-alone mode, driven CY7C67300. When co-processor mode, these four LEDs driven Cypress StrongARM SBC.
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3.8.3.3
Green when connected device drives nDASP line.
3.8.4
Pushbuttons
EZ-Host board pushbuttons on-board. Pushbutton causes hard reset board when standalone mode. effect co-processor mode. Note that this pushbutton disabled removing shunt J23. Pushbuttons through general purpose input buttons that used during operation design examples. Note that pushbuttons read cleared CY7C67300 stand-alone mode Cypress StrongARM co-processor mode.
Power
EZ-Host board receive power either from external five volt wall transformer through co-processor connectors. When standalone mode, power from external five volt wall transformer fused board fast acting non-resetable fuse volt regulator provides volts logic board. When co-processor mode, power provided Cypress StrongARM SBC; five volts through volts through J30.
3.10 Ports
EZ-Host board four host ports, peripheral ports, port. ports connected same time. CY7C67300 datasheet table possible simultaneous active ports. Some details section follow: host VBUS current limiting Each four host ports current limiting device VBUS prevent device from drawing much current over VBUS that host would damaged. These current limiting devices automatically reset after overcurrent situation remedied. host VBUS power Each four host ports supply 500mA current device, four ports simultaneously supply 500mA peripherals. more than host ports should connected devices consuming greater than 100mA current five volt power board will drawn down. VBUS detect peripheral ports board supports detection valid VBUS both peripheral ports. Peripheral port VBUS detected VBUS that connects CY7C67300. Peripheral port VBUS detected several ways:
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standalone co-processor mode, register CPLD read that shows VBUS level. Refer Chapter "Developing with EZ-Host EZ-OTG Boards" register settings. standalone co-processor mode VBUS level output GPIO_30 setting register CPLD. Refer Chapter "Developing with EZ-Host EZ-OTG Boards" register settings. standalone mode, loaded VBUS GPIO_20.
3.11 Miscellaneous
EZ-Host board several features allow easy development debug listed below. Voltage supervisor on-board voltage supervisor ensures clean system resets under conditions including voltage brownout. EEPROM support board support four separate EEPROMs. These EEPROMs shipped 256-Kbit devices, smaller size also used custom development. 16Kbit smaller EEPROMs loaded, resistors must moved opposite position (see schematic). Boot support board automatically sets boot pins CY7C67300 correct configuration based switches. board forced into single boot configuration regardless switch settings appropriate combination R18, R19, R21, loaded removed. Debug headers 20-pin headers board compatible with Agilent logic analyzer terminator adapters. This feature allows quick simple debug connection.
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Chapter Cypress EZ-OTG Development Board
Introduction
Cypress EZ-OTG development board versatile development platform used demonstrate develop with Cypress EZ-OTG host/peripheral controller (CY7C67200). Other features include: Cypress CY16 microprocessor Cypress EZ-OTG Host/peripheral controller (CY7C67200) User interface including seven segment display, LEDs, pushbuttons In-circuit Programmable CPLD Serial Port Multiple Host peripheral ports On-The-Go (OTG) support Charge pump 10mA five volt power VBUS High signal visibility with quick connect logic analyzer support User selectable operation either standalone mode co-processor mode Support co-processor mode connection Cypress StrongARM Support power from external wall transformer co-processor
System Block Diagram
following block diagram Cypress EZ-OTG development board containing Cypress EZ-OTG host/peripheral controller (CY7C67200).
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GPIO EEPROM EEPROM GPIO xcvr
RS-232 xcvr Jumpers
CY7C67200 Controller
EEPROM EEPROM
switches
GPIO
Pushbuttons
CPLD TQFP44
GPIO
GPIO
Latch
Seven Segment Display
Latch
GPIO
LEDs Error, Host, Peripheral, Session Active
Pushbutton nRESET CY7C67200 Voltage Reset
xcvr
GPIO
Extra headers
SPI, HSS, Jack
xcvr
Ports
"A", "B", "OTG
3.3v
X_NRD, X_NWR, Data, NCS,
signals
signals
xcvrs/latches
Reset from inputs
Expansion Port
Figure 4-1. Cypress EZ-OTG Development Board Block Diagram
Processor Memory
Cypress EZ-OTG development board centered around Cypress EZ-OTG host/ peripheral controller (CY7C67200). This controller several on-chip features listed below: 16-bit RISC Processor Kbytes Internal BIOS Kbytes Internal SRAM UARTs Full-speed compliant host ports Full-speed compliant peripheral ports Full-speed compliant On-The-Go (OTG) port Watch-dog Timer Controller Master/Slave Controller Timers
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Asynchronous Serial Ports
4.4.1 UART
This serial port provides debug development interface EZ-OTG chip. does support hardware software handshaking. This port external DB9F connector labeled silkscreen "DEBUG PORT". Note that serial debug port EZ-OTG board cannot used when co-processor mode. serial port standalone mode, header must have shunts applied between pins 3-4. addition, UART should used firmware uses switches SSD. shunts must removed coprocessor mode.
4.4.2 High Speed Serial (HSS)
This serial port provides high speed asynchronous serial interface co-processor. routed through buffer expansion connectors (signal names GPIO_12, GPIO_13, GPIO_14, GPIO_15). EZ-OTG board connected co-processor Cypress StrongARM operation selected appropriate switch settings, port communicates with serial ports SBC. port supports hardware handshaking. optional connection would load components (and surrounding capacitors), RS232 compliant port. Note that these optional components used, baud rate limited maximum switching frequency serial transceiver U16.
CY7C67200 contains master/slave controller. When EZ-OTG board connected Cypress StrongARM operation selected appropriate switch settings, port operates slave mode only buffered before connecting SBC. buffered signals available (SBC_NSSI, SBC_SCK, SBC_MOSI, SBC_MISO). switches configure EZ-OTG board operation.
Co-processor Connection
EZ-OTG board group connectors (J24, J25, J26, J29, J30, J31, J32) which allow connection Cypress StrongARM SBC. even standalone mode, UART should used firmware accesses switches board. switches configure EZ-OTG board operation three co-processor modes: HPI, SPI, HSS.
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Note: careful when removing this board from expansion port Cypress StrongARM SBC. high number 0.1" spacing dual connectors expansion port creates much static friction that removal expansion cards cause flex possible damage.
CPLD
CPLD Cypress series part offering flexibility in-circuit programming. CPLD controls mode CY7C67200 powers reading switch settings driving boot pins (GPIO_30, GPIO_31) appropriately. also controls serial EEPROM selection, buffer control, pushbutton control. header position allows in-circuit programmer update CPLD.
User Interface
4.8.1 Seven Segment Display
Seven Segment Display (SSD) allows digits displayed user. When standalone mode, driven CY7C67200. When co-processor mode, driven Cypress StrongARM SBC.
4.8.2 Switches
bank eight switches controls operation EZ-OTG board. Based switch settings, EZ-OTG board powers standalone mode with four serial EEPROMs active, three co-processor modes. switches also select several demonstration examples. Refer Chapter "Developing with EZ-Host EZ-OTG Boards" table switch settings their definitions.
4.8.3 LEDs
EZ-OTG board several LEDs on-board allow user feedback about board operation.
4.8.3.1
Power LEDs
Green when volts available Green when volts available
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4.8.3.2
General Purpose LEDs
when error encountered during design example Green when board operating host position during design example Green when board operating peripheral position during design example Green when board active session during design example
Note: When stand-alone mode, driven CY7C67200. When co-processor mode, these four LEDs driven Cypress StrongARM SBC.
4.8.4 Pushbuttons
EZ-OTG board pushbuttons on-board. Pushbutton causes hard reset board when standalone mode. effect co-processor mode. Note that this pushbutton disabled removing shunt J23. Pushbuttons through general purpose input buttons that used during operation design examples. Note that pushbuttons read cleared CY7C67200 stand-alone mode Cypress StrongARM co-processor mode.
Power
EZ-OTG board receive power either from external five volt wall transformer through co-processor connectors. When standalone mode, power from external five volt wall transformer fused board fast acting non-resetable fuse volt regulator provides volts logic board. When co-processor mode power provided Cypress StrongARM SBC; five volts through volts through J30.
4.10 Ports
EZ-OTG board host ports, peripheral ports, port. ports connected same time. CY7C67200 datasheet table possible simultaneous active ports. Some details section follow: host VBUS current limiting Each host ports current limiting device VBUS prevent device from drawing much current over VBUS that host would damaged. These current limiting devices automatically reset after overcurrent situation remedied.
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host VBUS power Each host ports supply 500mA current device. VBUS detect peripheral ports board supports detection valid VBUS both peripheral ports. Peripheral port VBUS detected VBUS that connects CY7C67200. Peripheral port VBUS detected several ways: standalone co-processor mode, register CPLD read that shows VBUS level. Refer Chapter "Developing with EZ-Host EZ-OTG Boards" register settings. standalone co-processor mode VBUS level output GPIO_30 setting register CPLD. Refer Chapter "Developing with EZ-Host EZ-OTG Boards" register settings. standalone mode, loaded VBUS GPIO_20.
4.11 Miscellaneous
EZ-OTG board several features allow easy development debug listed below. Voltage supervisor on-board voltage supervisor ensures clean system resets under conditions including voltage brownout. EEPROM support board support four separate EEPROMs. These EEPROMs shipped 128Kbit devices, smaller size also used custom development. 16Kbit smaller EEPROMs loaded, then resistors must moved opposite position (see schematic). Boot support board automatically sets boot pins CY7C67200 correct configuration based switches. board forced into single boot configuration regardless switch settings appropriate combination R18, R19, R21, loaded removed. Debug headers 20-pin headers board compatible with Agilent logic analyzer terminator adapters. This feature allows quick simple debug connection.
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Chapter Developing with EZ-Host EZ-OTG Boards
Standalone Mode Operation
5.1.1 Power-up EEPROM Selection
Since signal present CP_PRESENT (co-processor present) line, CPLD looks switch settings decides which EEPROM should enabled.
5.1.2 Switches
Read CPLD Note EZ-OTG board, Debug UART being used, then upper positions cannot read.
5.1.3 Pushbutton Inputs
inputs latched CPLD Read through CPLD Cleared through CPLD write, write button
5.1.4 LEDs: ERROR, SESSION ACTIVE, HOST, PERIPHERAL
Written through CPLD.
5.1.5 LEDs: RUN/STOP
Only available EZ-Host board. write external space affects these LEDs based lowest data bits follows:
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Table 5-1. Run/Stop LEDs
CY7C67300 memory data (D1) CY7C67300 memory data (D0) STOP (red) (green)
NOTE: LEDs reset power-up
5.1.6 Seven Segment Display
Similar LEDs. Written through CPLD Note that UART enabled EZ-OTG board, upper segments cannot written will driven whatever happens UART pins time write.
5.1.7 Debugging Through UART
UART will work situations with EZ-Host board. UART used standalone mode with EZ-OTG board. limitation that whenever CPLD accessed, GPIO_6 must changed from UART configuration input. because UART uses GPIO_6 GPIO_7, upper switch positions cannot reliably read, upper segments cannot reliably written Seven Segment Display.
5.1.8 CPLD Accesses
stand-alone mode, CY7C67300 CY7C67200 accesses peripherals through CPLD creating typical memory access type cycle using following GPIO signals: Address: (GPIO_19) Chip Select: (GPIO_21) Read Strobe: (GPIO_23) Write Strobe: (GPIO_22) Data: D[7:0] (GPIO_[7:0], where GPIO_7 most significant bit)
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waveform diagram below. Note that mutually exclusive; that only should asserted (low) access. Timing should issues since bit-banging these signal bits creating plenty timing margin between signal transitions.
D[7:0] D[7:0]
Address Valid
Note: Only active during cycle, both
Read Data Valid Write Data Valid
Figure 5-1. Timing Waveforms
Co-processor Mode Operation
5.2.1 Power-up Port Selection
Since CP_PRESENT will driven SBC, EZ-Host/OTG CPLD will strap boot pins whatever inputs select (HPI, HSS, SPI), assuming legitimate combination demo communication method. EZ-Host/OTG controller will power into that mode. NOTE: mode, EZ-Host/OTG controller must configured tri-state GPIO[24:19] GPIO[7:0] cannot read write switches, pushbuttons, LEDS, SSD.
5.2.2 Switches
mode: read them through EZ-Host/OTG CPLD mode: read them through EZ-Host/OTG CPLD mode: read them through EZ-Host/OTG CPLD Additionally, read them through CPLD (the CPLD)
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5.2.3 Push Button Inputs
mode: read them through EZ-Host/OTG CPLD clear them individually through EZ-Host/OTG CPLD mode: read them through EZ-Host/OTG CPLD clear them individually through EZ-Host/OTG CPLD mode: read them through EZ-Host/OTG CPLD clear them individually through EZ-Host/OTG CPLD
5.2.4 LEDs
mode: write them EZ-Host/OTG CPLD mode: write them EZ-Host/OTG CPLD mode: write them EZ-Host/OTG CPLD
5.2.5 Seven Segment Display
Similar LEDs three co-processor modes
5.2.6 CPLD Accesses
co-processor will access EZ-Host/OTG CPLD with normal asynchronous memory-type access. Refer Section 5.3. "Addressing EZ-Host/OTG CPLD" more details.
5.2.7 Debugging Through UART
UART will work situations with EZ-Host board. UART cannot reliably used co-processor mode with EZ-OTG board. Unrelated memory cycles will clobber both transmit receive data randomly.
Addressing EZ-Host/OTG CPLD
EZ-Host/OTG CPLD activity controlled indirect addressing. There direct registers CPLD: pointer register (called ADD_Reg), data register (called Data_Reg). Writing CPLD with (this GPIO_19 pin) will write ADD_Reg, which makes Data_Reg register point indirect register. Reading writing with will read write that indirect register.
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Table 5-2. Memory Direct CPLD Registers
Direct Address Register Name ADD_Reg Data_Reg Description Address Pointer Register. Writes pointer register Read write from/to indirect register pointed Address Pointer Register (ADD_Reg) Write Only (Read value accessed indirectly) Read/Write
5.3.1 ADD_Reg
Register that contains address pointer indirect registers Address (Direct address) Write only Resets XXX00000 Description Address pointer indirect registers Unused
5.3.2 Data_Reg
Register that writes reads from indirect register. Controlled address ADD_Reg register Address (Direct address) Read/Write Resets XXXXXXXX Description Data indirect register pointed ADD_Reg
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Memory Indirect CPLD Registers
Table 5-3. Memory Indirect CPLD Registers
Register Name PB_Read PB_UP_Clr PB_LEFT_Clr PB_RIGHT_Clr PB_DOWN_Clr PB_ENTER_Clr DIP_Read LED_Write SSD_Write VBUS_Level VBUS_On_GPIO_30 ADD_Reg_Read EEPROM_MFG_CTL Indirect Address Read only Write only Write only Write only Write only Write only Read only Write only Write only Read only Read/Write Read only Read/Write
EZ-Host/OTG CPLD Indirect Register Descriptions
5.5.1 PB_Read
Register that holds latched value push-buttons Address Read only Resets XXX11111 Description PB_UP latched value latched, unlatched) PB_LEFT latched value PB_RIGHT latched value PB_DOWN latched value PB_ENTER latched value Unused
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5.5.2 PB_UP_Clr
Register that clears latch pushbutton Address Write only write value this register will result PB_UP latch being cleared.
5.5.3 PB_LEFT_Clr
Register that clears latch pushbutton Address Write only write value this register will result PB_LEFT latch being cleared.
5.5.4 PB_RIGHT_Clr
Register that clears latch pushbutton Address Write only write value this register will result PB_RIGHT latch being cleared.
5.5.5 PB_DOWN_Clr
Register that clears latch pushbutton Address Write only write value this register will result PB_DOWN latch being cleared.
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5.5.6 PB_ENTER_Clr
Register that clears latch pushbutton Address Write only write value this register will result PB_ENTER latch being cleared.
5.5.7 DIP_Read
Register that allows read bank switches Address Read only Description DIP_1 switch value DIP_2 switch value DIP_3 switch value DIP_4 switch value DIP_5 switch value DIP_6 switch value DIP_7 switch value DIP_8 switch value
5.5.8 LED_Write
Register that allows four individual LEDs written Address Write only Resets XXXXXXXX Description ERROR Writing turns HOST PERIPHERAL SESSION ACTIVE connected. Write value
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5.5.9 SSD_Write
Register that allows Seven-Segment-Display written Address Write only Resets XXXXXXXX Description Segment Writing turns Segment Segment Segment Segment Segment Segment Segment
5.5.10 VBUS_Level
Register that contains VBUS level peripheral port SIE2 EZ-Host/OTG controller.
Note: This input reading analog voltage. actual VBUS voltage between about volts volts, register read high. Address Read only Description VBUS level peripheral port SIE2 Unused
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5.5.11 VBUS_On_GPIO_30
Register that drives VBUS from peripheral port SIE2 EZ-Host/OTG controller onto signal GPIO_30.
NOTE: standalone mode GPIO_30 used EEPROM clock (SCL), make sure EEPROM activity done before configuring GPIO_30 reflect SIE2 VBUS level. Address Read/Write Resets XXXXXXX0 Description set, drive level VBUS peripheral port SIE2 onto GPIO_30. clear, GPIO_30 driven level dictated switches used
5.5.12 Add_Reg_Read
Register that contains indirect register address. This register probably very useful. Address Read Only Resets XXXXXXXX Description Value indirect register address used
5.5.13 EEPROM_MFG_CTL
Register that allows co-processor drive EEPROM address lines, clock data lines. also allows EZ-Host/OTG controller select EEPROM regardless switch settings. This register meant manufacturing probably useful development.
NOTE: Control EEPROM using this register does allow EEPROM reads through CPLD. actual data EEPROM (SDA) read through SBC's directly connected general purpose pins. Also, when reading EEPROM, user must make sure drive
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high (set this register) because that drives pull-up, which required that signal. Address Read/Write Resets XXX00000 Description Value drive Value drive Setting this makes other bits this register drive EEPROM address lines control lines. EEPROM address select set. table below. EEPROM address select set. table below. used
Table 5-4. EEPROM Address Select Bits
EEPROM_MFG_CTL[4] EEPROM_MFG_CTL[3] EEPROM Selected EEPROM EEPROM EEPROM EEPROM
EZ-Host/OTG Board Pushbutton Switch Definitions
5.6.1 Switch Settings
There bank eight switches EZ-Host/OTG board. Note that only switches EZ-Host/OTG board will used configure demos, switches SBC. switches labeled part also have "OFF" "OPEN" label direction. Note: "OFF" logical when read hardware, "ON" logical when read hardware. addition combinations Communication Mode (DIP switches valid with combinations Design Example Number (DIP switches
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Table 5-5. Switch Settings Switch
Switch Switch Communication Mode Standalone
Table 5-6. Switch Settings Switch
Switch Switch Switch Switch Design Example Default Design Example Standalone mode Valid, EEPROM enabled Coprocessor mode Valid, only Design Example Dual Slave Standalone mode Invalid Coprocessor mode Valid Design Example Peripheral-Host Passthrough Standalone mode- Valid, EEPROM enabled Coprocessor mode Valid, only Design Example Dual Host Standalone mode Valid, EEPROM enabled Coprocessor mode Valid, only Invalid Invalid Invalid Standalone mode Valid, enabled, CPLD inactive, EEPROM Enabled Coprocessor mode Invalid Invalid Invalid Standalone mode Valid, EEPROM enabled Coprocessor mode Invalid
Default means following: Standalone mode: Power with EEPROM (BIOS configures EZ-Host/OTG controller) Coprocessor mode: Power mode.
Note: four switches assigned selecting Design Example more than currently necessary, they allow more selections demos added future.
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Note: invalid switch combination EZ-Host/OTG board connected co-processor, EZ-Host/OTG controller will power mode, will able talk EZ-Host/OTG controller. can, however, talk rest board. invalid switch combination EZ-Host/OTG board connected co-processor, will power standalone mode with boot EEPROM. Table 5-7. Switch Settings Switch
Switch Switch Function Default allow demos Undefined Undefined
Note: EZ-Host/OTG board does look switches power-up configuration. Table 5-8. Table Valid Switch Combinations
DIP[6:1] 000000 000100 000110 001001 001010 001011 001100 001110 010000 010010 1100XX 111100 Description "User" setting. Standalone mode EEPROM selected. Co-processor mode enabled. Demo OTG, Standalone mode, EEPROM Active Demo OTG, Co-processor mode, communication Demo Dual Slave, Co-processor mode, communication Demo Dual Slave, Co-processor mode, communication Demo Dual Slave, Co-processor mode, communication Demo Peripheral Host Passthrough, Standalone mode, EEPROM Active Demo Peripheral Host Passthrough, Co-processor mode, communication Demo Dual Host, Standalone mode, EEPROM Active Demo Dual Host, Co-processor mode, communication Standalone mode, EEPROM active, mode, CPLD disabled Standalone mode, EEPROM active
Note: this table, OFF=0 ON=1
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5.6.2 Pushbuttons
pushbuttons necessary EZ-Host/OTG board demo functionality follows. They laid form factor resembling board shown diagram below.
button PB_UP, labeled "INC" (increment "+") Bottom button PB_DOWN, labeled "DEC" (decrement "-") Left Button PB_LEFT, labeled "Request HNP" (request Host Negotiation Protocol device moment) Right Button PB_RIGHT, labeled "SRP/Session End" (Request Session Request Protocol device there active session. Force session host) Center button PB_ENTER, labeled "ENTER". used demos.
Note: There pushbutton (S6) available that causes hard reset EZ-Host/OTG board. Note that would idea push this button when connected because communication with would broken likely recoverable without system power cycle.
5.6.3 LEDs
There "OTG ERROR" indicate that reportable errors occurred, such over current VBUS line device supported. This will work conjunction with display. case error, "OTG ERROR" will appropriate error code will displayed display. Silkscreen board will errors. LED_Write register "OTG ERROR" position. There "HOST" separate "PERIPHERAL" board that will displayed when board acting appropriate function. These LEDs will only useful when running demo because some other demos require EZHost/OTG board host peripheral simultaneously. LED_Write register "HOST" "Peripheral" position. There "SESSION ACTIVE" LED. Once again, only useful demo. LED_Write register "SESSION ACTIVE" position. There "+5v" "+3.3v" LED. These will when appropriate power present.
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5.6.4 Display
seven segment display available. will used demo show incrementing decrementing value display error code. This display also used other demos debugging aid. SSD_Write register positions.
Co-processor Mode Hints
When EZ-Host/OTG board co-processor mode, will: Power idle until toggles hardware reset. Read switch settings. Detect co-processor mode. Detect what method communication with based switch settings. Configure itself that mode. Wait communication from SBC. ability Determine that EZ-Host/OTG board attached. Control hardware reset line EZ-Host/OTG board. Read switch settings EZ-Host/OTG board matter what mode EZHost/OTG board thinks ability read switches gives opportunity report back controlling software user configured EZHost/OTG board correctly.
couple things aware are: should reset EZ-Host/OTG board. must wait reasonable amount time EZ-Host/OTG board BIOS configure itself (see datasheet minimum time delay). When EZ-Host/OTG board powered correctly, will then have access pushbuttons switches must drive LEDs seven-segment display EZ-Host/OTG board appropriately.
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Recommended GPIO Settings EZ-Host/OTG Boards
following table gives recommended GPIO settings EZ-Host/OTG controller when used either EZ-Host EZ-OTG board. Note differences parenthesis EZ-OTG controller. Table Key: Input Output Bidirectional BIOS sets Table 5-9. GPIO Settings
GPIO Standalone Co-processor Co-processor EZ-OTG) EZ-OTG) Co-processor EZ-OTG) EZ-OTG) EZ-OTG) EZ-OTG)
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Table 5-9. GPIO Settings
GPIO Standalone Co-processor Co-processor Co-processor
Restoring EZ-Host EZ-OTG Boards Factory Defaults
EZ-Host board EZ-OTG board restored factory defaults doing following things: EZ-Host EZ-OTG board connected expansion port SBC, remove switches OPEN position Plug cable from either board's peripheral ports. Note must have CY3663 software installed. Power EZ-Host EZ-OTG board. board will power debug mode. Open window. Alternatively, open BASH shell. Change your prompt BASH shell prompt Tools\Utilities subdirectory that installed from that originally shipped with kit. switches only switch Type following prompt. This runs utility that downloads de1_scan.bin file over board programs into EEPROM that selected switch settings (EEPROM this case). Note that using BASH shell must replace backslash characters with forward slash characters.
qtui2c
Wait prompt come back. design example restored factory default. NOTE: This programming step only valid EZ-Host board since EZ-OTG board does support design example standalone mode. switches only
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Type following prompt. This runs utility that downloads de3_scan.bin file over board programs into EEPROM that selected switch settings (EEPROM this case). Note that using BASH shell must replace backslash characters with forward slash characters.
qtui2c
Wait prompt come back. Peripheral-Host design example restored factory default switches only Type following prompt. This runs utility that downloads de4_scan.bin file over board programs into EEPROM that selected switch settings (EEPROM this case). Note that using BASH shell must replace backslash characters with forward slash characters.
qtui2c
Wait prompt come back. Dual Host design example restored factory default. NOTE: This programming step only valid EZ-Host board since EZ-OTG board does support Dual Host design example standalone mode.
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Chapter Developing with Cypress StrongArm
Normal Operation Cypress StrongARM
6.1.1 Running Design Examples
Cypress StrongARM used normal operation Design Examples right box. following connect Connect desired mezzanine card (either EZ-Host board EZ-OTG board) expansion port. Connect running OTG-Host Navigator software serial port marked Serial #2". Verify that bank switches near switches position. Connect power supply SBC. Follow instructions Design Example tutorial software.
6.1.2 Operation Linux Muti-port Host
Cypress StrongARM used multi-port host system right box. Linux kernel that ships board class driver support hub, mass storage, audio. following boot board into multi-port host system mode: already attached, connect desired mezzanine card (either EZ-Host board EZ-OTG board) expansion port. Connect running serial terminal program such HyperTerminal serial port marked Serial #1". terminal software should 115200 baud, parity, data bits, stop bit, flow control. Verify that bank switches near switches OPEN position. Verify that bank switches EZ-Host EZ-OTG card (which connected expansion port SBC) OPEN position. Connect power supply SBC.
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Watch terminal window boot Linux login prompt. Login username "root", there password.
Linux Development with Cypress StrongARM
6.2.1 Boot Sequence
normal boot sequence Cypress StrongARM follows: power-on-reset, ARMBoot boot loader executes. Boot loader configures board's hardware. boot loader starts countdown. uninterrupted user, countdown zero reached Linux image resident FLASH then booted. desired, user follow boot progress login Linux doing following: Connect running serial terminal program such HyperTerminal serial port marked Serial #1". terminal software should 115200 baud, parity, data bits, stop bit, flow control. Watch terminal window boot Linux login prompt. Login username "root", there password. Note that terminal connection should prior powering board. development Linux kernel desired, user will generally want have boot loader download kernel from network TFTP server each bootup. following boot sequence should then followed: Upon power-on-reset, ARMBoot boot loader executes. Boot loader configures board's hardware, then requests address from network DHCP server DHCP enabled static address assigned. Once address obtained, boot loader starts countdown. uninterrupted user, countdown zero reached boot loader looks TFTP server named "serverip" environmental setting. Once TFTP server found, boot loader looks Linux image named "bootcmd" environmental setting downloads image into RAM. address relinquished DHCP server DHCP enabled) Linux boots from downloaded image. desired, user follow boot progress login Linux doing following: Connect running serial terminal program such HyperTerminal serial port marked Serial #1". terminal software should 115200 baud, parity, data bits, stop bit, flow control. Watch terminal window boot Linux login prompt. Login username "root", there password. Note that terminal connection should prior powering board.
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6.2.2 Using Ethernet Downloads During Development
changes necessary boot loader download image from TFTP server instead FLASH resident image. make these changes, boot loader must interrupted user during countdown user typing terminal (i.e. Windows HyperTerminal with baudrate 115200) connected serial port labeled Serial #1". Once ARMBoot prompt, user view environmental settings typing "printenv" make following changes: Tell boot loader different TFTP server updating "serverip" environmental setting. example change
<ARMBoot prompt>setenv serverip 172.19.3.137
above command tells boot loader look TFTP server that address. Tell boot loader download Linux image from TFTP server instead using onboard FLASH resident image updating "bootcmd" environmental setting. example change
<ARMBoot prompt>setenv bootcmd tftp c0000000 vmlinux.img\; bootm
above command tells boot loader download file vmlinux.img from tftp server, then boot image. NOTE: boot loader's bootcmd environmental settings back using resident FLASH Linux image following:
<ARMBoot prompt>setenv bootcmd bootm 80000
This tells boot loader load image located 0x80000 FLASH. dynamic address desired from network DHCP server, enable DHCP boot loader setting "dhcpen" environmental setting follows:
<ARMBoot prompt>setenv dhcpen
NOTE: disable DHCP support boot loader, remove "dhcpen" environmental setting follows:
<ARMBoot prompt>setenv dhcpen
NOTE: static address desired, make sure "dhcpen" environmental setting removed shown above. Then assign static address boot loader follows (your actual address will different than example shown below):
<ARMBoot prompt>setenv ipaddr 172.19.3.151
After environmental settings have been made, update them permanently FLASH doing following:
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<ARMBoot prompt>saveenv
above command tells ARMBoot write environmental settings FLASH, they will used each power-up. After environment saved, reboot board network setting changes take effect. reboot either pushing button typing following:
<ARMBoot prompt>reset
6.2.2.1
Updating FLASH contents over Ethernet
some point, user want write Linux image FLASH. that case, following sequence ARMBoot commands should followed. Note: assumed that Ethernet network available board configured properly Ethernet instructed previous section. Note: Overwriting resident Linux image FLASH will most likely prevent Design Examples shipped with from operating.
<ARMBoot <ARMBoot <ARMBoot <ARMBoot prompt>tftp c0000000 vmlinux.img prompt>protect 1:4-31 prompt>erase 1:4-31 prompt>cp.b c0000000 80000 37FFFF
first command copies image over network from TFTP server RAM. second command turns write protect FLASH sectors erased. third command erases FLASH sectors. fourth command copies image from into FLASH. some point, user want write JFFS FLASH file system FLASH. that case, following sequence ARMBoot commands should followed. NOTE: Overwriting resident FLASH file system will most likely prevent Design Examples shipped with from operating.
<ARMBoot <ARMBoot <ARMBoot <ARMBoot <ARMBoot prompt>mw.b c0000000 c00000 prompt>tftp c0000000 rootfs.jffs prompt>protect 1:32-127 prompt>erase 1:32-127 prompt>cp.b c0000000 400000 BFFFFF
first command fills memory with pattern. second command copies image over network from TFTP server RAM. third command turns write protect FLASH sectors erased. fourth command erases FLASH sectors. fifth command copies image from into FLASH. NOTE: Because FLASH file system very large, time needed write FLASH several minutes.
6.2.3 Using Serial Downloads During Development
development using Ethernet network possible, kernel downloaded over serial terminal port booted. course, serial download much slower than network down-
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load, Ethernet infrastructure needed. following shows example download using Windows HyperTerminal. HyperTerminal correctly (115200, connected serial cable serial port labeled Serial #1". Stop boot process ARMBoot prompt. ARMBoot prompt, type following. This tells ARMBoot going download file over serial using kermit transfer protocol address 0xc0000000.
<ARMBoot prompt>loadb c0000000
HyperTerminal, choose Transfer menu. Choose Send File. Browse your file (probably vmlinux.img), make sure Protocol Kermit. Choose Send. file transfer process will probably take several minutes. When file fully transferred, located starting address 0xc0000000. ARMBoot prompt, type following boot kernel:
<ARMBoot prompt>bootm c0000000
6.2.3.1
Updating FLASH contents over Serial
kernel filesystem residing FLASH updated over serial port updating using Ethernet network possible. following shows example download kernel write FLASH using Windows HyperTerminal. HyperTerminal correctly (115200, connected serial cable serial port labeled Serial #1". Stop boot process ARMBoot prompt ARMBoot prompt, type following. This tells ARMBoot going download file over serial using kermit transfer protocol address 0xc0000000.
<ARMBoot prompt>loadb c0000000
HyperTerminal, choose Transfer menu. Choose Send File. Browse your file (probably vmlinux.img), make sure Protocol Kermit. Choose Send. file transfer process will probably take several minutes. Copy file residing FLASH with following commands.
<ARMBoot prompt>protect 1:4-31 <ARMBoot prompt>erase 1:4-31 <ARMBoot prompt>cp.b c0000000 80000 37FFFF
following shows example download jffs filesystem write FLASH using Windows HyperTerminal. HyperTerminal correctly (115200, connected serial cable serial port labeled Serial #1". Stop boot process ARMBoot prompt
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ARMBoot prompt, type following. This fills memory with default value, then tells ARMBoot going download file over serial using kermit transfer protocol address 0xc0000000.
<ARMBoot prompt>mw.b c0000000 c00000 <ARMBoot prompt>loadb c0000000
HyperTerminal, choose Transfer menu. Choose Send File. Browse your file (probably rootfs.jffs), make sure Protocol Kermit. Choose Send. file transfer process will probably take several minutes. Copy file residing FLASH with following commands.
<ARMBoot prompt>protect 1:32-127 <ARMBoot prompt>erase 1:32-127 <ARMBoot prompt>cp.b c0000000 400000 bFFFFF
Restoring Factory Defaults
Cypress StrongARM restored factory defaults doing following things: Linux kernel been modified, follow procedure "Updating FLASH contents over Ethernet" section "Updating FLASH contents over Serial" section restore kernel original. original kernel binary found CY3663 Binaries\coprocessor subdirectory that installed from that shipped with kit. jffs FLASH filesystem been modified, follow procedure "Updating FLASH contents over Ethernet" section "Updating FLASH contents over Serial" section restore filesystem original. original filesystem binary found CY3663 Binaries\coprocessor subdirectory that installed from that shipped with kit. ARMBoot prompt, type following. These commands return boot loader environment default settings.
<ARMBoot prompt>setenv dhcpen <ARMBoot prompt>setenv bootcmd bootm 80000 <ARMBoot prompt>saveenv
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Cypress StrongARM Memory
memory will display several layers. first overview StrongARM memory map, then FLASH, expansion port, CPLD regions will blown show more detail. Table 6-1. StrongARM Memory
Physical Address Range E800,0000FFFF,FFFF E000,0000E7FF,FFFF D800,0000DFFF,FFFF D000,0000D7FF,FFFF C800,0000CFFF,FFFF C000,0000C7FF,FFFF B000,0000BFFF,FFFF A000,0000AFFF,FFFF 9000,00009FFF,FFFF 8000,00008FFF,FFFF 5000,00007FFF,FFFF 4800,00004FFF,FFFF 4000,000047FF,FFFF 3000,00003FFF,FFFF 2000,00002FFF,FFFF 1800,00001FFF,FFFF 1000,000017FF,FFFF 0800,00040FFF,FFFF 0000,000007FF,FFFF Resource Size Reserved Mbyte Zeros Bank Mbyte SDRAM bank Mbyte SDRAM bank Mbyte SDRAM bank Mbyte StrongARM SDRAM bank Mbyte Control Mbyte Memory Control Mbyte Reserved Cache flush Empty Empty Empty SDRAM bank Internal Internal Read zeros, cycle Mbyte: bits wide 3663 Size: Width
SA-1110 System Control Internal Mbyte Peripheral Control Mbyte Internal
Module Register
Reserved Mbyte StrongARM Chip Select (nCS5) Mbyte StrongARM Chip Select (nCS4) Mbyte StrongARM PCMCIA/CF Slot Mbyte StrongARM PCMCIA/CF Slot Mbyte StrongARM Chip Select (nCS3) Mbyte StrongARM Chip Select (nCS2) Mbyte StrongARM Chip Select (nCS1) Mbyte StrongARM Chip Select (nCS0) Mbyte
Reserved Expansion Port
EZ-Host/EZ-OTG access. detailed Expansion Port Memory Various decodes: Network, Decode CPLD. CPLD User Interface, etc. Memory Used Used Used Expansion Port EZ-Host/EZ-OTG CPLD access: Bit. detailed Expansion Port Memory KBytes: bits wide MBytes: bits wide. detailed FLASH Memory
SRAM Boot/Application flash
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Table 6-2. FLASH Memory
Physical Address Range 0040,000000FF,FFFF 0008,0000003F,FFFF 0006,00000007,FFFF 0004,00000005,FFFF 0002,00000003,FFFF 0000,00000001,FFFF Description Sectors Sectors Sector Sector Sector Sector JFFS Flash File System (CFG_JFFS2_FIRST_SECTOR Linux Kernel Spare (Unused) ARMboot Autoscripts Boot Parameters ARMboot Boot Loader ARMboot Boot Loader Code Size 12.58M 3670K 128K 128K 128K 128K
Table 6-3. Expansion Port Memory
Physical Address Range 1000,0100 1000,0000 4800,0300 4800,0200 4800,0100 4800,0000 Linux Virtual Address D900,0100 D900,0000 D800,0300 D800,0200 D800,0100 D800,0000 Description Expansion Port: StrongARM Chip Select (nCS2) Expansion Port: StrongARM Chip Select (nCS2) Expansion Port: StrongARM Chip Select (nCS5) Expansion Port: StrongARM Chip Select (nCS5) Expansion Port: StrongARM Chip Select (nCS5) Expansion Port: StrongARM Chip Select (nCS5) CPLD Data Register EZ-Host EZ-OTG mezzanine cards CPLD Address Register EZ-Host EZ-OTG mezzanine cards Port Status Register EZHost EZ-OTG mezzanine cards Mailbox Register EZ-Host EZ-OTG mezzanine cards Address Register EZ-Host EZ-OTG mezzanine cards Data Register EZ-Host EZ-OTG mezzanine cards
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CPLD programmed with control decode logic many functions. CPLD activity uses memory range assigned StrongARM Chip Select memory this range below. Table 6-4. CPLD Memory
Physical Address Range 4380,0000 43FF,FFFF 4330,0000 437F,FFFF 4320,0000 432F,FFFF 4310,0000 431F,FFFF 4300,0000 430F,FFFF 4280,0000 42FF,FFFF 4200,0000 427F,FFFF 4180,0000 41FF,FFFF 4100,0000 417F,FFFF 4080,0000 40FF,FFFF 4000,0000 407F,FFFF D200,0000 D730,0000 D720,0000 Linux Virtual Address Description
CPLD: StrongARM Chip Select Used: DEBUG area, (nCS4) decoded CPLD CPLD: StrongARM Chip Select Used (nCS4) CPLD: StrongARM Chip Select Expansion Port (nCS4) Switches register (MEZ_CARD_DIP) CPLD: StrongARM Chip Select Expansion Card Present (nCS4) regiser (MEZ_CARD_PRESENT) CPLD: StrongARM Chip Select Expansion Port Reset Con(nCS4) trol register (SBC_EXP_RST) CPLD: StrongARM Chip Select CPLD Version register (nCS4) (CPLD_VERSION) CPLD: StrongARM Chip Select control registers (nCS4) CPLD: StrongARM Chip Select control register (nCS4) (LED_CTL) CPLD: StrongARM Chip Select switches pushbut(nCS4) tons registers (DIP_PB_CTL) CPLD: StrongARM Chip Select Used (nCS4) CPLD: StrongARM Chip Select network chip select decode (nCS4) region (NETWORK_DECODE)
D710,0000
D700,0000 D600,0000 D500,0000 D400,0000 D300,0000
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CY3663 Hardware User's Guide
CPLD Register Descriptions
Note: accesses CPLD memory region must 16-bit accesses
6.5.1 NETWORK_DECODE
Address range that decodes Cirrus CS-8900A Ethernet Physical Address range: 0x40000000 0x407FFFFF Virtual Address range: 0xD2000000 0xD20FFFFF Read/Write
6.5.2 DIP_PB_CTL
Register that holds current switch values latched value push-buttons; also allows clearing push-button latches. Physical Address: 0x41000000 Virtual Address: 0xD3000000 Read/Write Resets binary XXX0,0000,XXXX,XXXX
Read
15:13 Description Value switch bank (switch etc.) PB_DOWN latched value latched, unlatched) PB_RIGHT latched value latched, unlatched) PB_ENTER latched value latched, unlatched) PB_LEFT latched value latched, unlatched) PB_UP latched value latched, unlatched) Unused
Write
write value this register will clear pushbutton latches.
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6.5.3 LED_CTL
Register that controls LEDS labeled "LED3" "LED4" Physical Address: 0x41800000 Virtual Address: 0xD4000000 Read/Write Resets binary XXXX,XXXX,XXXX,XX00
Read/Write
15:2 Description LED3 value (low turns off, high turns LED4 value (low turns off, high turns Unknown
6.5.4 LCD_CTL
Register that holds characters written allows either automatic manual control LCD. When using LCD, user normally reads LCD_STATUS_3 register, clear, writes character proper control bits this register (user writes character bits positions 7:0, either command data value Bits 12:10 should written zeros). When this register written, state machine CPLD automatically transfers character LCD. Alternatively, this register allows manual bit-bang control 16-character 2-line LCD. used Optrex DMC16204NY-LY. character control bits found "Character User's Manual", which downloaded from Optrex site. Physical Address: 0x42000000 0x427FFFFF Virtual Address: 0xD5000000 Write only Resets binary XXX1,0001,0000,0000
Write
Description data bits. effect clear. Read/Write bit. High read, write.
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Register Select bit. Chooses either command accesses data accesses LCD. enable bit. This read write strobe that causes access bit-bang mode. effect clear. Bit-bang bit. set, values bits 10:0 LCD_CTL register driven (Note: set, drives data LCD, bits will have effect.) Auto Init bit. set, this forces initialization LCD. This automatically clears itself. Unused
15:13
6.5.5 LCD_STATUS_0
Register that allows read-back LCD_CTL register. Physical Address: 0x42000000 Virtual Address: 0xD5000000 Read only Resets binary XXX1,0001,0000,0000
Read
12:0 15:13 Description Read value LCD_CTL register Unknown
6.5.6 LCD_STATUS_1
Register that allows values signals read Physical Address: 0x42000002 Virtual Address: 0xD5000002 Read only Resets binary XXXX,XXXX,XXXX,XXXX
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Read
15:11 Description Value data lines Value signal NDRW Value signal Value signal Unknown
6.5.7 LCD_STATUS_3
Register used when CPLD state machine control desired. user monitors this register keep from writing characters fast. When clear, user writes character code LCD_CTL register. Physical Address: 0x42000004 Virtual Address: 0xD5000004 Read only Resets binary XXXX,XXXX,XXXX,XXXX
Read
15:3 Description AUTO_LCD_INIT high, actively being initialized. low, initialized. LCD_WRITE_REQUEST high, control state machine actively writing character LCD. LCD_BUSY high, don't write LCD. low, write character LCD. This logical bits this register. Unknown
6.5.8 CPLD_VERSION
Register used find programmed version CPLD. Physical Address: 0x42800000 Virtual Address: 0xD6000000 Read only Resets binary XXXX,XXXX,XXXX,XXXX
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Read
15:4 Description Version CPLD Unknown
6.5.9 SBC_EXP_RST
Register used control reset line expansion port. Physical Address: 0x43000000 Virtual Address: 0xD7000000 Read/Write Resets binary XXXX,XXXX,XXXX,XXX0
Read/Write
15:1 Description Value driven CPLD_IO[11] signal which goes expansion port. Currently this signal used master expansion port reset. Unknown. effect.
6.5.10 MEZ_CARD_PRESENT
Register used detect presence mezzanine card attached expansion port. Both EZ-Host EZ-OTG boards will drive this signal attached. Physical Address: 0x43100000 Virtual Address: 0xD7100000 Read Only Resets binary XXXX,XXXX,XXXX,XXXX
Read
15:1 Description high, expansion card present. low, expansion card present. This reflects level CPLD_IO[2] SBC. Unknown
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6.5.11 MEZ_CARD_DIP
Register used read value bank switches residing mezzanine card. Physical Address: 0x43200000 Virtual Address: 0xD7200000 Read Only Resets binary XXXX,XXXX,XXXX,XXXX
Read
15:8 Description DIP1 mezzanine card, which connected CPLD_IO[4] DIP2 mezzanine card, which connected CPLD_IO[5] DIP3 mezzanine card, which connected CPLD_IO[6] DIP4 mezzanine card, which connected CPLD_IO[7] DIP5 mezzanine card, which connected CPLD_IO[8] DIP6 mezzanine card, which connected CPLD_IO[9] DIP7 mezzanine card, which connected CPLD_IO[10] DIP8 mezzanine card, which connected CPLD_IO[15] Unknown
Chapter Developing with Cypress StrongArm
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Appendix
Definitions
Term CY16-DVK Expansion Card CPLD EZ-Host Definition RISC processor core EZ-Host EZ-OTG controllers. Development Kit. Cypress series CPLD either EZ-Host board EZ-OTG board that controls several functions those cards, including accesses from Cypress StrongARM SBC, attached. development that contains Cypress CY7C67300 Host/Peripheral controller. EZ-Host board operate stand-alone device mezzanine card connected expansion port Cypress StrongARM SBC. general name used describe either EZ-Host (CY7C67300) EZ-OTG (CY7C67200) Host/Peripheral controllers. CPLD resident either EZ-Host EZ-OTG board. Expansion Card CPLD. development that contains Cypress CY7C67200 Host/Peripheral controller. EZ-OTG board operate stand-alone device mezzanine card connected expansion port Cypress StrongARM SBC. Host Port Interface. 16-bit interface from external device EZ-Host/OTG controller. High Speed Serial. asynchronous serial interface EZ-Host/OTG controller that operate very high baud rates three available co-processor communication modes. Cypress StrongARM Single Board Computer Cypress series CPLD resident Cypress StrongARM that controls several logic decode functions. Serial Peripheral Interface. synchronous serial interface EZ-Host/ controller that three available co-processor modes. Seven Segment Display. display present EZ-Host/OTG boards.
EZ-Host/OTG EZ-Host/OTG CPLD EZ-OTG
CPLD
Appendix
CY3663 Hardware User's Guide
CY3663 Hardware User's Guide v1.5
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