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CS5510/11/12/13 16-bit 20-bit, 8-pin ADCs
Delta-sigma Analog-to-digital Converter Linearity Error: 0.0015% Noise-free Resolution: Bits Differential VREF 50/60
CS5510/11/12/13 low-cost, easy-to-use, analog-to-digital converters (ADCs) which chargebalance techniques achieve 16-bit (CS5510/11) 20-bit (CS5512/13) performance. ADCs available space-efficient, 8-pin SOIC package optimized measuring signals weigh scale, process control, other industrial applications. accommodate these applications, ADCs include fourth-order modulator digital filter. When configured with external master clock 32.768 kHz, filter CS5510/12 provides better than simultaneous line rejection, outputs conversion words 53.5 Sps. CS5511/13 include on-chip oscillator which eliminates need external clock source. Low-power, flexible supply configurations, compact pinout, ease make these products ideal solutions cost-conscience space-constrained applications.
Bipolar Analog Inputs
Input Range from
Simultaneous Rejection (CS5510/12) Output Word Rate Oscillator (CS5511/13)
On-chip
Power Supply Configurations: Multiple Dual-supply Arrangements Power Consumption Normal Mode, Sleep Mode, Low-cost, Lead-free
Compact, 8-pin Package Device Package Options
ORDERING INFORMATION page
AIN+ AINVREF ~0.8X Differential 4th-order Delta-sigma Modulator Digital Filter Output Control Logic
SCLK Oscillator (CS5511/13 only) VClock Gen.
(CS5510/12 only)
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2009 (All Rights Reserved)
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TABLE CONTENTS
CHARACTERISTICS SPECIFICATIONS ANALOG CHARACTERISTICS DIGITAL CHARACTERISTICS DYNAMIC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS SWITCHING CHARACTERISTICS CS5510/12 SWITCHING CHARACTERISTICS CS5511/13 GENERAL DESCRIPTION Analog Input 2.1.1 Analog Input Model Voltage Reference Input 2.2.1 Voltage Reference Input Model Power Supply Arrangements 2.3.1 Digital Logic Levels Clock Generator 2.4.1 External Clock Source CS5510/12 2.4.2 Internal Oscillator CS5511/13 Performing Conversions 2.5.1 Reading Conversions CS5510/12 2.5.2 Reading Conversions CS5511/13 2.5.3 Output Coding 2.5.4 Digital Filter 2.5.5 Multiplexed Applications Digital Off-chip System Calibration Power Consumption, Sleep Reset Layout DESCRIPTIONS SPECIFICATION DEFINITIONS ORDERING INFORMATION ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION PACKAGE DIMENSIONS REVISION HISTORY
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LIST FIGURES
Figure Read Timing CS5510/12 Figure Read Timing CS5511/13 Figure Input models AIN+ AIN- pins. Figure CS5512/13 Measured Noise-Free Bits VREF. Figure Input model VREF pin. Figure CS5510/11/12/13 Configured with +5.0 Analog Supply. Figure CS5510/11/12/13 Configured with ±2.5 Analog Supplies. Figure CS5510/11/12/13 Configured with +3.3 -1.7 +3.0 -2.0 Figure SCLK Digital Input Levels. Figure Digital Output Levels. Figure Serial Port Output Drive Logic. Figure External (CMOS Compatible) Clock Source. Figure Using Microcontroller Clock Source. Figure Typical Linearity Error CS5510. Figure Typical Linearity Error CS5512. Figure Data Word Timing CS5510. Figure Data Word Timing CS5511. Figure Data Word Timing CS5512. Figure Data Word Timing CS5513. Figure Digital Filter Response.
LIST TABLES
Table CS5512/13 Output Conversion Data Register Description (Flags bits). Table CS5510/11 Output Conversion Data Register Description (Flags bits). Table CS5510/11/12/13 Output Coding. Table Digital Filter Response 32.768 kHz.
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CHARACTERISTICS SPECIFICATIONS
ANALOG CHARACTERISTICS
±5%; VREF (relative V-); CS5510/12, SCLK 32.768 kHz; CS5511/13, fosc kHz; (Output Word Rate) 53.5 CS5510/12; CS5511/13) (See Note Parameter Accuracy Linearity Error (CS5510/11) Linearity Error (CS5512/13) Missing Codes (CS5510/11) Missing Codes (CS5512/13) Bipolar Offset (CS5510/11) Bipolar Offset (CS5512/13) Offset Drift Over Temperature Gain Drift Over Temperature Analog Input Common Mode Signal AIN+ AINDual Supply Input Range (Bipolar) Common Mode Rejection Input Capacitance Current AIN+, AIN(Note |(AIN+ AIN-)/(VREF V-)| 60Hz (CS5510/12) VREF (Note (Note (Notes (Note ±0.0015 ±0.0007 ±0.003 ±0.0015 ±100 Bits Bits LSB16 LSB20 nV/°C ppm/°C Unit
Typical Noise (Notes Output Word Rate (Hz) 53.5 Filter Frequency (Hz) 12.5 Noise RMS)
Notes: Specifications guaranteed design, characterization, and/or test. Specification applies device only does include effects external parasitic thermocouples. Drift over specified temperature range after power-up Wideband noise aliased into baseband. Referred input. Typical values shown peak-to-peak noise multiply 6.6. section data sheet which discusses Analog Input Models. CS5511/13, 50%.
Specifications subject change without notice.
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ANALOG CHARACTERISTICS (Continued)
Parameter Voltage Reference Input Range Input Capacitance current Power Supplies Supply Voltages Power Supply Currents {(V+) (V-)} (Note CS5510 CS5511 CS5512 CS5513 CS5510 CS5511 CS5512 CS5513 (Note CS5510 CS5511 CS5512 CS5513 (Note 4.75 5.25 {(VREF) (V-)} (Note 0.250 (V+) (V-) Unit
Power Consumption
Sleep Power Supply Rejection Notes: Positive Supply Negative Supply
VREF referenced must less than equal current through pin, always same value. outputs unloaded. inputs CMOS levels V)). must inactive (logic high) during sleep meet this power specification.
DIGITAL CHARACTERISTICS
±5%; (See Notes 12.) Parameter High-Level Input Voltage: Low-Level Input Voltage: Input Current: High-Level Output Voltage: Low-Level Output Voltage: Input Leakage Current 3-State Leakage Current
SCLK
Symbol
CSLow
0.45
±0.015
(CSLow)
Unit
(Note SCLK (Note SDO, Isource 5.0mA (Note SDO, Isink 1.0mA SCLK SCLK
(V+)
Notes: measurements performed under static conditions. signal provides sink current path when low. external drive logic therefore, must able handle logic-low current drive levels devices attached SDO. voltage specified relative CSLow. Section 2.3.1, "Digital Logic Levels" Figure more details.
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DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Output Word Rate Filter Settling Time (Full Scale Step) CS5510/12 CS5511/13 CS5510/12 CS5511/13 Symbol Ratio SCLK/4 fosc/4 SCLK/612 fosc/612 4/OWR Units
ABSOLUTE MAXIMUM RATINGS
(See Note 15.) Parameter Power Supplies (Note Positive Negative (Notes (Note pins Symbol VIIN IOUT VINA VIND Tstg -0.3 -6.0 (V-)+(-0.3) (V-)+(-0.3) +6.0 +0.3 (V+)+0.3 (V+)+0.3 +150 Unit
Input Current, Except Supplies Output Current Package Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: voltages with respect must satisfy 0.0V {(V+) (V-)} +6.0 Applies pins including continuous overvoltage conditions analog input (AIN) pins. Transient current will cause latch-up. Maximum input current power supply Total power dissipation, including input currents output currents. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
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SWITCHING CHARACTERISTICS CS5510/12
±5%; Input Levels: Logic Logic Parameter Master Clock Timing Master Clock Frequency (CS5510) Master Clock Frequency (CS5512) Master Clock Duty Cycle Rise Times (Note SCLK (Note SCLK trise tfall 32.768 32.768 2000 (Note SCLK (Note SCLK 32.768 32.768 Symbol Unit
Fall Times
Serial Port Timing Serial Clock Frequency (CS5510) Serial Clock Frequency (CS5512) SCLK High Enter Sleep SCLK Exit Sleep Serial Clock Read Timing
Data Valid
(Note SCLK (Note SCLK (Note Pulse Width High Pulse Width tSLP (Note tWAKE
SCLK Falling Data
Rising Hi-Z Falling SCLK Rising
Notes: Device parameters specified with 32.768 clock; however, clocks (CS5510) (CS5512) used increased throughput. Higher clock rates will result degraded linearity specifications, shown Figures Specified using points waveform interest. Output loaded with CS5510/12, serial clock input (SCLK) provides master clock operate converter well serial data clock used read conversion data. SCLK held high (logic tSLP longer, CS5510/12 enters sleep. exit from sleep mode, SCLK must held (logic tWAKE longer.
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SWITCHING CHARACTERISTICS CS5511/13
±5%; Input Levels: Logic Logic Parameter Internal Oscillator Timing Internal Oscillator Frequency Internal Oscillator Drift Over Temperature Serial Port Timing Serial Clock Frequency SCLK High Enter Sleep SCLK Exit Sleep Rise Times (Note SCLK (Notes (Note SCLK (Note SCLK Pulse Width High Pulse Width tSLP trise tfall (Notes tWAKE 2000 (Note fosc -0.02 %/°C Symbol Unit
Fall Times
Serial Clock Read Timing
Data Valid
SCLK Falling Data
Rising Hi-Z Falling SCLK Rising
Notes: internal oscillator CS5511/13 provides master clock performing conversions. Data retrieved from serial port using SCLK input pin. minimum SCLK rate CS5511/13 assumes that SCLK logic when idle. When data being read from ADC, SCLK must burst minimum rate with minimum percent duty cycle. Rates slower than this potentially into sleep sleep mode entered after SCLK logic tSLP time. CS5511/13, serial clock (SCLK) used transfer data from CS5511/13. SCLK held high (logic tSLP longer, CS5511/13 enters sleep mode. exit from sleep mode, SCLK must held (logic tWAKE longer. Specified using points waveform interest. Output loaded with
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SCLK
Figure Read Timing CS5510/12 (Not Scale).
SCLK
Figure Read Timing CS5511/13 (Not Scale).
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GENERAL DESCRIPTION
CS5510/11/12/13 low-cost, easy-to-use, analog-to-digital converters (ADCs) which charge balance techniques achieve 16-bit (CS5510/11) 20-bit (CS5512/13) performance. ADCs available space-efficient, 8-pin, SOIC package optimized measuring signals weigh scale, process control, other industrial applications. accommodate these applications, ADCs include fourth-order modulator digital filter. When configured with external master clock 32.768 kHz, filter CS5510/12 provides better than simultaneous line rejection, outputs conversion words 53.5 Sps. CS5511/13 include on-chip oscillator which eliminates need external clock source. CS5510/11/12/13 ADCs designed operate from single supply variety dual-supply configurations optimized digitize bipolar signals industrial applications. achieve cost, CS5510/11/12/13 family converters have on-chip calibration features. CS5510/11/12/13 offer very offset drift, gain drift, excellent linearity. ferential voltage reference (VREF V-). This translates typically ±4.0 fully differential when reference voltage between VREF typically ±2.0 fully differential
Note: When smaller reference voltage used, resulting code widths smaller. Since output codes exhibit more changing codes fixed amount noise, converter appears noisier.
2.1.1
Analog Input Model
Figure illustrates input model pins. model includes coarse/fine charge buffer which reduces dynamic current demands from signal source. buffer designed accommodate rail-to-rail (common-mode plus signal) input voltages. Typical (sampling) current about Application Note "Switched-capacitor Input Structures", details various input architectures.
Voltage Reference Input
Analog Input
CS5510/11/12/13 provides differential input span approximately ±(0.80 0.08) times dif-
voltage between VREF pins converter determines voltage reference converter. This voltage great (V+) (V-). VREF connected directly pin. This will establish voltage reference equal (V+) (V-) converter. effective resolution part (noisefree bits single sample with averaging) will vary with VREF. Figure shows VREF voltage affects noise-free resolution
Fine
Coarse 32.768
Figure Input models AIN+ AIN- pins.
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CS5512/13. CS5510/11 follow same curve, limited bits resolution. Note that reference voltage should established prior having supply voltages pins. reference. Typical (sampling) current about (See Figure nominal input span converter defined bipolar span equal ±(VREF V-)*(0.80 ±0.08).
2.2.1
Voltage Reference Input Model
Power Supply Arrangements
Figure illustrates input model VREF pin. includes coarse/fine charge buffer which reduces dynamic current demand exter-
Effective Bits
CS5510/11/12/13 designed operate from single dual supplies. Figure illustrates CS5510/11/12/13 connected with single supply measure differential inputs relative common mode Figure illustrates CS5510/11/12/13 connected with ±2.5 analog supplies measure ground-referenced, bipolar signals. necessary that dual supples ADCs balanced, however, they must five volts. Figure illustrates ADCs configured with +3.3 -1.7 accommodating +3.3 digital supply.
2.3.1
Digital Logic Levels
VREF
Figure CS5512/13 Measured Noise-Free Bits VREF.
many power supply configurations available CS5510/11/12/13 allow wide range digital logic levels. logic-high input output levels determined pin. logic-low output referenced driven current logic-low voltage Since CS5510/11/12/13 include dedicated
Fine
Coarse VREF 32.768
Figure Input model VREF pin.
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+5.0 Supply
Voltage Reference Differential Input VREF)
VREF CS5510/11/12/13 AIN+ AINSCLK
Serial Data Interface
Clock Source (Required CS5510/12 Applications)
Common Mode
Figure CS5510/11/12/13 Configured with +5.0 Analog Supply.
+2.5 Supply
Reference Voltage Differential Input VREF) AINSCLK Common Mode VVREF CS5510/11/12/13
AIN+
Serial Data Interface
Clock Source (Required CS5510/12 Applications)
V-2.5 Supply Implies ground return between supplies.
Figure CS5510/11/12/13 Configured with ±2.5 Analog Supplies.
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+3.3 V/+3.0V Supply
Voltage Reference VREF CS5510/11/12/13
AIN+
V/3.0V
Serial Data Interface
Differential Input VREF)
AIN-
SCLK Common Mode
Clock Source (Required CS5510/12 Applications)
V-1.7 V/-2.0V Supply
Implies ground return between supplies.
Figure CS5510/11/12/13 Configured with +3.3 -1.7 +3.0 -2.0
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ground pin, CSLow defines logic-low level digital interface. Figures illustrate threshold levels CS5510/11/12/13 serial interface (CS, SCLK, SDO). accommodate opto-isolators, SCLK input designed with Schmitt-trigger allow optoisolator with slower rise fall times directly drive pin. Additionally, capable sinking sourcing directly drive opto-isolator LED. will have less than loss drive voltage when sinking sourcing current. shown Figure signal provides sink current path when voltage (i.e. voltage specified relative CSLow.).
2.4.1
External Clock Source CS5510/12
user must provide external (CMOS compatible) clock CS5510/12. clock input SCLK where then divided down provide master clock ADC. output word rate (OWR) CS5510/12 derived from SCLK, equal SCLK/612. Figure illustrates external 32.768-kHz, CMOS-compatible clock oscillator that user might consider. Another clock generation option microcontroller. Some microcontrollers have dedicated timer/counter circuitry which generate clock signal output with software overhead. Such microcontroller circuit shown Figure Note that CS5510 operate with external, CMOS-compatible clock frequencies kHz, CS5512 operate with external clock with maximum jitter. Linearity performance degraded slightly with higher clock speeds, shown Figures noise performance parts, however, affected higher clock speeds.
Clock Generator
CS5510/12 CS5511/13 provide distinct modes generating master clock ADCs. CS5510/12 uses SCLK input operating clock. CS5511/13 on-chip oscillator that provides master clock. SCLK CS5511/13 used only read data part into sleep mode.
2.4.2
Internal Oscillator CS5511/13
0.45V 0.6V
CS5511/13 includes on-chip oscillator. This oscillator provides master clock
Output Drive Logic
Figure SCLK Digital Input Levels.
Source
(from Control Logic)
VOH= 0.6V
Sink
0.6V
Control Logic)
Figure Digital Output Levels.
Figure Serial Port Output Drive Logic.
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5.25 Fairchild NC7SU04 74HCU04 SCLK
Counter/Timer
SCLK
49.9
CS5510/12
32.768
Figure External (CMOS Compatible) Clock
Figure Using Microcontroller Clock
CS5511/13 oscillates kHz. output word rate (OWR) CS5511/13 derived from internal oscillator, equal fosc/612. part-to-part variances oscillator frequency, CS5511/13 vary between Sps.
Performing Conversions
After power clock source established CS5510/11/12/13, ADCs begin performing conversions. three sections that follow explain
read conversion data from each ADC, decode conversion word into respective flag data bits. Keep mind that CS5510/12, SCLK provides external clock source converter. Data clocked from CS5510/12 rate external clock source (typically 32.768 kHz). CS5511/13 provides on-chip oscillator master clock. CS5511/13, SCLK asynchronous onchip oscillator clocked rate MHz.
0.004 Linearity Error (%FS)
0.003 Linearity Error (%FS) 0.0025 0.002 0.0015 0.001 0.0005 SCLK (kHz) SCLK
SCLK
0.0035 0.003 0.0025 0.002 0.0015 0.001 0.0005 SCLK (kHz)
Figure Typical Linearity Error CS5510.
Figure Typical Linearity Error CS5512.
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2.5.1 Reading Conversions CS5510/12
conversion word when conversion data available.
After power-up, CS5510/12 will begin converting once clock source applied SCLK pin. When conversion completed, there data output register, line will fall logic-low level also logic-low state (SDO will always high-impedance when high). conversion cycle, will fall rising edge SCLK. After SCLK falls, next SCLK cycle (high, then low) will begin clocking data. first data therefore, SCLK cycles wide. Twenty-four SCLK cycles (after initial high-low transition) needed retrieve conversion word from device (see Figures 17). data bits read rising edge SCLK, next data output falling edge SCLK. Once entire data word been read, will return logic-high state until there conversion word available. logic-high conversion cycle, data will shifted part until brought logic-low state during next conversion cycle. conversion becomes available while current data being read, data register will updated, conversion word will lost. user need read every conversion. user chooses read conversion, should remain logic-high state duration conversion cycle. Note that goes logic-high state during read, current conversion data will lost replaced
2.5.2
Reading Conversions CS5511/13
After power-up, CS5511/13 begins converting updating output register. When there data output register conversion cycle) line will fall logic-low level also logic-low state (SDO will always high-impedance when high). Twenty-four SCLK cycles needed retrieve conversion word from device (see Figures 19). data bits read rising edge SCLK, next data output falling edge SCLK. Once entire data word been read, will return logic-high state until there conversion word available. conversions become available while current data being read, data register will updated, conversions will lost. user need read every conversion. user chooses read conversion after falls, will rise seventeen oscillator clock cycles internal oscillator) before next conversion word available then fall again signal that conversion complete. Note that conversion word read before next conversion word ready, goes logic-high state during read, current conversion data will lost replaced conversion word when conversion data available.
Figure Data Word Timing CS5510. DS337F4
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2.5.3 Output Coding
bits conversion data, which output first (Table Bits D22-D21 flag bits. (Overrange Flag) logic time input signal more positive than positive full scale, more negative than negative full scale. cleared back logic whenever conversion word occurs which overranged. (Oscillation Detect) logic time that oscillatory condition detected modulator. This does occur under normal operating conditions, occur whenever input converter
shown Tables CS5510/11/12/13 present output conversions 24-bit conversion words. first conversion word indicates that conversion done through falling from logic high logic level. first fourth bits output will always zero. second third bits error flags, representing overflow oscillation condition. CS5510/11, there four more bits zero, remaining bits conversion data, output first (Table CS5512/13, final
SCLK
Figure Data Word Timing CS5511.
Figure Data Word Timing CS5512.
Figure Data Word Timing CS5513.
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Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 Two's Complement (20-Bit) 7FFFF 7FFFF -7FFFE 00000 -FFFFF 80001 -80000 Two's Complement (16-Bit) 7FFF 7FFF -7FFE 0000 -FFFF 8001 -8000
-0.5
-VFS+0.5
Note: table equals voltage between AIN+ AIN-. text about error flags under overrange conditions. Table CS5510/11/12/13 Output Coding.
cessively overranged. set, conversion data bits completely erroneous. flag will cleared logic four output words after modulator becomes stable again. flag occur independent with spike input. Both flag bits should tested overrange condition occurs. Table illustrates output coding CS5510/11/12/13. Conversions output two's complement values representing bipolar input signals.
2.5.4
Digital Filter
CS5510/11/12/13 have modified Sinc4 digital filter that provides CLK/612 conversion rates
(CLK represents SCLK CS5510/12 internal oscillator CS5511/13). filters optimized yield better than rejection between (i.e. minimum rejection both when master clock 32.768 kHz. filter response shown Figure Table shows filter response frequencies from Note that response CS5511/13 will similar, frequencies scale with on-chip oscillator's frequency, which from (i.e. conversion rates vary between Sps). Further note that after initial power after returning from sleep mode, filter requires four conversion cycles produce
Table CS5512/13 Output Conversion Data Register Description (Flags bits).
Table CS5510/11 Output Conversion Data Register Description (Flags bits). DS337F4
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CS5510/12 SCLK 32.768
Magnitude (dB)
-100
-120 -140
Frequency (Hz)
Figure Digital Filter Response.
Frequency (Hz)
Rejection (dB)
Frequency (Hz)
Rejection (dB)
Frequency (Hz)
Rejection (dB)
Frequency (Hz)
Rejection (dB)
Table Digital Filter Response 32.768 kHz.
valid conversion modified Sinc4 filter characteristics.
2.5.5
Multiplexed Applications
settling performance CS5510/11/12/13 multiplexed applications determined Sinc4 filter. settle, step input requires full conversion cycles after analog input switched. this case, throughput reduced factor four first three conversions after step applied will fully settled. application does require maximum throughput possible from ADC, multiplexer switched time. this case, system must wait least five conversion cycles fully-settled result from ADC.
maximum throughput required multiplexed application, multiplexer must switched correct time during data collection process. maximum throughput with CS5510/12, switching multiplexer should occur SCLK cycles after falls. maximum throughput with CS5511/13, switching multiplexer should occur rising edge during conversion which data word read. conversion data that immediately available when falls again valid, represents analog input from previous multiplexer setting. next three conversions from part will unsettled values, fourth conversion will represent fully-settled result from multiplexer setting. multiplexer should switched again appro-
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priate time during third conversion cycle ensure maximum possible throughput. will equivalent 0x7FFF*Vcal/(0.80*Vref) CS5510/11, 0x7FFFF*Vcal/(0.80*Vref) CS5512/13. gain error (GE) equal ZP)/Ci. correct both offset gain error subsequent conversions, subtract offset error, then divide gain error.
Digital Off-chip System Calibration
CS5510/11/12/13 exhibit excellent linearity with offset gain drift, without need calibration. precision voltage measurements required system, however, software-based offset gain calibration performed system. perform software offset calibration, "zeropoint" system should established applying input system equal zero. Then, user obtain conversion store memory system's zero point (ZP). This number then used zero point subsequent conversion words. 20-bit devices (CS5512 CS5513), multiple conversions averaged arrive more accurate offset value. 16-bit devices (CS5510 CS5511), averaging meaningful, because noise will below size when using nominal voltages VREF (2.5 software gain calibration performed bringing system known calibration Voltage value (Vcal) acquiring conversion (note that Vcal should enough compensate possible gain error ADC). Multiple conversions averaged this point improve accuracy calibration. code obtained from this conversion real value (Cr) calibration Voltage input, will differ from ideal value. ideal value this conversion (Ci)
Power Consumption, Sleep Reset
CS5510/11/12/13 accommodates power modes: normal sleep. normal mode default mode entered after power established ADC. normal mode, ADCs typically consumes Sleep entered when user leaves SCLK high least ADCs guaranteed sleep after SCLK high (logic sleep mode reduces consumed power less than when high (logic (logic this time, drive logic will still active, consumed sleep power will greater. exit sleep return normal mode, user must return SCLK least After sleep exited, ADCs reset their internal logic, including their digital filters, begin performing conversions. Since filters reset, first three conversion after returning normal mode will fully settled.
Layout
CS5510/11/12/13 should placed entirely over analog ground. Place analog-digital plane split immediately adjacent digital pins chip.
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DESCRIPTIONS
VREF AIN+ AINCS SCLK
Control Pins Serial Data
Chip Select,
dual function pin, which determines state SDO, well digital logic-low output level. When low, will active. When high, will output high-impedance state. logic-low level will match active-low voltage
Serial Data Output,
serial data output. will output high-impedance state logic-low level will match active-low voltage
SCLK Serial Clock Input,
SCLK serial bit-clock which controls shifting data from ADCs. This input goes through Schmitt trigger allow slow rise fall time signals. held high, device will enter sleep mode. CS5510/12, this input also used master clock source which determines conversion speeds throughput. CS5511/13, SCLK only used read conversion data part sleep mode.
Measurement Reference Inputs
AIN+, AIN- Differential Analog Input, Pins
Differential input pins into device
VREF Voltage Reference Input,
Input Voltage which establishes voltage reference, with respect on-chip modulator
Power Supply Connections
Positive Power,
Positive supply voltage
Negative Supply,
Negative supply voltage
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SPECIFICATION DEFINITIONS
Linearity Error
deviation code from straight line which connects points Converter transfer function. point located below first code transition other point located beyond code transition ones. Units percent full-scale.
Differential Nonlinearity
deviation code's width from ideal width. Units LSBs.
Full Scale Error
deviation last code transition from ideal [{(VREF) (V-)} LSB]. Units LSBs.
Bipolar Offset
deviation mid-scale transition (111.111 000.000) from ideal (1/2 below voltage AIN- pin). Units LSBs.LK
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ORDERING INFORMATION
Device Number CS5510-ASZ CS5511-ASZ CS5512-BSZ CS5513-BSZ Oscillator External Internal External Internal Resolution Bits Linearity Error (Max) Temperature Range ±0.003% -40°C +85°C Bits ±0.0015% 8-pin SOIC Lead-free Package
ENVIRONMENTAL, MANUFACTURING, HANDLING INFORMATION
Model Number CS5510-ASZ CS5511-ASZ CS5512-BSZ CS5513-BSZ Days Peak Reflow Temp Rating* Floor Life
(Moisture Sensitivity Level) specified IPC/JEDEC J-STD-020.
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PACKAGE DIMENSIONS
SOIC (208 BODY) PACKAGE DRAWING
SEATING PLANE
0.076 0.004 0.013 0.006 0.206 0.204 0.040 0.302 0.019
INCHES 0.080 0.007 0.016 0.008 0.208 0.208 0.050 0.310 0.025
0.084 0.010 0.020 0.010 0.210 0.212 0.060 0.318 0.030 EIAJ PACKAGE
1.93 0.10 0.33 0.15 5.23 5.18 1.02 7.67 0.48
MILLIMETERS 2.03 0.175 0.406 0.20 5.28 5.28 1.27 7.88 0.64
2.13 0.25 0.51 0.25 5.33 5.38 1.52 8.08 0.76
Controlling Dimension Inches
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REVISION HISTORY
Date 2005 2005 2009 Changes Added lead-free (Pb) device ordering information. Updated lead-free (Pb) device ordering information. Added data. Removed devices containing lead (Pb) from ordering information.
Revision
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Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
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DS337F4

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