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CYRF6936
WirelessUSBLP Radio
Direct Sequence Spread Spectrum (DSSS) radio transceiver Operates unlicensed worldwide Industrial, Scientific Medical (ISM) band (2.400 GHz-2.483 GHz) operating current (Transmit dBm) Transmit power Receive sensitivity Sleep Current Operating range: 10m+ DSSS data rates kbps, GFSK data rate Mbps external component count Auto Transaction Sequencer (ATS) intervention Framing, Length, CRC16, Auto Power Management Unit (PMU) MCU/Sensor Fast Startup Fast Channel Changes Separate 16-byte Transmit Receive FIFOs AutoRate- dynamic data rate reception Receive Signal Strength Indication (RSSI) Serial Peripheral Interface (SPI) control while sleep mode microcontroller interface Battery Voltage Monitoring Circuitry Supports coin-cell operated applications Operating voltage from 1.8V 3.6V Operating temperature from 70°C Space saving 40-pin package
Applications
Wireless Keyboards Mice Wireless Gamepads Remote Controls Toys VOIP Wireless Headsets White Goods Consumer Electronics Home Automation Automatic Meter Readers Personal Health Entertainment
Applications Support
www.cypress.com development tools, reference designs, application notes.
Functional Description
CYRF6936 WirelessUSBLP radio second generation member Cypress's WirelessUSB Radio System-On-Chip (SoC) family. CYRF6936 interoperable with first generation CYWUSB69xx devices. CYRF6936 adds range enhanced features, including increased operating voltage range, reduced supply current operating modes, higher data rate options, reduced crystal start synthesizer settling link turnaround times.
CYRF6936 Simplified Block Diagram
VBAT VREG PACTL RFBIAS
Power Management
GFSK Modulator
MISO MOSI
Data Interface Sequencer RSSI
DSSS Baseband Framer GFSK Demodulator
Xtal XTAL XOUT
Synthesizer Block Diagram
Cypress Semiconductor Corporation Document 38-16015 Rev.
Champion Court
Jose, 95134-1709
408-943-2600 Revised April 2007
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CYRF6936
Descriptions
Name Type Default RFBIAS PACTL XTAL XOUT MISO MOSI Description Differential signal to/from antenna Differential signal to/from antenna 1.8V reference voltage Control signal external switch, GPIO crystal Buffered 0.75, 1.5, clock, PACTL, GPIO. Tri-states sleep mode (configure GPIO drive LOW) clock data output (Master Slave Out), GPIO 3-pin mode). Tri-states when 3PIN deasserted data input (Master Slave In), SDAT enable, active assertion. Enables frames transfers Interrupt output (configurable active HIGH LOW), GPIO Device reset. Internal kohm pull down resistor. Active HIGH, typically connect through 0.47 capacitor VBAT. Must have event first time power applied radio. Otherwise state radio control registers unknown inductor/diode connection, when used. used, connect boosted output voltage feedback Decoupling 1.8V logic regulator, connect through 0.47 capacitor VBAT 1.8V 3.6V. Main supply 2.4V 3.6V. Typically connected VREG interface voltage, 1.8-3.6V Must connected Connect Ground Ground
VREG VBAT RESV
E-PAD
Figure CYRF6936, View
CYRF6936 View*
VREG XTAL VBAT VBAT BIAS RESV VBAT
PACTL GPIO XOUT GPIO MISO GPIO MOSI SDAT
CYRF6936 40-lead
GPIO
E-PAD BOTTOM SIDE
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CYRF6936
Functional Overview
CYRF6936 provides complete WirelessUSB antenna wireless MODEMs. designed implement wireless device links operating worldwide frequency band. intended systems compliant with worldwide regulations covered ETSI 489-1 V1.41, ETSI 328-1 V1.3.1 (Europe), Part (USA Industry Canada) TELEC ARIB_T66_March, 2003 (Japan). contains GHz, Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), interface data transfer device configuration. radio supports discrete channels (regulations limit some these channels certain jurisdictions). baseband performs DSSS spreading/despreading, Start Packet (SOP), Packet (EOP) detection, CRC16 generation checking. baseband also configured automatically transmit Acknowledge (ACK) handshake packets whenever valid packet received. When receive mode, with packet framing enabled, device always ready receive data transmitted supported rates, enabling implementation mixed-rate systems which different devices different data rates. This also enables implementation dynamic data rate systems that high data rates shorter distances low-moderate interference environment both, change lower data rates longer distances high interference environments both. addition, CYRF6936 Power Management Unit (PMU), which allows direct connection device battery voltage range 1.8V 3.6V. conditions battery voltage provide supply voltages required device, supply external devices. Data Transmission Modes supports four different data transmission modes: GFSK mode, data transmitted Mbps, without DSSS. mode, eight bits encoded each derived code symbol transmitted. mode, bits encoded each derived code symbol transmitted. CYWUSB6934 mode). mode, encoded each derived code symbol transmitted. CYWUSB6934 standard modes.)
Both chip chip Pseudo Noise (PN) codes supported. four data transmission modes apply data after SOP. particular length, data, CRC16 sent same mode. general, lower data rates reduce packet error rate given environment. Link Layer Modes CYRF6936 device supports following data packet framing features: Packets begin with two-symbol Start Packet marker. This required GFSK modes, optional mode supported mode; framing disabled then event inferred whenever successive correlations detected. SOP_CODE_ADR code used different from that used "body" packet, desired different length. must configured same length both sides link. Length There options detecting packet. enabled, then length field should enabled. GFSK must enable length field. This first eight bits after symbol, transmitted payload data rate. When length field enabled, Packet condition inferred after reception number bytes defined length field, plus bytes CRC16 (when enabled-see following paragraph). alternative using length field infer condition from configurable number successive noncorrelations; this option available GFSK mode only recommended when using mode. CRC16 device configured append CRC16 each packet. CRC16 uses polynomial with added programmability seed. enabled, receiver verifies calculated CRC16 payload data against received value CRC16 field. seed value CRC16 calculation configurable, CRC16 transmitted calculated using either loaded seed value zero seed; received data CRC16 checked against both configured zero CRC16 seeds. CRC16 detects following errors: error bits error matter apart, which column, number bits error matter where they are) error burst wide checksum itself Figure shows example packet with SOP, CRC16 lengths fields enabled, Figure page shows standard packet.
Figure Example Packet Format
16us
Packet
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CYRF6936
Figure Example Packet Format
16us
Packet Buffers data transmission reception uses byte packet buffers-one transmission reception. transmit buffer allows complete packet bytes payload data loaded burst transaction, then transmitted with further intervention. Similarly, receive buffer allows entire packet payload data bytes received with firmware intervention required until packet reception complete. CYRF6936 supports packets bytes. However, actual maximum packet length depends accuracy clock each link data mode; interrupts provided allow transmit receive buffers FIFOs. When transmitting packet longer than bytes, load bytes initially, further bytes transmit buffer transmission data creates space buffer. Similarly, when receiving packets longer than bytes, must fetch received data from FIFO periodically during packet reception prevent from overflowing. Auto Transaction Sequencer (ATS) CYRF6936 provides automated support transmission reception acknowledged data packets. When transmitting transaction mode, device automatically: Starts crystal synthesizer Enters transmit mode Transmits packet transmit buffer Transitions receive mode waits packet Transitions transaction state when either packet received, timeout period expires Similarly, when receiving transaction mode, device automatically: Waits receive mode valid packet received Transitions transmit mode, transmits packet Transitions transaction state (receive mode await next packet, on.) contents packet buffers affected transmission reception packets. each case, entire packet transaction takes place without need firmware action long packets bytes less used); transmit data simply must load data packet transmitted, length, bit. Similarly, when receiving packets transaction mode, firmware simply must retrieve fully received packet
response interrupt request indicating reception packet. Backward Compatibility CYRF6936 fully interoperable with main modes first generation devices. 62.5 kbps mode supported selecting chip mode. Similarly, 15.675 kbps mode supported selecting chip mode. this way, suitably configured CYRF6936 device transmit data receive data from first generation device, both. Backwards compatibility requires disabling SOP, length, CRC16 fields. Data Rates combining code lengths data transmission modes described previously, CYRF6936 supports following data rates: 1000 kbps (GFSK) kbps chip 8DR) kbps chip 8DR) 62.5 kbps chip DDR) 31.25 kbps chip DDR) 15.625 kbps chip SDR)
Functional Block Overview
Radio radio transceiver dual conversion architecture optimized power range/robustness. radio employs channel-matched filters achieve high performance presence interference. integrated Power Amplifier (PA) provides transmit power, with output power control range seven steps. supply current device reduced output power reduced. Table Internal Output Power Step Table Setting Typical Output Power (dBm) Page
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CYRF6936
Table Typical Range Observed Table Environment Outdoor Office Home Typical Range (meters)
bits address. Eight bits data. device receives from application pin. Data from application shifted MOSI pin. Data application shifted MISO pin. active Slave Select (SS) must asserted initiate transfer. application initiate data transfers using multi-byte transaction. first byte Command/Address byte, following bytes data bytes shown Figure through Figure page communications interface burst mechanism, where first byte followed many data bytes desired. burst transaction terminated deasserting slave select communications interface single read burst read sequences shown Figure Figure respectively. communications interface single write burst write sequences shown Figure Figure respectively. This interface optionally operated 3-pin mode with MISO MOSI functions combined single bidirectional data (SDAT). When using 3-pin mode, user firmware should ensure that MOSI high impedance state except when MOSI actively transmitting data. device registers written read from byte time, several sequential register locations written/read single transaction using incrementing burst mode. addition single byte configuration registers, device includes register files; register files FIFOs written read from using nonincrementing burst transactions. function optionally multiplexed onto MOSI pin; when this option enabled function available while LOW. When using this configuration, user firmware should ensure that MOSI high impedance state whenever HIGH. interface dependent internal clock. Registers therefore read from written while device sleep mode, oscillator disabled. interface pins have separate voltage reference (VIO), enabling device interface directly MCUs operating voltages below CYRF6936 supply voltage.
Note: Range observed with CY4636 WirelessUSB v1.0 (Keyboard)
Frequency Synthesizer Before transmission reception begin, frequency synthesizer must settle. settling time varies depending channel; fast channels provided with maximum settling time `fast channels' (less than settling time) every third channel, starting including (for example, 9.69, 72). Baseband Framer baseband framer blocks provide DSSS encoding decoding, generation reception CRC16 generation checking, well detection length field. Packet Buffers Radio Configuration Registers Packet data configuration registers accessed through interface. configuration registers directly addressed through address field packet CYWUSB6934). Configuration registers allow configuration DSSS codes, data rate, operating mode, interrupt masks, interrupt status, Interface CYRF6936 interface supporting communications between application more slave devices (including CYRF6936). interface supports single-byte multi-byte serial transfers using either 4-pin 3-pin interfacing. communications interface consists Slave Select (SS), Serial Clock (SCK), Master Out-Slave (MOSI), Master In-Slave (MISO), Serial Data (SDAT). communications follows: Command Direction (bit enables write transaction. enables read transactions. Command Increment (bit enables auto address increment. When set, address field automatically increments each data byte burst access, otherwise same address accessed.
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CYRF6936
Figure Transaction Format
Byte Name [5:0] Address Byte [7:0] Data
Figure Single Read Sequence
addr
MOSI MISO
data
Figure Incrementing Burst Read Sequence
addr
MOSI MISO
data mcu1
data mcu1+N
Figure Single Write Sequence
addr
data from
MOSI MISO
Figure Incrementing Burst Write Sequence
addr
data from mcu1
data from mcu1+N
MOSI MISO
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CYRF6936
Interrupts device provides interrupt (IRQ) output, which configurable indicate occurrence various different events. programmed either active HIGH active LOW, either CMOS open drain output. full description available interrupts found "Register Descriptions" page CYRF6936 features three sets interrupts: transmit, receive, system interrupts. These interrupts share single (IRQ), independently enabled/disabled. contents enable registers preserved when switching between transmit receive modes. more than interrupt enabled time, necessary read relevant status register determine which event caused assert. Even when given interrupt source disabled, status condition that would otherwise cause interrupt determined reading appropriate status register. therefore possible devices without polling status registers wait event, rather than using pin. Clocks crystal better) directly connected between XTAL without need external capacitors. digital clock function provided, with selectable output frequencies 0.75, 1.5, MHz. This output used clock external microcontroller (MCU) ASIC. This output enabled default, disabled. Listed below requirements crystal directly connected XTAL GND. Nominal Frequency: Operating Mode: Fundamental Mode Resonance Mode: Parallel Resonant Frequency Initial Stability: Series Resistance: ohms Load Capacitance: Drive Level: µW-100 Power Management operating voltage device 1.8V 3.6V which applied VBAT pin. device shut down fully static sleep mode writing STATE bits XACT_CFG_ADR register over interface. device enters sleep mode within after last positive edge this transaction. Alternatively, device configured automatically enter sleep mode after completing packet transmission reception. When sleep mode, on-chip oscillator stopped, interface remains functional. device wakes from sleep mode automatically when device
commanded enter transmit receive mode. When resuming from sleep mode, there short delay while oscillator restarts. device configured assert when oscillator stabilized. output voltage (VREG) Power Management Unit (PMU) configurable several minimum values between 2.4V 2.7V. VREG used provide (average load) external devices. possible disable PMU, provide externally regulated supply voltage device's main supply range 2.4V 3.6V. also provides regulated 1.8V supply logic. designed provide high boost efficiency (74-85% depending input voltage, output voltage load) when using Schottky diode power inductor, eliminating need external boost converter many systems where other components require boosted voltage. However, reasonable efficiencies (69-82% depending input voltage, output voltage, load) achieved when using cost components such SOT23 diodes 0805 inductors. also provides configurable battery detection function, which read over interface. seven thresholds between 1.8V 2.7V selected. interrupt configured assert when voltage VBAT falls below configured threshold. latched event. Battery monitoring disabled when device sleep mode. Noise Amplifier Received Signal Strength Indication gain receiver controlled directly clearing writing Noise Amplifier (LNA) RX_CFG_ADR register. Clearing reduces receiver gain approximately allowing accurate reception very strong received signals (for example when operating receiver very close transmitter). Approximately receiver attenuation added setting Attenuation (ATT) bit; this allows data reception limited devices very short ranges. Disabling enabling recommended unless receiving from device using external When device receive mode RSSI_ADR register returns relative signal strength on-channel signal power. When receiving, device automatically measures stores relative strength signal being received five value. RSSI reading taken automatically when detected. addition, RSSI reading taken every time previous reading read from RSSI_ADR register, allowing background energy level given channel easily measured when RSSI read when signal being received. reading occur fast once every
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power supply decoupling shown VBAT0 recommended cost effective configuration: C6=No Load 1ohm C7=10uF ceramic. this configuration, required that installed.
VBAT
0402
0805
0402
0805
alternate decoupling configuration following: C6=47uF ceramic R2=0ohm C7=.047uF. this configuration, required load C18.
0.047 6.3V 0.047
Application Examples
Radio Decoupling Caps
reference design part numbers, please refer Bill Materials file 121-26504_A.xls.
0402
0.047
0402
0402
0.047
0402
0402
0.047
0402
0.01
0.01
0.47 VBAT
VDD2 VDD1
BIND
0402
CYRF6936
0402
VBAT2 VBAT1 VBAT0
VREG
RFbias
0.47
VCC1 VCC2 VCC3
IND0402
PUSHBUTTON
P1_0 P1_1 MOSI MISO P1_0 P1_1 P1_2 P1_3 SSEL P1_4 SCLK P1_5 SMOSI P1_6 SMISO P1_7 MOSI MISO MOSI MISO PACTL XTAL ROW1 ROW2 ROW3 ROW4 ROW5 ROW6 ROW7 ROW8 P0_0 CLKIN P0_1 CLKOUT P0_2 INT0 P0_3 INT1 P0_4 INT2 P0_5 TIO0 P0_6 TIO1 P0_7 COL1 COL2 COL3 COL4 COL5 COL6 COL7 COL8
0402
PACTL
0402
0402
COL9 COL10 COL11 COL12 COL13 COL14 COL15 COL16 P3_0 P3_1 P3_2 P3_3 P3_4 P3_5 P3_6 P3_7 P2_0 P2_1 P2_2 P2_3 P2_4 P2_5 P2_6 P2_7
XOUT
CLKOUT
Crystal
COL17 COL18 P4_0 P4_1 P4_2 P4_3
Serial debug header
VSS2 VSS1
RESV NC10 NC11 NC12 NC13 NC14 NC15 NC16
GND1
CY7C60123-PVXC
E-PAD
E-PAD must soldered ground.
VBAT
SOT23
BAT400D
0805
1210
Load
EVCC 6.3V
0603
LOAD
ISSP
P1_0 P1_1
Figure Recommended Circuit Systems Where VBAT Fall Below 2.4V
2-pin jumper installed from J3.1 J2.1 enables radio power processor. Jumper removal required when programming disconnect radio from Miniprog source. XRES SCLK SDATA
CYRF6936
zero resistor that should installed production units only, following programming.
Layout J2.1 0.100" spacing configuration
Document 38-16015 Rev.
0.047 6.3V EVCC
Buffer Filter
0402
0402
ANT1 WIGGLE
IND0603
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CYRF6936
Table Recommended Bill Materials Systems Where VBAT Fall Below 2.4V Item Part Number
730-10012 730-11955 730-11398 730R-13322 730-13037 730-13400 730-13404 730-11952 710-13201 730-10794 730-13036 800-13248 420-11964 420-11496 800-13401 800-11651 800-13253 610-13402 620-10539 630-11356 CYRF6936-40LFC CY7C60323-PVXC 800-13259 PDC-9302-*C 920-11206 920-30200
Reference
ANT1 C5,C17 C12,C7 C9,C10,C11, C13,C15,C16
Description
2.5GHZ H-STUB WIGGLE ANTENNA 63MIL CERAMIC 0402 1.5PF CERAMIC 0402 0.47UF 6.3V 0402
Manufacturer
Part Number
ECJ-0EC1H150J C0402C209C5GACTU ECJ-0EC1H1R5C GRM155R60J474KE19D C0805C106K9PACTU ECJ-0EB0J105M 0402YD473KAT2A C0402C104K8PACTU EEU-FC1A101S ECJ-0EB1C103K C0603C105K8PACTU SS12 103185-1 103185-5 ELJ-RE22NGF2 ELJ-RF1N8DF CDH53100LC ERJ-2GEJ470X ERJ-3GEYJ104V 9C06031A5R11FGHFT 9C08052A1R00FKHFT
15PF CERAMIC 0402 Panasonic Kemet PANASONIC Murata
CERAMIC 10UF 6.3V 0805 Kemet 6.3V CERAMIC 0402 Panasonic 0.047 CERAMIC 0402 100UF ELECT
CERAMIC 0402 Kemet Panasonic Panasonic
C20,C23,C24,C2 10000PF CERAMIC 0402 C26,C27,C28 R6,R7,R8 LABEL1 LABEL2 DIODE SCHOTTKY HEADER 0.230 MODII 0.100CL
CERAMIC 1.0UF 0603 Kemet Taiwan Semiconductor AMP/Tyco
CONN BRKWAY 5POS Division TYCO INDUCTOR 22NH FIXED 0603 INDUCTOR 1.8NH +-.3NH FIXED 0402 COIL 10UH 1.23A UNSHIELDED 1/16W 0402 100K 1/16W 0603 Panasonic Panasonic Sumida Panasonic Panasonic
CHIP 5.11 1/16W 0603 Yageo America 1.00 1/8W 0805 Yageo WIRELESS MICROCONTROLLER SSOP28 CRYSTAL 12.00MHZ HC49 PRINTED CIRCUIT BOARD Serial Number
RADIO QFN-40 Cypress Semiconductor CYRF6936 Cypress Semiconductor CY7C60323-PVXC eCERA GF-1200008
Cypress Semiconductor PDC-9302-*C 121-30200
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1500
0402
0.47
DM/P1_1 DP/P1_0
VBAT2 VBAT1 VBAT0 VREG VCC1 VCC2 VCC3
IND0603
PLUG
IND0402
nLED2 nLED1 RFbias PACTL XTAL
0402
SSEL/P1_3 SCLK/P1_4 MOSI/P1_5 MISO/P1_6
0402
zero MOSI MISO MOSI MISO
P0_0 P0_1 P0_2/INT0 P0_3/INT1 P0_4/INT2 P0_5/TIO0 P0_6/TIO1
0402
MOSI MISO
0402
CY7C63803-SXC
XOUT
TV-20R
Crystal
Green nLED2
"CONNECT/ACTIVITY"
nLED1
GND1 E-PAD
RESV NC10 NC11 NC12 NC13 NC14 NC15 NC16
Figure Recommended Circuit Systems Where VBAT 2.4V 3.6V (PMU disabled)
0402
E-PAD must soldered ground.
"BIND"
PUSH
0402
0.047
0402
0.047
0402
0.047
0402
0.047
0402
0.047
0402
0.047
Power Supply
0805
CYRF6936
0805
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VREG
VBUS
VBUS CYRF6936
0402
ANT1 WIGGLE
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CYRF6936
Table Recommended Bill Materials Systems Where VBAT 2.4V 3.6V (PMU disabled) Item
Part Number
730-10012 730-11955 730-11398 730-13322 730-13404 730-11953 730-13040 730-12003 800-13333 420-13046 800-13401 800-11651 610-10343 610-13472 200-13471 CYRF6936-40LFC CY7C63803-SXC 800-13259 PDC-9263-*B
Reference
ANT1 C6,C7,C8,C9, C10,C11 LABEL1 LABEL2
Description
2.5GHZ H-STUB WIGGLE ANTENNA 32MIL CERAMIC 0402 1.5PF CERAMIC 0402 0.47 6.3V CERAMIC 0402 0.047 CERAMIC 0402 1500PF CERAMIC 0402 CERAMIC 4.7UF 6.3V 0805
Manufacturer
Part Number
ECJ-0EC1H150J C0402C209C5GACTU ECJ-0EC1H1R5C GRM155R60J474KE19D 0402YD473KAT2A C0402C152K5RACTU C0805C475K9PACTU GRM21BR71A225KA01L LTST-C155KGJRKT UAR72-4N5J10 ELJ-RE22NGF2 ELJ-RF1N8DF ERJ-2GE0R00X ERJ-2GEJ621X EVQ-P7J01K
15PF CERAMIC 0402 Panasonic Kemet PANASONIC Murata Kemet Kemet
2.2UF 0805 Murata Electronics North America GREEN/RED BICOLOR 1210 INDUCTOR 22NH FIXED 0603 INDUCTOR 1.8NH +-.3NH FIXED 0402 LITEON
CONN PLUG TYPE ACON Panasonic Panasonic
ZERO 1/16W 0402 Panasonic CHIP 1/16W 0402 Panasonic SWITCH 3.5MMX2.9MM 160GF LOW-SPEED ENCORE CONTROLLER SOIC16 CRYSTAL 12.00MHZ HC49 PRINTED CIRCUIT BOARD Serial Number Panasonic
RADIO QFN-40 Cypress Semiconductor CYRF6936 Cypress Semiconductor CY7C63803-SXC eCERA XXXXXX 121-26305 GF-1200008
Cypress Semiconductor PDC-9263-*B
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CYRF6936
Register Descriptions
registers read writable, except where noted. Registers written read from either individually sequential groups. Table Register Summary
Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 Mnemonic CHANNEL_ADR TX_LENGTH_ADR TX_CTRL_ADR TX_CFG_ADR TX_IRQ_STATUS_ADR RX_CTRL_ADR RX_CFG_ADR 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x26 0x27 0x28 0x29 0x32 0x35 0x39 RX_IRQ_STATUS_ADR RX_STATUS_ADR RX_COUNT_ADR RX_LENGTH_ADR PWR_CTRL_ADR XTAL_CTRL_ADR IO_CFG_ADR GPIO_CTRL_ADR XACT_CFG_ADR FRAMING_CFG_ADR DATA32_THOLD_ADR DATA64_THOLD_ADR RSSI_ADR EOP_CTRL_ADR CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR TX_CRC_LSB_ADR TX_CRC_MSB_ADR RX_CRC_LSB_ADR RX_CRC_MSB_ADR TX_OFFSET_LSB_ADR TX_OFFSET_MSB_ADR MODE_OVERRIDE_ADR RX_OVERRIDE_ADR TX_OVERRIDE_ADR XTAL_CFG_ADR CLK_OVERRIDE_ADR CLK_EN_ADR RX_ABORT_ADR AUTO_CAL_TIME_ADR AUTO_CAL_OFFSET_ADR ANALOG_CTRL_ADR RSVD RSVD RSVD Used Channel Length TXB8 TXB0 IRQEN IRQEN Default[1] -1001000 00000000 00000011 -000101 DATA MODE TXB8 TXB0 TXBERR RXB8 RXB1 RXBERR IRQEN IRQEN IRQEN FAST TURN HILO Used RXB8 RXB1 RXBERR CRC0 Code Count Length Used Used XOUT SETTING IRQEN IRQEN -00000111 10010-10 RXOW Data Mode -00000000 00000000 10100000 000-100 00000000 0000-1-000000 10100101 -0100 -01010 0-100000 10100100 00000000 00000000 -11111111 11111111 00000000 -0000 00000-0 000000000000000 00000000 00000000 00000000 00000000 00000011 00000000 RSVD SLOW 00000000 Access[1] -bbbbbbb bbbbbbbb bbbbbbbb -bbbbbb rrrrrrrr bbbbbbbb bbbbb-bb brrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbb-bbbb bbb-bbb bbbbbbbb bbbbrrrr b-bbbbbb bbbbbbbb -bbbb -bbbbb r-rrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr bbbbbbbb -bbbb wwwww-w bbbbbbbbbbbbbbb wwwwwww wwwwwww wwwwwww wwwwwww wwwwwww wwwwwww wwwwwww wwwwwww rrrrrrrr bbbbbbbb bbbbbbbb bbbbbbbb rrrrrrrr
Used RXOW
Used RSVD SOPDET
TXB15 IRQEN DATA CODE LENGTH TXB15 RXB16 IRQEN RXB16
TXBERR IRQEN
IRQEN
IRQEN
LVIRQ
XOUT XOUT MISO Used Used Used Used Used Used
Mode Force XSIRQ MISO PACTL Used Used HINT
OUTV
Used RSVD RSVD RSVD RSVD RSVD
Used RSVD RXTX RSVD RSVD RSVD RSVD
Used RXACK RSVD RSVD RSVD RSVD ABORT
Used FREQ PACTL PACTL GPIO 3PIN GPIO XOUT MISO PACTL STATE Used TH32 TH64 RSSI SEED SEED STRIM Used STRIM AWAKE Used Used RXDR CRC0 RXCRC Used TXACK OVRD TXCRC RSVD RSVD START RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD
AUTO_CAL_TIME AUTO_CAL_OFFSET RSVD RSVD
Register Files 0x20 TX_BUFFER_ADR 0x21 0x22 0x23 0x24 0x25 RX_BUFFER_ADR SOP_CODE_ADR DATA_CODE_ADR PREAMBLE_ADR MFG_ID_ADR
Buffer File Buffer File Code File Data Code File Preamble File File
-Note Note Note
Notes read/write; read only; write only; used, default value undefined. SOP_CODE_ADR default 0x17FF9E213690C782. DATA_CODE_ADR default PREAMBLE_ADR default 0x333302.
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CYRF6936
Mnemonic Default Read/Write Function Bits Used
CHANNEL_ADR Channel
Address
0x00
Used. This field selects channel. 0x00 sets 2400 MHz; 0x62 sets 2498 MHz. Values above 0x62 valid. default channel fast channel above frequency typically used non-overlapping WiFi systems. write this register impacts time takes synthesizer settle. fast (100 medium (180 slow (270 Usable channels subject regulation. access modify this register during Transmit Receive.
Mnemonic Default Read/Write Function Bits
TX_LENGTH_ADR Length
Address
0x01
This register sets length packet transmitted. length zero valid, transmits packet with SOP, length CRC16 fields enabled), data field. Packet lengths more than bytes require that some data bytes written after transmission packet begun. Typically, length updated prior setting maximum packet length packets bytes except framed chip where maximum packet length bytes.
Maximum packet length limited delta between transmitter receiver crystals better.
Mnemonic Default Read/Write Function
TX_CTRL_ADR TXB15 IRQEN TXB8 IRQEN TXB0 IRQEN TXBERR IRQEN
Address IRQEN
0x02
IRQEN
Start Transmission. Setting this triggers transmission packet. Writing this flag effect. This cleared automatically packet transmission. transmit buffer loaded either before after setting this bit. data loaded after setting this bit, length time available load buffer depends starting state (sleep, idle synth), length code, length preamble, packet data rate. example, starting from idle mode fast channel mode with chip codes time available (synth start) (preamble) (SOP length) (length byte) there bytes buffer transmission length field, TXBERR occurs. Clear Buffer. Writing this register clears transmit buffer. Writing this effect. previous packet fewer bytes) retransmitted setting setting this bit. Buffer Full Interrupt Enable. TX_IRQ_STATUS_ADR description. Buffer Half Empty Interrupt Enable. TX_IRQ_STATUS_ADR description. Buffer Empty Interrupt Enable. TX_IRQ_STATUS_ADR description. Buffer Error Interrupt Enable. TX_IRQ_STATUS_ADR description. Transmission Complete Interrupt Enable. IRQEN IRQEN must together. TX_IRQ_STATUS_ADR description. Transmit Error Interrupt Enable. IRQEN IRQEN must together. TX_IRQ_STATUS_ADR description.
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Mnemonic Default Read/Write Function Used Bits Bits Used
TX_CFG_ADR Data Code Length Data Mode
Address Setting
0x03
Data Code Length. This selects length DATA_CODE_ADR code data portion packet. This ignored when data mode GFSK. chip codes. chip codes. Data Mode. This field sets data transmission mode. 1-Mbps GFSK. Mode. Mode. Mode. recommended that firmware SLOW register ANALOG_CTRL_ADR when using GFSK data rate mode. Setting. This field sets transmit signal strength. dBm, dBm, dBm, dBm, dBm, dBm, dBm, dBm.
Mnemonic Default Read/Write Function
TX_IRQ_STATUS_ADR TXB15 TXB8 TXB0 TXBERR
Address
0x04
state status bits valid regardless whether enabled. output device active state whenever more bits this register corresponding enable also set. Status bits non-atomic (different flags change value different times response single event). Oscillator Stable Status. This when internal crystal oscillator settled (synthesizer sequence starts). Voltage Interrupt Status. This when voltage VBAT below threshold (see PWR_CTL_ADR). This interrupt automatically disabled whenever disabled. When enabled, this reflects voltage VBAT. Buffer Full Interrupt Status. This whenever there fewer bytes remaining transmit buffer. Buffer Half Empty Interrupt Status. This whenever there eight fewer bytes remaining transmit buffer. Buffer Empty Interrupt Status. This time that transmit buffer empty. Buffer Error Interrupt Status. This triggered either events: When transmit buffer (TX_BUFFER_ADR) empty number bytes remaining transmitted greater than zero. When byte written transmit buffer buffer already full. This cleared setting TX_CTRL_ADR. Transmission Complete Interrupt Status. This triggered when transmission complete. transaction mode enabled then this interrupt triggered immediately after transmission last CRC16. transaction mode enabled, this interrupt triggered transaction. Reading this register clears this bit. flags change value different times response single event. transaction mode enabled first read this register returns then firmware must execute second read this register determine error occurred examining status TXE. There case when this triggered when there error transmission. first read this register returns then firmware must execute second read from this register given transaction. received asserted instead IRQ. Transmit Error Interrupt Status. This triggered when there error transmission. This interrupt only applicable transaction mode. triggered whenever valid packet received within timeout period. Reading this register clears this bit. IRQ, above.
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Mnemonic Default Read/Write Function RSVD
RX_CTRL_ADR RXB16 IRQEN RXB8 IRQEN RXB1 IRQEN RXBERR IRQEN
Address IRQEN
0x05
IRQEN
Start Receive. Setting this causes device transition receive mode. necessary, crystal oscillator synthesizer start automatically after this set. Firmware must never clear this bit. This must again until after clears. recommended method exit receive mode when error occurred force STATE then dummy read RX_COUNT_ADR bytes from RX_BUFFER_ADR poll RSSI_ADR.SOP (bit until set. XACT_CFG_ADR RX_ABORT_ADR description. Reserved. Must zero. Buffer Full Interrupt Enable. RX_IRQ_STATUS_ADR description. Buffer Half Empty Interrupt Enable. RX_IRQ_STATUS_ADR description. Buffer Empty Interrupt Enable. RXB1 IRQEN must when RXB8 IRQEN vice versa. RX_IRQ_STATUS_ADR description. Buffer Error Interrupt Enable. RX_IRQ_STATUS_ADR description. Packet Reception Complete Interrupt Enable. RX_IRQ_STATUS_ADR description. Receive Error Interrupt Enable. RX_IRQ_STATUS_ADR description.
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Mnemonic Default Read/Write Function
RX_CFG_ADR HILO FAST TURN Used
Address RXOW
0x06
Status bits non-atomic (different flags change value different times response single event). Automatic Gain Control (AGC) Enable. When this set, enabled, controlled circuit. When this cleared controlled manually using bit. Typical applications clear this during initialization. recommended that this cleared (LNA) unless device used system where receive data from device using external transmit signals more than dBm. Noise Amplifier (LNA) Manual Control. When (Bit cleared, this controls state receiver LNA; when set, this effect. Setting this enables LNA; clearing this disables LNA. Device current receive mode slightly lower when disabled. Typical applications this during initialization. Receive Attenuator Enable. Setting this enables receiver attenuator. receiver attenuator used desensitize receiver that only very strong signals received. This should only when disabled manually disabled. HILO. When FAST TURN set, this used select whether device uses high frequency channel selected, frequency. When FAST TURN enabled this also controls high-low receiver should left default value high side receive injection. Typical applications clear this during initialization. Fast Turn Mode Enable. When this set, HILO determines whether device receives data transmitted above Synthesizer frequency below receiver synthesizer frequency. this mode allows very fast turnaround, because same synthesizer frequency used both transmit receive, thus eliminating synthesizer resettling period between transmit receive. Note that when this set, HILO cleared, received data bits automatically inverted compensate inversion data received `image' frequency. Typical applications this during initialization. Overwrite Enable. When this set, detected while receive buffer empty, then existing contents receive buffer lost, packet loaded into receive buffer. When this set, RXOW enabled. this cleared, then receive buffer overwritten packet, whenever receive buffer empty conditions ignored, possible receive data until previously received packet been completely read from receive buffer. Valid Flag Enable. When this set, receive buffer store eight bytes data. Typically, this only when interoperability with first generation devices desired. RX_BUFFER_ADR more detail.
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Mnemonic Default Read/Write Function RXOW
RX_IRQ_STATUS_ADR SOPDET RXB16 RXB8 RXB1 RXBERR
Address
0x07
state Status bits valid regardless whether enabled. output device active state whenever more bits this register corresponding enable also set. Status bits non-atomic (different flags change value different times response single event). Receive Overwrite Interrupt Status. This triggered when receive buffer overwritten packet being received before previous packet been read from buffer. This cleared writing value this register. This condition only possible when RXOW RX_CFG_ADR set. This must written firmware before packet read from receive buffer. Start packet detect. This whenever start packet symbol detected. Receive Buffer Full Interrupt Status. This whenever receive buffer full, cleared otherwise. Receive Buffer Half Full Interrupt Status. This whenever there eight more bytes remaining receive buffer. Firmware must read exactly eight bytes when reading RXB8 IRQ. Receive Buffer Empty Interrupt Status. This time that there more bytes receive buffer, cleared when receive buffer empty. possible, rare cases, that last byte packet remain buffer even though RXB1 flag cleared. This ONLY happen last byte packet only packet data being read buffer while packet still being received. flag trustworthy under other conditions, bytes prior last. When using RXB1 unloading packet data during reception, user must make sure RX_COUNT_ADR value, after IRQ/RXE IRQ, unload last remaining bytes number bytes unloaded less than reported count, even though RXB1 set. Receive Buffer Error Interrupt Status. This triggered ways: When receive buffer empty there attempt read data When receive buffer full more data received; this flag cleared when received. Packet Receive Complete Interrupt Status. This triggered when packet been received. transaction mode enabled, then this until after transmission ACK. transaction mode enabled then this soon valid packet received. This cleared when this register read. flags change value different times response single event. There cases when this triggered when there error reception. Therefore, firmware should examine IRQ, IRQ, determine receive status. first read this register returns then firmware must execute second read this register determine error occurred examining status IRQ. first read this register returns then firmware must execute second read this register given transaction. Receive Error Interrupt Status. This triggered when there error reception. triggered whenever packet received with CRC16, unexpected detected, packet type (data ACK) mismatch, packet dropped because receive buffer still empty when next packet starts. exact cause error determined reading RX_STATUS_ADR. This cleared when this register read.
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Mnemonic Default Read/Write Function
RX_STATUS_ADR CRC0 Code
Address
0x08
Data Mode
expected that firmware does read this register until after self clears. Status bits non-atomic (different flags change value different times response single event). Packet Type. This when received packet packet, cleared when received packet standard packet. Receive Packet Type Error. This when packet type received what expected cleared when packet type received expected. example, data packet expected received, this set. Unexpected EOP. This when detected before expected data length CRC16 fields have been received. This cleared when pattern next packet been received. This includes case where there invalid bits detected length field length field forced `0'. Zero-seed CRC16. This whenever CRC16 last received packet zero seed. CRC16. This when CRC16 last received packet incorrect. Receive Code Length. This indicates DATA_CODE_ADR code length used last correctly received packet. chip code, chip code. Receive Data Mode. These bits indicate data mode last correctly received packet. Mbps GFSK; 8DR; DDR; Valid. These bits apply unframed packets.
Bits
Mnemonic Default Read/Write Function
RX_COUNT_ADR Count
Address
0x09
Count bits non-atomic (updated different times). Bits This register contains total number payload bytes received during reception current packet. After packet reception complete, this register matches value RX_LENGTH_ADR unless there packet error. This register cleared when RX_LENGTH_ADR automatically loaded, length enabled, after SOP. Count should read when RX_GO during transaction.
Mnemonic Default Read/Write Function
RX_LENGTH_ADR Length
Address
0x0A
Length bits non-atomic (different flags change value different times response single event). Bits This register contains length field which updated with reception length field (shortly after start packet detected). there error received length field, 0x00 loaded instead, except when using GFSK data rate, error flagged.
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Mnemonic Default Read/Write Function
PWR_CTRL_ADR Mode Force PFET Disable
Address
0x0B
LVIRQ
OUTV
Power Management Unit (PMU) Enable. Setting this enables only Mode Force (bit set. Otherwise effect. Mode Force (bit description more information. Voltage Interrupt Enable. Setting this enables interrupt. When this interrupt enabled, VBAT voltage falls below threshold voltage interrupt generated. available when device sleep mode. event automatically disabled whenever disabled. Mode Force. this set, operation based state Enable (bit this then disabled Sleep mode enabled when Sleep mode, enabled always (even during sleep). disabled always. 1and disabled only Sleep Mode. Voltage Interrupt Threshold. This field sets voltage VBAT which triggered. 1.8V; 2.0V; 2.2V; OUTV voltage. Output Voltage. This field sets minimum output voltage PMU. 2.4V; 2.5V; 2.6V; 2.7V. When active, voltage output VREG never less than this voltage, provided that total load VREG less than specified maximum value, voltage VBAT greater than specified minimum value.
Bits Bits
order writing these bits impacts value Sleep current ISB.
Mnemonic Default Read/Write Function Bits XOUT
XTAL_CTRL_ADR XSIRQ Used Used
Address FREQ
0x0C
XOUT Function. This field selects between different functions XOUT pin. Clock frequency XOUT FREQ; Active Control; Radio data serial stream. this option selected configured 3-wire mode then MISO outputs serial clock associated with this data stream; GPIO. disable this output, GPIO mode, GPIO state IO_CFG_ADR. Crystal Stable Interrupt Enable. This enables interrupt. When enabled, this interrupt generates event when crystal stabilized after device awaken from sleep mode. This event cleared writing this bit. XOUT Frequency. This field sets frequency output XOUT when XOUT MHz; MHz, MHz, MHz, 0.75 MHz; other values defined.
Bits
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Mnemonic Default Read/Write Function
IO_CFG_ADR MISO XOUT PACTL PACTL GPIO
Address 3PIN
0x0D
GPIO
GPIO input, output mode must open drain, written corresponding output register bit. Drive Strength. Setting this configures open drain output. Clearing this configures standard CMOS output, with output drive voltage being equal voltage. Polarity. Setting this configures signal polarity active HIGH. Clearing this configures signal polarity active low. MISO Drive Strength. Setting this configures MISO open drain output. Clearing this configures MISO standard CMOS output, with output drive voltage being equal voltage. XOUT Drive Strength. Setting this configures XOUT open drain output. Clearing this configures XOUT standard CMOS output, with output drive voltage being equal voltage. PACTL Drive Strength. Setting this configures PACTL open drain output. Clearing this configures PACTL standard CMOS output, with output drive voltage being equal voltage. PACTL Function. When this set, PACTL available GPIO. Mode. When this cleared, interface acts standard 4-wire Slave interface. When this set, interface operates "3-Wire Mode" combining MISO MOSI same (SDAT). MISO available GPIO pin. Function. When this cleared, asserted when active; polarity this signal configurable POL. When this set, available GPIO pin, function multiplexed onto MOSI pin. this case signal state presented MOSI whenever signal inactive (HIGH).
Mnemonic Default Read/Write Function XOUT
GPIO_CTRL_ADR PACTL XOUT MISO
Address PACTL
0x0E
MISO
GPIO input, output mode must open drain, written corresponding output register bit. XOUT Output. When XOUT configured GPIO, state this sets output state XOUT pin. MISO Output. When MISO configured GPIO, state this sets output state MISO pin. PACTL Output. When PACTL configured GPIO, state this sets output state PACTL pin. Output. When configured GPIO, state this sets output state pin. XOUT Input. state this reflects voltage XOUT pin. MISO Input. state this reflects voltage MISO pin. PACTL Input. state this reflects voltage PACTL pin. Input. state this reflects voltage pin.
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Mnemonic Default Read/Write Function
XACT_CFG_ADR STATE
Address
0x0F
Used
Acknowledge Enable. When this set, packet automatically transmitted whenever valid packet received; this case device considered transaction mode. After transmission packet, device automatically transitions STATE. When this cleared, device transitions directly STATE immediately after packet transmission. This affects both transmitting receiving devices. Force State. Setting this forces transition state STATE. setting desired STATE same time setting this device forced immediately transition from current state other state. This automatically cleared upon completion. Firmware MUST never force STATE while set, when already been received (packet reception already progress). Transaction State. This field defines mode which device transitions after receiving transmitting packet. Sleep Mode; Idle Mode; Synth Mode (TX); Synth Mode (RX); Mode. normal use, this field typically `000' `001' when device transmitting packets, `100' when device receiving packets. Note that when device transitions receive mode STATE, receiver must still armed setting before device begin receiving data. system only supports packets less than equal bytes then firmware should examine determine status packet. system supports packets more than bytes, make sure that STATE sleep, force perform receive operation, force necessary STATE back sleep. Timeout. When device configured transaction mode, this field sets timeout period after transmission packet during which must correctly received order prevent transmit error condition from being detected. This timeout period expressed terms number SOP_CODE_ADR code lengths; set, then timeout period this value multiplied cleared then timeout this value multiplied 12x; SOP_CODE_ADR code length. ACK_TO must greater than Data Code Length (only 8DR) Preamble Length Code Length (x2).
Bits
Bits
Mnemonic Default Read/Write Function
FRAMING_CFG_ADR
Address
0x10
Enable. When this set, each transmitted packet begins with field, only packets beginning with valid field received. this cleared, field generated when packet transmitted, packet reception begins whenever successive correlations against DATA_CODE_ADR code detected. Code Length. When this SOP_CODE_ADR code length chips. When this cleared SOP_CODE_ADR code length chips. Packet Length Enable. When this value contained TX_LENGTH_ADR transmitted immediately after field. receive mode, bits immediately following field interpreted length packet. When this cleared packet length field transmitted. always sends packet length field (LEN setting ignored). GFSK requires user Correlator Threshold. This receive data correlator threshold used when attempting detect symbol. There single threshold SOP_CODE_ADR code. This threshold applied independently each SOP1 SOP2 fields. When set, bits this field used. When cleared, most significant disregarded. Typical applications configure SOP32 SOP64.
Bits
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Mnemonic Default Read/Write Function Bits Bits Used
DATA32_THOLD_ADR Used Used Used TH32
Address
0x11
Used. Chip Data Code Correlator Threshold. This register sets correlator threshold used DSSS modes when DATA CODE LENGTH (see TX_CFG_ADR) Typical applications configure TH32 05h.
Mnemonic Default Read/Write Function Bits Bits Used
DATA64_THOLD_ADR Used Used TH64
Address
0x12
Used. Chip Data Code Correlator Threshold. This register sets correlator threshold used DSSS modes when DATA CODE LENGTH (see TX_CFG_ADR) Typical applications configure TH64 0Eh.
Mnemonic Default Read/Write Function Used
RSSI_ADR RSSI
Address
0x13
Received Signal Strength Indicator (RSSI) reading taken automatically when symbol detected. addition, RSSI reading taken whenever RSSI_ADR read. contents this register valid after device configured receive mode until either symbol detected, register (re)read. conversion occur often once every approximate slope curve dB/count, guaranteed. desired measure background signal strength channel before packet been received then should perform "dummy" read this register, results which should discarded. This "dummy" read causes RSSI measurement taken, therefore subsequent readings register yield valid data. RSSI Reading. When set, this indicates that reading RSSI field taken when symbol detected. When cleared, this indicates that reading stored RSSI field triggered previous read this register. State. This indicates state when RSSI reading taken. When cleared, this indicates that disabled when RSSI reading taken; this indicates that enabled when RSSI reading taken. RSSI Reading. This field indicates instantaneous strength signal being received time that RSSI reading taken. larger value indicates stronger signal. signal strength measured signal configured channel, measured after stage.
Bits
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Mnemonic Default Read/Write Function
EOP_CTRL_ADR HINT
Address
0x14
set, then contents this register have effect. cleared, then this register used configure (end packet) condition detected. Hint Enable. When set, this causes detected correlations have been detected number symbol periods HINT field last received bytes match calculated CRC16 previously received bytes. this mode reduces chance noncorrelations middle packet from being detected condition. Bits Bits Hint Symbol Count. minimum number symbols consecutive noncorrelations which last bytes checked against calculated CRC16 detect condition. Symbol Count. condition deemed exist when number consecutive noncorrelations detected.
Mnemonic Default Read/Write Function
CRC_SEED_LSB_ADR
Address
0x15
SEED
CRC16 seed allows different devices generate recognize different CRC16s same payload data. transmitter receiver randomly selected CRC16 seed, probability correctly receiving data intended different receiver 1/65535, even other transmitter/receiver using same SOP_CODE_ADR codes channel. Bits CRC16 Seed Least Significant Byte. starting value CRC16 calculation.
Mnemonic Default Read/Write Function Bits
CRC_SEED_MSB_ADR
Address
0x16
SEED CRC16 Seed Most Significant Byte. starting value CRC16 calculation.
Mnemonic Default Read/Write Function Bits
TX_CRC_LSB_ADR
Address
0x17
Calculated CRC16 LSB. CRC16 that calculated last transmitted packet. This value only valid after packet transmission complete.
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Mnemonic Default Read/Write Function Bits
TX_CRC_MSB_ADR
Address
0x18
Calculated CRC16 MSB. CRC16 that calculated last transmitted packet. This value only valid after packet transmission complete.
Mnemonic Default Read/Write Function Bits
RX_CRC_LSB_ADR
Address
0x19
Received CRC16 LSB. CRC16 field extracted from last received packet. This value valid whether CRC16 field matched calculated CRC16 received packet.
Mnemonic Default Read/Write Function Bits
RX_CRC_MSB_ADR
Address
0x1A
Received CRC16 MSB. CRC16 field extracted from last received packet. This value valid whether CRC16 field matched calculated CRC16 received packet.
Mnemonic Default Read/Write Function Bits
TX_OFFSET_LSB_ADR STRIM
Address
0x1B
least significant bits synthesizer offset value. This complement signed number, which used offset transmit frequency device ±1.5 MHz. positive value increases transmit frequency, negative value reduces transmit frequency. value increases transmit frequency 732.6 value decreases transmit frequency 732.6 value 0x0555 increases transmit frequency MHz; value 0xAAB decreases transmit frequency MHz. Typically, this register loaded with 0x55 during initialization. This feature used avoid need change synthesizer frequency when switching between frequency offset from synthesizer frequency; therefore, transmitting with offset allows same synthesizer frequency used both transmit receive.
Synthesizer offset effect receive frequency.
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Mnemonic Default Read/Write Function Bits Bits Used
TX_OFFSET_MSB_ADR Used Used Used
Address
0x1C
STRIM
Used. most significant bits synthesizer trim value. Typically, this register loaded with 0x05 during initialization.
Mnemonic Default Read/Write Function Bits Bits Bits RSVD
MODE_OVERRIDE_ADR RSVD AWAKE Used
Address Used
0x1D
Reserved. Must zero. Manually Initiate Synthesizer. Setting this forces synthesizer start. Clearing this effect. this operate correctly, oscillator must running before this set. Force Awake. Force device sleep mode. Setting both bits this field forces oscillator keep running times regardless STATE setting. Clearing both these bits disables this function. Used. Reset. Setting this forces full reset device. Clearing this effect.
Mnemonic Default Read/Write Function
RX_OVERRIDE_ADR RXTX RXACK RXDR CRC0 RXCRC
Address
0x1E
Used
This register provides ability override some automatic features device. When this set, device uses transmit synthesizer frequency rather than receive synthesizer frequency given channel when automatically entering receive mode. When this enabled, transmission packet delayed Force Expected Packet Type. When this set, device receive mode, device configured receive packet data rate defined TX_CFG_ADR. Force Receive Data Rate. When this set, receiver ignores data rate encoded symbol, receives data data rate defined TX_CFG_ADR. Reject packets with zero-seed CRC16. Setting this causes receiver reject packets with zero-seed, accept only packets with CRC16 that matches seed CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR. CRC16 checker disabled. packets with CRC16 enabled received, CRC16 treated payload data stored receive buffer. Accept CRC16. Setting this causes receiver accept packets with CRC16 that match seed CRC_SEED_LSB_ADR CRC_SEED_MSB_ADR. sent regardless condition received CRC16. Used.
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Mnemonic Default Read/Write Function
TX_OVERRIDE_ADR RSVD TXACK OVRD TXCRC
Address RSVD
0x1F
This register provides ability override some automatic features device. When this set, device uses receive synthesizer frequency rather than transmit synthesizer frequency given channel when automatically entering transmit mode. Force Preamble. When this set, device transmits continuous repetition preamble pattern (see PREAMBLE_ADR) after set. This mode useful some regulatory approval procedures. Firmware should MODE_OVERRIDE_ADR exit this mode. Reserved. Must zero. Transmit Packet. When this set, device sends packet when set. Override. TX_CFG_ADR determine data rate CRC16 used when transmitting packet. Disable Transmit CRC16. When set, CRC16 field present transmitted packets. Reserved. Must zero. Data Invert. When this transmit bitstream inverted.
Mnemonic Default Read/Write Function Bits Bits RSVD RSVD
XTAL_CFG_ADR RSVD RSVD START RSVD
Address RSVD
0x26
RSVD
This register provides ability override some automatic features device. Reserved. Must zero. Crystal Startup Delay. Setting this bit, sets crystal startup delay handle warm restarts crystal. Firmware MUST this during initialization. Reserved. Must zero.
Mnemonic Default Read/Write Function Bits RSVD
CLK_OVERRIDE_ADR RSVD RSVD RSVD RSVD RSVD
Address
0x27
RSVD
This register provides ability override some automatic features device. Reserved. Must zero. Force Receive Clock. Streaming applications MUST this during receive mode, otherwise this cleared. Reserved. Must zero.
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Mnemonic Default Read/Write Function Bits RSVD RSVD
CLK_EN_ADR RSVD RSVD RSVD RSVD
Address
0x28
RSVD
This register provides ability override some automatic features device. Reserved. Must zero. Force Receive Clock Enable. Streaming applications MUST this during initialization. Reserved. Must zero.
Mnemonic Default Read/Write Function Bits Bits RSVD RSVD
RX_ABORT_ADR ABORT RSVD RSVD RSVD
Address RSVD
0x29
RSVD
This register provides ability override some automatic features device. Reserved. Must zero. Receive Abort Enable. Typical applications disrupt pending receive first setting this bit, otherwise this cleared. Reserved. Must zero.
Mnemonic Default Read/Write Function Bits
AUTO_CAL_TIME_ADR
Address
0x32
AUTO_CAL_TIME Auto Time. Firmware MUST write this register during initialization.
This register provides ability override some automatic features device.
Mnemonic Default Read/Write Function Bits
AUTO_CAL_OFFSET_ADR
Address
0x35
AUTO_CAL_OFFSET Auto Offset. Firmware MUST write this register during initialization.
This register provides ability override some automatic features device.
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Mnemonic Default Read/Write Function Bits RSVD
ANALOG_CTRL_ADR RSVD RSVD RSVD RSVD RSVD
Address
0x39
SLOW
This register provides ability override some automatic features device. Reserved. Must zero. Receive Invert. When set, incoming receive data inverted. Firmware MUST this when interoperability with first generation devices desired. Slow. When set, synth settling time channels same slow channels. recommended that firmware this when using GFSK data rate mode.
Register Files Files written read from using nonincrementing burst read write transactions. most cases, accessing file destructive; file must completely read/written, otherwise contents altered. When accessing file registers, bytes presented least significant byte first.
Mnemonic Length Default TX_BUFFER_ADR Bytes Address 0x20
transmit buffer FIFO. Writing this file adds byte packet being sent. Writing more bytes this file than packet length TX_LENGTH_ADR effect, these bytes lost. FIFO accumulates data until reset using TX_CTRL_ADR. previously sent packet, bytes less, transmitted TX_GO without resetting FIFO. contents TX_BUFFER_ADR affected transmission Auto ACK.
Mnemonic Length Default
RX_BUFFER_ADR Bytes
Address
0x21
receive buffer FIFO. Received bytes read from this file register time that empty, when reading from this file register before packet been completely received care must taken ensure that error packets (for example with CRC16) handled correctly. When receive buffer configured overwritten packets (the alternative packets discarded receive buffer empty), similar care must taken verify after packet been read from buffer that part overwritten newly received packet while this file register being read. When RX_CFG_ADR set, bytes this file register alternate-the first byte read data, second byte valid flag each first byte, third byte data, fourth byte valid flags, modes valid flag correlation coefficient exceeds correlator threshold, cleared does not. mode, valid flags byte indicates whether correlation coefficient corresponding received symbol exceeds threshold. seven LSBs contain number erroneous chips received data.
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Mnemonic Length Default
SOP_CODE_ADR Bytes
0x17FF9E213690C782
Address
0x22
When using chip SOP_CODE_ADR codes, only first four bytes this register used; order complete file write process, these four bytes must followed four bytes "dummy" data. However, class codes known "multiplicative codes" used; there chip codes with good auto-correlation cross-correlation properties where least significant chips themselves have good auto-correlation cross-correlation properties when used chip codes. this case same eight byte value loaded into this file used both chip chip symbols. When reading this file, eight bytes must read; fewer than eight bytes read from file, contents file will have been rotated number bytes read. This applies writes, well. access modify this register during Transmit Receive. Recommended Codes:
0x91CCF8E291CC373C 0x0FA239AD0FA1C59B 0x2AB18FD22AB064EF 0x507C26DD507CCD66 0x44F616AD44F6E15C 0x46AE31B646AECC5A 0x3CDC829E3CDC78A1 0x7418656F74198EB9 0x49C1DF6249C0B1DF 0x72141A7F7214E597
Mnemonic Length Default
DATA_CODE_ADR Bytes
Address
0x23
GFSK mode, this file register ignored. mode, only first eight bytes used. mode, only eight bytes used. format these eight bytes: where represents unused locations. Example: where "B86BC0DC" represents AAAAAAAA, "00000000" represents unused locations, "B2BB092B" represents BBBBBBBB, "00000000" represents unused locations. modes, sixteen bytes used. When reading this file, sixteen bytes must read; fewer than sixteen bytes read from file, contents file will have been rotated number bytes read. This applies writes, well. Certain byte sequences have been calculated that provide excellent auto-correlation cross-correlation properties, recommended that such sequences used; default value this register such sequence. typical applications, devices same DATA_CODE_ADR codes, devices systems addressed using different SOP_CODE_ADR codes; such cases never necessary change contents this register from default value. Typical applications should default code. access modify this register during Transmit Receive.
Mnemonic Length Default
PREAMBLE_ADR Bytes 0x333302
Address
0x24
byte number repetitions preamble sequence that transmitted. preamble disabled writing 0x00 this byte. byte Least significant eight chips preamble sequence byte Most significant eight chips preamble sequence using communicate with CYWUSB69xx devices, number repetitions four optimum performance When reading this file, three bytes must read; fewer than three bytes read from file, contents file will have been rotated number bytes read. This also applies writes. access modify this register during Transmit Receive.
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Mnemonic Length Default
MFG_ID_ADR Bytes
Address
0x25
minimize ~190 current consumption (default), execute "dummy" single-byte write this address with zero data stage after contents have been read. Non-zero enable reading fuses. Zero disable reading fuses.
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Absolute Maximum Ratings
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage power supply relative -0.3V +3.9V Voltage Logic Inputs[5] -0.3V +0.3V Voltage applied Outputs High-Z State -0.3V +0.3V Static Discharge Voltage (Digital)[6] .>2000V
Static Discharge Voltage (RF)[6] 1100V Latch Current .+200 -200
Operating Conditions
.2.4V 3.6V .1.8V 3.6V VBAT .1.8V 3.6V (Ambient Temperature Under Bias) +70°C Ground Voltage. FOSC (Crystal Frequency). 12MHz
Characteristics
25°C, VBAT 2.4V, disabled, fOSC 12.000000MHz)
Parameter VBAT VREG[7] VREG[7] VIO[8] VOH1 VOH2 (GFSK)[10]
Description Battery Voltage Output Voltage Output Voltage Voltage Voltage Output High Voltage Condition Output High Voltage Condition Output Voltage Input High Voltage Input Voltage Input Leakage Current Input Capacitance 0-70°C 0-70°C 2.4V mode 2.7V mode
Conditions
2.4[9] 0.7VIO
2.43 2.73
Unit
0.45 0.3VIO 0.26 0.87 31.4 20.8 26.2 34.1 18.4 21.2
-100.0 -2.0
except XTAL, RFN, RFP, RFBIAS
Average ICC, Mbps, slow channel way, bytes/10 Sleep Mode Sleep Mode Radio off, XTAL Active during Synth Start during Transmit during Transmit during Transmit during Receive during Receive Boost Converter Efficiency dBm) dBm) dBm) off, VBAT 2.5V, VREG 2.73V, ILOAD enabled XOUT disabled
(32-8DR)[10] Average ICC, kbps, fast channel way, bytes/10 ISB[11] ISB[11] IDLE Isynth Boost
Notes permissible connect voltages above inputs through series resistor limiting input current timing guaranteed. Human Body Model (HBM). VREG depends battery input voltage. sleep mode, interface voltage reference VBAT. sleep mode, min. 1.8V. Includes current drawn while starting crystal, starting synthesizer, transmitting packet (including CRC16), changing receive mode, receiving handshake. Device sleep except during this transaction. guaranteed connected voltages higher than VIO.
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CYRF6936
Characteristics
25°C, VBAT 2.4V, disabled, fOSC 12.000000MHz)
(continued) Conditions VBAT 1.8V, VREG 2.73V, 0-50°C, Mode VBAT 1.8V, VREG 2.73V, 50-70°C, Mode Unit
Parameter ILOAD_EXT ILOAD_EXT
Description Average External Load current Average External Load current
Characteristics[12]
Table Interface[13] Parameter tSCK_CYC tSCK_HI tSCK_LO tDAT_SU tDAT_HLD tDAT_VAL tDAT_VAL_TRI tSS_SU tSS_HLD tSS_PW tSCK_SU tSCK_HLD tRESET Clock Period Clock High Time Clock Time Input Data Setup Time Input Data Hold Time Output Data Valid Time Output Data Tri-state (MOSI from Slave Select Deassert) Slave Select Setup Time before first positive edge SCK[14] Slave Select Hold Time after last negative edge Slave Select Minimum Pulse Width Slave Select Setup Time Hold Time Minimum Pulse Width Figure Timing
tSCK_CYC tSCK_SU tSS_SU tDAT_SU MOSI input tDAT_VAL MISO tDAT_VAL_TRI tDAT_HLD tSS_HLD tSCK_HI tSCK_LO tSCK_HLD
Description
238.1
Unit
MOSI output
Notes values guaranteed voltage exceed VIO. CLOAD must start time goes LOW, otherwise success transactions guaranteed.
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Characteristics
Table Radio Parameters Parameter Description Frequency Range Note Receiver 25°C, 3.0V, fOSC 12.000000MHz, 1E-3) Sensitivity kbps 64-8DR 1E-3 Sensitivity kbps 32-8DR Sensitivity Sensitivity GFSK Gain Gain Maximum Received Signal RSSI Value PWRin RSSI Slope Interference Performance (CER 1E-3) Co-channel Interference rejection Carrier-to-Interference (C/I) Adjacent MHz) channel selectivity Adjacent MHz) channel selectivity Adjacent MHz) channel selectivity Out-of-Band Blocking MHz-12.75 MHz[16] Intermodulation Receive Spurious Emission Transmitter 25°C, 3.0V) Maximum Transmit Power Maximum Transmit Power Maximum Transmit Power Maximum Transmit Power Power Control Range Power Range Control Step Size Frequency Deviation Frequency Deviation Error Vector Magnitude (FSK error) Occupied Bandwidth Transmit Spurious Emission In-band Spurious Second Channel Power MHz) In-band Spurious Third Channel Power MHz) Seven steps, monotonic Code Pattern 10101010 Code Pattern 11110000 dBc, ResBW %rms ResBW ResBW ResBW dBm, 5,10 1E-3 1E-3 1E-3, SLOW Conditions 2.400 22.8 -31.7 2.497 Unit Count dB/Count
Notes Subject regulation. Exceptions 5C/3.
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CYRF6936
Table Radio Parameters (continued) Parameter Description Non-Harmonically Related Spurs (800 MHz) Non-Harmonically Related Spurs (1.6 GHz) Non-Harmonically Related Spurs (3.2 GHz) Harmonic Spurs (Second Harmonic) Harmonic Spurs (Third Harmonic) Fourth Greater Harmonics Power Management (Crystal eCERA GF-1200008) Crystal Start 10ppm Crystal Start Synth Settle Synth Settle Synth Settle Link Turnaround Time Link Turnaround Time Link Turnaround Time Link Turnaround Time Packet Length Packet Length XSIRQ Slow channels Medium channels Fast channels GFSK kbps kbps <125 kbps crystal-to-crystal modes except 64-DDR crystal-to-crystal 64-DDR bytes bytes Conditions Unit
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CYRF6936
Typical Operating Characteristics[17]
Transmit Power Temperature (Vcc 2.7v) Output Power (dBm) Temp (deg Output Power (dBm) Transmit Power (PMU off)
Transmit Power Channel
Output Power (dBm)
Channel
Typical RSSI Count Input Power
Average RSSI Temperature signal -70dBm) RSSI Count Temp (deg
Average RSSI signal -70dBm)
RSSI Count RSSI Count
-120
-100 Input Power (dBm)
RSSI Channel signal -70dBm)
Sensitivity (1Mbps CER) Receiver Sensitivity (dBm)
Sensitivity Temperature (1Mbps CER) Receiver Sensitivity (dBm)
RSSI Count Channel
8DR32
8DR32
Temp (deg
Receiver Sensitivity Frequency Offset Receiver Sensitivity (dBm) -150
Receiver Sensitivity (dBm)
Receiver Sensitivity Channel (3.0v, Room Temp) 20.0
Carrier Interferer (Narrow band, modulation)
GFSK
10.0
GFSK
(dB)
-10.0 -20.0 -30.0 -40.0 -50.0 -60.0
DDR32 8DR64
DDR32
Channel
8DR32
-100
Crystal Offset (ppm)
Channel Offset (MHz)
Note With off, above -2dBm erroneous RSSI values read, cross-checking RSSI with off/on recommended accurate readings.
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CYRF6936
Data Threshold (32-DDR) (SOP Threshold slow)
Data Threshold (32-8DR) (SOP Threshold slow)
GFSK (SOP Threshold slow) %BER 0.01 0.001 0.0001 0.00001 -100
Thru
%BER 0.01 0.001 0.0001 0.00001 -100
%BER 0.01 0.001 0.0001 0.00001 -100
GFSK
Input Power (dBm)
Input Power (dBm)
Input Power (dBm)
(LNA OFF) OPERATING CURRENT (mA) OPERATING CURRENT (mA) 20.5 19.5 18.5 17.5 TEMPERATURE 24.5
(LNA
SYNTH
3.3V 3.0V 2.7V 2.4V
23.5 22.5 21.5 20.5 19.5
3.3V 3.0V 2.7V 2.4V
TEMPERATURE
OPERATING CURRENT (mA)
3.3V 3.0V 2.7V 2.4V
TEMPERATURE
SYNTH OPERATING CURRENT (mA) 16.5 15.5 14.5 TEMPERATURE
17.5 OPERATING CURRENT (mA)
OPERATING CURRENT (mA)
3.3V 3.0V 2.7V 2.4V
3.3V 3.0V 2.7V 2.4V
16.5 15.5 14.5
3.3V 3.0V 2.7V 2.4V
TEMPERATURE
TEMPERATURE
OPERATING CURRENT (mA) 17.5 16.5 15.5 TEMPERATURE
20.5 OPERATING CURRENT (mA)
3.3V 3.0V 2.7V 2.4V
OPERATING CURRENT (mA)
18.5 17.5 16.5 15.5
3.3V 3.0V 2.7V 2.4V
19.5 18.5 17.5 16.5
3.3V 3.0V 2.7V 2.4V
TEMPERATURE
TEMPERATURE
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CYRF6936
23.5 OPERATING CURRENT (mA) OPERATING CURRENT (mA) 22.5 21.5 20.5 19.5 TEMPERATURE
40.5 39.5 38.5 37.5 36.5 35.5 34.5 33.5 32.5
28.5 27.5 26.5 25.5 24.5
OPERATING CURRENT (mA)
3.3V 3.0V 2.7V 2.4V
29.5
3.3V 3.0V 2.7V 2.4V
3.3V 3.0V 2.7V 2.4V
TEMPERATURE
TEMPERATURE
Test Loads Waveforms Digital Pins
Figure Test Loads Waveforms Digital Pins
Test Loads
OUTPUT INCLUDING SCOPE OUTPUT
Test Load
OUTPUT
INCLUDING Typical SCOPE INPUT PULSES Rise time: V/ns Equivalent EQUIVALENT OUTPUT
Parameter
1071 3.00
Unit
Fall time: V/ns
Ordering Information
Table Ordering Information Part Number CYRF6936-40LFXC Radio Transceiver Package Name Package Type Quad Flat Package Leads Lead-Free Operating Range Commercial
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CYRF6936
Package Description
Figure 40-lead Pb-Free (Subcon Punch Type with EPAD) LY40
VIEW SIDE VIEW BOTTOM VIEW
0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. 0.18[0.007] 0.28[0.011] PIN1 0.20[0.008] 0.45[0.018]
0.08[0.003] 5.90[0.232] 6.10[0.240] 5.70[0.224] 5.80[0.228] 0.60[0.024] DIA. 1.00[0.039] MAX.
5.70[0.224] 5.80[0.228]
5.90[0.232] 6.10[0.240]
0°-12°
0.30[0.012] 0.50[0.020] SEATING PLANE 4.45[0.175] 4.55[0.179]
0.50[0.020]
0.24[0.009] 0.60[0.024]
(4X)
NOTES: HATCH SOLDERABLE EXPOSED AREA
REFERENCE JEDEC#: MO-220 PACKAGE WEIGHT: 0.086g DIMENSIONS [MIN/MAX] PACKAGE CODE PART LY40 LF40 DESCRIPTION PB-FREE STANDARD
51-85190-*A
recommended dimension size E-PAD underneath (width length). This document subject change, found contain errors omission changes parameters. feedback technical support regarding Cypress WirelessUSB products, contact Cypress www.cypress.com. WirelessUSB, PSoC, enCoRe trademarks Cypress Semiconductor. product company names mentioned this document trademarks their respective holders.
Document 38-16015 Rev.
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Cypress Semiconductor Corporation, 2007. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges.
4.45[0.175] 4.55[0.179]
SOLDERABLE EXPOSED
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Document History Page
Description Title: CYRF6936 WirelessUSBLP Radio Document Number: 38-16015 REV. 307437 377574 Issue Date Orig. Change data sheet Preliminary release- updated Section Features updated Section Applications added Section Applications Support updated Section Functional Descriptions updated Section Description added Figure updated Section Functional Overview added Section Functional Block Overview added Section Register Descriptions updated Section 10.0 Absolute Maximum Ratings updated Section 11.0 Operating Conditions updated Section 12.0 Characteristics updated Section 13.0 Characteristics updated Section 14.0 Characteristics added Section 16.0 Ordering Information ES-10 update- changed part updated Section Register Descriptions updated Section 12.0 Characteristics updated Section 14.0 Characteristics ES-10 update- updated Section Functional Descriptions updated Section Descriptions updated Section Functional Overview updated Section Functional Block Overview updated Section Register Descriptions updated Section 10.0 Absolute Maximum Ratings updated Section 11.0 Operating Conditions updated Section 14.0 Characteristics updated Section Features updated Section Descriptions updated Section Functional Overview updated Section Functional Block Overview updated Section Register Descriptions added Section 10.0 Recommended Radio Circuit Schematic updated Section 11.0 Absolute Maximum Ratings updated Section 12.0 Operating Conditions updated Section 13.0 Characteristics updated Section 14.0 Characteristics updated Section 15.0 Characteristics Final data sheet removed "Preliminary" notation updated Section Features updated Section Descriptions updated Section Functional Overview updated Section Functional Block Overview updated Section Application Example updated Section Register Descriptions updated Section 12.0 Characteristics updated Section 13.0 Characteristics updated Section 14.0 Characteristics added Section 15.0 Typical Operating Characteristics Description Change
398756
412778
435578
460458 487261
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CYRF6936
Description Title: CYRF6936 WirelessUSBLP Radio Document Number: 38-16015 778236 OYR/ARI -modified radio function register descriptions -changed description -footnotes added -changed Capacitor from 0.1uF 0.47 -updated Figure Recommended Circuit Systems -updated Table Recommended bill materials systems -updated package diagram from
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