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COP688CL COP684CL COP888CL COP884CL COP988CL COP984CL


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ADAPTER circuit AC TO DC 220V TO 6V - ADAPTER circuit AC TO DC 220V TO 6V  
COP688CL - COP688CL  
COP684CL - COP684CL  
COP888CL - COP888CL  
COP884CL - COP884CL  
COP988CL - COP988CL  
COP984CL - COP984CL  

COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL 8-Bit Microcontroller
COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL 8-Bit Microcontroller
COP888 family microcontrollers uses 8-bit single chip core architecture fabricated with National Semiconductor's M2CMOSprocess technology. COP888CL member this expandable 8-bit core processor family microcontrollers. fully static part, fabricated using double-metal silicon gate microCMOS technology. Features include 8-bit memory mapped architecture, MICROWIRE/PLUS serial I/O, 16-bit timer/counters supporting three modes (Processor Independent generation, External Event counter, Input Capture mode capabilities), power savings modes (HALT IDLE), both with multisourced wakeup/interrupt capability. This multi-sourced interrupt capability also used independent HALT IDLE modes. Each software selectable configurations. device operates over voltage range 2.5V High throughput achieved with efficient, regular instruction operating maximum instruction rate. Software selectable options TRI-STATE Output, Push-Pull Output, Weak Pull-Up Input, High Impedance Input) High current outputs Schmitt trigger inputs port Packages: PLCC with pins with pins with pins with pins
CPU/Instruction Feature
instruction cycle time multi-source vectored interrupts servicing External Interrupt with selectable edge Idle Timer Timers (Each with interrupts) MICROWIRE/PLUS Multi-Input Wake Software Trap Default (default interrupt) Versatile easy instruction 8-bit Stack Pointer (SP) stack 8-bit Register Indirect Data Memory Pointers
Features
16-bit timers, each with 16-bit registers supporting: Processor Independent mode External Event counter mode Input Capture mode kbytes on-chip bytes on-chip
Fully Static CMOS
current drain (typically Single supply operation: 2.5V 6.0V Temperature ranges: +70°C, -40°C +85°C, -55°C +125°C
Additional Peripheral Features
Idle Timer Multi-input Wake (MIWU) with optional interrupts WATCHDOG Clock Monitor logic MICROWIRE/PLUSserial
Development Support
Emulation devices Real time emulation full program debug offered MetaLink Development System
Features
Memory mapped
MICROWIRE/PLUSTM, M2CMOSTM, COPSmicrocontrollers, MICROWIREare trademarks National Semiconductor Corporation. iceMASTERis trademark MetaLink Corporation.
2000 National Semiconductor Corporation
DS009766
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Block Diagram
DS009766-1
FIGURE Block Diagram
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Connection Diagrams
Plastic Chip Carrier Dual-In-Line Package
DS009766-2
View Order Number COP688CL-XXX/V, COP888CL-XXX/V, COP988CL-XXX/V COP988CLH-XXX/V Plastic Chip Package Number V44A
DS009766-4
View Order Number COP688CL-XXX/N, COP888CL-XXX/N, COP988CL-XXX/N COP988CLH-XXX/N Molded Package Number N40A Dual-In-Line Package
DS009766-5
View Order Number COP688CL-XXX/N, COP884CL-XXX/N, COP984CL-XXX/N COP984CLH-XXX/N Molded Package Number N28B Order Number COP684CL-XXX/WM, COP884CL-XXX/WM, COP984CL-XXX/WM, COP984CLHXXX/WM Surface Mount Package Number M28B FIGURE Connection Diagrams
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Connection Diagrams
Port Unused (Note Unused (Note RESET
(Continued)
Pinouts 28-, 44-Pin Packages Type WDOUT I/CKO HALT RESTART Alt. MIWU MIWU MIWU MIWU MIWU MIWU MIWU MIWU Alt. 28-Pin Pack. 40-Pin Pack. 44-Pin Pack.
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Connection Diagrams
(Continued)
Note 40-pin package Pins must connected GND.
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Absolute Maximum Ratings (Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Supply Voltage (VCC) Voltage -0.3V 0.3V
Total Current into (Source) Total Current (Sink) Storage Temperature Range
-65°C +140°C
Note Absolute maximum ratings indicate limits beyond which damage device occur. electrical specifications ensured when operating device absolute maximum ratings.
Electrical Characteristics
COP98XCL: 70°C unless otherwise specified. Parameter Operating Voltage COP98XCL COP98XCLH Power Supply Ripple (Note Supply Current (Note HALT Current (Note IDLE Current Input Levels RESET Logic High Logic (External Crystal Osc. Modes) Logic High Logic Other Inputs Logic High Logic Hi-Z Input Leakage Input Pullup Current Port Input Hysteresis Output Current Levels Outputs Source Sink Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink/Source Current Outputs (Sink) others
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Conditions
12.5
Units
Peak-to-Peak
-250 0.35
3.3V 2.5V, 1.8V 2.5V, 0.4V 2.7V 2.5V, 1.8V 3.3V 2.5V, 1.8V 0.4V 2.5V, 0.4V 6.0V
-0.4 -0.2 -2.5 -0.4 -0.2 -100
COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Electrical Characteristics
Parameter Maximum Input Current without Latchup (Note Retention Voltage, Input Capacitance Load Capacitance
Note Rate voltage change must less then V/ms.
(Continued)
COP98XCL: 70°C unless otherwise specified. Conditions 25°C Rise Fall Time (Min) 1000 Units
Note Supply current measured after running 2000 cycles with square wave input, open, inputs rails outputs open. Note HALT mode will stop from oscillating Crystal configurations. Test conditions: inputs tied VCC, G0-G5 configured outputs high. port zero. clock monitor disabled.
Electrical Characteristics
70°C unless otherwise specified. Parameter Instruction Cycle Time (tc) Crystal Resonator Oscillator Inputs tSETUP tHOLD Output Propagation Delay (Note tPD1, tPD0 Others MICROWIRESetup Time (tUWS) MICROWIRE Hold Time (tUWH) MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width Interrupt Input High Time Interrupt Input Time Timer Input High Time Timer Input Time Reset Pulse Width 2.5V 2.5V 1.75 2.5V 2.5V 2.2k, 2.5V 2.5V Conditions Units
Note Pins RESET designed with high voltage input network factory testing. These pins allow input voltages greater than pins will have sink current VCCwhen biased voltages greater than (the pins have source current when biased voltage below VCC). effective resistance (typical). These pins will latch voltage pins must limited less than 14V. Note output propagation delay referenced instruction cycle where output change occurs.
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Absolute Maximum Ratings (Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. Supply Voltage (VCC) Voltage -0.3V 0.3V
Total Current into (Source) Total Current (Sink) Storage Temperature Range
-65°C +140°C
Note Absolute maximum ratings indicate limits beyond which damage device occur. electrical specifications ensured when operating device absolute maximum ratings.
Electrical Characteristics
COP88XCL: -40°C +85°C unless otherwise specified Parameter Operating Voltage Power Supply Ripple (Note Supply Current (Note HALT Current (Note IDLE Current Input Levels RESET Logic High Logic (External Crystal Osc. Modes) Logic High Logic Other Inputs Logic High Logic Hi-Z Input Leakage Input Pullup Current Port Input Hysteresis Output Current Levels Outputs Source Sink Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage Allowable Sink/Source Current Outputs (Sink) others Maximum Input Current without Latchup (Note 25°C 2.7V 2.5V, 1.8V 3.3V 2.5V, 1.8V 0.4V 2.5V, 0.4V 6.0V -2.5 -0.4 -0.2 -100 3.3V 2.5V, 1.8V 2.5V, 0.4V -0.4 -0.2 -250 0.35 12.5 Peak-to-Peak Conditions Units
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Electrical Characteristics
Parameter Retention Voltage, Input Capacitance Load Capacitance
Note Rate voltage change must less then V/ms.
(Continued)
COP88XCL: -40°C +85°C unless otherwise specified Conditions Rise Fall Time (Min) 1000 Units
Note Supply current measured after running 2000 cycles with square wave input, open, inputs rails outputs open. Note HALT mode will stop from oscillating Crystal configurations. Test conditions: inputs tied VCC, G0-G5 configured outputs high. port zero. clock monitor disabled.
Electrical Characteristics
-40°C +85°C unless otherwise specified Parameter Instruction Cycle Time (tc) Crystal Resonator Oscillator Inputs tSETUP tHOLD Output Propagation Delay (Note tPD1, tPD0 Others MICROWIRE Setup Time (tUWS) MICROWIRE Hold Time (tUWH) MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width Interrupt Input High Time Interrupt Input Time Timer Input High Time Timer Input Time Reset Pulse Width 2.5V 1.75 2.5V 2.5V 2.2k, 2.5V 2.5V Conditions Units
2.5V
Note Pins RESET designed with high voltage input network factory testing. These pins allow input voltages greater than pins will have sink current when biased voltages greater than (the pins have source current when biased voltage below VCC). effective resistance (typical). These pins will latch voltage pins must limited less than 14V. Note output propagation delay referenced instruction cycle where output change occurs.
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Electrical Specifications
ELECTRICAL SPECIFICATIONS
Note Absolute maximum ratings indicate limits beyond which damage device occur. electrical specifications ensured when operating device absolute maximum ratings.
COP688CL Absolute Specifications
Supply Voltage (VCC) Voltage Total Current into (Source) Total Current (Sink) Storage Temperature Range -65°C +150°C -0.3V 0.3V
Electrical Characteristics
COP68XCL: -55°C +125°C unless otherwise specified Parameter Operating Voltage Power Supply Ripple (Note Supply Current (Note HALT Current (Note IDLE Current Input Levels RESET Logic High Logic (External Crystal Osc. Modes) Logic High Logic Other Inputs Logic High Logic Hi-Z Input Leakage Input Pullup Current Port Input Hysteresis Output Current Levels Outputs Source Sink Others Source (Weak Pull-Up Mode) Source (Push-Pull Mode) Sink (Push-Pull Mode) TRI-STATE Leakage 4.5V, 3.8V 4.5V, 3.8V 4.5V, 0.4V 5.5V -9.0 -0.4 -5.0 +5.0 -140 4.5V, 3.8V 4.5V, 1.0V -0.4 5.5V 5.5V, -400 0.35 5.5V, 5.5V, 5.5V, 5.5V, 5.5V, 12.5 Peak-to-Peak Conditions Units
Note Rate voltage change must less then V/ms. Note Supply current measured after running 2000 cycles with square wave input, open, inputs rails outputs open. Note HALT mode will stop from oscillating Crystal configurations. Test conditions: inputs tied VCC, G0-G5 configured outputs high. port zero. clock monitor disabled.
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Electrical Characteristics
-55°C +25°C unless otherwise specified Parameter Allowable Sink/Source Current Outputs (Sink) others Maximum Input Current without Latchup (Note Retention Voltage, Input Capacitance Load Capacitance
Note Rate voltage change must less then V/ms. Note Supply current measured after running 2000 cycles with square wave input, open, inputs rails outputs open. Note HALT mode will stop from oscillating Crystal configurations. Test conditions: inputs tied VCC, ports TRI-STATE mode tied ground, outputs tied ground. Clock Monitor comparators disabled.
Conditions
Units
Rise Fall Time (Min) 1000
Specifications COP688CL Electrical Characteristics
-55°C +125°C unless otherwise specified Parameter Instruction Cycle Time (tc) Crystal, Resonator, External Oscillator Oscillator (div-by Inputs tSETUP tHOLD Output Propagation Delay (Note tPD1, tPD0 Others MICROWIRE Setup Time (tUWS) MICROWIRE Hold Time(tUWH) MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width Interrupt Input High Time Interrupt Input Time Timer Input High Time Timer Input Time Reset Pulse Width 4.5V 4.5V 4.5V 4.5V 2.2k, 4.5V 4.5V Conditions Units
Note Pins RESET designed with high voltage input network factory testing. These pins allow input voltages greater than pins will have sink current VCCwhen biased voltages greater than (the pins have source current when biased voltage below VCC). effective resistance (typical). These pins will latch voltage pins must limited less than 14V. Note output propagation delay referenced instruction cycle where output change occurs.
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Electrical Characteristics
(Continued)
DS009766-26
FIGURE MICROWIRE/PLUS Timing
Typical Performance Characteristics
Halt
-40°C +85°C unless otherwise specified Idle IDD(Crystal Clock Option)
DS009766-27
DS009766-28
Dynamic (Crystal Clock Option)
Port L/C/G Weak Pull-Up Source Current
DS009766-29
DS009766-30
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Typical Performance Characteristics
Port L/C/G Push-Pull Source Current
-40°C +85°C unless otherwise specified (Continued) Port L/C/G Push-Pull Sink Current
DS009766-31
DS009766-32
Port Source Current
Port Sink Current
DS009766-33
DS009766-34
Descriptions
power supply pins. clock input. This come from generated oscillator, crystal oscillator conjunction with CKO). Oscillator Description section. RESET master reset input. Reset Description section. device contains three bidirectional 8-bit ports where each individual independently configured input (Schmitt trigger inputs ports output TRI-STATE under program control. Three data memory address locations allocated each these ports. Each port associated 8-bit memory mapped registers, CONFIGURATION register output DATA register. memory mapped address also reserved input pins each port. (See memory various addresses associated with ports.) Figure shows port configurations. DATA CONFIGURATION registers allow each port individually configured under software control shown below:
CONFIGURATION Register
DATA Register
Port Set-Up
Hi-Z Input (TRI-STATE Output) Input with Weak Pull-Up Push-Pull Zero Output Push-Pull Output
DS009766-6
FIGURE Port Configurations
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Descriptions
(Continued)
PORT 8-bit port. L-pins have Schmitt triggers inputs. Port supports Multi-Input Wakeup (MIWU) eight pins. used timer input functions T2B. Port following alternate features: MIWU MIWU MIWU MIWU MIWU MIWU MIWU MIWU Port 8-bit port with pins (G0, G2-G5), input (G6), dedicated output pins G7). Pins G2-G6 have Schmitt Triggers their inputs. serves dedicated WDOUT WATCHDOG output, while either input output depending oscillator mask option selected. With crystal oscillator option selected, serves dedicated output clock output. With single-pin oscillator mask option selected, serves general purpose input pin, also used bring device HALT mode with high transition. There registers associated with Port, data register configuration register. Therefore, each bits (G0, G2-G5) individually configured under software control. Since input only dedicated clock output general purpose input (R/C clock configuration), associated bits data configuration registers used special purpose functions outlined below. Reading data bits will return zeros. Note that chip will placed HALT mode writing Port Data Register. Similarly chip will placed IDLE mode writing Port Data Register. Writing Port Configuration Register enables MICROWIRE/PLUS operate with alternate phase clock. configuration bit, high, enables clock start delay after HALT when clock configuration used. Config Reg. CLKDLY Alternate Data Reg. HALT IDLE
Port 8-bit port. 40-pin device does have full complement Port pins. unavailable pins terminated. read operation these unterminated pins will return unpredictable values. Port 8-bit Hi-Z input port. 40-pin device does have full complement Port pins. Pins this package must connected GND. 28-pin device four pins (I0, I5). user should attention when reading port fact that positions rather than unavailable pins (I4-I7) terminated i.e., they floating. read operation these unterminated pins will return unpredictable values. user must ensure that software takes into account either masking restricting accesses operations. unterminated port pins will draw power only when addressed. Port 8-bit output port that preset high when RESET goes low. user more port outputs (except together order higher drive.
Note: Care must exercised with operation. RESET, external loads this must ensure that output voltages stay above prevent chip from entering special modes. Also keep external loading less than 1000
Functional Description
architecture device modified Harvard architecture. With Harvard architecture, control store program memory (ROM) separated from data store memory (RAM). Both have their separate addressing space with separate address buses. architecture, though based Harvard architecture, permits transfer data from RAM. REGISTERS 8-bit addition, subtraction, logical shift operation instruction (tc) cycle time. There five registers: 8-bit Accumulator Register 15-bit Program Counter Register upper bits program counter (PC) lower bits program counter (PC) 8-bit address pointer, which optionally post auto incremented decremented. 8-bit alternate address pointer, which optionally post auto incremented decremented. 8-bit stack pointer, which points subroutine/ interrupt stack RAM). initialized address with reset. registers memory mapped with exception Accumulator Program Counter (PC). PROGRAM MEMORY Program memory consists 4096 bytes ROM. These bytes hold program instructions constant data (data tables LAID instruction, jump vectors instruction, interrupt vectors instruction). program memory addressed 15-bit program counter (PC). interrupts vector program memory location Hex.
Port following alternate features: INTR (External Interrupt Input) (Timer Capture Input) (Timer I/O) (MICROWIRE Serial Data Output) (MICROWIRE Serial Clock) (MICROWIRE Serial Data Input) Port following dedicated functions: WDOUT WATCHDOG and/or Clock Monitor dedicated output Oscillator dedicated output general purpose input
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Functional Description
DATA MEMORY
(Continued)
data memory address space includes on-chip data registers, registers (Configuration, Data Pin), control registers, MICROWIRE/PLUS shift register, various registers, counters associated with timers (with exception IDLE timer). Data memory addressed directly instruction indirectly pointers. device bytes RAM. Sixteen bytes mapped "registers" addresses Hex. These registers loaded immediately, also decremented tested with DRSZ (decrement register skip zero) instruction. memory pointer registers memory mapped into this space address locations respectively, with other registers (other than reserved register 0FF) being available general usage. instruction permits memory set, reset tested. registers (except memory mapped; therefore, bits register bits directly individually set, reset tested. accumulator bits also directly individually tested.
Note: contents undefined upon power-up.
DS009766-7
Power Supply Rise Time
FIGURE Recommended Reset Circuit
Oscillator Circuits
chip driven clock input input which between MHz. output clock (crystal configuration). input frequency divided down produce instruction cycle clock (1/tc).
Figure shows Crystal diagrams.
CRYSTAL OSCILLATOR connected make closed loop crystal resonator) controlled oscillator.
Reset
RESET input when pulled initializes microcontroller. Initialization will occur whenever RESET input pulled low. Upon initialization, data configuration registers Ports cleared, resulting these Ports being initialized TRI-STATE mode. Port exception noted below) since dedicated WATCHDOG and/or Clock Monitor error output pin. Port initialized high with RESET PSW, CNTRL, ICNTRL, T2CNTRL control registers cleared. Multi-Input Wakeup registers WKEN, WKEDG, WKPND cleared. Stack Pointer, initialized Hex. device comes reset with both WATCHDOG logic Clock Monitor detector armed, with both WATCHDOG service window bits Clock Monitor set. WATCHDOG Clock Monitor detector circuits inhibited during reset. WATCHDOG service window bits initialized maximum WATCHDOG service window clock cycles. Clock Monitor initialized high, will cause Clock Monitor error following reset clock reached minimum specified frequency termination reset. Clock Monitor error will cause active error output This error output will continue until 16-32 clock cycles following clock frequency reaching minimum specified value, which time output will enter TRI-STATE mode. external network shown should used ensure that RESET held until power supply chip stabilizes.
Table shows component values required various standard crystal values.
OSCILLATOR selecting single oscillator input, single oscillator circuit connected available general purpose input, and/or HALT restart pin.
Table shows variation oscillator frequencies functions component values.
DS009766-8
DS009766-9
FIGURE Crystal Oscillator Diagrams
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Oscillator Circuits
(pF) (pF)
(Continued)
TABLE Oscillator Configuration, 25°C 5.0V (pF) Freq (MHz) Instr. Cycle (µs) 10.8 Conditions
TABLE Crystal Oscillator Configuration, 25°C Freq (MHz) 0.455 Conditions
30-36 30-36 100-150
Note 200k,
Control Registers
CNTRL Register (Address X'00EE) Timer1 (T1) MICROWIRE/PLUS control register contains following bits: Select MICROWIRE/PLUS clock divide IEDG External interrupt edge polarity select Rising edge, Falling edge) MSEL Selects MICROWIRE/PLUS signals respectively T1C0 Timer Start/Stop control timer modes Timer Underflow Interrupt Pending Flag timer mode T1C1 Timer mode control T1C2 Timer mode control T1C3 Timer mode control T1C3 T1C2 T1C1 T1C0 MSEL IEDG ICNTRL Register (Address X'00E8) ICNTRL register contains following bits: T1ENB Timer Interrupt Enable Input capture edge T1PNDB Timer Interrupt Pending Flag capture edge µWEN Enable MICROWIRE/PLUS interrupt µWPND MICROWIRE/PLUS interrupt pending T0EN T0PND LPEN Timer Interrupt Enable (Bit toggle) Timer Interrupt pending Port Interrupt Enable (Multi-Input Wakeup/ Interrupt) could used flag
Unused LPENT0PND T0EN µWPND µWENT1PNDB T1ENB
Register (Address X'00EF) register contains following select bits: Global interrupt enable (enables interrupts) EXEN Enable external interrupt BUSY MICROWIRE/PLUS busy shifting flag EXPND External interrupt pending T1ENA Timer Interrupt Enable Timer Underflow Input capture edge T1PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow Mode capture edge mode Carry Flag Half Carry Flag T1PNDA T1ENA EXPND BUSY EXEN
T2CNTRL Register (Address X'00C6) T2CNTRL register contains following bits: T2ENB Timer Interrupt Enable Input capture edge T2PNDB Timer Interrupt Pending Flag capture edge T2ENA Timer Interrupt Enable Timer Underflow Input capture edge T2PNDA Timer Interrupt Pending Flag (Autoreload mode Underflow mode capture edge mode T2C0 Timer Start/Stop control timer modes Timer Underflow Interrupt Pending Flag timer mode Timer mode control Timer mode control Timer mode control
T2C1 T2C2 T2C3
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
Half-Carry also affected instructions that affect Carry flag. (Set Carry) (Reset Carry) instructions will respectively clear both carry flags. addition instructions, ADC, SUBC, instructions affect carry Half Carry flags.
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Timers
device contains very versatile timers (T0, T2). timers associated autoreload/capture registers power containing random data.
Figure shows block diagram timers.
DS009766-11
FIGURE Timers TIMER (IDLE TIMER) device supports applications that require maintaining real time power with IDLE mode. This IDLE mode support furnished IDLE timer which 16-bit timer. Timer runs continuously fixed rate instruction cycle clock, user cannot read write IDLE Timer which count down timer. Timer supports following functions: Exit Idle Mode (See Idle Mode description) WATCHDOG logic (See WATCHDOG description) Start delay HALT mode IDLE Timer generate interrupt when thirteenth toggles. This toggle latched into T0PND pending flag, will occur every maximum clock frequency µs). control flag T0EN allows interrupt from thirteenth Timer enabled disabled. Setting T0EN will enable interrupt, while resetting will disable interrupt. TIMER TIMER device powerful timer/counter blocks, associated features functioning timer block described referring timer block Since timer blocks, identical, comments equally applicable either timer block. Each timer block consists 16-bit timer, supporting 16-bit autoreload/capture registers, RxB. Each timer block pins associated with
TxB. supports required timer block, while input timer block. powerful flexible timer block allows device easily perform timer functions with minimal software overhead. timer block three operating modes: Processor Independent mode, External Event Counter mode, Input Capture mode. control bits TxC3, TxC2, TxC1 allow selection different modes operation. Mode Processor Independent Mode name suggests, this mode allows device generate signal with very minimal user intervention. user only define parameters signal time time). Once begun, timer block will continuously generate signal completely independent microcontroller. user software services timer block only when parameters require updating. this mode timer counts down fixed rate Upon every underflow timer alternately reloaded with contents supporting registers, RxB. very first underflow timer causes timer reload from register RxA. Subsequent underflows cause timer reloaded from registers alternately beginning with register RxB. Timer control bits, TxC3, TxC2 TxC1 timer mode operation.
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Timers
(Continued)
Figure shows block diagram timer mode.
DS009766-13
FIGURE Timer Mode underflows programmed toggle output pin. underflows also programmed generate interrupts. Underflows from timer alternately latched into pending flags, TxPNDA TxPNDB. user must reset these pending flags under software control. control enable flags, TxENA TxENB, allow interrupts from timer underflow enabled disabled. Setting timer enable flag TxENA will cause interrupt when timer underflow causes register reloaded into timer. Setting timer enable flag TxENB will cause interrupt when timer underflow causes register reloaded into timer. Resetting timer enable flags will disable associated interrupts. Either both timer underflow interrupts enabled. This gives user flexibility interrupting once period either rising falling edge output. Alternatively, user choose interrupt both edges output. Mode External Event Counter Mode This mode quite similar processor independent mode described above. main difference that timer, clocked input signal from pin. timer control bits, TxC3, TxC2 TxC1 allow timer clocked either positive negative edge from pin. Underflows from timer latched into TxPNDA pending flag. Setting TxENA control flag will cause interrupt when timer underflows. this mode input used independent positive edge sensitive interrupt input TxENB control flag set. occurrence positive edge input latched into TxPNDB flag.
Figure shows block diagram timer External Event Counter mode.
Note: output available this mode since being used counter input clock.
DS009766-14
FIGURE Timer External Event Counter Mode Mode Input Capture Mode device precisely measure external frequencies time external events placing timer block, input capture mode.
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this mode, timer constantly running fixed rate. registers, RxB, capture regis-
COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Timers
(Continued)
ters. Each register acts conjunction with pin. register acts conjunction with register acts conjunction with pin. timer value gets copied over into register when trigger event occurs corresponding pin. Control bits, TxC3, TxC2 TxC1, allow trigger events specified either positive negative edge. trigger condition each input specified independently. trigger conditions also programmed generate interrupts. occurrence specified trigger condition pins will respectively latched into pending flags, TxPNDA TxPNDB. control flag TxENA allows interrupt either enabled disabled. Setting TxENA flag enables interrupts generated when selected trigger condition occurs pin. Similarly, flag TxENB controls interrupts from pin. Underflows from timer also programmed generate interrupts. Underflows latched into timer TxC0 pending flag (the TxC0 control serves timer underflow interrupt pending flag Input Capture mode). Consequently, TxC0 control should reset when entering Input Capture mode. timer underflow interrupt enabled with TxENA control flag. When interrupt occurs Input Capture mode, user must check both
TxPNDA TxC0 pending flags order determine whether input capture timer underflow both) caused interrupt.
Figure shows block diagram timer Input Capture mode.
TIMER CONTROL FLAGS timers have indentical control structures. control bits their functions summarized below. TxC0 Timer Start/Stop control Modes (Processor Independent External Event Counter), where Start, Stop Timer Underflow Interrupt Pending Flag Mode (Input Capture) TxPNDA Timer Interrupt Pending Flag TxPNDB Timer Interrupt Pending Flag TxENA Timer Interrupt Enable Flag TxENB Timer Interrupt Enable Flag Timer Interrupt Enabled Timer Interrupt Disabled TxC3 Timer mode control TxC2 Timer mode control TxC1 Timer mode control
DS009766-15
FIGURE Timer Input Capture Mode
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Timers
TxC3
(Continued)
timer mode control bits (TxC3, TxC2 TxC1) detailed below: TxC2 TxC1 Timer Mode MODE (External Event Counter) MODE (External Event Counter) MODE (PWM) Toggle MODE (PWM) Toggle MODE (Capture) Captures: Pos. Edge Pos. Edge MODE (Capture) Captures: Pos. Edge Neg. Edge MODE (Capture) Captures: Neg. Edge Pos. Edge MODE (Capture) Captures: Neg. Edge Neg. Edge Interrupt Source Timer Underflow Timer Underflow Autoreload Autoreload Pos. Edge Timer Underflow Pos. Edge Timer Underflow Neg. Edge Timer Underflow Neg. Edge Timer Underflow Neg. Edge Pos. Edge Neg. Edge Edge Pos. Edge Autoreload Autoreload Pos. Edge Interrupt Source Pos. Pos. Edge Neg. Edge Timer Counts
Power Save Modes
device offers user power save modes operation: HALT IDLE. HALT mode, microcontroller activities stopped. IDLE mode, on-board oscillator circuitry timer active other microcontroller activities stopped. either mode, on-board RAM, registers, states, timers (with exception unaltered. HALT MODE device placed HALT mode writing HALT flag data bit). microcontroller activities, including clock, timers, stopped. WATCHDOG logic disabled during HALT mode. However, clock monitor circuitry, enabled, remains active will cause WATCHDOG output (WDOUT) low. HALT mode used user does want activate WDOUT pin, Clock Monitor should disabled after device comes reset (resetting Clock Monitor control with first write WDSVR register). HALT mode, power requirements device minimal applied voltage (VCC) decreased 2.0V) without altering state machine. device supports three different ways exiting HALT mode. first method exiting HALT mode with Multi-Input Wakeup feature port. second method with high transition (G7) pin.
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This method precludes crystal clock configuration (since becomes dedicated output), used with clock configuration. third method exiting HALT mode pulling RESET low. Since crystal ceramic resonator selected oscillator, Wakeup signal allowed start chip running immediately since crystal oscillators ceramic resonators have delayed start time reach full amplitude frequency stability. IDLE timer used generate fixed delay ensure that oscillator indeed stabilized before allowing instruction execution. this case, upon detecting valid Wakeup signal, only oscillator circuitry enabled. IDLE timer loaded with value clocked with instruction cycle clock. clock derived dividing oscillator clock down factor Schmitt trigger following inverter chip ensures that IDLE timer clocked only when oscillator sufficiently large amplitude meet Schmitt trigger specifications. This Schmitt trigger part oscillator closed loop. startup timeout from IDLE timer enables clock signals routed rest chip. clock option being used, fixed delay introduced optionally. control bit, CLKDLY, mapped configuration controls whether delay
COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Power Save Modes
(Continued)
introduced not. delay included CLKDLY set, excluded CLKDLY reset. CLKDLY cleared reset. device mask options associated with HALT mode. first mask option enables HALT mode feature, while second mask option disables HALT mode. With HALT mode enable mask option, device will enter exit HALT mode described above. With HALT disable mask option, device cannot placed HALT mode (writing HALT flag will have effect). WATCHDOG detector circuit inhibited during HALT mode. However, clock monitor circuit, enabled, remains active during HALT mode order ensure clock monitor error device inadvertently enters HALT mode result runaway program power glitch. IDLE MODE device placed IDLE mode writing IDLE flag data bit). this mode, activity, except associated on-board oscillator circuitry, WATCHDOG logic, clock monitor IDLE Timer stopped. with HALT mode, device returned normal operation with reset, with Multi-Input Wake-up from Port. Alternately, microcontroller resumes normal operation from IDLE mode when thirteenth (representing 4.096 internal clock frequency MHz, IDLE Timer toggles. This toggle condition thirteenth IDLE Timer latched into T0PND pending flag. user option being interrupted with transition thirteenth IDLE Timer interrupt enabled disabled T0EN control bit. Setting T0EN flag enables interrupt vice versa. user enter IDLE mode with Timer interrupt enabled. this case, when T0PND gets set, device will first execute Timer interrupt service routine then return instruction following "Enter Idle Mode" instruction. Alternatively, user enter IDLE mode with IDLE Timer interrupt disabled. this case, device will resume normal operation with instruction immediately following "Enter IDLE Mode" instruction.
Note: necessary program instructions following both HALT mode IDLE mode instructions. These instructions necessary allow clock resynchronization following HALT IDLE modes.
Multi-Input Wakeup
Multi-Input Wakeup feature used return (wakeup) device from either HALT IDLE modes. Alternately Multi-Input Wakeup/Interrupt feature also used generate edge selectable external interrupts.
Figure shows Multi-Input Wakeup logic. Multi-Input Wakeup feature utilizes Port. user selects which particular port combination Port bits) will cause device exit HALT IDLE modes. selection done through Reg: WKEN. Reg: WKEN 8-bit read/write register, which contains control every port bit. Setting particular WKEN enables Wakeup from associated port pin. user select whether trigger condition selected Port going either positive edge (low high transition) negative edge (high transition). This selection made Reg: WKEDG, which 8-bit control register with assigned each Port pin. Setting control will select trigger condition negative edge that particular Port pin. Resetting selects trigger condition positive edge. Changing edge select entails several steps order avoid pseudo Wakeup condition result edge change. First, associated WKEN should reset, followed edge select change WKEDG. Next, associated WKPND should cleared, followed associated WKEN being re-enabled. example serve clarify this procedure. Suppose wish change edge select from positive (low going high) negative (high going low) Port where previously been enabled input interrupt. program would follows: RBIT WKEN SBIT WKEDG RBIT WKPND SBIT WKEN port bits have been used outputs then changed inputs with Multi-Input Wakeup/Interrupt, safety procedure should also followed avoid inherited pseudo wakeup conditions. After selected port bits have been changed from output input before associated WKEN bits enabled, associated edge select bits WKEDG should reset desired edge selects, followed associated WKPND bits being cleared. This same procedure should used following reset, since port inputs left floating result reset. occurrence selected trigger condition Multi-Input Wakeup latched into pending register called WKPND. respective bits WKPND register will occurrence selected trigger edge corresponding Port pin. user responsibility clearing these pending flags. Since WKPND pending register occurrence selected wakeup conditions, device will enter HALT mode Wakeup both enabled pending. Consequently, user responsibility clearing pending flags before attempting enter HALT mode. WKEN, WKPND WKEDG read/write registers, cleared reset.
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Multi-Input Wakeup
(Continued)
DS009766-16
FIGURE Multi-Input Wake Logic PORT INTERRUPTS Port provides user with additional eight fully selectable, edge sensitive interrupts which vectored into same service subroutine. interrupt from Port shares logic with wake circuitry. register WKEN allows interrupts from Port individually enabled disabled. register WKEDG specifies trigger condition either positive negative edge. Finally, register WKPND latches pending trigger conditions. (Global Interrupt Enable) enables interrupt function. control flag, LPEN, functions global interrupt enable Port interrupts. Setting LPEN flag will enable interrupts vice versa. separate global pending flag needed since register WKPND adequate. Since Port also used waking device HALT IDLE modes, user elect exit HALT IDLE modes either with without interrupt enabled. elects disable interrupt, then device will restart execution from instruction immediately following instruction that placed microcontroller HALT IDLE modes. other case, device will first execute interrupt service routine then revert normal operation. Wakeup signal will start chip running immediately since crystal oscillators ceramic resonators have finite start time. IDLE Timer (T0) generates fixed delay ensure that oscillator indeed stabilized before allowing device execute instructions. this case, upon detecting valid Wakeup signal, only oscillator circuitry IDLE Timer enabled. IDLE Timer loaded with value clocked from instruction cycle clock. clock derived dividing down oscillator clock factor Schmitt trigger following on-chip inverter ensures that IDLE timer clocked only when oscillator sufficiently large amplitude meet Schmitt trigger specifications. This Schmitt trigger part oscillator closed loop.
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startup timeout from IDLE timer enables clock signals routed rest chip. clock option used, fixed delay under software control. control flag, CLKDLY, configuration allows clock start delay optionally inserted. Setting CLKDLY flag high will cause clock start delay inserted resetting will exclude clock start delay. CLKDLY flag cleared during reset, clock start delay present following reset with clock options.
Interrupts
device supports vectored interrupt scheme. supports total interrupt sources. following table lists possible interrupt sources, their arbitration ranking memory locations reserved interrupt vector each source. bytes program memory space reserved each interrupt source. interrupt sources except software interrupt maskable. Each maskable interrupts have Enable Pending bit. maskable interrupt active associated enable pending bits set. interrupt active, then processor will interrupted soon ready start executing instruction except above conditions happen during Software Trap service routine. This exception described Software Trap sub-section. interruption process accomplished with INTR instruction (opcode 00), which jammed inside Instruction Register replaces opcode about executed. following steps performed every interrupt: (Global Interrupt Enable) reset. address instruction about executed pushed into stack. (Program Counter) branches address 00FF. This procedure takes cycles execute.
COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Interrupts
(Continued) Arbitration Ranking Highest Source Software Reserved External Timer Timer Timer MICROWIRE/PLUS Reserved Reserved Reserved Timer Timer Reserved Reserved (10) Lowest
page,
Vector Description INTR Instruction Future Edge Underflow T1A/Underflow BUSY Goes Future UART UART T2A/Underflow Future Future Port Edge Instr. Execution without Interrupts Address Hi-Low Byte 0yFE-0yFF 0yFC-0yFD 0yFA-0yFB 0yF8-0yF9 0yF6-0yF7 0yF4-0yF5 0yF2-0yF3 0yF0-0yF1 0yEE-0yEF 0yEC-0yED 0yEA-0yEB 0yE8-0yE9 0yE6-0yE7 0yE4-0yE5 0yE2-0yE3 0yE0-0yE1
Port L/Wakeup Default
this time, since other maskable interrupts disabled. user free whatever context switching required saving context machine stack with PUSH instructions. user would then program (Vector Interrupt Select) instruction order branch interrupt service routine highest priority interrupt enabled pending time VIS. Note that this necessarily interrupt that caused branch address location 00FF prior context switching. Thus, interrupt with higher rank than which caused interruption becomes active before decision which interrupt service made VIS, then interrupt with higher rank will override lower ones will acknowledged. lower priority interrupt(s) still pending, however, will cause another interrupt immediately following completion interrupt service routine associated with higher priority interrupt just serviced. This lower priority interrupt will occur immediately following RETI (Return from Interrupt) instruction interrupt service routine just completed. Inside interrupt service routine, associated pending cleared software. RETI (Return from Interrupt) instruction interrupt service routine will (Global Interrupt Enable) bit, allowing processor interrupted again another interrupt active pending. instruction looks active interrupts time executed performs indirect jump beginning service routine with highest rank. addresses different interrupt service routines, called vectors, chosen user stored table starting 01E0 (assuming that located between 00FF 01DF). vectors 15-bit wide therefore occupy locations.
vector table must located same 256-byte block (0y00 0yFF) except located last address block. this case, table must next block. vector table cannot inserted first 256-byte block. vector maskable interrupt with lowest rank located 0yE0 (Hi-Order byte) 0yE1 (Lo-Order byte) forth increasing rank number. vector maskable interrupt with highest rank located 0yFA (Hi-Order byte) 0yFB (Lo-Order byte). Software Trap highest rank vector located 0yFE 0yFF. accident, gets executed interrupt active, then (Program Counter) will branch vector located 0yE0-0yE1. WARNING Default interrupt handle routine must present. minimum, this handler should confirm that cleared (this indicates that interrupt sequence been taken), take care required housekeeping, restore context return. Some sort Warm Restart procedure should implemented. These events occur without error part system designer programmer.
Note: There always possibility interrupt occurring during instruction which attempting reset other interrupt enable bit. this occurs when single cycle instruction being used reset interrupt enable bit, interrupt enable will reset interrupt still occur. This because interrupt processing started same time interrupt being reset. avoid this scenario, user should always two, three, four cycle instruction reset interrupt enable bits.
Figure shows Interrupt block diagram.
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Interrupts
(Continued)
DS009766-18
FIGURE Interrupt Block Diagram SOFTWARE TRAP Software Trap (ST) special kind non-maskable interrupt which occurs when INTR instruction (used acknowledge interrupts) fetched from placed inside instruction register. This happen when pointing beyond available address space when stack over-popped. When occurs, user re-initialize stack pointer recovery procedure (similar reset, necessarily containing same initialization procedures) before restarting. occurrence latched into pending bit. affected pending (not accessible user) used inhibit other interrupts direct program service routine with instruction. RPND instruction used clear software interrupt pending bit. This pending also cleared reset. highest rank among interrupts. Nothing (except another interrupt being serviced. lower limit service window fixed 2048 instruction cycles. Bits WDSVR register allow user pick upper limit service window. Table shows four possible combinations lower upper limits WATCHDOG service window. This flexibility choosing WATCHDOG service window prevents undue burden user software. Bits WDSVR register represent 5-bit Data field. data fixed 01100. WDSVR Register Clock Monitor Select bit. TABLE WATCHDOG Service Register (WDSVR) Window Select Data Clock Monitor
TABLE WATCHDOG Service Window Select WDSVR WDSVR Service Window (Lower-Upper Limits) 2k-8k Cycles 2k-16k Cycles 2k-32k Cycles 2k-64k Cycles
WATCHDOG
device contains WATCHDOG clock monitor. WATCHDOG designed detect user program getting stuck infinite loops resulting loss program control "runaway" programs. Clock Monitor used detect absence clock very slow clock below specified rate pin. WATCHDOG consists independent logic blocks: UPPER LOWER. UPPER establishes upper limit service window LOWER defines lower limit service window. Servicing WATCHDOG consists writing specific value WATCHDOG Service Register named WDSVR which memory mapped RAM. This value composed three fields, consisting 2-bit Window Select, 5-bit Data field, 1-bit Clock Monitor Select field. Table shows WDSVR register.
Clock Monitor
Clock Monitor aboard device selected deselected under program control. Clock Monitor guaranteed reject clock instruction cycle clock (1/tc) greater equal kHz. This equates clock input rate greater equal kHz.
WATCHDOG Operation
WATCHDOG Clock Monitor disabled during reset. device comes reset with WATCHDOG armed, WATCHDOG Window Select bits (bits WDSVR Register) set, Clock Monitor (bit
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WATCHDOG Operation
(Continued)
WDSVR Register) enabled. Thus, Clock Monitor error will occur after coming reset, instruction cycle clock frequency reached minimum specified value, including case where oscillator fails start. WDSVR register written only once after reset data (bits through WDSVR Register) must match valid write. This write WDSVR register involves irrevocable choices: selection WATCHDOG service window (ii) enabling disabling Clock Monitor. Hence, first write WDSVR Register involves selecting deselecting Clock Monitor, select WATCHDOG service window match WATCHDOG data. Subsequent writes WDSVR register will compare value being written user WATCHDOG service window value data (bits through WDSVR Register. Table shows sequence events that occur. user must service WATCHDOG least once before upper limit serivce window expires. WATCHDOG serviced more than once every lower
limit service window. user service WATCHDOG many times wished time period between lower upper limits service window. first write WDSVR Register also counted WATCHDOG service. WATCHDOG output associated with This WDOUT pin, port WDOUT active low. WDOUT high impedance state inactive state. Upon triggering WATCHDOG, logic will pull WDOUT (G1) additional tc-32 cycles after signal level WDOUT goes below lower Schmitt trigger threshold. After this delay, device will stop forcing WDOUT output low. WATCHDOG service window will restart when WDOUT goes high recommended that user WDOUT back through resistor order pull WDOUT high. WATCHDOG service while WDOUT signal active will ignored. state WDOUT guaranteed reset, powers then WATCHDOG will time WDOUT will enter high impedance state.
TABLE WATCHDOG Service Actions Data Match Don't Care Mismatch Don't Care Window Data Match Mismatch Don't Care Don't Care Clock Monitor Match Don't Care Don't Care Mismatch Valid Service: Restart Service Window Error: Generate WATCHDOG Output Error: Generate WATCHDOG Output Error: Generate WATCHDOG Output Action
TABLE MICROWIRE/PLUS Master Mode Clock Select Clock Monitor forces upon detecting clock frequency error. Clock Monitor error will continue until clock frequency reached minimum specified value, after which output will enter high impedance TRI-STATE mode following tc-32 clock cycles. Clock Monitor generates continual Clock Monitor error oscillator fails start, fails reach minimum specified frequency. specification Clock Monitor follows: 1/tc clock rejection. 1/tc Guaranteed clock rejection. WATCHDOG CLOCK MONITOR SUMMARY following salient points regarding WATCHDOG Clock Monitor should noted:
Where instruction cycle clock
initial WATCHDOG service must match data value WATCHDOG Service register WDSVR order avoid WATCHDOG error. Subsequent WATCHDOG services must match three data fields WDSVR order avoid WATCHDOG errors. correct data value cannot read from WATCHDOG Service register WDSVR. attempt read this data value 01100 from WDSVR will read data value 0's. WATCHDOG detector circuit inhibited during both HALT IDLE modes. Clock Monitor detector circuit active during both HALT IDLE modes. Consequently, device inadvertently entering HALT mode will detected Clock Monitor error (provided that Clock Monitor enable option been selected program). With single-pin oscillator mask option selected CLKDLY reset, WATCHDOG service window will resume following HALT mode from where left before entering HALT mode.
Both WATCHDOG Clock Monitor detector circuits inhibited during reset. Following reset, WATCHDOG Clock Monitor both enabled, with WATCHDOG having maximum service window selected. WATCHDOG service window Clock Monitor enable/disable option only changed once, during initial WATCHDOG service following reset.
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WATCHDOG Operation
(Continued)
With crystal oscillator mask option selected, with single-pin oscillator mask option selected CLKDLY set, WATCHDOG service window will selected value from WDSVR following HALT. Consequently, WATCHDOG should serviced least 2048 instruction cycles following HALT, must serviced within selected window avoid WATCHDOG error. IDLE timer initialized with reset. user sync IDLE counter cycle with IDLE counter (T0) interrupt monitoring T0PND flag. T0PND flag whenever thirteenth IDLE counter toggles (every 4096 instruction cycles). user responsible resetting T0PND flag. hardware WATCHDOG service occurs just device exits IDLE mode. Consequently, Watchdog should serviced least 2048 instruction cycles following IDLE, must serviced within selected window avoid WATCHDOG error. Following reset, initial WATCHDOG service (where service window Clock Monitor enable/disable must selected) programmed anywhere within maximum service window (65,536 instruction cycles) initialized RESET. Note that this initial WATCHDOG service programmed within initial 2048 instruction cycles without causing WATCHDOG error.
ers, E2PROMs etc.) with other microcontrollers which support MICROWIRE interface. consists 8-bit serial shift register (SIO) with serial data input (SI), serial data output (SO) serial shift clock (SK). Figure shows block diagram MICROWIRE logic. shift clock selected from either internal source external source. Operating MICROWIRE/PLUS arrangement with internal clock source called Master mode operation. Similarly, operating MICROWIRE arrangement with external shift clock called Slave mode operation.
DS009766-20
FIGURE MICROWIRE/PLUS Block Diagram CNTRL register used configure control MICROWIRE/PLUS mode. MICROWIRE/PLUS, MSEL CNTRL register one. master mode, clock rate selected bits, SL1, CNTRL register. Table details different clock rates that selected. MICROWIRE/PLUS OPERATION Setting BUSY register causes MICROWIRE/PLUS start shifting data. gets reset when eight data bits have been shifted. user reset BUSY software allow less than bits shift. enabled, interrupt generated when eight data bits have been shifted. device enter MICROWIRE/PLUS mode either Master Slave. Figure shows COP888CL microcontrollers several peripherals interconnected using MICROWIRE/PLUS arrangements. Warning: register should only loaded when clock low. Loading register while clock high will result undefined data register. clock normally when shifting. Setting BUSY flag when input clock high MICROWIRE/PLUS slave mode cause current clock shift register narrow. safety, BUSY flag should only when input clock low. MICROWIRE/PLUS Master Mode Operation MICROWIRE/PLUS Master mode operation shift clock (SK) generated internally. MICROWIRE Master always initiates data exchanges. MSEL CNTRL register must enable functions onto Port. pins must also selected outputs setting appropriate bits Port configuration register. Table summarizes settings required Master mode operation.
Detection Illegal Conditions
device detect various illegal conditions resulting from coding errors, transient noise, power supply voltage drops, runaway programs, etc. Reading undefined gets zeros. opcode software interrupt zero. program fetches instructions from undefined ROM, this will force software interrupt, thus signaling that illegal condition occurred. subroutine stack grows down each call (jump subroutine), interrupt, PUSH, grows each return POP. stack pointer initialized location during reset. Consequently, there more returns than calls, stack pointer will point addresses (which undefined RAM). Undefined from addresses read 1's, which turn will cause program return address 7FFF Hex. This undefined location instruction fetched (all 0's) from this location will generate software interrupt signaling illegal condition. Thus, chip detect following illegal conditions: Executing from undefined Over "POP"ing stack having more returns than calls. When software interrupt occurs, user re-initialize stack pointer recovery procedure before restarting (this recovery program probably similar that following reset, might contain same program initialization procedures). recovery program should reset software interrupt pending using RPND instruction.
MICROWIRE/PLUS
MICROWIRE/PLUS serial synchronous communications interface. MICROWIRE/PLUS capability enables device interface with National Semiconductor's MICROWIRE peripherals (i.e. converters, display drivwww.national.com
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MICROWIRE/PLUS
(Continued)
Alternate Phase Operation device allows either normal clock alternate phase clock shift data register. both modes normally low. normal mode data shifted rising edge clock data shifted falling edge clock. register shifted each falling edge clock. alternate phase operation, data shifted falling edge clock shifted rising edge clock.
MICROWIRE/PLUS Slave Mode Operation MICROWIRE/PLUS Slave mode operation clock generated external source. Setting MSEL CNTRL register enables functions onto Port. must selected input selected output setting resetting appropriate Port configuration register. Table summarizes settings required enter Slave mode operation. user must BUSY flag immediately upon entering Slave mode. This will ensure that data bits sent Master will shifted properly. After eight clock pulses BUSY flag will cleared sequence repeated.
DS009766-21
FIGURE MICROWIRE/PLUS Application control flag, SKSEL, allows either normal clock alternate clock selected. Resetting SKSEL causes MICROWIRE/PLUS logic clocked from normal signal. Setting SKSEL flag selects alternate clock. SKSEL mapped into configuration bit. SKSEL flag will power reset condition, selecting normal signal. This table assumes that control flag MSEL set. TABLE (SO) Config. (SK) Config. TRISTATE TRISTATE Int. Int. Ext. Ext. MICROWIRE/PLUS Master MICROWIRE/PLUS Master MICROWIRE/PLUS Slave MICROWIRE/PLUS Slave Fun. Fun. Operation
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Memory
RAM, ports registers (except mapped into data memory address space Address Contents On-Chip bytes Unused Address Space Timer Lower Byte Timer Upper Byte Timer Autoload Register T2RA Lower Byte Timer Autoload Register T2RA Upper Byte Timer Autoload Register T2RB Lower Byte Timer Autoload Register T2RB Upper Byte Timer Control Register WATCHDOG Service Register (Reg:WDSVR) MIWU Edge Select Register (Reg:WKEDG) MIWU Enable Register (Reg:WKEN) MIWU Pending Register (Reg:WKPND) Reserved Reserved Reserved Port Data Register Port Configuration Register Port Input Pins (Read Only) Reserved Port Port Data Register Port Configuration Register Port Input Pins (Read Only) Port Input Pins (Read Only) Port Data Register Port Configuration Register Port Input Pins (Read Only) Reserved Port Port Data Register Reserved Port Reserved Timer Autoload Register T1RB Lower Byte Timer Autoload Register T1RB Upper Byte ICNTRL Register MICROWIRE Shift Register Timer Lower Byte Timer Upper Byte Timer Autoload Register T1RA Lower Byte Timer Autoload Register T1RA Upper Byte
Address Register
Contents CNTRL Control Register On-Chip Mapped Registers Register Register Register Reserved
Reading memory locations 70-7F will return ones. Reading other unused memory locations will return undefined data.
Addressing Modes
device addressing modes, operand addressing four transfer control. OPERAND ADDRESSING MODES Register Indirect This "normal" addressing mode. operand data memory addressed pointer pointer. Register Indirect (with auto post increment decrement pointer) This addressing mode used with instructions. operand data memory addressed pointer pointer. This register indirect mode that automatically post increments decrements register after executing instruction. Direct instruction contains 8-bit address field that directly points data memory operand. Immediate instruction contains 8-bit immediate field operand. Short Immediate This addressing mode used with Load Immediate instruction. instruction contains 4-bit immediate field operand. Indirect This addressing mode used with LAID instruction. contents accumulator used partial address (lower bits accessing data operand from program memory. TRANSFER CONTROL ADDRESSING MODES Relative This mode used instruction, with instruction field being added program counter program location. range from allow 1-byte relative jump implemented instruction). There "pages" when using since bits used. Absolute This mode used with instructions, with instruction field bits replacing lower bits program counter (PC). This allows jumping location current program memory segment.
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Addressing Modes
Absolute Long
(Continued)
contents this program memory location serve partial address (lower bits jump next instruction.
Note: special case Indirect Transfer Control addressing mode, where double byte vector associated with interrupt transferred from adjacent addresses program memory into program counter (PC) order jump associated interrupt service routine.
This mode used with JMPL JSRL instructions, with instruction field bits replacing entire bits program counter (PC). This allows jumping location current program memory space. Indirect This mode used with instruction. contents accumulator used partial address (lower bits accessing location program memory.
Instruction Register Symbol Definition
Registers 8-Bit Accumulator Register 8-Bit Address Register 8-Bit Address Register 8-Bit Stack Pointer Register 15-Bit Program Counter Register Upper Bits Lower Bits Register Carry Register Half Carry Register Global Interrupt Enable Interrupt Vector Upper Byte Interrupt Vector Lower Byte Symbols Meml Memory Indirectly Addressed Register Memory Indirectly Addressed Register Direct Addressed Memory Direct Addressed Memory Direct Addressed Memory Immediate Data 8-Bit Immediate Data Register Memory: Addresses (Includes Number Loaded with Exchanged with
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Instruction
SUBC ANDSZ IFEQ IFEQ IFNE IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND LAID DCOR SWAP IFNC PUSH JMPL
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(Continued)
INSTRUCTION
A,Meml A,Meml A,Meml A,Meml A,Imm A,Meml A,Meml MD,Imm A,Meml A,Meml A,Meml with Carry Subtract with Carry Logical Logical Immed., Skip Zero Logical Logical EXclusive EQual EQual Equal Greater Than Equal Decrement Reg., Skip Zero Reset Reset PeNDing Flag A,Mem A,[X] A,Meml A,[X] B,Imm Mem,Imm Reg,Imm ],Imm EXchange with Memory EXchange with Memory LoaD with Memory LoaD with Memory LoaD with Immed. LoaD Memory Immed LoaD Register Memory Immed. EXchange with Memory EXchange with Memory LoaD with Memory LoaD with Memory LoaD Memory Immed. CLeaR INCrement DECrementA Load InDirect from Decimal CORrect Rotate Right thru Rotate Left thru SWAP nibbles Reset Addr. Addr. Disp. stack into PUSH onto stack Vector Interrupt Service Routine Jump absolute Long Jump absolute Jump relative short
Meml Meml Carry Half Carry MemI Carry Half Carry Meml Skip next Imm) Meml Meml Compare Imm, next Compare Meml, next Meml Compare Meml, next Meml Compare Meml, next Meml next lower bits RegReg- Skip bit, (bit immediate) bit, true next instruction Reset Software Interrupt Pending Flag AMem A[X] AMeml A[X] A[B], A[X], [B], [X], Imm, (PU,A) ABCD correction (follows ADC, SUBC) A7.A4 A3.A0 true, next instruction true, next instruction SPSP [SP] [SP]A, [VU], [VL] bits, 32k) PC9.0i bits) +32, except
#,Mem #,Mem #,Mem
COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Instruction
(Continued) (Continued) [SP] [SP-1] PU,SP-2, [SP] [SP-1] PU,SP-2, PC9.0 (PU,A) SP+2, [SP], [SP-1] SP+2, [SP],PU [SP-1] SP+2, [SP],PU [SP-1],GIE [SP] [SP-1] SP-2, PC+1
INSTRUCTION
JSRL RETSK RETI INTR Addr. Addr
Jump SubRoutine Long Jump SubRoutine Jump InDirect RETurn from subroutine RETurn SKip RETurn from Interrupt Generate Interrupt OPeration
Instruction Execution Time
Most instructions single byte (with immediate addressing mode instructions taking bytes). Most single byte instructions take cycle time execute. Skipped instructions require number cycles skipped, where equals number bytes skipped instruction opcode. BYTES CYCLES INSTRUCTION table details. Bytes Cycles Instruction following table shows number bytes cycles each instruction format byte/cycle. Arithmetic Logic Instructions SUBC IFEQ IFNE IFGT IFBNE DRSZ SBIT RBIT IFBIT RPND Direct Immed. Instructions Using CLRA INCA DECA LAID DCOR RRCA RLCA SWAPA IFNC PUSHA POPA ANDSZ
Transfer Control Instructions JMPL JSRL RETSK RETI INTR
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Instruction Execution Time
Memory Transfer Instructions Register Indirect Mem, Reg, IFEQ
(Continued)
Direct
Immed.
Register Indirect Auto Incr. Decr. [B+, [X+,
Memory location addressed directly.
Opcode Table
Upper Nibble Along X-Axis Lower Nibble Along Y-Axis 0F0, 0F1, 0F2, 0F3, 0F4, 0F5, 0F6, 0F7, 0F8, 0F9, 0FA, 0FB, 0FC, 0FD, 0FE, 0FF, DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ DRSZ
RRCA [X+] [X-] RPND A,[X]
A,[B+] A,[B-] LAID A,[B]
A,#i SUBC IFEQ A,#i IFGT A,#i A,#i A,#i A,#i A,#i A,#i IFNE A,#i [B+],#i [B-],#i A,Md A,Md [B],#i B,#i INCA DECA POPA
A,[B] A,[B] IFEQ A,[B] IFGT A,[B] A,[B] A,[B] A,[B] A,[B] IFNC
IFNE A,[B] A,[X+] A,[X-] Md,#i A,[X]
RLCA IFEQ Md,#i A,[B+] A,[B-] JMPL JSRL A,[B]
RETSK RETI
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Opcode Table
(Continued)
Upper Nibble Along X-Axis Lower Nibble Along Y-Axis IFBIT 0,[B] IFBIT 1,[B] IFBIT 2,[B] IFBIT 3,[B] IFBIT 4,[B] IFBIT 5,[B] IFBIT 6,[B] IFBIT 7,[B] SBIT 0,[B] SBIT 1,[B] SBIT 2,[B] SBIT 3,[B] SBIT 4,[B] SBIT 5,[B] SBIT 6,[B] SBIT 7,[B] RBIT 0,[B] RBIT 1,[B] RBIT 2,[B] RBIT 3,[B] RBIT 4,[B] RBIT 5,[B] RBIT 6,[B] RBIT 7,[B] B,#00 IFBNE B,#01 IFBNE B,#02 IFBNE B,#03 IFBNE B,#04 IFBNE B,#05 IFBNE B,#06 IFBNE B,#07 IFBNE PUSHA B,#08 IFBNE DCORA B,#09 IFBNE SWAPA B,#0A IFBNE CLRA B,#0B IFBNE
ANDSZ
B,#0F B,#0E B,#0D B,#0C
IFBNE IFBNE IFBNE IFBNE
x000-x0FF x100-x1FF x200-x2FF x300-x3FF x400-x4FF x500-x5FF x600-x6FF x700-x7FF x800-x8FF x900-x9FF xA00-xAFF xB00-xBFF xC00-xCFF xD00-xDFF xE00-xEFF xF00-xFFF
x000-x0FF x100-x1FF x200-x2FF x300-x3FF x400-x4FF x500-x5FF x600-x6FF x700-x7FF x800-x8FF x900-x9FF xA00-xAFF xB00-xBFF xC00-xCFF xD00-xDFF xE00-xEFF xF00-xFFF
INTR
Where, immediate data directly addressed memory location
unused opcode
Note opcode also opcode IFBIT #i,A
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Mask Options
mask programmable options shown below. options programmed same time pattern submission. OPTION CLOCK CONFIGURATION Crystal Oscillator (CKI/10) (CKO) clock generator output crystal/resonator clock input Single-pin controlled oscillator (CKI/10) available HALT restart and/or general purpose input OPTION HALT Enable HALT mode Disable HALT mode OPTION BONDING 44-Pin 40-Pin N.A. 28-Pin 28-Pin
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Development Support
SUMMARY
full hardware configurable break, trace trace control, pass count increment events. Tool integrated interactive symbolic debugger supports both assembler (COFF) Compiler (.COD) linked object formats. Real time performance profiling analysis; selectable bucket definition. Watch windows, content updated automatically each execution break. Instruction instruction memory/register changes displayed source window when single step operation. Single base unit debugger software reconfigurable support entire COP8 family; only probe personality needs change. Debugger software processor customized, reconfigured from master model file. Processor specific symbolic display registers level assignments, configured from master model file. Halt/Idle mode notification. On-line HELP customized specific processor using master model file. Includes copy COP8-DEV-IBMA assembler linker SDK.
iceMASTER: IM-COP8/400 Full feature in-circuit emulation COP8 products. full COP8 Basic Feature Family device package specific probes available.
COP8 Debug Module: Moderate cost in-circuit emulation development programming unit. COP8 Evaluation Programming Unit: EPU-COP888GG cost in-circuit simulation development programming unit. Assembler: COP8-DEV-IBMA. installable cross development Assembler, Linker, Librarian Utility Software Development Tool Kit. Compiler: COP8C. installable cross development Software Tool kit. OPT/EPROM Programmer Support: Covering needs from engineering prototype, pilot production full production environments.
IceMASTER (IM) IN-CIRCUIT EMULATION iceMASTER IM-COP8/400 full feature, based, in-circuit emulation tool developed marketed MetaLink Corporation support whole COP8 family products. National resale vendor these products. Figure configuration. iceMASTER IM-COP8/400 with device specific COP8 Probe provides rich feature developing, testing maintaining product:
Order Information Base Unit IM-COP8/400-1 IM-COP8/400-2 iceMASTER Probe MHW-884CL28DWPC MHW-888CL40DWPC MHW-888CL44PWPC Adapter package MHW-SO -SOIC28 PLCC iceMASTER Base Unit, 110V Power Supply iceMASTER Base Unit, 220V Power Supply
Real-time in-circuit emulation; full 2.4V-5.5V operation range, full DC-10 clock. Chip options programmable jumper selectable. Direct connection application board package compatible socket surface mount assembly. Full kbyte loadable programming space that overlays (replaces) on-chip EPROM. On-chip blocks used directly recreated probe necessary. Full frame synchronous trace memory. Address, instruction, unspecified, circuit connectable trace lines. Display source (e.g., source), assembly mixed.
DS009766-35
FIGURE COP8 iceMASTER Environment
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Development Support
IceMASTER DEBUG MODULE (DM)
(Continued)
Debugger software processed customized, reconfigured from master model file. Processor specific symbolic display registers level assignments, configured from master model file. Halt/Idle mode notification. Programming menu supports full product line programmable EPROM COP8 products. Program data taken directly from overlay RAM. Programming 44PLCC 68PLCC parts requires external programming adapters. Includes wallmount power supply. On-board generator from input connection external supply supported. Requires VPPlevel adjustment family programming specification (correct level provided on-screen pop-down display). ON-Line HELP customized specific processor using master model file. Includes copy COP8-DEV-IBMA assembler linker SDK.
iceMASTER IM-COP8/400 based, combination in-circuit emulation tool COP8 based OPT/EPROM programming tool developed marketed MetaLink Corporation support whole COP8 family products. National resale vendor these products. Figure configuration. iceMASTER Debug Module moderate cost development tool. capability in-circuit emulation specific COP8 microcontroller addition serves programming tool COP8 EPROM product families. Summary features follows:
Real-time in-circuit emulation; full operating voltage range operation, full DC-10 clock. processor pins cabled application development board with package compatible cable socket surface mount assembly. Full kbyte loadable programming space that overlays (replaces) on-chip EPROM. On-chip blocks used directly recreated probe necessary. frames synchronous trace memory. display source source), assembly mixed. most recent history prior break available trace memory. Configured break points; uses INTR instruction which modestly intrusive. Software only supported features selectable. Tool integrated interactive symbolic debugger supports both assembler (COFF) Compiler (.COD) linked object formats. Instruction instruction memory/register changes displayed when single step operation.
Order Information Debug Module Unit COP8-DM/888CF Cable Adapters DM-COP8/28D DM-COP8/40D DM-COP8/44P Adapter package MHW-SO -SOIC28 PLCC
DS009766-36
FIGURE COP8-DM Environment
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Development Support
(Continued)
COP8 ASSEMBLER/LINKER SOFTWARE DEVELOPMENT TOOL National Semiconductor offers relocateable COP8 macro cross assembler, linker, librarian utility software development tool kit. Features summarized follows:
COP8 COMPILER Compiler developed marketed Byte Craft Limited. COP8C compiler fully integrated development tool specifically designed support compact embedded configuration COP8 family products. Features summarized follows: ANSI with some restrictions extensions that optimize development COP8 embedded application. BITS data type extension. Register declaration #pragma with direct level definitions.
Basic Feature Family instruction "device" type Nested macro capability. Extensive assembler directives. Supported PC/DOS platform. Generates National standard COFF output files. Integrated Linker Librarian. Integrated utilities generate code file outputs. DUMPCOFF utility. This product integrated part MetaLink tools development kit, fully supported MetaLink debugger. ordered separately bundled with MetaLink products additional cost.
Order Information Assembler SDK: COP8-DEV-IBMA Assembler installable 3.5" PC/DOS Floppy Disk Drive format. Periodic upgrades most recent version available National's Internet. Approved List Manufacturer Microsystems Data North America (800) 225-2102 (713) 688-4600 Fax: (713) 688-0920 (800) 426-1045 (206) 881-6444 Fax: (206) 882-1043 HI-LO Technology MetaLink (510) 623-8860 (800) 624-8949 (919) 430-7915 (800) 638-2423 (602) 926-0797 Fax: (602) 693-0681 Systems General Needhams (916) 924-8037 Fax: (916) 924-8065 (408) 263-6667
language support interrupt routines. Expert system, rule based code geration optimization. Performs consistency checks against architectural definitions target COP8 device. Generates program memory code. Supports linking compiled object COP8 assembled object formats. Global optimization linked code. Symbolic debug load format fully source level supported MetaLink debugger.
Europe +49-8152-4183 +49-8856-932616 +44-0734-440011
Asia +852-234-16611 +852-2710-8121 Call North America
Call Asia +44-1226-767404 Fax: 0-1226-370-434 +49-80 9156 96-0 Fax: +49-80 9123 +41-1-9450300
+886-2-764-0215 Fax: +886-2-756-6403
+852-737-1800
+886-2-917-3005 Fax: +886-2-911-1283
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Development Support
(Continued)
DIAL-A-HELPER Standard Modem Modem: CANADA/U.S.: EUROPE: Baud: Set-Up: (800) NSC-MICRO (800) 672-6427 (+49) 0-8141-351332 14.4k Length: Parity: Stop Bit: Operation: 8-Bit None
SINGLE CHIP OTP/EMULATOR SUPPORT COP8 family supported single chip emulators. detailed information refer emulator specific datasheet emulator selection table below: Emulator Ordering Information Device Number COP87L84CLN-XE COP87L84CLM-XE COP87L88CLN-XE COP87L88CLV-XE Clock Option Crystal Crystal Crystal Crystal PLCC COP884CL COP884CL COP888CL COP888CL Package Emulates
Hours, Days
DIAL-A-HELPER nscmicro.nsc.com user: password: anonymous username @yourhost.site.domain
INDUSTRY WIDE OTP/EPROM PROGRAMMING SUPPORT Programming support, addition MetaLink development tools, provided full range independent approved vendors meet needs from engineering laboratory full production. AVAILABLE LITERATURE more information, please COP8 Basic Family User's Manual, Literature Number 620895, COP8 Feature Family User's Manual, Literature Number 620897 National's Family 8-bit Microcontrollers COP8 Selection Guide, Literature Number 630009. DIAL-A-HELPER SERVICE Dial-A-Helper service provided Microcontroller Applications group. Dial-A-Helper Electronic Information System that accessed Bulletin Board System (BBS) data modem, site Internet standard client application site Internet using standard Internet browser such Netscape Mosaic. Dial-A-Helper system provides access automated information storage retrieval system. system capabilities include MESSAGE SECTION (electronic mail, when accessed BBS) communications from Microcontroller Applications Group FILE SECTION which consists several file areas where valuable application software utilities could found.
DIAL-A-HELPER WorldWide Browser ftp://nscmicro.nsc.com National Semiconductor WorldWide WorldWide http://www.national.com CUSTOMER RESPONSE CENTER Complete product information technical support available from National's customer response centers. CANADA/U.S.: email: EUROPE email: Deutsch English Francais Italiano JAPAN: S.E. ASIA: Beijing Hong Kong Korea Malaysia Taiwan AUSTRALIA: INDIA: Tel: Tel: Tel: Tel: Tel: Tel: Tel: Tel: Tel: Tel: Tel: Tel: Shanghai Tel: Tel: (800) 272-9959 support @tevm2.nsc.com europe.support@nsc.com 180-530 180-532 180-532 180-534 +81-043-299-2309 (+86)10-6856-8601 (+86)21-6415-4092 (+852) 2737-1600 (+82) 2-3771-6909 (+60-4) 644-9061 (+65) 255-2226 +886-2-521-3288 (+61) 3-9558-9999 (+91) 80-559-9467
Singapore Tel:
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Physical Dimensions
inches (millimeters) unless otherwise noted
28-Lead Small Outline Package Order Number COP684CL-XXX/WM, COP884CL-XXX/WM, COP984CL-XXX/WM COP984CLH-XXX/WM Package Number M28B
Molded Dual-In-Line Package Order Number COP684CL-XXX/N, COP884CL-XXX/N, COP984CL-XXX/N COP984CLH-XXX/N Package Number N28B
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package Order Number COP688CL-XXX/N, COP888CL-XXX/N, COP988CL-XXX/N COP988CLH-XXX/N Package Number N40A
Plastic Leaded Chip Carrier Order Number COP688CL-XXX/V, COP888CL-XXX/V, COP988CL-XXX/V, COP988CLH-XXX/V Package Number V44A
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COP688CL/COP684CL, COP888CL/COP884CL, COP988CL/COP984CL 8-Bit Microcontroller
Notes
LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT GENERAL COUNSEL NATIONAL SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com www.national.com National Semiconductor Europe Fax: 180-530 Email: europe.support@nsc.com Deutsch Tel: 9508 6208 English Tel: 2171 Tel: 8790
critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap.support@nsc.com
National Semiconductor Japan Ltd. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507
National does assume responsibility circuitry described, circuit patent licenses implied National reserves right time without notice change said circuitry specifications.

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