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Implications of Slow or Floating CMOS Inputs
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Implications Slow Floating CMOS Inputs
Copyright 1994, Texas Instruments Incorporated
Title Page Introduction 13-25 Characteristics Slow Floating CMOS Inputs 13-25 Slow Input Edge Rate 13-26 Floating Inputs 13-27 Recommendations Designing More Reliable Systems Control Pullup Pulldown Resistors Bus-Hold Circuits 13-28 13-28 13-29 13-30
Figure Title Page Input Structures LVT/LVC Devices 13-25 Supply Current Versus Input Voltage (One Input) 13-26
Input ransition Rise Fall Rate Specified Data Sheets Input/Output Model
Supply Current Change Input Level Specified Data Sheets Supply Current ersus Input oltage Inputs) ypical Bidirectional
13-28 13-29 13-31 13-32
Inactive Model With Defined Level ypical Hold Cell
Stand Alone Hold Cell (SN74ACT107x) Diode Characteristics (SN74ACT107x)
Input Structure ABT/L VC/L Families With Hold Hold Input Characteristics Driver Receiver System
Output aveforms Driver With Without Receiver's Hold Hold Supply Current
13-35 13-36 13-37
Input Power With Without Hold Different Frequencies Data Sheet Minimum Specification Hold
Widebus Widebus+ trademarks Texas Instruments Incorporated. 13-3
recent years, CMOS (AC, ACT, LVC) BiCMOS (ABT, LVT) logic families have further strengthened their position semiconductor market. designs have adopted both technologies almost every system that exists, whether workstation, digital switch. reason very obvious: power consumption becoming major issue today's market. However, when designing systems using CMOS BiCMOS devices, must understand characteristics these families inputs outputs behave systems. very important designer follow rules restrictions that manufacturer requires well designing within data sheet specifications. Because data sheets cover input behavior device detail, this application note explains input characteristics CMOS BiCMOS families general. also explains ways deal with problem issues when designing with such families where floating inputs concern. Understanding behavior these inputs results more robust designs better reliability.
Drops Supply Voltage
Input Inverter Internal Stage Input Inverter
Figure Input Structures LVT/LVC Devices
Characteristics Slow Floating CMOS Inputs
Both advanced CMOS BiCMOS (ABT/LVT) families have CMOS input structure. This structure inverter consisting channel channel shown Figure With low-level input, p-channel transistor channel off, causing current flow from pulling node high state. With high-level input, n-channel transistor channel current flows GND, pulling node low. both cases, current flows from GND. However, when switching from state another, input crosses threshold region causing channel channel turned simultaneously, generating current path between GND. This current surge damaging, depending length time that input threshold region (0.8 supply current (ICC) rise several milliamperes input, peaking approximately (see Figure This problem when switching states data-sheet-specified input transition time (see Figure
Supply Current Input Voltage 25°C Driven From
Figure Supply Current Versus Input Voltage (One Input)
recommended operating conditions
octals Input transition rise rate fall Widebus Widebus+LVT, LVC, ALVC UNIT
Figure Input Transition Rise Fall Rate Specified Data Sheets
Slow Input Edge Rate
With increased speed, logic devices have become more sensitive slow input edge rates. slow input edge rate, coupled with noise generated power rails when output switches, cause excessive output errors oscillations. Similar situations occur unused input left floating actively held valid logic level. These functional problems voltage transients induced device's power system output load current (IO) flows through parasitic lead inductances during switching (see Figure Because device's internal power supply nodes used voltage references throughout integrated circuit, inductive voltage spikes, VGND, affect signals appear internal gate structures. example, voltage device's ground node rises, input signal, appears decrease magnitude. This undesirable phenomena then erroneously change output threshold violation occurs. case slowly rising input edge, change voltage large enough, apparent signal, device will appear driven back through threshold output will start switch opposite direction. worst-case conditions prevail (simultaneously switching outputs with large transient load currents), slow input edge will repeatedly driven back through threshold, causing output oscillation. Therefore, maximum input transition time device should violated damage circuit package occur (refer Figure maximum transition rate each family).
Figure Input /Output Model
voltage between applied input prolonged period time, this situation becomes critical should ignored, especially with higher count more dense packages (SSOP, TSSOP). example, 18-bit transceiver pins floating threshold, current from could high This approximately power consumed device, which leads serious overheating problem. This continuous overheating device affects reliability. Also, because inputs threshold region, outputs tend oscillate, resulting damage internal circuit over long period time. data sheet shows increase supply current (ICC) when input level [for (see Figure 5)]. This becomes more critical when input threshold region seen Figure These characteristics typical CMOS input circuits, including microprocessors memories.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER LVC, ALVC, TEST CONDITIONS Other inputs Other inputs input input UNIT
This increase supply current each input that specified voltage level rather than GND.
Figure Supply Current Change Input Level Specified Data Sheets
Supply Current 25°C Bits Driven From
Figure Supply Current Versus Input Voltage Inputs) long driver active transmission path bus, receiver's input always valid state. input specification violated long rise fall times within data sheet limits. However, when driver high-impedance state, receiver input longer defined level tends float. This situation worsen when several transceivers share same bus. Figure example typical system. When transceivers inactive, line levels undefined. When voltage that determined leakage currents each component reached, condition known floating state. result considerable increase power consumption risk damaging components bus. Holding inputs pins valid logic level when they being used when part driving them high-impedance state recommended.
Figure Typical Bidirectional
Recommendations Designing More Reliable Systems
Control simplest avoid floating inputs system ensure that either always active inactive limited time when voltage buildup does exceed maximum specification (0.8 TTL-compatible input). this voltage, corresponding value device operates without problem concern (see Figures
avoid damaging components, designer must know maximum time float. First, assuming that maximum leakage current total capacitance (I/O line capacitance) change voltage with respect time inactive line that exceeds 0.8-V level calculated equation
permissible floating time this example should reduced maximum, which ensures that will exceed 0.8-V level specified above. time constant does change when multiple components involved because their leakage currents capacitances summed. advantage this method that requires additional cost adding special components. Unfortunately, this method does always apply because buses always active. Pullup Pulldown Resistors When buses disabled more than maximum allowable time, other ways should used prevent components from being damaged overheated. pullup pulldown resistor GND, respectively, should used keep defined state. size resistor plays important role resistance chosen properly, problem occur. Usually, 10-k resistor recommended. maximum input transition time must violated when selecting pullup pulldown resistors (see Figure Otherwise, components destroyed.
Figure Inactive Model With Defined Level Assume that active-low goes high-impedance state modeled Figure represents device plus line capacitance pullup resistor VCC. value required resistor calculated equation Where: maximum allowable floating voltage total capacitance pullup resistor maximum input rise time specified Figure data sheet
Solving equation becomes:
multiple transceivers bus: Where: number components connected Assuming that there components connected bus, each with capacitance requiring maximum rise time ns/V, 50-ns total rise time input, maximum resistor size calculated:
This pullup resistor method recommended ac-powered systems; however, recommended battery-operated equipment because power consumption very critical. Instead, bus-hold feature that discussed next section. overall advantage using pullup resistors that they ensure defined levels when floating helps eliminate some line reflections because resistors terminations well. Bus-Hold Circuits most effective method provide defined levels floating Texas Instruments built-in bus-hold feature selected families external component like SN74ACT1071 SN74ACT1073 (refer Table Table Devices With Hold
DEVICE TYPE SN74ACT1071 SN74ACT1073 Widebus+(32 Bit) Octals WidebusLow Voltage (LVT ALVC) WidebusBUS HOLD INCORPORATED 10-bit hold with clamping diodes 16-bit hold with clamping diodes devices Selected devices only devices devices
hold circuit used Texas Instruments selected families help solve floating input problem eliminate need pullup pulldown resistors. consists back-to-back inverters with output back input through resistor (see Figure order understand bus-hold cell operates, assume that active driver switched line high level. This results current flowing through feedback circuit. Now, driver goes high-impedance state bus-hold circuit holds high level through feedback resistor. current requirement hold determined only leakage current circuit. same condition applies when state then goes inactive.
Figure Typical Bus-Hold Cell
mentioned earlier this section, Texas Instruments offers hold stand-alone 10-bit 16-bit devices (SN74ACT1071 SN74ACT1073) with clamping diodes added protection against line reflections caused impedance mismatch bus. Because purely ohmic resistors cannot implemented easily CMOS circuits, configuration known transmission gate used feedback element (see Figure 10). channel channel arranged parallel between input output buffer stage. gate n-channel transistor connected gate channel connected GND. When output buffer high, channel when output low, channel Both channels relatively small surface area resistance from drain source, Rdson, about
Figure Stand-Alone Bus-Hold Cell (SN74ACT107x) Now, assume that practical application leakage current driver voltage drop across (this value assumed ensure defined logic level). Then, maximum number components that hold handle calculated follows:
74ACT1071 74ACT1073 also provide clamping diodes added feature hold. These diodes useful clamping overshoot undershoot generated line reflections. Figure shows characteristics diodes when input voltage above below GND. -1V, diode source about which help eliminate undershoots. This very useful when noisy buses concern.
UPPER CLAMPING DIODE
Forward Current Forward Current -1.75 -1.5 -1.25 0.75 0.25
LOWER CLAMPING DIODE
Figure Diode Characteristics (SN74ACT107x)
Texas Instruments also offers bus-hold circuit feature added some advanced-family drivers receivers. This circuit similar stand-alone circuit with diode added drain second inverter (ABT only, Figure 12). diode blocks overshoot current when input voltage higher than VCC), only leakage current present. This circuit uses device's input stage first inverter; second inverter creates feedback feature. calculation maximum number components that hold handle similar previous example. However, advantage this circuit over stand-alone hold that eliminates need external components resistors that occupy more area board. This becomes very critical some designs, especially when wide buses used. Also, because cost board-dimension restrictions major concern, designers prefer easy fix: drop-in replaceable parts. Texas Instruments offers this feature most commonly used functions several families (refer Table more details).
ABT/LVT FAMILY Hold Input Input ALVC/LVC FAMILY Hold
Figure Input Structure ABT/LVT ALVC/LVC Families With Hold
Figure shows input characteristics hold 3.3-V operations, input voltage swept from These characteristics similar behavior weak driver. This driver sinks current into part when input sources current part when input high. When voltage near threshold, circuit tries switch other state, always keeping input valid level. This result internal feedback circuit. plot also shows that current maximum when input near threshold. II(hold) maximum approximately 3.3-V input input.
I(hold) Hold Current Output Voltage
I(hold) Hold Current
Figure Bus-Hold Input Characteristics
When multiple devices with hold driven single driver, concerned about switching capability driver becoming weaker. small drivers, bus-hold cells require current switch them. This current significant when using Texas Instruments CMOS BiCMOS families. Figure shows 4-mA buffer driving LVT16244 devices. trace transmission line. receivers separated with driver located center trace. Figure shows bus-hold loading effect driver when connected receivers switching high. also shows same system with hold disconnected from receivers. Both plots show effect hold driver's rise fall times. Initially, hold tries counteract driver, causing rise fall time increase. Then, hold changes states (note crossover point), which helps driver switch faster, decreasing rise fall time.
Figure Driver Receiver System
DRIVER SWITCHING FROM HIGH
Receivers: With Hold Without Hold Output Voltage Output Voltage 25°C
DRIVER SWITCHING FROM HIGH
Receivers: With Hold Without Hold
Figure Output Waveforms Driver With Without Receiver's Hold
Figure shows supply current (ICC) bus-hold circuit input swept from Again, spike seen about 1.5-V both channel channel conducting simultaneously. This CMOS transistor characteristics.
Figure Bus-Hold Supply Current Versus Input Voltage
power consumption hold minimal when switching input higher frequencies. Figure shows power consumed input different frequencies with without hold. seen, increase power consumption hold higher frequencies significant enough considered power calculations.
POWER PLOT INPUT WITH HOLD
POWER PLOT INPUT WITHOUT HOLD
Figure Input Power With Without Hold Different Frequencies
Figure shows data sheet specifications hold. first test condition minimum current required hold These voltages meet specified high levels inputs. second test condition maximum current that hold sources sinks input voltage between (for low-voltage families) between (for ABT). bus-hold current becomes minimal input voltage approaches rail voltage. output leakage currents, IOZH IOZL, insignificant transceivers with hold because true leakage test cannot performed existence bus-hold circuit. Because hold behaves small driver, tends source sink current that opposite direction leakage current. This situation true transceivers with hold only does apply buffers. LVT, Widebus+TM, selected octal Widebusdevices have bus-hold feature (refer Table contact local Texas Instruments sales office more information).
electrical characteristics over recommended operating free-air temperature range (for families with bus-hold feature)
PARAMETER LVT, LVC, ALVC II(hold) Data inputs I/Os Widebus+ Widebus+and selected WidebusWid LVT, LVC, ALVC LVT, LVC, ALVC TEST CONDITIONS UNIT
Transceivers with hold IOZH/IOZL Buffers with hold
This test true test since hold always active pin. tends supply current that opposite direction output leakage current. This test true test since hold does exist output pin.
Figure Data Sheet Minimum Specification Hold
Floating inputs slow rise fall times important issues consider when designing with CMOS advanced BiCMOS families. important understand complications associated with floating inputs. Terminating properly plays major role achieving reliable systems. three methods that were recommended this application note should considered. possible control directly adding pullup pulldown resistors impractical power-consumption board-space limitations, hold best choice. Texas Instruments designed hold reduce need resistors used designs, reducing number components board improving overall reliability system.
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