CII51001-1
|
|
|
Top Searches for this datasheet
EP2C50 - EP2C50
EP2C20 - EP2C20
18-bit DDR2 SDRAM - 18-bit DDR2 SDRAM
CII51001-1 - CII51001-1
Chapter
CII51001-1.0
Altera's low-cost CycloneII FPGA family based 1.2-V, 90-nm SRAM process with densities over logic elements (LEs) Mbits embedded RAM. With features like embedded multipliers support high-performance applications, phase-locked loops (PLLs) system clock management, high-speed external memory interface support SRAM DRAM devices, Cyclone devices cost-effective solution high-volume applications. Cyclone devices support differential single-ended standards, including LVDS data rates megabits second (Mbps) receiver Mbps transmitter, 64-bit, 66-MHz PCI-X interfacing with processors ASSP ASIC devices. Altera also offers low-cost serial configuration devices configure Cyclone devices. Cyclone device family offers following features:
Features
High-density architecture with 4,480 68,288 embedded memory blocks Mbits available without reducing available logic 4,096 memory bits block (4,608 bits block including parity bits) Variable port configurations True dual-port (one read write, reads, writes) operation modes Byte enables data input masking during writes 250-MHz operation Embedded multipliers 18-bit multipliers each configurable independent 9-bit multipliers with 250-MHz performance Optional input output registers Advanced support High-speed differential standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, differential SSTL Single-ended standard support, including 2.5-V 1.8-V SSTL class 1.8-V 1.5-V HSTL class 3.3-V
Altera Corporation June 2004
Preliminary
Features
PCI-X 1.0, 3.3-, 2.5-, 1.8-, 1.5-V LVCMOS, 3.3-, 2.5-, 1.8-V LVTTL Peripheral component interconnect Special Interest Group (PCI SIG) Local Specification, Revision compliance 3.3-V operation 64-bit interfaces 100-MHz PCI-X specification compatibility High-speed external memory support, including DDR, DDR2, SDRAM, QDRII SRAM Three dedicated registers element (IOE): input register, output register, output-enable register Programmable bus-hold feature Programmable output drive strength feature Programmable delays from logic array bank grouping unique VCCIO and/or VREF bank settings MultiVoltI/O standard support 1.5-, 1.8-, 2.5-, 3.3-V interfaces Hot-socketing operation support Tri-state with weak pull-up pins before during configuration Programmable open-drain outputs Flexible clock management circuitry Hierarchical clock network 402.5-MHz performance four PLLs device provide clock multiplication division, phase shifting, programmable duty cycle, external clock outputs, allowing system-level clock management skew control global clock lines global clock network that drive throughout entire device Device configuration Fast serial configuration allows configuration times less than Decompression feature allows smaller programming file storage faster configuration times Supports multiple configuration modes: active serial, passive serial, JTAG-based configuration Supports configuration through low-cost serial configuration devices Device configuration supports multiple voltages (either 3.3, 2.5, Intellectual property Altera megafunction support Altera MegaCore® function support Altera Megafunctions Partners Program (AMPPSM) megafunctions support
Cyclone Device Handbook, Volume
Preliminary
Altera Corporation June 2004
Table lists Cyclone device family features. Table lists Cyclone device package offerings maximum user pins.
Table 1-1. Cyclone FPGA Family Features Feature
blocks Kbits plus parity bits Total bits Embedded multipliers PLLs Maximum user pins Note Table 1-1:
This total number multipliers. total number multipliers device, multiply total number multipliers
EP2C5
4,608 119,808
EP2C8
8,256 165,888
EP2C20
18,752 239,616
EP2C35
33,216 483,840
EP2C50
50,528 594,432
EP2C70
68,416 1,152,000
Table 1-2. Cyclone Package Options Maximum User Pins Device
EP2C5 EP2C8 EP2C20 EP2C35 EP2C50 EP2C70 Notes Table 1-2:
Note
144-Pin TQFP 208-Pin PQFP 256-Pin 484-Pin 672-Pin 896-Pin FineLine FineLine FineLine FineLine
Cyclone devices support vertical migration within same package (i.e., designers migrate between EP2C20 device 484-pin FineLine BGA® package EP2C35 EP2C50 devices same package). TQFP: thin quad flat pack. PQFP: plastic quad flat pack. Contact your local Altera sales representative more information this device.
Altera Corporation June 2004
Preliminary
Cyclone Device Handbook, Volume
Features
Cyclone Device Handbook, Volume
Preliminary
Altera Corporation June 2004
Other recent searches
LM3S9997 - LM3S9997 LM3S9997 Datasheet
LL15XB60 - LL15XB60 LL15XB60 Datasheet
ES2A - ES2A ES2A Datasheet
ES2D - ES2D ES2D Datasheet
CMT04N60 - CMT04N60 CMT04N60 Datasheet
AL5DS9xx9V - AL5DS9xx9V AL5DS9xx9V Datasheet
AL5DS9349V - AL5DS9349V AL5DS9349V Datasheet
AL5DS9269V - AL5DS9269V AL5DS9269V Datasheet
AL5DS9159V - AL5DS9159V AL5DS9159V Datasheet
AL5DS9069V - AL5DS9069V AL5DS9069V Datasheet
74LCX245 - 74LCX245 74LCX245 Datasheet
Privacy Policy | Disclaimer
© 2013 Datasheets.org.uk