CC2550
|
|
|
Top Searches for this datasheet
frequency hopping spread spectrum - frequency hopping spread spectrum
DN004 - DN004
cc2500 microcontroller interfacing - cc2500 microcontroller interfacing
CC2500* - CC2500*
CC2550 - CC2550
CC2550
CC2550
Low-Cost Low-Power Transmitter
2400-2483.5 ISM/SRD band systems Consumer electronics Wireless game controllers Wireless audio enabled remote controls
Product Description
CC2550 low-cost transmitter designed very low-power wireless applications. circuit intended 24002483.5 (Industrial, Scientific Medical) (Short Range Device) frequency band. transmitter integrated with highly configurable baseband modulator. modulator supports various modulation formats configurable data rate kBaud. CC2550 provides extensive hardware support packet handling, data buffering burst transmissions. main operating parameters 64byte transmit FIFO CC2550 controlled interface. typical system, CC2550 will used together with microcontroller passive components.
Features Performance
Programmable output power Programmable data rate from kBaud Frequency range: 2400 2483.5
Low-Power Features
SLEEP mode current consumption Fast startup time: from SLEEP mode (measured design [3]) 64-byte data FIFO (enables burst mode data transmission)
Analog Features
OOK, 2-FSK, GFSK, supported Suitable frequency hopping multichannel systems fast settling frequency synthesizer with settling time Integrated analog temperature sensor
General
external components: Complete onchip frequency synthesizer, external filters needed Green package: RoHS compliant antimony bromine Small size (QLP package, pins) Suited systems compliant with class (Europe), CFR47 Part (US), ARIB STDT66 (Japan) Support asynchronous synchronous serial transmit mode backwards compatibility with existing radio communication protocols
Digital Features
Flexible support packet oriented systems: On-chip support sync word insertion, flexible packet length, automatic handling Efficient interface: registers programmed with "burst" transfer Optional automatic whitening data
SWRS039B
Page
CC2550
Table Contents
APPLICATIONS PRODUCT DESCRIPTION.1 FEATURES PERFORMANCE ANALOG FEATURES DIGITAL FEATURES.1 LOW-POWER FEATURES.1 GENERAL TABLE CONTENTS ABBREVIATIONS.4 ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS GENERAL CHARACTERISTICS.5 ELECTRICAL SPECIFICATIONS CURRENT CONSUMPTION TRANSMIT SECTION CRYSTAL OSCILLATOR FREQUENCY SYNTHESIZER CHARACTERISTICS ANALOG TEMPERATURE SENSOR CHARACTERISTICS POWER-ON RESET CONFIGURATION.9 CIRCUIT DESCRIPTION APPLICATION CIRCUIT CONFIGURATION OVERVIEW CONFIGURATION SOFTWARE.14 4-WIRE SERIAL CONFIGURATION DATA INTERFACE 10.1 CHIP STATUS BYTE 10.2 REGISTERS ACCESS 10.3 READ 10.4 COMMAND STROBES 10.5 FIFO ACCESS 10.6 PATABLE ACCESS 11.1 11.2 13.1 13.2 13.3 13.4 14.1 14.2 14.3 15.1 15.2 MICROCONTROLLER INTERFACE CONFIGURATION CONFIGURATION INTERFACE GENERAL CONTROL STATUS PINS DATA RATE PROGRAMMING.19 PACKET HANDLING HARDWARE SUPPORT DATA WHITENING PACKET FORMAT PACKET HANDLING TRANSMIT MODE PACKET HANDLING FIRMWARE MODULATION FORMATS FREQUENCY SHIFT KEYING MINIMUM SHIFT KEYING.23 AMPLITUDE MODULATION FORWARD ERROR CORRECTION WITH INTERLEAVING FORWARD ERROR CORRECTION (FEC).23 INTERLEAVING RADIO CONTROL.25
SWRS039B Page
CC2550
16.1 16.2 16.3 16.4 16.5 19.1 22.1 26.1 26.2 27.1 27.2 27.3 27.4 27.5 27.6 27.7 27.8 27.9 28.1 28.2 29.1 29.2 29.3 29.4 29.5 32.1 32.2 POWER-ON START-UP SEQUENCE CRYSTAL CONTROL VOLTAGE REGULATOR CONTROL.26 MODE TIMING FIFO FREQUENCY PROGRAMMING.28 SELF-CALIBRATION VOLTAGE REGULATORS OUTPUT POWER PROGRAMMING CRYSTAL OSCILLATOR.32 REFERENCE SIGNAL EXTERNAL MATCH LAYOUT RECOMMENDATIONS.33 GENERAL PURPOSE TEST OUTPUT CONTROL PINS ASYNCHRONOUS SYNCHRONOUS SERIAL OPERATION ASYNCHRONOUS OPERATION SYNCHRONOUS SERIAL OPERATION SYSTEM CONSIDERATIONS GUIDELINES REGULATIONS FREQUENCY HOPPING MULTI-CHANNEL SYSTEMS WIDEBAND MODULATION USING SPREAD SPECTRUM DATA BURST TRANSMISSIONS.36 CONTINUOUS TRANSMISSIONS SPECTRUM EFFICIENT MODULATION COST SYSTEMS BATTERY OPERATED SYSTEMS INCREASING OUTPUT POWER CONFIGURATION REGISTERS.37 CONFIGURATION REGISTER DETAILS STATUS REGISTER DETAILS.49 PACKAGE DESCRIPTION (QLP 16).52 RECOMMENDED LAYOUT PACKAGE (QLP PACKAGE THERMAL PROPERTIES SOLDERING INFORMATION TRAY SPECIFICATION CARRIER TAPE REEL SPECIFICATION ORDERING INFORMATION.54 REFERENCES GENERAL INFORMATION.55 DOCUMENT HISTORY PRODUCT STATUS DEFINITIONS ADDRESS INFORMATION WORLDWIDE TECHNICAL SUPPORT.57
SWRS039B
Page
CC2550
Abbreviations
Abbreviations used this data sheet described below.
ARIB FHSS FIFO 2-FSK GFSK Adjacent Channel Power Analog Digital Converter Automatic Gain Control Automatic Meter Reading Association Radio Industries Businesses Amplitude Shift Keying Error Rate Bandwidth-Time product Code Federal Regulations Cyclic Redundancy Check Direct Current Equivalent Series Resistance Federal Communications Commission Forward Error Correction Frequency Hopping Spread Spectrum First-In-First-Out Frequency Shift Keying Gaussian shaped Frequency Shift Keying In-Phase/Quadrature Industrial, Scientific Medical Inductor-Capacitor Local Oscillator Microcontroller Unit Most Significant Minimum Shift Keying QPSK WLAN XOSC XTAL Applicable Return Zero (coding) Local Oscillator Occupied Bandwidth Keying Power Amplifier Printed Circuit Board Power Down Packet Error Rate Phase Locked Loop Power-on Reset Quadrature Phase Shift Keying Quad Leadless Package Radio Frequency Receive, Receive Mode Surface Mount Device Signal Noise Ratio Serial Peripheral Interface Short Range Device Transmit, Transmit Mode Voltage Controlled Oscillator Wireless Local Area Networks Crystal Oscillator Crystal
Absolute Maximum Ratings
Under circumstances must absolute maximum ratings given Table violated. Stress exceeding more limiting values cause permanent damage device.
Caution! sensitive device. Precaution should used when handling device order prevent permanent damage. Parameter Supply voltage Voltage digital Voltage pins RF_P, RF_N DCOUPL Storage temperature range Solder reflow temperature -0.3 -0.3 -0.3 VDD+0.3, <500 Units According IPC/JEDEC J-STD-020D According JEDEC method A114, Human Body Model Condition/Note supply pins must have same voltage
Table Absolute Maximum Ratings
SWRS039B
Page
CC2550
Operating Conditions
Unit supply pins must have same voltage Condition/Note
CC2550 operating conditions listed Table below.
Parameter Operating temperature Operating supply voltage
Table Operating Conditions
General Characteristics
2400 2483.5 Unit kBaud kBaud kBaud 2-FSK GFSK (Shaped) (also known differential offset QPSK) Optional Manchester encoding (the data rate kbps will half baud rate). Condition/Note
Parameter Frequency range Data rate
Table General Characteristics
Electrical Specifications
Current Consumption
25°C, nothing else stated. measurement results obtained using CC2550EM reference design ([3]). Parameter Current consumption power down modes Current consumption Unit Condition/Note Voltage regulator digital part (SLEEP state). pins programmed 0x2F Voltage regulator digital part other modules power down (XOFF state) Only voltage regulator digital part crystal oscillator running (IDLE state) Only frequency synthesizer running (FSTXON state). This current consumption also representative other intermediate states when going from IDLE including calibration state. Transmit mode, output power Transmit mode, output power Transmit mode, output power Transmit mode, output power
Current consumption, states
11.2 14.7 19.4 21.3
Table Current Consumption
SWRS039B
Page
CC2550
Transmit Section
25°C, nothing else stated. measurement results obtained using CC2550EM reference design ([3]). Parameter Differential load impedance Output power, highest setting Unit Condition/Note Differential impedance seen from RF-port (RF_P RF_N) towards antenna. Follow CC2550EM reference design ([3]) available from website. Output power programmable full range available across entire frequency band. Delivered single-ended load CC2550EM reference design ([3]) matching network. Output power, lowest setting Output power programmable full range available across entire frequency band. Delivered single-ended load CC2550EM reference design ([3]) matching network. possible program less than output power, this recommended large variation output power across operating conditions processing corners these settings. Adjacent channel power (ACP) @2440 Spurious emissions 47-74, 87.5-118, 174230, 470-862 1800-1900 Otherwise above latency Serial operation. Time from sampling data transmitter data input until observed output ports. Restricted band Europe Restricted bands kBaud, 38.2 deviation, 2-FSK, channel spacing kBaud, 38.2 deviation, 2-FSK, channel spacing kBaud, MSK, channel spacing kBaud, MSK, channel spacing
Table Transmit Parameters
SWRS039B
Page
CC2550
Crystal Oscillator
25°C, nothing else stated. measurement results obtained using CC2550EM reference design ([3]). Parameter Crystal frequency Tolerance Unit This total tolerance including initial tolerance, crystal loading, aging temperature dependence. acceptable crystal tolerance depends frequency channel spacing bandwidth. Start-up time Measured CC2500EM reference design ([3]) using crystal AT-41CD2 from NDK. This parameter large degree crystal dependent. Condition/Note
Table Crystal Oscillator Parameters Frequency Synthesizer Characteristics
25°C, nothing else stated. measurement results obtained using CC2550EM reference design ([3]). figures given using crystal. figures given using crystal. Parameter Programmed frequency resolution Synthesizer frequency tolerance carrier phase noise @2440 FXOSC/ Unit Condition/Note 26-27 crystal. Given crystal used. Required accuracy (including temperature aging) depends frequency band channel bandwidth spacing. offset from carrier offset from carrier offset from carrier offset from carrier offset from carrier offset from carrier offset from carrier Time from leaving IDLE state until arriving FSTXON state, when performing calibration. Crystal oscillator running. Calibration initiated manually automatically before entering after leaving RX/TX.
-106 -114 -117
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 88.4
turn-on time
85.1
88.4
calibration time
Table Frequency Synthesizer Parameters
SWRS039B
Page
CC2550
Analog Temperature Sensor characteristics analog temperature sensor supply voltage listed Table below. Note that necessary write 0xBF PTEST register analog temperature sensor IDLE state.
Parameter Output voltage -40°C Output voltage Output voltage +40°C Output voltage +80°C Temperature coefficient Error calculated temperature, calibrated
0.660 0.755 0.859 0.958 2.54
Unit mV/°C
Condition/Note
Fitted from -20°C +80°C From -20°C +80°C when using 2.54 after 1-point calibration room temperature
indicated minimum maximum error with 1point calibration based simulated values typical process parameters
Current consumption increase when enabled
Table Analog Temperature Sensor Parameters Characteristics
25°C nothing else stated. Digital Inputs/Outputs Logic input voltage Logic input voltage Logic output voltage Logic output voltage Logic input current Logic input current VDD-0.7 VDD-0.3 Unit output current output current Input equals Input equals Condition/Note
Table Characteristics Power-On Reset
When power supply complies with requirements Table below, proper Power-OnReset functionality guaranteed. Otherwise, chip should assumed have unknown state until transmitting SRES strobe over interface. Section 16.1 page further details.
Parameter Power-up ramp-up time Power time Unit Condition/Note From until reaching Minimum time between power power-on.
Table Power-on Reset Requirements
SWRS039B
Page
CC2550
Configuration
DGUARD RBIAS AVDD AVDD RF_N RF_P XOSC_Q1 AVDD XOSC_Q2 GDO0 (ATEST) Exposed attach
SCLK (GDO1) DVDD DCOUPL
Figure Pinout View Note: exposed attach must connected solid ground plane this main ground connection chip.
Name SCLK (GDO1)
Type Digital Input Digital Output
Description Serial configuration interface, clock input Serial configuration interface, data output. Optional general output when high
DVDD DCOUPL
Power (Digital) Power (Digital)
digital power supply digital I/O's digital core voltage regulator digital power supply output decoupling. NOTE: This intended with CC2550 only. used provide supply voltage other devices.
XOSC_Q1 AVDD XOSC_Q2 GDO0 (ATEST)
Analog Power (Analog) Analog Digital
Crystal oscillator external clock input analog power supply connection Crystal oscillator Digital output general use: Test signals FIFO status signals Clock output, down-divided from XOSC Serial input data
Also used analog test prototype/production testing RF_P RF_N AVDD AVDD RBIAS DGUARD Digital Input Output Output Power (Analog) Power (Analog) Analog Power (Digital) Digital Input Serial configuration interface, chip select Positive output signal from Negative output signal from analog power supply connection analog power supply connection External bias resistor reference current Power supply connection digital noise isolation Serial configuration interface, data input
Table Pinout Overview
SWRS039B Page
CC2550
Circuit Description
RADIO CONTROL INTERLEAVER
MODULATOR
RF_N
FIFO
RF_P
FREQ SYNTH
DIGITAL INTERFACE
SCLK (GDO1) GDO0 (ATEST)
BIAS
XOSC
RBIAS XOSC_Q1 XOSC_Q2
Figure CC2550 Simplified Block Diagram simplified block diagram CC2550 shown Figure CC2550 transmitter based direct synthesis frequency. frequency synthesizer completely on-chip VCO. includes XOSC_Q2. crystal oscillator generates reference frequency synthesizer, well clocks digital part. 4-wire serial interface used configuration data buffer access. digital baseband includes support channel configuration, packet handling data buffering.
crystal connected XOSC_Q1
Application Circuit
balun filter component values their placement important keep performance optimized. highly recommended follow CC2550EM reference design ([3]). Crystal crystal oscillator uses external crystal with loading capacitors (C51 C71). Section page details. Power supply decoupling power supply must properly decoupled close supply pins. Note that decoupling capacitors shown application circuit. placement size decoupling capacitors very important achieve optimum performance. CC2550EM reference design ([3]) should followed closely.
Only external components required using CC2550. recommended application circuit shown Figure external components described Table typical values given Table Bias resistor bias resistor R141 used accurate bias current. Balun matching components between RF_N/RF_P pins point where signals joined together (C102, C112, L101, L111) form balun that converts differential signal CC2550 single-ended signal. C101 C111 needed blocking. Together with appropriate network, balun components also transform impedance match antenna cable). Suggested values listed Table
SWRS039B
PACKET HANDLER
Page
CC2550
Component
C51/C71 C101/C111 C102/C112 C103/C104 L101/L111 L102 R141 XTAL
Description
Decoupling capacitor on-chip voltage regulator digital part Crystal loading capacitors, Section page details balun blocking capacitors balun/matching capacitors filter/matching capacitors balun/matching inductors (inexpensive multi-layer type) filter inductor (inexpensive multi-layer type) Resistor internal bias current reference 26-27 crystal, Section page details
Table Overview External Components (excluding supply decoupling capacitors)
1.8V-3.6V power supply
DGUARD RBIAS
R141
AVDD
Antenna Ohm) L111 C111 C101 L101 C102 C112 L102 C103
Digital Inteface
SCLK (GDO1)
SCLK (GDO1)
AVDD RF_N
DVDD ATTACH PAD:RF_P XOSC_Q2 5XOSC_Q1 4DCOUPL GDO0 AVDD
CC2550
C104
GDO0 (optional)
Alternative: Folded dipole antenna external components needed)
XTAL
Figure Typical Application Evaluation Circuit (excluding supply decoupling capacitors)
SWRS039B
Page
CC2550
Component
C101 C102 C103 C104 C111 C112 L101 L102 L111 R141 XTAL
Value
nF±10%, 0402 pF±5%, 0402 pF±5%, 0402 pF±5%, 0402 pF±0.25pF, 0402 pF±0.25pF, 0402 pF±0.25pF, 0402 pF±5%, 0402 pF±0.25pF, 0402 nH±0.3nH, 0402 monolithic nH±0.3nH, 0402 monolithic nH±0.3nH, 0402 monolithic k±1%, 0402 26.0 surface mount crystal
Manufacturer
Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata LQG15 series Murata LQG15 series Murata LQG15 series RK73 series NDK, AT-41CD2
Table Bill Materials Application Circuit Measurements have been performed with multi-layer inductors from other manufacturers (e.g. measurement results were same when using Murata part. Gerber files CC2550EM reference design ([3]) available from website.
SWRS039B
Page
CC2550
Configuration Overview
Forward Error interleaving Data Whitening Correction (FEC) with
CC2550 configured achieve optimum performance many different applications. Configuration done using interface. following parameters programmed:
Power-down power mode Crystal oscillator power-up power down Transmit mode channel selection Data rate Modulation format output power Data buffering with 64-byte transmit FIFO Packet radio hardware support
Details each configuration register found Section starting page Figure shows simplified state diagram that explains main CC2550 states, together with typical usage current consumption. detailed information controlling CC2550 state machine, complete state diagram, Section starting page
Figure Simplified State Diagram with Typical Current Consumption
SWRS039B
Page
CC2550
Configuration Software
After chip reset, registers have default values shown tables Section optimum register setting might differ from default value. After reset registers that shall different from default value therefore needs programmed through interface.
Studio software ([4]). SmartRF® Studio software highly recommended obtaining optimum register settings, evaluating performance functionality. screenshot SmartRF® Studio user interface CC2550 shown Figure
CC2550 configured using SmartRF®
Figure SmartRF® Studio User Interface
4-wire Serial Configuration Data Interface
cancelled. timing address data transfer interface shown Figure with reference Table When pulled low, must wait until CC2500 goes before starting transfer header byte. This indicates that crystal running. Unless chip SLEEP XOFF states, will always immediately after taking low.
CC2550 configured simple 4-wire SPIcompatible interface (SI, SCLK CSn) where CC2550 slave. This interface also used write buffered data. transfer interface done most significant first. transactions interface start with header byte containing bit, burst access (B), 6-bit address A0). must kept during transfers bus. goes high during transfer header byte during read/write from/to register, transfer will
SWRS039B
Page
CC2550
SCLK: CSn: Write register:
Hi-Z
Hi-Z
Read from register:
Hi-Z
Hi-Z
Figure Configuration Registers Write Read Operations
Parameter
fSCLK
Description
SCLK frequency
delay inserted between address byte data byte (single access), between address data, between each data byte (burst access).
Units
SCLK frequency, single access
delay between address data byte
Single access Burst access
SCLK frequency, burst access
delay between address data byte, between data bytes
tsp,pd trise tfall
positive edge SCLK, power-down mode positive edge SCLK, active mode Clock high Clock Clock rise time Clock fall time Setup data (negative SCLK edge) positive edge SCLK
(tsd applies between address data bytes, between data bytes)
Hold data after positive edge SCLK Negative edge SCLK high
Table Interface Timing Requirements Note: minimum tsp,pd figure Table used cases where user does read CHIP_RDYn signal. positive edge SCLK when chip woken from power-down depends start-up time crystal being used. Table crystal oscillator start-up time measured CC2550EM reference design ([3]) using crystal AT-41CD2 from NDK. before first positive edge SCLK. CHIP_RDYn signal indicates that crystal running. Bits comprise STATE value. This value reflects state chip. XOSC power digital core IDLE state, other modules power
Page
10.1 Chip Status Byte When header byte, data byte, command strobe sent interface, chip status byte sent CC2550 pin. status byte contains status signals, useful MCU. first bit, CHIP_RDYn signal; this signal must
SWRS039B
CC2550
down. frequency channel configuration should only updated when chip this state. state active when chip transmitting. last four bits (3:0) status byte contains FIFO_BYTES_AVAILABLE. write operations (the header byte FIFO_BYTES_AVAILABLE field
Bits
contains number bytes that written FIFO. When FIFO_BYTES_AVAILABLE=15, more bytes available/free. Table gives status byte summary.
Name
CHIP_RDYn STATE[2:0]
Description
Stays high until power crystal have stabilized. Should always when using interface. Indicates current main state machine mode Value State IDLE Description Idle state (Also reported some transitional states instead SETTLING CALIBRATE)
FIFO_BYTES_AVAILABLE[3:0]
used FSTXON CALIBRATE SETTLING used TXFIFO_UNDERFLOW FIFO underflowed. Acknowledge with SFTX Transmit mode Frequency synthesizer ready start transmitting Frequency synthesizer calibration running settling
number free bytes FIFO (the header byte must
Table Status Byte Summary
10.2 Registers Access configuration registers CC2550 located addresses from 0x00 0x2E. Table page lists configuration registers. highly recommended SmartRF® Studio generate optimum register settings. detailed description each register found Section 28.1, starting page configuration registers both written read. controls register should written read. When writing registers, status byte sent each time header byte data byte transmitted pin. When reading from registers, status byte sent each time header byte transmitted pin. Registers with consecutive addresses accessed efficient setting
SWRS039B
burst header byte. address bits sets start address internal address counter. This counter incremented each byte (every clock pulses). burst access either read write access must terminated setting high. register addresses range 0x300x3D, burst used select between status registers, burst one, command strobes, burst zero (see Section 10.4 below). Because this, burst access available status registers they must accessed time. status registers only read. 10.3 Read When reading register fields over interface while register fields updated
Page
CC2550
radio hardware (e.g. MARCSTATE TXBYTES), there small, finite, probability that single read from register being corrupt. example, probability single read from TXBYTES being corrupt, assuming maximum data rate used, approximately ppm. Refer CC2550 Errata Note more details. 10.4 Command Strobes Command strobes viewed single byte instructions CC2550. addressing command strobe register, internal sequences will started. These commands used disable crystal oscillator, enable transmit mode, flush FIFO etc. command strobes listed Table page command strobe registers accessed transferring single header byte data being transferred). That only bit, burst access (set address bits range 0x30 through 0x3D) written. When writing command strobes, status byte sent pin. command strobe followed other access without pulling high. However, SRES strobe being issued, will have wait again before next header byte issued shown Figure command strobes executed immediately, with exception SPWD SXOFF strobes that executed when goes high. header byte then consecutive data bytes until terminating access setting high. following header bytes access FIFO: 0x3F: Single byte access FIFO 0x7F: Burst access FIFO
When writing FIFO, status byte (see Section 10.1) output each data byte shown Figure This status byte used detect FIFO underflow while writing data FIFO. Note that status byte contains number bytes free before writing byte progress FIFO. When last byte that fits FIFO transmitted status byte received concurrently will indicate that byte free FIFO. FIFO flushed issuing SFTX command strobe. SFTX command strobe only issued IDLE TX_UNDERFLOW states. FIFO flushed when going SLEEP state. Figure gives brief overview different register access types possible. 10.6 PATABLE Access 0x3E address used access PATABLE, which used selecting power control settings. PATABLE 8byte table, entries into this table used. entries selected 3bit value FREND0.PA_POWER. When using 2-FSK, GFSK, modulation only first entry into this table used (index When using modulation first entries into this table used (index index
Figure SRES Command Strobe 10.5 FIFO Access 64-byte FIFO accessed through 0x3F address write-only. burst used determine FIFO access single byte access burst access. single byte access method expects header byte with burst zero data byte. After data byte header byte expected; hence, remain low. burst access method expects
SWRS039B
Since PATABLE 8-byte table, table written read from lowest setting highest (7), byte time. index counter used control access table. This counter incremented each time byte read written table, lowest index when high. When highest value reached counter restarts
Page
CC2550
access PATABLE either single byte burst access depending burst bit. When using burst access index counter will count when reaching counter will restart controls whether access write access (R/W=0) read access (R/W=1). byte written PATABLE this value read then must high before read access order index counter back zero. Note that content PATABLE lost when entering SLEEP state. Section page output power programming details.
Figure Register Access Types
Microcontroller Interface Configuration
interface. default setting GDO1/SO 3-state output. selecting other programming options GDO1/SO will become generic pin. When low, will always function normal pin. synchronous asynchronous serial modes, GDO0 used serial data input while transmit mode. GDO0 also used on-chip analog temperature sensor. measuring voltage GDO0 with external ADC, temperature calculated. Specifications temperature sensor found Section page With default PTEST register setting (0x7F) temperature sensor output only available when frequency synthesizer enabled (e.g. MANCAL, FSTXON states). necessary write 0xBF PTEST register analog temperature sensor IDLE state. Before leaving IDLE state, PTEST register should restored default value (0x7F).
typical system, CC2550 will interface microcontroller. This microcontroller must able Program CC2550 into different modes Write buffered data Read back status information 4-wire SPI-bus configuration interface (SI, SCLK CSn) 11.1 Configuration Interface microcontroller uses four pins configuration interface (SI, SCLK CSn). described Section page 11.2 General Control Status Pins CC2550 dedicated configurable (GDO0) shared (GDO1) that output internal status information useful control software. These pins used generate interrupts MCU. Section page more details signals that programmed. GDO1 shared with
SWRS039B
Page
CC2550
Data Rate Programming
DRATE_M rounded nearest integer becomes 256, increment DRATE_E DRATE_M=0. data rate from kBaud kBaud with minimum step size
data rate used when transmitting programmed MDMCFG3.DRATE_M MDMCFG4.DRATE_E configuration registers. data rate given formula below. formula shows, programmed data rate depends crystal frequency.
RDATA
(256 DRATE DRATE
XOSC
Data Rate Start [kBaud]
Typical Data Rate [kBaud]
1.2/2.4 19.6 38.4 76.8 153.6
Data Rate Stop [kBaud]
3.17 6.35 12.7 25.4 50.8 101.6 203.1 406.3
Data Rate Step Size [kBaud]
0.0062 0.0124 0.0248 0.0496 0.0992 0.1984 0.3967 0.7935 1.5869
following approach used find suitable values given data rate:
3.17 6.35 12.7
DATA DRATE XOSC DRATE DATA XOSC DRATE
25.4 50.8 101.6 203.1 406.3
Table Data Rate Step Size
Packet Handling Hardware Support
Whitening data with sequence. Forward error correction interleaving coding data (convolutional coding).
CC2550 built-in hardware support packet oriented radio protocols. transmit mode, packet handler configured following elements packet stored FIFO: programmable number preamble bytes byte synchronization (sync) word. duplicated give 4-byte sync word. possible only insert preamble only insert sync word. checksum computed over data field.
Note that register fields that control packet handling features should only altered when CC2550 IDLE state. 13.1 Data whitening From radio perspective, ideal over data random free. This results smoothest power distribution over occupied bandwidth. This also gives regulation loops receiver uniform operation conditions data dependencies). Real world data often contain long sequences zeros ones. Performance then improved whitening data before transmitting, de-whitening data receiver. With CC2550, combination with CC2500 receiver end, this done automatically setting PKTCTRL0
Page
system where CC2550 used transmitter CC2500 receiver, recommended setting 4-byte preamble 4-byte sync word, except kBaud data rate where recommended preamble length bytes. addition, following implemented data field optional 2-byte checksum:
SWRS039B
CC2550
.WHITE_DATA=1. data, except preamble sync word, then XOR-ed with 9-bit pseudo-random (PN9) sequence before being transmitted shown Figure receiver end, data XOR-ed with same pseudo-random sequence. This way, whitening reversed, original data appear receiver. sequence reset 1's. Data whitening only used when PKTCTRL0.CC2400_EN=0 (default).
Figure Data Whitening Mode Synchronization word Optional length byte Optional address byte Payload Optional byte
13.2 Packet Format format data packet configured consists following items (see Figure 10): Preamble
Optional data whitening Optionally encoded/decoded Optional CRC-16 calculation Address field Length field Sync word
Legend: Inserted automatically processed removed CRC-16 Optional user-provided fields processed processed removed Unprocessed user data (apart from and/or whitening)
Preamble bits (1010.1010)
Data field
bits
16/32 bits
bits
bits
bits
bits
Figure Packet Format preamble pattern alternating sequence ones zeros (101010101.). minimum length preamble programmable. When enabling modulator will start transmitting preamble. When programmed number preamble
SWRS039B
bytes been transmitted, modulator will send sync word then data from FIFO data available. FIFO empty, modulator will continue send preamble bytes until first byte written FIFO. modulator will then send
Page
CC2550
sync word then data bytes. number preamble bytes programmed with MDMCFG1.NUM_PREAMBLE value. synchronization word two-byte value SYNC1 SYNC0 registers. onebyte sync word emulated setting SYNC1 value preamble pattern. also possible emulate sync word using MDMCFG2.SYNC_MODE=3 sync word will then repeated twice. Note that minimum packet length supported (excluding optional length byte CRC) byte payload data. 13.2.1 Packet Length Reprogramming packet automation control register, PCKCTRL0, during mode opens possibility transmit packets that longer than bytes still able packet handling hardware support. start packet, infinite packet length mode (PCKCTRL0.LENGTH_CONFIG=2) must active. PKTLEN register mod(length, 256). When less than bytes remains packet disables infinite packet length mode activates fixed packet length mode. When internal byte counter reaches PKTLEN value, transmission ends radio enters state determined TXOFF_MODE). Automatic appending used setting PKTCTRL0.CRC_EN=1). When example 600-byte packet transmitted, should following (see also Figure 11): PKTCTRL0.LENGTH_CONFIG=2. Pre-program PKTLEN mod(600,256)=88. register
CC2550 supports both fixed packet length
protocols variable packet length protocols. Variable fixed packet length mode used packets bytes. longer packets, infinite packet length mode must used. Fixed packet length mode selected setting PKTCTRL0.LENGTH_CONFIG=0. desired packet length PKTLEN register. variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, packet length configured first byte after sync word. packet length defined payload data, excluding length byte optional automatic CRC. With PKTCTRL0.LENGTH_CONFIG=2, packet length infinite transmission will continue until turned manually. described next section, this used support packet formats with different length configuration than natively supported CC2550. should make sure that mode turned during transmission first half byte. Refer CC2550 Errata Notes more details.
Transmit least bytes (600 255), example filling 64-byte FIFO times (384 bytes transmitted). PKTCTRL0.LENGTH_CONFIG=0. transmission ends when packet counter reaches total bytes transmitted.
Figure Packet Length
SWRS039B Page
CC2550
13.3 Packet Handling Transmit Mode payload that transmitted must written into FIFO. first byte written must length byte when variable packet length enabled. length byte value equal payload packet (including optional address byte). fixed packet length enabled, then first byte written FIFO interpreted destination address, this feature enabled device that receives packet. modulator will first send programmed number preamble bytes. data available FIFO, modulator will send two-byte (optionally 4-byte) sync word then payload FIFO. enabled, checksum calculated over data pulled from FIFO result sent extra bytes payload data. FIFO runs empty before complete packet been transmitted, radio will enter TXFIFO_UNDERFLOW state. only exit this state issuing SFTX strobe. Writing FIFO after underflowed will restart mode. whitening enabled, everything following sync words will whitened. This done before optional FEC/Interleaver stage. Whitening enabled setting PKTCTRL0.WHITE_DATA=1. FEC/Interleaving enabled, everything following sync words will scrambled interleaver, encoded before being modulated. enabled setting MDMCFG.FEC_EN=1. 13.4 Packet Handling Firmware FIFO needs refilled while This means that needs know number bytes that written FIFO. There possible solutions necessary status information: Interrupt driven solution possible pins give interrupt when sync word been transmitted and/or when complete packet been transmitted (IOCFGx=0x06). addition, there configurations IOCFGx register that associated with FIFO (IOCFGx=0x02 IOCFG=0x03) that used interrupt sources provide information many bytes FIFO. Table polling PKTSTATUS register polled given rate information about current GDO0 value. TXBYTES register polled given rate information about number bytes FIFO. Alternatively, number bytes FIFO read from chip status byte returned MISO line each time header byte, data byte, command strobe sent bus. This only valid when explained Section 10.3 CC2550 Errata Notes [1], when using polling there small, finite, probability that single read from registers PKTSTATUS TXBYTES being corrupt. same case when reading chip status byte. therefore recommended employ interrupt driven solution. Refer website examples ([5] [6]).
When implementing packet oriented radio protocol firmware, needs know when packet been transmitted. Additionally, packets longer than bytes
Modulation Formats
Manchester encoding supported same time using FEC/Interleaver option.
CC2550 supports amplitude, frequency phase shift modulation formats. desired modulation format MDMCFG2.MOD_FORMAT register.
Optionally, data stream Manchester coded modulator. This option enabled setting MDMCFG2.MANCHESTER_EN=1.
SWRS039B
Page
CC2550
14.1 Frequency Shift Keying 2-FSK optionally shaped Gaussian filter with BT=1, producing GFSK modulated signal. frequency deviation programmed with DEVIATION_M DEVIATION_E values DEVIATN register. value exponent/mantissa form, resultant deviation given 14.2 Minimum Shift Keying When using MSK1, complete transmission (preamble, sync word payload) will modulated. Phase shifts performed with constant transition time. fraction symbol period used change phase modified with DEVIATN.DEVIATION_M setting. This equivalent changing shaping symbol.
xosc DEVIATION DEVIATION
CC2550 inverts sync word data
compared e.g. signal generators. 14.3 Amplitude Modulation
modulation format implemented
symbol encoding shown Table
Format
2-FSK\GFSK
Symbol
Coding
Deviation Deviation
supported amplitude modulation On-Off Keying (OOK) simply turns modulate respectively. Identical offset QPSK with half-sine shaping (data coding differ)
Table Symbol Encoding 2-FSK/GFSK Modulation
Forward Error Correction with Interleaving
transient time-varying phenomena will produce occasional errors even otherwise good reception conditions. will mask such errors and, combined with interleaving coded data, even correct relatively long periods faulty reception (burst errors). scheme adopted CC2550 convolutional coding, which bits generated based input bits most recent input bits, forming code stream able withstand certain number errors between each coding state (the m-bit window). convolutional coder rate code with constraint length m=4. coder codes input produces output bits; hence, effective data rate halved. I.e. transmit same effective data rate when using FEC, necessary twice high over-the-air data rate. I.e. transmit same effective data rate when using FEC, necessary twice high over-the-air data rate. This will require higher CC2500 receiver bandwidth, thus reduced sensitivity. other words, improved reception using degraded
Page
15.1 Forward Error Correction (FEC)
CC2550 built support Forward Error Correction (FEC) that used with CC2500 receiver end. enable this option, MDMCFG1.FEC_EN=1. employed data field word order reduce gross error rate when operating near sensitivity limit. Redundancy added transmitted data such that CC2500 restore original data presence some errors.
allows correct reception lower SNR, thus extending communication range. Alternatively, given SNR, using decreases error rate (BER). packet error rate (PER) related
BER) packet length
lower used allow longer packets, higher percentage packets given length, transmitted successfully. Finally, realistic radio environments,
SWRS039B
CC2550
sensitivity from higher receiver bandwidth will counteracting factors. 15.2 Interleaving Data received through radio channels will often experience burst errors interference time-varying signal strengths. order increase robustness errors spanning multiple bits, interleaving used when enabled. After de-interleaving receiver side, continuous span errors received stream will become single errors spread apart. into rows matrix, whereas data passed onto convolutional decoder read from columns matrix. When interleaving used least extra byte required trellis termination. addition, amount data transmitted over must multiple size interleaver buffer (two bytes). packet control hardware therefore automatically inserts extra bytes packet, that total length data interleaved even number. Note that these extra bytes invisible user, they removed before received packet enters FIFO CC2500 [9]. When interleaving used minimum data payload bytes. Note that CC2500 transceiver only supported fixed packet length mode (PKTCTRL0.LENGTH_CONFIG=0).
CC2550 employs matrix interleaving, which illustrated Figure on-chip interleaving buffer matrix. data bits from rate convolutional coder written into rows matrix, whereas sequence transmitted read from columns matrix. Conversely, CC2500 receiver, received symbols written
Interleaver Write buffer
Interleaver Read buffer
Packet Engine
Encoder
Modulator
Figure General Principle Matrix Interleaving
SWRS039B
Page
CC2550
Radio Control
SIDLE SPWD IDLE SCAL SFSTXON SXOFF XOFF SLEEP
CAL_COMPLETE MANCAL 3,4,5
FS_WAKEUP
FS_AUTOCAL SFSTXON
FS_AUTOCAL SFSTXON
CALIBRATE
SFSTXON FSTXON
SETTLING 9,10,11
CAL_COMPLETE
TXOFF_MODE
TXOFF_MODE
19,20
TXFIFO_UNDERFLOW TXOFF_MODE FS_AUTOCAL
TX_UNDERFLOW
TXOFF_MODE FS_AUTOCAL
CALIBRATE
SFTX
IDLE
Figure Complete Radio Control State Diagram
CC2550 built-in state machine that used switch between different operation states (modes). change state done either using command strobes internal events such FIFO underflow.
simplified state diagram, together with typical usage current consumption, shown Figure page complete radio control state diagram shown Figure
SWRS039B
numbers refer state number readable MARCSTATE status register. This register primarily test purposes. 16.1 Power-On Start-Up Sequence When power supply turned system must reset. following
Page
CC2550
sequences must followed: Automatic power-on reset (POR) manual reset. 16.1.1 Automatic power-on reset circuit included CC2550. minimum requirements stated Section must followed power-on reset function properly. internal powerup sequence completed when CHIP_RDYn goes low. CHIP_RDYn observed after pulled low. Section 10.1 more details CHIP_RDYn. When CC2550 reset completed chip will IDLE state crystal oscillator will running. chip sufficient time crystal oscillator stabilize after power-on-reset, will immediately after taking low. taken before reset completed will first high, indicating that crystal oscillator stabilized, before going shown Figure
XOSC voltage regulator switched XOSC Stable
SRES
Figure Power-On Reset with SRES Note that above reset procedure only required just after power supply first turned user wants reset CC2550 after this, only necessary issue SRES command strobe. 16.2 Crystal Control crystal oscillator automatically turned when goes low. will turned SXOFF SPWD command strobes issued; state machine then goes XOFF SLEEP respectively. This only done from IDLE state. XOSC will turned when released (goes high). XOSC will automatically turned again when goes low. state machine will then IDLE state. interface must pulled before interface ready used; described Section 10.1 page Crystal oscillator start-up time depends crystal load capacitances. electrical specification crystal oscillator found Section page 16.3 Voltage Regulator Control voltage regulator digital core controlled radio controller. When chip enters SLEEP state, which state with lowest current consumption, voltage regulator disabled. This occurs after released when SPWD command strobe been sent interface. chip SLEEP state. Setting again will turn regulator crystal oscillator make chip enter IDLE state. CC2550 register values (with exception MCSM0.PO_TIMEOUT field) lost
Figure Power-On Reset
16.1.2 Manual Reset other global reset possibility CC2550 SRES command strobe. issuing this strobe, internal registers states default, IDLE state. manual powerup sequence follows (see Figure 15): Strobe high. Hold high least relative pulling Pull wait (CHIP_RDYn). Issue SRES strobe line. When goes again, reset complete chip IDLE state.
SWRS039B
Page
CC2550
SLEEP state. After chip gets back IDLE state, registers will have default (reset) contents must reprogrammed over interface. 16.4 Mode Transmit mode activated using command strobe. frequency synthesizer must calibrated regularly. CC2550 manual calibration option (using SCAL strobe), three automatic calibration options, controlled MCSM0.FS_AUTOCAL setting: Calibrate when going from IDLE FSTXON) Calibrate when going from IDLE automatically Calibrate every fourth time when going from IDLE automatically FSTXON: Frequency synthesizer ready frequency. Activate with STX. Start sending preambles
SIDLE command strobe always used force radio controller IDLE state. 16.5 Timing
CC2550, such synthesizer calibration
radio controller controls most timing
lock time. Timing from IDLE constant, dependent auto calibration setting. calibration time constant 18739 clock periods. Table shows timing crystal clock cycles state transitions. Power time XOSC start-up times variable, within limits stated Table Note that frequency hopping spread spectrum multi-channel protocol calibration time reduced from approximately This explained Section 27.2.
radio goes from IDLE issuing SIDLE strobe, calibration will performed. calibration takes constant number XOSC cycles (see Table timing details). After activating mode, chip will remain state until current packet been successfully transmitted. Then state will change indicated MCSM1.TXOFF_MODE setting. possible destinations are: IDLE
Description
Idle TX/FSTXON, calibration Idle TX/FSTXON, with calibration IDLE, calibration IDLE, including calibration Manual calibration
XOSC Periods
2298 ~21037 ~18739 ~18739
Crystal
88.4
Table State Transition Timing
FIFO
header byte Section 10.1 page contains more details this. number bytes FIFO also read from TXBYTES.NUM_TXBYTES status register. 4-bit FIFOTHR.FIFO_THR setting used program threshold points FIFO. Table lists FIFO_THR settings corresponding thresholds FIFO. signal will assert when number bytes FIFO equal higher than programmed threshold. signal
Page
CC2550 contains byte FIFO data transmitted. interface used writing FIFO. Section 10.5 contains details FIFO access. FIFO controller will detect underflow FIFO. When writing FIFO responsibility avoid FIFO overflow. FIFO overflow will result error FIFO content. chip status byte that available while transferring address contains fill grade FIFO
SWRS039B
CC2550
viewed pins (see Section page 33). Figure shows number bytes FIFO when threshold flag toggles, case FIFO_THR=13. Figure shows signal FIFO filled above threshold, then drained below.
NUM_TXBYTES
Figure FIFO_THR=13 Number Bytes FIFO (GDOx_CFG=0x02)
FIFO_THR (0000) (0001) (0010) (0011) (0100) (0101) (0110) (0111) (1000) (1001) (1010) (1011) (1100) (1101) (1110) (1111)
Bytes FIFO
FIFO_THR=13
Underflow margin
bytes TXFIFO
Figure Example FIFO Threshold
Table FIFO_THR Settings Corresponding FIFO Thresholds
Frequency Programming
base start frequency frequency word located FREQ2, FREQ1 FREQ0 registers. This word will typically centre lowest channel frequency that used. desired channel number programmed with 8-bit channel number register, CHANNR.CHAN, which multiplied channel offset. resultant carrier frequency given
frequency programming CC2550 designed minimize programming needed channel-oriented system. system with channel numbers, desired channel spacing programmed with MDMCFG0.CHANSPC_M MDMCFG1.CHANSPC_E registers. channel spacing registers mantissa exponent respectively.
carrier
XOSC FREQ CHAN (256 CHANSPC CHANSPC
SWRS039B
Page
CC2550
With crystal maximum channel spacing kHz. e.g. channel spacing solution channel spacing select each third channel CHANNR.CHAN. frequency programming register altered when frequency synthesizer running, synthesizer give undesired response. Hence, frequency programming should only updated when radio IDLE state.
calibration initiated when SCAL command strobe activated IDLE mode. calibration values maintained sleep mode. Therefore, CC2550 must recalibrated after reprogramming configuration registers when chip been SLEEP state. check that lock user program register IOCFGx.GDOx_CFG 0x0A lock detector output available GDOx interrupt positive transition GDOx means that lock. alternative user read register FSCAL1. lock register content different from 0x3F. Refer also CC2550 Errata Notes [1]. more robust operation source code could include check that recalibrated until lock achieved does lock first time.
completely integrated on-chip. 19.1 Self-Calibration characteristics will vary with temperature supply voltage changes, well desired operating frequency. order ensure reliable operation, CC2550 includes frequency synthesizer self-calibration circuitry. This calibration should done regularly, must performed after turning power before using frequency channel). number XOSC cycles completing calibration given Table page calibration initiated automatically manually. synthesizer automatically calibrated each time synthesizer turned each time synthesizer turned automatically. This configured with MCSM0.FS_AUTOCAL register setting. manual mode,
Voltage Regulators
chip programmed enter power-down mode, (SPWD strobe issued), power will turned after goes high. power crystal oscillator will turned again when goes low. voltage regulator output should only used driving CC2550.
CC2550 contains several on-chip linear voltage regulators, which generate supply voltage needed low-voltage modules. These voltage regulators invisible user, viewed integral parts various modules. user must however make sure that absolute maximum ratings required voltages Table Table exceeded. voltage regulator digital core requires external decoupling capacitor.
Setting turns voltage regulator digital core starts crystal oscillator. interface must before first positive edge SCLK (setup time given Table 14).
SWRS039B
Page
CC2550
Output Power Programming
FREND0.PA_POWER value shall Table contains recommended PATABLE settings various output levels frequency bands. Section 10.6 page PATABLE programming details. SmartRF® Studio software should used obtain optimum PATABLE settings various output powers. PATABLE must programmed burst mode writing other entries than PATABLE(0) (OOK modulation). Note that content PATABLE lost when entering SLEEP state.
output power level from device levels programmability, illustrated Figure output power level from device programmed through PATABLE register. 2-FSK, GFSK modulation used desired output power programmed index PATABLE register (PATABLE(0)[7:0]). 3-bit FREND0.PA_POWER value shall (reset default value). modulation used desired output power logic logic power levels programmed index index PATABLE register respectively (PATABLE(0)[7:0] PATABLE(1)[7:0]). 3-bit
Figure PA_POWER PATABLE
SWRS039B
Page
CC2550
PATABLE(7)[7:0] PATABLE(6)[7:0] PATABLE(5)[7:0] PATABLE(4)[7:0] PATABLE(3)[7:0] PATABLE(2)[7:0] PATABLE(1)[7:0] PATABLE(0)[7:0] Index into PATABLE(7:0) Settings PA_POWER used during ramp-up start transmission ramp-down transmission, modulation. uses this setting.
PA_POWER[2:0] FREND0 register
SmartRF® Studio software should used obtain optimum PATABLE settings various output powers.
Figure PA_POWER PATABLE
Output Power, Typical, [dBm]
(-55 less)
PATABLE Value
0x00 0x44 0x41 0x43 0x84 0x82 0x47 0xC8 0x85 0x59 0xC6 0x97 0xD6 0x7F 0xA9 0xBF 0xEE 0xFF
Current Consumption, Typical [mA]
10.0 11.6 10.2 11.6 11.2 12.0 12.9 14.7 16.2 18.1 19.4 21.3
Table Optimum PATABLE Settings Various Output Power Levels
SWRS039B
Page
CC2550
Crystal Oscillator
crystal oscillator circuit shown Figure Typical component values different values given Table crystal oscillator amplitude regulated. This means that high current used start oscillations. When amplitude builds current reduced what necessary maintain approximately signal swing. This ensures fast start-up, keeps drive level minimum. crystal should within specification order ensure reliable start-up (see Section page
crystal frequency range 26-27 must connected between XOSC_Q1 XOSC_Q2 pins. oscillator designed parallel mode operation crystal. addition, loading capacitors (C51 C71) crystal required. loading capacitor values depend total load capacitance, specified crystal. total load capacitance seen between crystal terminals should equal crystal oscillate specified frequency.
parasitic
XOSC_Q1 XOSC_Q2
parasitic capacitance constituted input capacitance stray capacitance. Total parasitic capacitance typically
XTAL
Figure Crystal Oscillator Circuit
CL=13
Component
CL=16
Table Crystal Oscillator Component Values XOSC_Q1 input. sine wave must connected XOSC_Q1 using serial capacitor. When using full-swing digital signal this capacitor omitted. XOSC_Q2 line must left un-connected. omitted when using reference signal
22.1 Reference Signal chip alternatively operated with reference signal from instead crystal. This input clock either fullswing digital signal VDD) sine wave maximum peak-peak amplitude. reference signal must connected
External Match
differential impedance seen from RFport (RF_P RF_N) towards antenna: Zout ensure optimal matching CC2550 differential output highly recommended follow CC2550EM reference design closely possible. Gerber files reference designs available download from website.
balanced output CC2550 designed simple, low-cost matching balun network printed circuit board. passive external components ensure proper matching. Although CC2550 balanced output, chip connected single-ended antenna with external cost capacitors inductors. passive matching/filtering network connected CC2550 should have following
SWRS039B
Page
CC2550
Layout Recommendations
capacitor should connected power line separate vias. best routing from power line decoupling capacitor then CC2550 supply pin. Supply power filtering very important. Each decoupling capacitor ground should connected ground plane using separate via. Direct connections between neighboring power pins will increase noise coupling should avoided unless absolutely necessary. external components should ideally small possible (0402 recommended) surface mount devices highly recommended. Please note that components smaller than those specified have differing characteristics. Precaution should used when placing microcontroller order avoid noise interfering with circuitry. CC2500/2550DK Development with fully assembled CC2550EM Evaluation Module available. strongly advised that this reference layout followed very closely order best performance. schematic, layout Gerber files available from website [3].
layer should used signal routing, open areas should filled with metallization connected ground using several vias. area under chip used grounding shall connected bottom ground plane with several vias good thermal performance sufficiently inductance ground. CC2550EM reference designs vias placed inside exposed attached pad. These vias should "tented" (covered with solder mask) component side avoid migration solder through vias during solder reflow process. solder paste coverage should 100%. gassing occur during reflow process, which cause defects (splattering, solder balling). Using "tented" vias reduces solder paste coverage below 100%. Figure solder resist paste masks. Figure recommended layout package. Each decoupling capacitor should placed close possible supply supposed decouple. Each decoupling
Figure Left: Paste Mask. Right: Solder Resist Mask (negative). Circles Vias.
General Purpose Test Output Control Pins
thus output programmed this will only valid when high. default value GDO1 3-stated, which useful when interface shared with other devices. default value GDO0 135-141 clock output (XOSC frequency divided 192). Since XOSC turned power-onPage
digital output pins GDO0 GDO1 general control pins configured with IOCFG0.GDO0_CFG IOCFG1.GDO1_CFG respectively. Table shows different signals that monitored pins. These signals used inputs MCU. GDO1 same interface,
SWRS039B
CC2550
reset, this used clock systems with only crystal. When running, change clock frequency writing IOCFG0.GDO0_CFG. on-chip analog temperature sensor enabled writing value (0x80) GDOx_CFG[5:0]
(0x00) (0x01) (0x02) (0x03) (0x04) (0x05) (0x06) (0x07) (0x09) (0x0A) (0x0B) (0x0C) (0x28) (0x29) (0x2A) (0x2B) (0x2C) (0x2D) (0x2E) (0x2F) (0x30) (0x31) (0x32) (0x33) (0x34) (0x35) (0x36) (0x37) (0x38) (0x39) (0x3A) (0x3B) (0x3C) (0x3D) (0x3E) (0x3F)
IOCFG0.GDO0_CFG register. voltage GDO0 then proportional temperature. Section page temperature sensor specifications. SLEEP mode, GDO1 will hardwired GDO0 will high impedance.
Description Reserved defined transceiver version. Reserved defined transceiver version. Associated FIFO: Asserts when FIFO filled above FIFO threshold. De-asserts when FIFO below same threshold. Associated FIFO: Asserts when FIFO full. De-asserts when FIFO drained below theTX FIFO threshold. Reserved defined transceiver version. Asserts when FIFO underflowed. De-asserts when FIFO flushed. Asserts when sync word been sent, de-asserts packet. will also de-assert FIFO underflows.
Reserved Lock detector output. lock lock detector output positive transition constantly logic high. check lock lock detector output should used interrupt MCU. Serial Clock. Synchronous data synchronous serial mode. mode, data sampled CC2550 rising edge serial clock when GDOx_INV=0. Reserved used test.
CHIP_RDY Reserved used test. XOSC_STABLE Reserved used test. GDO0_Z_EN_N. When this output GDO0 configured input (for serial data). High impedance (3-state) (HW1 achieved with _INV signal). used control external CLK_XOSC/1 CLK_XOSC/1.5 CLK_XOSC/2 CLK_XOSC/3 CLK_XOSC/4 CLK_XOSC/6 CLK_XOSC/8 Note: There pins, only CLK_XOSC/n selected output CLK_XOSC/12 time. CLK_XOSC/n monitored pins, other must CLK_XOSC/16 configured value less than 0x30. GDO0 default value CLK_XOSC/192. CLK_XOSC/24 CLK_XOSC/32 CLK_XOSC/48 CLK_XOSC/64 CLK_XOSC/96 CLK_XOSC/128 CLK_XOSC/192
Table GDOx Signal Selection
Asynchronous Synchronous Serial Operation
significantly offload microcontroller simplify software development. 26.1 Asynchronous Operation backward compatibility with systems already using asynchronous data transfer from other Chipcon products, asynchronous
Page
Several features modes operation have been included CC2550 provide backward compatibility with previous Chipcon products other existing communication systems. systems, recommended built-in packet handling features, they give more robust communication,
SWRS039B
CC2550
transfer also included CC2550. When asynchronous transfer enabled, several support mechanisms that included CC2550 will disabled, such packet handling hardware, buffering FIFO asynchronous transfer mode does allow data whitener, interleaver FEC, possible Manchester encoding. Note that asynchronous transfer. supported synchronous mode, data transferred wire serial interface. CC2550 provides clock that used data data input line. Data input data) GDO0 pin. This will automatically configured input when active. Preamble sync word insertion active, dependent sync mode MDMCFG3.SYNC_MODE. preamble sync word disabled, other packet handler features should also disabled. must then handle preamble sync word insertion software. preamble sync word insertion left packet handling features used. When using packet handling features synchronous serial mode, CC2550 will insert preamble sync word will only provide data payload. This equivalent recommended FIFO operation mode.
Setting PKTCTRL0.PKT_FORMAT enables asynchronous serial mode.
GDO0 used data input data). CC2550 modulator samples level asynchronous input times faster than programmed data rate. timing requirement asynchronous stream that error period must less than eighth programmed data rate. 26.2 Synchronous Serial Operation Setting PKTCTRL0.PKT_FORMAT enables synchronous serial operation mode.
System considerations Guidelines
27.1 Regulations International regulations national laws regulate radio receivers transmitters. most important regulations band (Europe), CFR47 part 15.247 15.249 (USA), ARIB STD-T66 (Japan). summary most important aspects these regulations found Application Note AN032 [2]. Please note that compliance with regulations dependent complete system performance. customer's responsibility ensure that system complies with regulations. 27.2 Frequency Hopping Channel Systems Multimakes system more robust with respect interference from other systems operating same frequency band. FHSS also combats multipath fading.
CC2550 highly suited FHSS multichannel systems agile frequency synthesizer effective communication interface. Using packet handling support data buffering also beneficial such systems these features will significantly offload host controller.
Charge pump current, current capacitance array calibration data required each frequency when implementing frequency hopping CC2550. There ways obtaining calibration data from chip: Frequency hopping with calibration each hop. calibration time approximately blanking interval between each frequency then approximately Fast frequency hopping without calibration each done calibrating each frequency startup saving resulting
Page
2.400 2.4835 band shared many systems both industrial, office home environments. therefore recommended frequency hopping spread spectrum (FHSS) multi-channel protocol because frequency diversity
SWRS039B
CC2550
FSCAL3, FSCAL2 FSCAL1 register values memory. Between each frequency hop, calibration process then replaced writing FSCAL3, FSCAL2 FSCAL1 register values corresponding next frequency. turn time approximately blanking interval between each frequency then approximately current calibration result available FSCAL2 dependent frequency. Neither charge pump current calibration result available FSCAL3. same value therefore used frequencies. calibration single frequency startup. Next write FSCAL3[5:4] disable charge pump calibration. After writing FSCAL3[5:4] strobe with MCSM0.FS_AUTOCAL=1 each frequency hop. That current capacitance calibration done charge pump current calibration. When charge pump current calibration disabled calibration time reduced from approximately approximately blanking interval between each frequency then approximately There trade between blanking time memory space needed storing calibration data non-volatile memory. Solution above gives shortest blanking interval, requires more memory space store calibration values. Solution gives approximately smaller blanking interval than solution 27.3 Wideband Modulation Spread Spectrum Using 27.4 Data Burst Transmissions high maximum data rate CC2550 opens burst transmissions. average data rate link (e.g. kBaud), realized using higher over-the-air data rate. Buffering data transmitting bursts high data rate (e.g. kBaud) will reduce time mode, hence also reduce average current consumption significantly. Reducing time mode will reduce likelihood collisions with other systems, e.g. WLAN. 27.5 Continuous Transmissions data streaming applications CC2550 opens continuous transmissions kBaud effective data rate. modulation done with closed loop PLL, there limitation length transmission (open loop modulation used some transceivers often prevents this kind continuous data streaming reduces effective data rate.) 27.6 Spectrum Efficient Modulation
CC2500 also possibility Gaussian shaped 2-FSK (GFSK). This spectrum-shaping feature improves adjacent channel power (ACP) occupied bandwidth. `true' 2-FSK systems with abrupt frequency shifting, spectrum inherently broad. making frequency shift `softer', spectrum made significantly narrower. Thus, higher data rates transmitted same bandwidth using GFSK.
27.7 Cost Systems differential antenna will eliminate need balun, biasing achieved antenna topology, Figure CC25XX Folded Dipole reference design contains schematics layout files CC2500EM with folded dipole antenna. This design note also used with CC2550. Please DN004 more details this design. HC-49 type crystal used CC2550EM reference design. Note that crystal package strongly influences price. size constrained design smaller, more expensive, crystal used. 27.8 Battery Operated Systems power applications, SLEEP state should used when CC2550 active.
Digital modulation systems under part 15.247 includes 2-FSK GFSK modulation. maximum peak output power (+30 dBm) allowed bandwidth modulated signal exceeds kHz. addition, peak power spectral density conducted antenna shall greater than band. Operating high data rates high frequency separation, CC2550 suited systems targeting compliance with digital modulation systems defined part 15.247. external power amplifier needed increase output above dBm.
SWRS039B
Page
CC2550
27.9 Increasing Output Power some applications necessary extend link range adding external power amplifier. power amplifier should inserted between antenna balun shown Figure
Figure Block Diagram CC2550 Usage with External Power Amplifier
Configuration Registers
FIFO accessed through 8-bit register. Only write operations allowed FIFO. During header byte transfer while writing data register FIFO, status byte returned line. This status byte described Table page Table summarizes address space. Registers that only defined CC2500 transceiver also listed. CC2500 CC2550 register compatible, registers fields only implemented transceiver always contain CC2550. address given adding base address left burst bits top. Note that burst different meaning base addresses above below 0x2F. Note that registers, (with exception MSCM0.PO_TIMEOUT field) will lose their content SLEEP mode.
configuration CC2550 done programming 8-bit registers. optimum configuration data based selected system parameters most easily found using SmartRF® Studio software [4]. Complete descriptions registers given following tables. After chip reset, registers have default values shown tables. optimum register setting might differ from default value. After reset registers that shall different from default value therefore needs programmed through interface. There command strobe registers, listed Table Accessing these registers will initiate change internal state mode. There normal 8-bit configuration registers, listed Table Some these registers test purposes only, need written normal operation CC2550. There also status registers, which listed Table These registers, which read-only, contain information about status CC2550.
SWRS039B
Page
CC2550
Address
0x30 0x31 0x32 0x33 0x35 0x36 0x39 0x3B 0x3D
Strobe Name
SRES SFSTXON SXOFF SCAL SIDLE SPWD SFTX SNOP
Description
Reset chip. Enable calibrate frequency synthesizer MCSM0.FS_AUTOCAL=1). Turn crystal oscillator. Calibrate frequency synthesizer turn (enables quick start). SCAL strobed IDLE state without setting manual calibration mode (MCSM0.FS_AUTOCAL=0). Enable Perform calibration first MCSM0.FS_AUTOCAL=1. Exit turn frequency synthesizer. Enter power down mode when goes high. Flush FIFO buffer. operation. used access chip status byte.
Table Command Strobes
SWRS039B
Page
CC2550
Address
0x01 0x02 0x03 0x04 0x05 0x06 0x08 0x0A 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x17 0x18 0x22 0x23 0x24 0x25 0x26 0x29 0x2A 0x2C 0x2D 0x2E
Register
IOCFG1 IOCFG0 FIFOTHR SYNC1 SYNC0 PKTLEN PKTCTRL0 CHANNR FREQ2 FREQ1 FREQ0 MDMCFG4 MDMCFG3 MDMCFG2 MDMCFG1 MDMCFG0 DEVIATN MCSM1 MCSM0 FREND0 FSCAL3 FSCAL2 FSCAL1 FSCAL0 FSTEST PTEST TEST2 TEST1 TEST0
Description
GDO1 output configuration GDO0 output configuration FIFO threshold Sync word, high byte Sync word, byte Packet length Packet automation control Channel number Frequency control word, high byte Frequency control word, middle byte Frequency control word, byte Modulator configuration Modulator configuration Modulator configuration Modulator configuration Modulator configuration Modulator deviation setting Main Radio Control State Machine configuration Main Radio Control State Machine configuration Front configuration Frequency synthesizer calibration Frequency synthesizer calibration Frequency synthesizer calibration Frequency synthesizer calibration Frequency synthesizer calibration control Production test Various test settings Various test settings Various test settings
Details Page Number
Table Configuration Registers Overview
Address
0x30 (0xF0) 0x31 (0xF1) 0x35 (0xF5) 0x38 (0xF8) 0x39 (0xF9) 0x3A (0xFA)
Register
PARTNUM VERSION MARCSTATE PKTSTATUS VCO_VC_DAC TXBYTES
Description
Details Page Number
CC2550 part number
Current version number Control state machine state Current GDOx status packet status Current setting from calibration module Underflow number bytes FIFO
Table Status Registers Overview
SWRS039B
Page
CC2550
Write Single byte +0x00 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Burst +0x40 Single byte +0x80 Reserved IOCFG1 IOCFG0 FIFOTHR SYNC1 SYNC0 PKTLEN Reserved PKTCTRL0 Reserved CHANNR Reserved Reserved FREQ2 FREQ1 FREQ0 MDMCFG4 MDMCFG3 MDMCFG2 MDMCFG1 MDMCFG0 DEVIATN Reserved MCSM1 MCSM0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved FREND0 FSCAL3 FSCAL2 FSCAL1 FSCAL0 Reserved Reserved FSTEST PTEST Reserved TEST2 TEST1 TEST0 SRES SFSTXON SXOFF SCAL Reserved SIDLE Reserved SPWD Reserved SFTX Reserved SNOP PATABLE FIFO SRES SFSTXON SXOFF SCAL Reserved SIDLE Reserved SPWD Reserved SFTX Reserved SNOP Reserved FIFO PARTNUM VERSION FREQEST Reserved Reserved MARCSTATE Reserved Reserved PKTSTATUS VCO_VC_DAC TXBYTES Reserved Read Burst +0xC0
PATABLE FIFO
Reserved FIFO
Table Address Space
SWRS039B
Command strobes, status registers (read only) multi byte registers
configuration registers, burst access possible
Page
CC2550
28.1 Configuration Register Details 0x01: IOCFG1 GDO1 Output Configuration
Field Name
GDO_DS GDO1_INV GDO1_CFG[5:0]
Reset
(0x2E)
Description
high output drive strength pins. Invert output, i.e. select active high Default 3-state (see Table page
0x02: IOCFG0 GDO0 Output Configuration
Field Name
TEMP_SENSOR_ENABLE
Reset
Description
Enable analog temperature sensor. Write other register bits when using temperature sensor. Note: PTEST must written 0xBF make on-chip temperature sensor available IDLE state.
GDO0_INV GDO0_CFG[5:0]
(0x3F)
Invert output, i.e. select active high Default CLK_XOSC/192 (see Table 22on page
0x03: FIFOTHR FIFO Threshold
Field Name
Reserved FIFO_THR[3:0]
Reset
(0000) (0111)
Description
Write (0000) compatibility with possible future extensions threshold FIFO. threshold exceeded when number bytes FIFO equal higher than threshold value. Setting (0000) (0001) (0010) (0011) (0100) (0101) (0110) (0111) (1000) (1001) (1010) (1011) (1100) (1101) (1110) (1111) Bytes FIFO
SWRS039B
Page
CC2550
0x04: SYNC1- Sync Word, High Byte
Field Name
SYNC[15:8]
Reset
(0xD3)
Description
16-bit sync word
0x05: SYNC0 Sync Word, Byte
Field Name
SYNC[7:0]
Reset
(0x91)
Description
16-bit sync word
0x06: PKTLEN Packet Length
Field Name
PACKET_LENGTH
Reset
(0xFF)
Description
Indicates packet length when fixed packet length enabled.
0x08: PKTCTRL0 Packet Automation Control
Field Name
Reserved WHITE_DATA
Reset
Description
Turn data whitening Whitening Whitening Data whitening only used when PKTCTRL0.CC2400_EN=0 (default).
PKT_FORMAT[1:0]
(00)
Format data Setting (00) (01) (10) (11) Packet format Normal mode, FIFO Synchronous serial mode, used backwards compatibility Random mode; sends random data using generator. Used test. Asynchronous serial mode. Data GDO0.
CC2400_EN
Enable CC2400 support. same implementation CC2400. PKTCTRL0.WHITE_DATA must PKTCTRL0.CC2400_EN=1.
CRC_EN
calculation enabled disabled
LENGTH_CONFIG[1:0]
(01)
Configure packet length Setting (00) (01) (10) (11) Packet length configuration Fixed packet length mode. Length configured PKTLEN register Variable packet length mode. Length configured first byte after sync word Infinite packet length mode Reserved
SWRS039B
Page
CC2550
0x0A: CHANNR Channel Number
Field Name
CHAN[7:0]
Reset
(0x00)
Description
8-bit unsigned channel number, which multiplied channel spacing setting added base frequency.
0x0D: FREQ2 Frequency Control Word, High Byte
Field Name
FREQ[23:22] FREQ[21:16]
Reset
(01) (0x1E)
Description
FREQ[23:22] always binary (the FREQ2 register range with 26-27 crystal) FREQ[23:0] base frequency frequency synthesiser increments FXOSC/2
carrier
XOSC FREQ
0x0E: FREQ1 Frequency Control Word, Middle Byte
Field Name
FREQ[15:8]
Reset
(0xC4)
Description
Ref. FREQ2 register
0x0F: FREQ0 Frequency Control Word, Byte
Field Name
FREQ[7:0]
Reset
(0xEC)
Description
Ref. FREQ2 register
0x10: MDMCFG4 Modulator Configuration
Field Name
Reserved DRATE_E[3:0]
Reset
Description
Defined transceiver version exponent user specified symbol rate
(1100)
0x11: MDMCFG3 Modulator Configuration
Field Name
DRATE_M[7:0]
Reset
(0x22)
Description
mantissa user specified symbol rate. symbol rate configured using unsigned, floating-point number with 9-bit mantissa 4-bit exponent. hidden `1'. resulting data rate
RDATA
(256 DRATE DRATE
XOSC
default values give data rate 115.051 kBaud (closest setting 115.2 kBaud), assuming 26.0 crystal.
SWRS039B
Page
CC2550
0x12: MDMCFG2 Modulator Configuration
Field Name
Reserved MOD_FORMAT[2:0]
Reset
Description
(001)
modulation format radio signal Setting (000) (001) (010) (011) (100) (101) (110) (111) Modulation format 2-FSK GFSK
MANCHESTER_EN
Enables Manchester encoding Disable Enable (Only supported fixed packet length mode, i.e. PKTCTRL0.LENGTH_CONFIG=0)
SYNC_MODE[2:0]
(010)
Sync-word mode. Setting (000) (001) (010) (011) (100) (101) (110) (111) Sync-word mode Disable preamble sync word transmission Enable 16-bit sync word transmission Enable 16-bit sync word transmission Repeated sync word transmission Disable preamble sync word transmission Enable 16-bit sync word transmission Enable 16-bit sync word transmission Repeated sync word transmission
SWRS039B
Page
CC2550
0x13: MDMCFG1 Modulator Configuration
Field Name
FEC_EN
Reset
Description
Enable Forward Error Correction (FEC) with interleaving packet payload Disable Enable
NUM_PREAMBLE[2:0]
(010)
Sets minimum number preamble bytes transmitted Setting (000) (001) (010) (011) (100) (101) (110) (111) Number preamble bytes
Reserved CHANSPC_E[1:0] (10)
exponent channel spacing
0x14: MDMCFG0 Modulator Configuration
Field Name
CHANSPC_M[7:0]
Reset
(0xF8)
Description
8-bit mantissa channel spacing (initial assumed). channel spacing multiplied channel number CHAN added base frequency. unsigned format:
CHANNEL
XOSC (256 CHANSPC CHANSPC CHAN
default values give 199.951 channel spacing (the closest setting kHz), assuming 26.0 crystal frequency.
SWRS039B
Page
CC2550
0x15: DEVIATN Modulator Deviation Setting
Field Name
Reserved DEVIATION_E[2:0] Reserved DEVIATION_M[2:0]
Reset
Description
(100)
Deviation exponent
(111)
When modulation enabled: Sets fraction symbol period used phase change. Refer SmartRF® Studio software correct DEVIATN setting when using MSK. When 2-FSK/GFSK modulation enabled: Deviation mantissa, interpreted 4-bit value with implicit resulting deviation given
xosc DEVIATION DEVIATION
default values give ±47.607 deviation, assuming 26.0 crystal frequency.
0x17: MCSM1 Main Radio Control State Machine Configuration
Field Name
Reserved Reserved TXOFF_MODE[1:0]
Reset
Description
Defined transceiver version Select what should happen when packet been sent (TX) Setting (00) (01) (10) (11) Next state after finishing packet transmission IDLE FSTXON Stay (start sending preamble) use, implemented CC2550
(00)
SWRS039B
Page
CC2550
0x18: MCSM0 Main Radio Control State Machine Configuration
Field Name
Reserved FS_AUTOCAL[1:0]
Reset
Description
(00)
Automatically calibrate when going back IDLE Setting (00) (01) (10) (11) When perform automatic calibration Never (manually calibrate using SCAL strobe) When going from IDLE FSTXON) When going from back IDLE Every time when going from IDLE
PO_TIMEOUT
(10)
Programs number times six-bit ripple counter must expire after XOSC stabilized before CHP_RDYn goes low. XOSC (stable) during power-down, PO_TIMEOUT should that regulated digital supply voltage time stabilize before CHP_RDYn goes (PO_TIMEOUT=2 recommended). Typical start-up time voltage regulator XOSC during power-down regulated digital supply voltage sufficient time stabilize while waiting crystal stable, PO_TIMEOUT robust operation recommended PO_TIMEOUT=2. Setting (00) (01) (10) (11) Expire count Timeout after XOSC start Approx. Approx. Approx. Approx.
Exact timeout depends crystal frequency. order reduce start time from SLEEP state, this field preserved powerdown (SLEEP state). Reserved Defined transceiver version
0x22: FREND0 Front Configuration
Field Name
Reserved LODIV_BUF_CURRENT_TX[1:0]
Reset
Description
(01)
Adjusts current buffer (input PA). value this field given SmartRF® Studio software [4].
Reserved PA_POWER[2:0] (000)
Selects power setting. This value index PATABLE. mode, this selects PATABLE index when transmitting `1'. PATABLE index zero used when transmitting `0'.
SWRS039B
Page
CC2550
0x23: FSCAL3 Frequency Synthesizer Calibration
Field Name
FSCAL3[7:6]
Reset
(10)
Description
Frequency synthesizer calibration configuration. value write this register before calibration given SmartRF® Studio software [4]. Disable charge pump calibration stage when Frequency synthesizer calibration result register. Digital vector defining charge pump output current, exponential scale: FSCAL3[3:0]/4 Fast frequency hopping without calibration each done calibrating upfront each frequency saving resulting FSCAL3, FSCAL2 FSCAL1 register values. Between each frequency hop, calibration replaced writing FSCAL3, FSCAL2 FSCAL1 register values corresponding next frequency.
CHP_CURR_CAL_EN[1:0] FSCAL3[3:0]
(10) (1001)
0x24: FSCAL2 Frequency Synthesizer Calibration
Field Name
Reserved VCO_CORE_H_EN FSCAL2[5:0]
Reset
Description
(0x0A)
Choose high Frequency synthesizer calibration result register. current calibration result override value Fast frequency hopping without calibration each done calibrating upfront each frequency saving resulting FSCAL3, FSCAL2 FSCAL1 register values. Between each frequency hop, calibration replaced writing FSCAL3, FSCAL2 FSCAL1 register values corresponding next frequency.
0x25: FSCAL1 Frequency Synthesizer Calibration
Field Name
Reserved FSCAL1[5:0]
Reset
Description
(0x20)
Frequency synthesizer calibration result register. Capacitor array setting coarse tuning. Fast frequency hopping without calibration each done calibrating upfront each frequency saving resulting FSCAL3, FSCAL2 FSCAL1 register values. Between each frequency hop, calibration replaced writing FSCAL3, FSCAL2 FSCAL1 register values corresponding next frequency.
0x26: FSCAL0 Frequency Synthesizer Calibration
Field Name
Reserved Reserved FSCAL0[4:0]
Reset
Description
(00) (0x0D)
Defined transceiver version Frequency synthesizer calibration control. value register field given SmartRF® Studio software [4].
SWRS039B
Page
CC2550
0x29: FSTEST Frequency Synthesizer Calibration Control
Field Name
FSTEST[7:0]
Reset
(0x57)
Description
test only. write this register.
0x2A: PTEST Production Test
Field Name
PTEST[7:0]
Reset
(0x7F)
Description
Writing 0xBF this register makes on-chip temperature sensor available IDLE state. default 0x7F value should then written back before leaving IDLE state. Other this register test only.
0x2C: TEST2 Various Test Settings
Field Name
TEST2[7:0]
Reset
(0x98)
Description
value this register given SmartRF® Studio software [4].
0x2D: TEST1 Various Test Settings
Field Name
TEST1[7:0]
Reset
(0x31)
Description
value this register given SmartRF® Studio software [4].
0x2E: TEST0 Various Test Settings
Field Name
TEST0[7:2] VCO_SEL_CAL_EN TEST0[0]
Reset
(0x02)
Description
value this register given SmartRF® Studio software [4]. Enable selection calibration stage when value this register given SmartRF® Studio software [4].
28.2 Status Register Details 0x30 (0xF0): PARTNUM Chip
Field Name
PARTNUM[7:0]
Reset
(0x82)
Description
Chip part number
0x31 (0xF1): VERSION Chip
Field Name
VERSION[7:0]
Reset
(0x02)
Description
Chip version number
SWRS039B
Page
CC2550
0x35 (0xF5): MARCSTATE Main Radio Control State Machine State
Field Name
Reserved MARC_STATE[4:0]
Reset
Description
Main Radio Control State Value (0x00) (0x01) (0x02) (0x03) (0x04) (0x05) (0x06) (0x07) (0x08) (0x09) (0x0A) (0x0B) (0x0C) (0x0D) (0x0E) (0x0F) (0x10) (0x11) (0x12) (0x13) (0x14) (0x15) (0x16) State name SLEEP IDLE XOFF VCOON_MC REGON_MC MANCAL VCOON REGON STARTCAL BWBOOST FS_LOCK IFADCON ENDCAL FSTXON TX_END TX_UNDERFLOW State (Figure page SLEEP IDLE XOFF MANCAL MANCAL MANCAL FS_WAKEUP FS_WAKEUP CALIBRATE SETTLING SETTLING SETTLING CALIBRATE FSTXON TX_UNDERFLOW
Note: possible read back SLEEP XOFF state numbers because setting will make chip enter IDLE mode from SLEEP XOFF states.
0x38 (0xF8): PKTSTATUS Current GDOx Status Packet Status
Field Name
Reserved Reserved GDO0
Reset
Description
Defined transceiver version
Current GDO0 value. Note: reading gives non-inverted value irrespective what IOCFG0.GDO0_INV programmed recommended check lock reading PKTSTATUS[0] with GDO0_CFG 0x0A.
SWRS039B
Page
CC2550
0x39 (0xF9): VCO_VC_DAC Current Setting from Calibration Module
Field Name
VCO_VC_DAC[7:0]
Reset
Description
Status register test only
0x3A (0xFA): TXBYTES Underflow Number Bytes
Field Name
TXFIFO_UNDERFLOW NUM_TXBYTES
Reset
Description
Number bytes FIFO
SWRS039B
Page
CC2550
Package Description (QLP
dimensions millimetres, angles degrees. NOTE: CC2550 available RoHS lead-free package only.
Figure Package Dimensions Drawing (the actual package pins)
Package type
(4x4) Typ.
0.75 0.85 0.95
0.005 0.025 0.045
0.55 0.65 0.75
3.90 4.00 4.10
3.65 3.75 3.85
3.90
3.65 3.75 3.85
0.45
0.190
0.23 0.28
2.30
4.00 4.10
2.30
0.55 0.65 0.245
0.65
0.35
Table Package Dimensions
SWRS039B
Page
CC2550
29.1 Recommended Layout Package (QLP
Figure Recommended layout package Note: figure illustration only scale. There five diameter holes distributed symmetrically ground under package. also CC2550EM reference design [3]. 29.2 Package Thermal Properties
Thermal Resistance
velocity [m/s] Rth,j-a [K/W] 40.1
Table Thermal Properties Package 29.3 Soldering Information recommendations lead-free reflow IPC/JEDEC J-STD-020D should followed.
SWRS039B
Page
CC2550
29.4 Tray Specification
CC2550 delivered standard shipping trays.
Tray Specification
Package Tray Width 135.9 Tray Height 7.62 Tray Length 322.6 Units Tray
Table Tray Specification 29.5 Carrier Tape Reel Specification Carrier tape reel accordance with Specification 481.
Tape Reel Specification
Package Tape Width Component Pitch Hole Pitch Reel Diameter inches Units Reel 2500
Table Carrier Tape Reel Specification
Ordering Information
Part Number
CC2550RTK CC2550RTKR CC2500-CC2550DK CC2550EMK
Description
Minimum Order Quantity (MOQ)
(tray) 2500 (tape reel)
CC2550 QLP16 RoHS Pb-free 490/tray CC2550 QLP16 RoHS Pb-free 2500/T&R CC2500_CC2550 Development CC2500 Evaluation Module
Table Ordering Information
References
CC2550 Errata Notes (swrz011.pdf) AN032 Regulations (swra060.pdf) CC2550EM Reference Design (swrr015.zip) SmartRF® Studio (swrc046.zip) CC1100 CC2500 Examples Libraries (swrc021.zip) CC1100/CC1150DK CC2500/CC2550DK Development Examples Libraries User Manual (swru109.pdf) CC25XX Folded Dipole Reference Design (swrc065.zip) DN004 Folded Dipole Antenna CCC25xx (swra118.pdf) CC2500 Data Sheet (cc2500.pdf)
SWRS039B
Page
CC2550
General Information
32.1 Document History
Revision
SWRS039B
Date
2007-09-30
Description/Changes
kbps replaced kBaud throughout document. Some sections been re-written easier read without having info added. Absolute maximum supply voltage rating increased from changed 2-FSK throughout document. Updates Abbreviation table. Updates Electrical Specifications section. Added performance. Added info about latency serial mode. Added info about default values after reset versus optimum register settings Configuration Software section. Changes Interface Timing Requirements. Info added about tsp,pd following figures have been changed: Configuration Registers Write Read Operations, SRES Command Strobe, Register Access Types. Register Access section, address range changed. Changes PATABLE Access section. Packet Format section, preamble pattern changed 10101010 info about related turning transmitter infinite packet length mode added. Added info about initial value sequence Data Whitening section. Added info about FIFO underflow state Packet Handling Transmit Mode section. Added section Packet Handling Firmware. Removed references voltage regulator relation with CHP_RDYn signal, this signal only related crystal. Removed references voltage regulator figures: Power-On Reset Power-On Reset with SRES. Changes line Power-On Reset with SRES figure. Added info three automatic calibration options. Output Power Programming section been changed. Only PATABLE entry used 2-FSK/GFSK/MSK PATABLE entries used OOK. Added info about PATABLE when entering SLEEP mode. PA_POWER PATABLE figure. Added section Layout Recommendations. section General Purpose Test Output Control Pins: Added info pins SLEEP state. Asynchronous transparent mode called asynchronous serial mode throughout document. Removed comments about having coding synchronous serial mode. Added info that Manchester encoding cannot used asynchronous serial mode. Changed field name and/or description following registers: MCSM0, FSCAL3, FSCAL2, FSCAL1 TEST0. Added references. Added figures table interface timing requirements. Added information about read. Updates text included figure section arbitrary length configuration. Added information that frequencies frequency integer number) should used spurious signals these frequencies Updates text included figures section power-on start-up sequence. Added information about check lock section VCO. Better explanation some signals table signal selection. Added section wideband modulation using spread spectrum under section system considerations guidelines. Added more detailed information PO_TIMEOUT register MCSM0. Changes ordering information. Updated TEST1 register default value. 26-27 crystal range. Added matching information. Added information about using reference signal instead crystal. First preliminary data sheet release.
SWRS039A
2006-06-28
2005-06-27 2005-01-24
Table Document History
SWRS039B
Page
CC2550
32.2 Product Status Definitions
Data Sheet Identification
Advance Information
Product Status
Planned Under Development Engineering Samples Pre-Production Prototypes
Definition
This data sheet contains design specifications product development. Specifications change manner without notice. This data sheet contains preliminary data, supplementary data will published later date. Chipcon reserves right make changes time without notice order improve design supply best possible product. product fully qualified this point. This data sheet contains final specifications. Chipcon reserves right make changes time without notice order improve design supply best possible product. This data sheet contains specifications product that been discontinued Chipcon. data sheet printed reference information only.
Preliminary
Identification Noted
Full Production
Obsolete
Production
Table Product Status Definitions
SWRS039B
Page
CC2550
Address Information
Texas Instruments Norway N-0349 Oslo NORWAY Tel: Fax: site: http://www.ti.com/lpw
Worldwide Technical Support
support.ti.com support.ti.com/sc/knowledgebase
Internet
Semiconductor Product Information Center Home Page: Semiconductor KnowledgeBase Home Page:
Product Information Centers
Americas Phone: Fax: Internet/Email: +1(972) 644-5580 +1(972) 927-6377
Europe, Middle East Africa Phone: Belgium (English) Finland (English) +358 25173948 France Germany 8161 Israel (English) 0107 Italy Netherlands (English) Russia Spain Sweden (English) 8587 United Kingdom 1604 Fax: 8161 2045 Internet: support.ti.com/sc/pic/euro.htm Japan Internet/Email International Domestic International Domestic +81-3-3344-5317 0120-81-0036 support.ti.com/sc/pic/japan.htm www.tij.co.jp/pic
SWRS039B
Page
CC2550
Asia Phone International Domestic Australia China Hong Kong India Indonesia Korea Malaysia Zealand Philippines Singapore Taiwan Thailand +886-2-23786800 Toll-Free Number 1-800-999-084 800-820-8682 800-96-5941 +91-80-51381665 (Toll) 001-803-8861-1006 080-551-2804 1-800-80-3973 0800-446-934 1-800-765-7404 800-886-1028 0800-006800 001-800-886-0010 +886-2-2378-6808 tiasia@ti.com ti-china@ti.com support.ti.com/sc/pic/asia.htm
Email Internet
SWRS039B
Page
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Dec-2009
TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing VQFN
Reel Reel Diameter Width (mm) (mm) (mm) 330.0 12.4 4.25
(mm) 4.25
(mm)
(mm)
Pin1 (mm) Quadrant 12.0
CC2550RSTR
2500
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Dec-2009
*All dimensions nominal
Device CC2550RSTR
Package Type VQFN
Package Drawing
Pins
2500
Length (mm) 378.0
Width (mm) 70.0
Height (mm) 346.0
Pack Materials-Page
IMPORTANT NOTICE
Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Information third parties subject additional restrictions. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. products authorized safety-critical applications (such life support) where failure product would reasonably expected cause severe personal injury death, unless officers parties have executed agreement specifically governing such use. Buyers represent that they have necessary expertise safety regulatory ramifications their applications, acknowledge agree that they solely responsible legal, regulatory safety-related requirements concerning their products products such safety-critical applications, notwithstanding applications-related information support that provided Further, Buyers must fully indemnify representatives against damages arising products such safety-critical applications. products neither designed intended military/aerospace applications environments unless products specifically designated military-grade "enhanced plastic." Only products designated military-grade meet military specifications. Buyers acknowledge agree that such products which designated military-grade solely Buyer's risk, that they solely responsible compliance with legal regulatory requirements connection with such use. products neither designed intended automotive applications environments unless specific products designated compliant with ISO/TS 16949 requirements. Buyers acknowledge agree that, they non-designated products automotive applications, will responsible failure meet such requirements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters DLP® Products Clocks Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF ZigBee® Solutions amplifier.ti.com dataconverter.ti.com www.dlp.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office 655303, Dallas, Texas 75265 Copyright 2009, Texas Instruments Incorporated
Other recent searches
USB20H04 - USB20H04 USB20H04 Datasheet
OM5242NM - OM5242NM OM5242NM Datasheet
OM5244NM - OM5244NM OM5244NM Datasheet
OM5246NM - OM5246NM OM5246NM Datasheet
OM5248NM - OM5248NM OM5248NM Datasheet
OM5243NM - OM5243NM OM5243NM Datasheet
OM5245NM - OM5245NM OM5245NM Datasheet
OM5247NM - OM5247NM OM5247NM Datasheet
FYLF-1870UW1C - FYLF-1870UW1C FYLF-1870UW1C Datasheet
DG300A - DG300A DG300A Datasheet
DG301A - DG301A DG301A Datasheet
DG303A - DG303A DG303A Datasheet
CO-431 - CO-431 CO-431 Datasheet
CO-451 - CO-451 CO-451 Datasheet
AS5040 - AS5040 AS5040 Datasheet
AS5140 - AS5140 AS5140 Datasheet
APTGF100DA120T1G - APTGF100DA120T1G APTGF100DA120T1G Datasheet
Privacy Policy | Disclaimer
© 2013 Datasheets.org.uk