CC2500
|
|
|
Top Searches for this datasheet
phase shifter ICs in SMD package - phase shifter ICs in SMD package
CC2500 PDF - CC2500 PDF
cc2500 microcontroller interfacing - cc2500 microcontroller interfacing
CC2500* - CC2500*
2 SC 9014 - 2 SC 9014
CC2500 - CC2500
CC2500
CC2500
Single Chip Cost Power Transceiver
2400-2483.5 ISM/SRD band systems Consumer Electronics Wireless game controllers Wireless audio Wireless keyboard mouse
Product Description
CC2500 cost true single chip transceiver designed very power wireless applications. circuit intended (Industrial, Scientific Medical) (Short Range Device) frequency band 2400-2483.5 MHz. transceiver integrated with highly configurable baseband modem. modem supports various modulation formats configurable data rate kbps. communication range increased enabling Forward Error Correction option, which integrated modem. microcontroller additional passive components.
CC2500 part Chipcon's generation
technology platform based 0.18 CMOS technology.
CC2500 provides extensive hardware support
packet handling, data buffering, burst transmissions, clear channel assessment, link quality indication wake-on-radio. main operating parameters 64byte transmit/receive FIFOs CC2500 controlled interface. typical system, CC2500 will used together with This data sheet contains preliminary data, supplementary data will published later date. Chipcon reserves right make changes time without notice order improve design supply best possible product. product fully qualified this point.
Features
Small size (QLP package, pins) True single chip transceiver Frequency range: 2400-2483.5 High sensitivity (-101 kbps, packet error rate) Programmable data rate kbps current consumption (13.3 kbps, input above sensitivity limit) Programmable output power Excellent receiver selectivity blocking performance Very external components: Completely on-chip frequency synthesizer, external filters switch needed Programmable baseband modem Ideal multi-channel operation Configurable packet handling hardware Suitable frequency hopping systems fast settling frequency synthesizer Optional Forward Error Correction with interleaving Separate 64-byte data FIFOs Efficient interface: registers programmed with "burst" transfer Digital RSSI output
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Features (continued from front page)
Suited systems compliant with class (Europe), CFR47 Part (US), ARIB STDT66 (Japan) Wake-on-radio functionality automatic low-power polling Many powerful digital features allow high-performance system made using inexpensive microcontroller Integrated analog temperature sensor Lead-free "green" package Flexible support packet oriented systems: chip support sync word detection, address check, flexible packet length automatic handling. Programmable channel filter bandwidth FSK, GFSK supported supported Automatic Frequency Compensation (AFC) used align frequency synthesizer received centre frequency Optional automatic whitening dewhitening data Support asynchronous transparent receive/transmit mode backwards compatibility with existing radio communication protocols Programmable Carrier Sense indicator Programmable Preamble Quality Indicator (PQI) detecting preambles improved protection against sync word detection random noise Support automatic Clear Channel Assessment (CCA) before transmitting (for listen-before-talk systems) Support per-package Link Quality Indication
Abbreviations
Abbreviations used this data sheet described below.
ARIB FIFO FHSS GFSK Adjacent Channel Power Analog Digital Converter Automatic Frequency Offset Compensation Automatic Gain Control Automatic Meter Reading Association Radio Industries Businesses Error Rate Bandwidth-Time product Clear Channel Assessment Code Federal Regulations Cyclic Redundancy Check Carrier Sense Direct Current Equivalent Series Resistance Federal Communications Commission Forward Error Correction First-In-First-Out Frequency Hopping Spread Spectrum Frequency Shift Keying Gaussian shaped Frequency Shift Keying Intermediate Frequency In-Phase/Quadrature Industrial, Scientific Medical Listen Before Transmit Inductor-Capacitor Noise Amplifier Local Oscillator Link Quality Indicator Microcontroller Unit RCOSC QPSK RSSI WLAN XOSC XTAL Minimum Shift Keying Applicable Keying Power Amplifier Printed Circuit Board Power Down Packet Error Rate Phase Locked Loop Power-on Reset Preamble Quality Indicator Preamble Quality Threshold Oscillator Quadrature Phase Shift Keying Quad Leadless Package Radio Frequency Received Signal Strength Indicator Receive, Receive Mode Surface Mount Device Signal Noise Ratio Serial Peripheral Interface Short Range Device Transmit/Receive Transmit, Transmit Mode Voltage Controlled Oscillator Wireless Local Area Networks Wake Radio, power polling Crystal Oscillator Crystal
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Table Contents
APPLICATIONS PRODUCT DESCRIPTION.1 FEATURES FEATURES (CONTINUED FROM FRONT PAGE).2 ABBREVIATIONS.2 TABLE CONTENTS ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS GENERAL CHARACTERISTICS.6 ELECTRICAL SPECIFICATIONS CURRENT CONSUMPTION RECEIVE SECTION TRANSMIT SECTION CRYSTAL OSCILLATOR POWER OSCILLATOR FREQUENCY SYNTHESIZER CHARACTERISTICS ANALOG TEMPERATURE SENSOR CHARACTERISTICS POWER-ON RESET CONFIGURATION.13 CIRCUIT DESCRIPTION APPLICATION CIRCUIT CONFIGURATION OVERVIEW CONFIGURATION SOFTWARE.18 4-WIRE SERIAL CONFIGURATION DATA INTERFACE 10.1 CHIP STATUS BYTE 10.2 REGISTER ACCESS 10.3 READ 10.4 COMMAND STROBES 10.5 FIFO ACCESS 10.6 PATABLE ACCESS MICROCONTROLLER INTERFACE CONFIGURATION 11.1 CONFIGURATION INTERFACE 11.2 GENERAL CONTROL STATUS PINS 11.3 OPTIONAL RADIO CONTROL FEATURE DATA RATE PROGRAMMING.24 RECEIVER CHANNEL FILTER BANDWIDTH DEMODULATOR, SYMBOL SYNCHRONIZER DATA DECISION.25 14.1 FREQUENCY OFFSET COMPENSATION.25 14.2 SYNCHRONIZATION 14.3 BYTE SYNCHRONIZATION PACKET HANDLING HARDWARE SUPPORT 15.1 DATA WHITENING 15.2 PACKET FORMAT 15.3 PACKET FILTERING RECEIVE MODE 15.4 CHECK 15.5 PACKET HANDLING TRANSMIT MODE 15.6 PACKET HANDLING RECEIVE MODE MODULATION FORMATS 16.1 FREQUENCY SHIFT KEYING 16.2 MINIMUM SHIFT KEYING.30
PRELIMINARY Data Sheet (Rev.1.2) SWRS040a Page
CC2500
16.3 17.1 17.2 17.3 17.4 17.5 17.6 18.1 18.2 19.1 19.2 19.3 19.4 19.5 19.6 19.7 22.1 26.1 29.1 29.2 30.1 30.2 30.3 30.4 30.5 30.6 30.7 30.8 30.9 30.10 31.1 31.2 31.3 32.1 32.2 32.3 32.4 32.5 AMPLITUDE MODULATION RECEIVED SIGNAL QUALIFIERS LINK QUALITY INFORMATION SYNC WORD QUALIFIER PREAMBLE QUALITY THRESHOLD (PQT) RSSI.31 CARRIER SENSE (CS).32 CLEAR CHANNEL ASSESSMENT (CCA) LINK QUALITY INDICATOR (LQI) FORWARD ERROR CORRECTION WITH INTERLEAVING FORWARD ERROR CORRECTION (FEC).34 INTERLEAVING RADIO CONTROL.35 POWER-ON START-UP SEQUENCE CRYSTAL CONTROL VOLTAGE REGULATOR CONTROL.37 ACTIVE MODES WAKE RADIO (WOR).37 TIMING TERMINATION TIMER DATA FIFO FREQUENCY PROGRAMMING.40 SELF-CALIBRATION VOLTAGE REGULATORS OUTPUT POWER PROGRAMMING SELECTIVITY.43 CRYSTAL OSCILLATOR.45 REFERENCE SIGNAL EXTERNAL MATCH GENERAL PURPOSE TEST OUTPUT CONTROL PINS ASYNCHRONOUS SYNCHRONOUS SERIAL OPERATION ASYNCHRONOUS OPERATION.48 SYNCHRONOUS SERIAL OPERATION SYSTEM CONSIDERATIONS GUIDELINES REGULATIONS FREQUENCY HOPPING MULTI-CHANNEL SYSTEMS WIDEBAND MODULATION USING SPREAD SPECTRUM DATA BURST TRANSMISSIONS.49 CONTINUOUS TRANSMISSIONS CRYSTAL DRIFT COMPENSATION SPECTRUM EFFICIENT MODULATION COST SYSTEMS BATTERY OPERATED SYSTEMS INCREASING OUTPUT POWER CONFIGURATION REGISTERS.51 CONFIGURATION REGISTER DETAILS REGISTERS WITH PRESERVED VALUES SLEEP STATE CONFIGURATION REGISTER DETAILS REGISTERS THAT LOSE PROGRAMMING SLEEP STATE STATUS REGISTER DETAILS PACKAGE DESCRIPTION (QLP 20).78 RECOMMENDED LAYOUT PACKAGE (QLP PACKAGE THERMAL PROPERTIES SOLDERING INFORMATION.79 TRAY SPECIFICATION CARRIER TAPE REEL SPECIFICATION
PRELIMINARY Data Sheet (Rev.1.2) SWRS040a Page
CC2500
34.1 34.2 ORDERING INFORMATION.80 GENERAL INFORMATION.80 DOCUMENT HISTORY PRODUCT STATUS DEFINITIONS ADDRESS INFORMATION WORLDWIDE TECHNICAL SUPPORT.82 IMPORTANT NOTICE.84
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Absolute Maximum Ratings
Under circumstances must absolute maximum ratings given Table violated. Stress exceeding more limiting values cause permanent damage device.
Caution! sensitive device. Precaution should used when handling device order prevent permanent damage. Parameter Supply voltage Voltage digital Voltage pins RF_P, RF_N DCOUPL Voltage ramp-up rate Input level Storage temperature range Solder reflow temperature -0.3 -0.3 -0.3 VDD+0.3, <500 Units kV/µs According IPC/JEDEC J-STD-020C According JEDEC method A114, Human Body Model Condition supply pins must have same voltage
Table Absolute maximum ratings
Operating Conditions
Unit supply pins must have same voltage Condition
operating conditions CC2500 listed Table below.
Parameter Operating temperature Operating supply voltage
Table Operating conditions
General Characteristics
2400 2483.5 Unit kbps kbps kbps GFSK (Shaped) (also known differential offset QPSK) Optional Manchester encoding (halves data rate). Condition/Note
Parameter Frequency range Data rate
Table General characteristics
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Electrical Specifications
Current Consumption
25°C, nothing else stated. measurement results obtained using CC2500EM reference design. Parameter Current consumption power down modes Current consumption Unit Condition Voltage regulator digital part off, register values retained (SLEEP state) Voltage regulator digital part off, register values retained, lowpower oscillator running (SLEEP state with enabled) Voltage regulator digital part off, register values retained, XOSC running (SLEEP state with MCSM0.OSC_FORCE_ON set) Voltage regulator digital part other modules power down (XOFF state) Automatic polling once each second, using low-power oscillator, with filter bandwidth kbps data rate, calibration every wakeup. Average current with signal channel below carrier sense level. Same above, with signal channel above carrier sense level, timeout, preamble/sync word found. Automatic polling every second, using low-power oscillator, with filter bandwidth kbps data rate, calibration every wakeup. Average current with signal channel below carrier sense level. Same above, with signal channel above carrier sense level, timeout, preamble/sync word found. Only voltage regulator digital part crystal oscillator running (IDLE state) Only frequency synthesizer running (after going from IDLE until reaching states, frequency calibration states) Receive mode, kbps, input sensitivity limit, MDMCFG2.DEM_DCFILT_OFF Receive mode, kbps, input above sensitivity limit, MDMCFG2.DEM_DCFILT_OFF Receive mode, kbps, input sensitivity limit, MDMCFG2.DEM_DCFILT_OFF Receive mode, kbps, input above sensitivity limit, MDMCFG2.DEM_DCFILT_OFF Receive mode, kbps, input sensitivity limit, MDMCFG2.DEM_DCFILT_OFF Receive mode, kbps, input above sensitivity limit, MDMCFG2.DEM_DCFILT_OFF Receive mode, kbps current optimized, input sensitivity limit, MDMCFG2.DEM_DCFILT_OFF Receive mode, kbps current optimized, input above sensitivity limit, MDMCFG2.DEM_DCFILT_OFF Receive mode, kbps, input sensitivity limit, MDMCFG2.DEM_DCFILT_OFF Receive mode, kbps, input above sensitivity limit, MDMCFG2.DEM_DCFILT_OFF
Current consumption, states 15.3 12.8 15.4 12.9 18.8 15.7 16.6 13.3 19.6 17.0
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Current consumption, states 11.1 15.1 21.2 Transmit mode, output power Transmit mode, output power Transmit mode, output power
Table Current consumption Receive Section
25°C, nothing else stated. measurement results obtained using CC2500EM reference design. Parameter Digital channel filter bandwidth Unit Condition/Note User programmable. bandwidth limits proportional crystal frequency (given values assume 26.0 crystal).
kbps data rate, current optimized, MDMCFG2.DEM_DCFILT_OFF (FSK, packet error rate, bytes packet length, digital channel filter bandwidth) Receiver sensitivity -104 sensitivity improved typically -106 setting MDMCFG2.DEM_DCFILT_OFF typical current consumption this case 17.0 sensitivity llimit. Desired channel above sensitivity limit. channel spacing Desired channel above sensitivity limit. channel spacing Figure plot selectivity versus frequency offset kbps data rate, current optimized, MDMCFG2.DEM_DCFILT_OFF (FSK, packet error rate, bytes packet length, digital channel filter bandwidth) Receiver sensitivity sensitivity improved typically -101 setting MDMCFG2.DEM_DCFILT_OFF typical current consumption this case 17.3 sensitivity llimit. Desired channel above sensitivity limit. channel spacing Desired channel above sensitivity limit. channel spacing Figure plot selectivity versus frequency offset kbps data rate, MDMCFG2.DEM_DCFILT_OFF (MSK, packet error rate, bytes packet length, digital channel filter bandwidth) Receiver sensitivity Saturation Adjacent channel rejection Alternate channel rejection Desired channel above sensitivity limit. channel spacing Desired channel above sensitivity limit. channel spacing Figure plot selectivity versus frequency offset
Saturation Adjacent channel rejection Alternate channel rejection
Saturation Adjacent channel rejection Alternate channel rejection
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Parameter Unit Condition/Note kbps data rate, current optimized, MDMCFG2.DEM_DCFILT_OFF (MSK, packet error rate, bytes packet length, digital channel filter bandwidth) Receiver sensitivity Saturation Adjacent channel rejection Alternate channel rejection Desired channel above sensitivity limit. channel spacing Desired channel above sensitivity limit. channel spacing Figure plot selectivity versus frequency offset kbps data rate, MDMCFG2.DEM_DCFILT_OFF (MSK, packet error rate, bytes packet length, digital channel filter bandwidth) Receiver sensitivity Saturation Adjacent channel rejection Alternate channel rejection General Blocking offset Blocking offset Blocking offset Spurious emissions Above Desired channel dBm. Compliant with ETSI class receiver requirements. Desired channel dBm. Compliant with ETSI class receiver requirements. Desired channel dBm. Compliant with ETSI class receiver requirements. Desired channel above sensitivity limit. channel spacing Desired channel above sensitivity limit. channel spacing Figure plot selectivity versus frequency offset
Table receive parameters
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Transmit Section
25°C, nothing else stated. measurement results obtained using CC2500EM reference design. Parameter Differential load impedance Unit Condition/Note Differential impedance seen from RF-port (RF_P RF_N) towards antenna. Follow CC2500EM reference design available from Chipcon websites. Output power programmable available across entire frequency band. Delivered single-ended load CC2500EM reference design matching network. Output power, lowest setting Output power programmable available across entire frequency band. Delivered single-ended load CC2500EM reference design matching network. Spurious emissions 47-74, 87.5-118, 174230, 470-862 1800-1900 Otherwise above Restricted band Europe Restricted bands
Output power, highest setting
Table transmit parameters Crystal Oscillator
25°C, nothing else stated. Parameter Crystal frequency Tolerance Unit This total tolerance including initial tolerance, crystal loading, aging temperature dependence. acceptable crystal tolerance depends frequency channel spacing bandwidth. Start-up time Measured CC2500EM reference design. Condition/Note
Table Crystal oscillator parameters
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Power Oscillator
25°C, nothing else stated. measurement results obtained using CC2500EM reference design. Parameter Calibrated frequency Frequency accuracy after calibration 34.6 34.7 +0.3 Unit Condition/Note Calibrated Oscillator frequency XTAL frequency divided oscillator contains error calibration routine that statistically occurs 17.3% calibrations performed. given maximum accuracy figures account calibration error. Refer also CC2500 Errata Note. Frequency drift when temperature changes after calibration Frequency drift when supply voltage changes after calibration When Oscillator enabled, calibration continuously done background long crystal oscillator running.
Temperature coefficient Supply voltage coefficient Initial calibration time
+0.4
Table oscillator parameters Frequency Synthesizer Characteristics
25°C, nothing else stated. measurement results obtained using CC2500EM reference design. Parameter Programmed frequency resolution Synthesizer frequency tolerance carrier phase noise FXOSC/ Unit Condition/Note 26-27 crystal. Given crystal used. Required accuracy (including temperature aging) depends frequency band channel bandwidth spacing. offset from carrier offset from carrier offset from carrier offset from carrier offset from carrier offset from carrier offset from carrier offset from carrier Time from leaving IDLE state until arriving FSTXON state, when performing calibration. Crystal oscillator running. Settling time frequency step from Settling time frequency step from Calibration initiated manually, automatically before entering after leaving RX/TX. Min/typ/max time 27/26/26 crystal frequency.
-100 -108 -116 -127
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
turn-on time
88.4
RX/TX settling time TX/RX settling time calibration time 0.69
21.5 18739 0.72 0.72
XOSC cycles
Table Frequency synthesizer parameters
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Analog Temperature Sensor characteristics analog temperature sensor listed Table below. Note that necessary write 0xBF PTEST register analog temperature sensor IDLE state.
Parameter Output voltage -40°C Output voltage Output voltage +40°C Output voltage +80°C Temperature coefficient Error calculated temperature, calibrated
0.660 0.755 0.859 0.958 2.54
Unit mV/°C
Condition/Note
Fitted from -20°C +80°C From -20°C +80°C when using 2.54 after 1-point calibration room temperature
indicated minimum maximum error with 1point calibration based simulated values typical process parameters
Current consumption increase when enabled
Table Analog temperature sensor parameters Characteristics
25°C nothing else stated. Digital Inputs/Outputs Logic input voltage Logic input voltage Logic output voltage Logic output voltage Logic input current Logic input current VDD-0.7 VDD-0.3 Unit output current output current Input equals Input equals Condition
Table characteristics Power-On Reset
When power supply complies with requirements Table below, proper Power-OnReset functionality guaranteed. Otherwise, chip should assumed have unknown state until transmitting SRES strobe over interface. Section 19.1 page further details.
Parameter Power ramp-up time Power time Unit Condition/Note From until reaching Minimum time between power-on power-off.
Table Power-on reset requirements
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Configuration
DGUARD
RBIAS
SCLK (GDO1) GDO2 DVDD DCOUPL GDO0 (ATEST) XOSC_Q1 AVDD XOSC_Q2 AVDD AVDD RF_N RF_P AVDD Exposed attach
Figure Pinout view Note: exposed attach must connected solid ground plane this main ground connection chip.
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
name SCLK (GDO1) type Digital Input Digital Output Description Serial configuration interface, clock input Serial configuration interface, data output. Optional general output when high GDO2 Digital Output Digital output general use: Test signals FIFO status signals Clear Channel Indicator Clock output, down-divided from XOSC Serial output data DVDD DCOUPL Power (Digital) Power (Digital) digital power supply digital I/O's digital core voltage regulator digital power supply output decoupling. NOTE: This intended with CC2500 only. used provide supply voltage other devices. GDO0 (ATEST) Digital Digital output general use: Test signals FIFO status signals Clear Channel Indicator Clock output, down-divided from XOSC Serial output data Serial input data Also used analog test prototype/production testing XOSC_Q1 AVDD XOSC_Q2 AVDD RF_P Digital Input Analog Power (Analog) Analog Power (Analog) Serial configuration interface, chip select Crystal oscillator external clock input analog power supply connection Crystal oscillator analog power supply connection Positive input signal receive mode Positive output signal from transmit mode RF_N Negative input signal receive mode Negative output signal from transmit mode AVDD AVDD RBIAS DGUARD Power (Analog) Power (Analog) Ground (Analog) Analog Power (Digital) Ground (Digital) Digital Input analog power supply connection analog power supply connection Analog ground connection External bias resistor reference current Power supply connection digital noise isolation Ground connection digital noise isolation Serial configuration interface, data input
Table Pinout overview
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Circuit Description
RADIO CONTROL DEMODULATOR
RXFIFO
RF_P RF_N
DIGITAL INTERFACE
INTERLEAVER
PACKET HANDLER
SCLK (GDO1) GDO0 (ATEST) GDO2
FREQ SYNTH
BIAS
XOSC
RBIAS
XOSC_Q1
XOSC_Q2
Figure CC2500 simplified block diagram simplified block diagram CC2500 shown Figure phase shifter generating signals down-conversion mixers receive mode. crystal connected XOSC_Q1 XOSC_Q2. crystal oscillator generates reference frequency synthesizer, well clocks digital part. 4-wire serial interface used configuration data buffer access. digital baseband includes support channel configuration, packet handling data buffering.
CC2500
features low-IF receiver. received signal amplified lownoise amplifier (LNA) down-converted quadrature intermediate frequency (IF). signals digitised ADCs. Automatic gain control (AGC), fine channel filtering, demodulation bit/packet synchronization performed digitally.
transmitter part CC2500 based direct synthesis frequency. frequency synthesizer includes completely on-chip degrees
Application Circuit
Balun matching C122, C132, L121 L131 form balun that converts differential signal CC2500 single-ended signal. C121 C131 needed blocking. Together with appropriate network, balun components also transform impedance match antenna cable). Component values balun network
SWRS040a Page
Only external components required using CC2500. recommended application circuit shown Figure external components described Table typical values given Table Bias resistor bias resistor R171 used accurate bias current.
PRELIMINARY Data Sheet (Rev.1.2)
TXFIFO
MODULATOR
CC2500
easily found using SmartRF® Studio software. Suggested values listed Table balun filter component values their placement important keep performance optimized. highly recommended follow CC2500EM reference design. Crystal crystal oscillator uses external crystal with loading capacitors (C81 C101). Section page details. Power supply decoupling power supply must properly decoupled close supply pins. Note that decoupling capacitors shown application circuit. placement size decoupling capacitors very important achieve optimum performance. CC2500EM reference design should followed closely.
Component C81/C101 C121/C131 C122/C132 C123/C124 L121/L131 L122 R171 XTAL
Description Decoupling capacitor on-chip voltage regulator digital part Crystal loading capacitors, Section page details balun blocking capacitors balun/matching capacitors filter/matching capacitors balun/matching inductors (inexpensive multi-layer type) filter inductor (inexpensive multi-layer type) Resistor internal bias current reference 26-27 crystal, Section page details
Table Overview external components (excluding supply decoupling capacitors)
1.8V-3.6V power supply
DGUARD RBIAS
R171
SCLK
SCLK (GDO1) GDO2 DVDD DCOUPL GDO0
AVDD AVDD
Antenna Ohm) L131 C131 C121 L121 C122 C132 L122 C123
Digital Inteface
(GDO1) GDO2 (optional)
CC2500
ATTACH PAD: XOSC_Q2 XOSC_Q1 AVDD
RF_N RF_P AVDD
C124
GDO0 (optional)
XTAL C101
Alternative: Folded dipole antenna external components needed)
Figure Typical application evaluation circuit (excluding supply decoupling capacitors)
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Component Value Manufacturer
C101 C121 C122 C123 C124 C131 C132 L121 L122 L131 R171 XTAL
±10%, 0402 ±5%, 0402 ±5%, 0402 ±5%, 0402 ±0.25 0402 ±0.25 0402 ±0.25 0402 ±5%, 0402 ±0.25 0402 ±0.3 0402 monolithic ±0.3 0402 monolithic ±0.3 0402 monolithic ±1%, 0402 26.0 surface mount crystal
Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata GRM15 series Murata LQG15 series Murata LQG15 series Murata LQG15 series RK73 series NDK, AT-41CD2
Table Bill Materials application circuit CC2500EM reference design shown Figure LQG15 series inductors from Murata have been used. Measurements have been performed with multi-layer inductors from other manufacturers (e.g. measurement results were same when using Murata part. Gerber files CC2500EM reference design available from Chipcon websites.
Figure CC2500EM reference design
Configuration Overview
Packet radio hardware support Forward Error Correction with interleaving Data Whitening Wake-On-Radio (WOR)
CC2500 configured achieve optimum performance many different applications. Configuration done using interface. following parameters programmed:
Power-down power mode Crystal oscillator power-up power-down Receive transmit mode channel selection Data rate Modulation format channel filter bandwidth output power Data buffering with separate 64-byte receive transmit FIFOs
Details each configuration register found Section starting page Figure shows simplified state diagram that explains main CC2500 states, together with typical usage current consumption. detailed information controlling CC2500 state machine, complete state diagram, Section starting page
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Lowest power mode. Most register values retained. Typ. current consumption 400nA, 900nA when wake-on-radio (WOR) enabled.
Sleep
SIDLE SPWD wake-on-radio (WOR)
Default state when radio receiving transmitting. Typ. current consumption: 1.5mA.
CSn=0
Idle
SXOFF
SCAL Used calibrating frequency synthesizer upfront (entering CSn=0 receive transmit mode Manual freq. then done quicker). synth. calibration SFSTXON wake-on-radio (WOR) Transitional state. Typ. current consumption: 7.4mA.
Crystal oscillator
register values retained. Typ. current consumption; 0.16mA.
Frequency synthesizer ready start transmitting. Transmission starts very quickly after receiving command strobe.Typ. current consumption: 7.4mA.
SFSTXON
Frequency synthesizer startup, optional calibration, settling
Frequency synthesizer turned optionally calibrated, then settles correct frequency. Transitional state. Typ. current consumption: 7.4mA.
Frequency synthesizer
wake-on-radio (WOR) TXOFF_MODE=01 SFSTXON RXOFF_MODE=01
Typ. current consumption: 11.1mA -12dBm output, 15.1mA -6dBm output, 21.2mA 0dBm output.
Transmit mode
RXOFF_MODE=10 TXOFF_MODE=11
Receive mode
Typ. current consumption: from 13.3mA (strong input signal) 16.6mA (weak input signal).
TXOFF_MODE=00
RXOFF_MODE=00
FIFO-based modes, transmission turned this state entered FIFO becomes empty middle packet. Typ. current consumption: 1.5mA.
Optional transitional state. Typ. current consumption: 7.4mA. FIFO underflow Optional freq. synth. calibration FIFO overflow
FIFO-based modes, reception turned this state entered FIFO overflows. Typ. current consumption: 1.5mA.
SFTX
SFRX
Idle
Figure Simplified state diagram, with typical usage current consumption kbps data rate MDMCFG2.DEM_DCFILT_OFF (current optimized)
Configuration Software
optimum register settings, evaluating performance functionality. screenshot SmartRF® Studio user interface CC2500 shown Figure
CC2500 configured using SmartRF®
Studio software, available download from http://www.ti.com. SmartRF® Studio software highly recommended obtaining
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Figure SmartRF® Studio user interface
4-wire Serial Configuration Data Interface
CC2500 configured simple 4-wire SPIcompatible interface (SI, SCLK CSn) where CC2500 slave. This interface also used read write buffered data. address data transfer interface done most significant first.
transactions interface start with header byte containing read/write bit, burst access 6-bit address. During address data transfer, (Chip Select, active low) must kept low. goes high during access, transfer will cancelled. timing address data transfer interface shown Figure with reference Table When goes low, must wait until
CC2500 goes before starting
transfer header byte. This indicates that voltage regulator stabilized crystal running. Unless chip SLEEP XOFF states SRES command strobe issued, will always immediately after taking low. Figure gives brief overview different register access types possible.
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
SCLK: CSn: Write register:
Hi-Z
Hi-Z
Read from register:
Hi-Z
Hi-Z
Figure Configuration register write read operations "burst" bit)
Parameter
Description
Units
fSCLK
SCLK frequency
delay inserted between address byte data byte (single access), between address data, between each data byte (burst access).
SCLK frequency, single access
delay between address data byte
Single access Burst access
SCLK frequency, burst access
delay between address data byte, between data bytes
tsp,pd trise tfall
positive edge SCLK, power-down mode positive edge SCLK, active mode
Clock high Clock Clock rise time Clock fall time Setup data (negative SCLK edge) positive edge SCLK
(tsd applies between address data bytes, between data bytes)
Hold data after positive edge SCLK Negative edge SCLK high
Table interface timing requirements
CSn: Command strobe(s): Read write register(s): Read write consecutive registers (burst): Read write bytes from/to FIFO: Combinations: ADDR strobe ADDR strobe ADDR strobe ADDR ADDR DATA DATA ADDR DATA DATA DATA ADDR DATA DATA DATA byte byte ADDR strobe ADDR FIFO DATA byte DATA byte DATA
ADDR FIFO DATA byte DATA byte DATA byte ADDR DATA ADDR ADDR strobe
Figure Register access types
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
10.1 Chip Status Byte When header byte, data byte command strobe sent interface, chip status byte sent CC2500 pin. status byte contains status signals, useful MCU. first bit, CHIP_RDYn signal; this signal must before first positive edge SCLK. CHIP_RDYn signal indicates that crystal running regulated digital supply voltage stable. Bits comprise STATE value. This value reflects state chip. XOSC power digital core IDLE state, other modules power down. frequency channel configuration should only updated when chip this state. state will active when chip receive mode. Likewise, active when chip transmitting. last four bits (3:0) status byte contains FIFO_BYTES_AVAILABLE. read operations, FIFO_BYTES_AVAILABLE field contains number bytes available reading from FIFO. write operations, FIFO_BYTES_AVAILABLE field contains number bytes free writing into FIFO. When FIFO_BYTES_AVAILABLE=15, more bytes available/free. Table gives status byte summary.
Bits
Name
Description
CHIP_RDYn STATE[2:0]
Stays high until power crystal have stabilized. Should always when using interface. Indicates current main state machine mode Value State IDLE Description Idle state
(Also reported some transitional states instead SETTLING CALIBRATE)
FIFO_BYTES_AVAILABLE[3:0]
FSTXON CALIBRATE SETTLING RXFIFO_OVERFLOW TXFIFO_UNDERFLOW
Receive mode Transmit mode Frequency synthesizer ready start transmitting Frequency synthesizer calibration running settling FIFO overflowed. Read useful data, then flush FIFO with SFRX FIFO underflowed. Acknowledge with
SFTX
number bytes available FIFO free bytes FIFO (depends read/write-bit). FIFO_BYTES_AVAILABLE=15, there more bytes FIFO less bytes FIFO.
Table Status byte summary read. When writing registers, status byte sent each time header byte data byte transmitted pin. When reading from registers, status byte sent each time header byte transmitted pin. Registers with consecutive addresses accessed efficient setting
SWRS040a Page
10.2 Register Access configuration registers CC2500 located addresses from 0x00 0x2F. Table page lists configuration registers. detailed description each register found Section 31.1, starting page configuration registers both written read. read/write controls register should written
PRELIMINARY Data Sheet (Rev.1.2)
CC2500
burst address header. address sets start address internal address counter. This counter incremented each byte (every clock pulses). burst access either read write access must terminated setting high. register addresses range 0x300x3D, "burst" used select between status registers command strobes (see below). status registers only read. Burst read available status registers, they must read time. 10.3 Read When reading register fields over interface while register fields updated radio hardware (e.g. MARCSTATE TXBYTES), there small, finite, probability that single read from register being corrupt. example, probability single read from TXBYTES being corrupt, assuming maximum data rate used, approximately ppm. Refer CC2500 Errata Note more details. 10.4 Command Strobes Command strobes viewed single byte instructions CC2500. addressing command strobe register, internal sequences will started. These commands used disable crystal oscillator, enable receive mode, enable wake-on-radio etc. command strobes listed Table page command strobe registers accessed same register write operation, data transferred. That only (set burst access (set address bits range 0x30 through 0x3D) written. When writing command strobes, status byte sent pin. command strobe followed other access without pulling high. After issuing SRES command strobe next command strobe issued when goes shown Figure command strobes executed immediately, with exception SPWD SXOFF strobes that executed when goes high. Figure SRES command strobe 10.5 FIFO Access 64-byte FIFO 64-byte FIFO accessed through 0x3F address. When read/write zero, FIFO accessed, FIFO accessed when read/write one. FIFO write-only, while FIFO read-only. burst used determine FIFO access single byte burst access. single byte access method expects address with burst zero data byte. After data byte address expected; hence, remain low. burst access method expects address byte then consecutive data bytes until terminating access setting high. following header bytes access FIFOs: 0x3F: Single byte access FIFO 0x7F: Burst access FIFO 0xBF: Single byte access FIFO 0xFF: Burst access FIFO
When writing FIFO, status byte (see Section 10.1) output each data byte shown Figure This status byte used detect FIFO underflow while writing data FIFO. Note that status byte contains number bytes free before writing byte progress FIFO. When last byte that fits FIFO transmitted pin, status byte received concurrently will indicate that byte free FIFO. transmit FIFO flushed issuing SFTX command strobe. Similarly, SFRX command strobe will flush receive FIFO. SFTX SFRX command strobe only issued IDLE, TXFIFO_UNDERLOW RXFIFO_OVERFLOW state. Both FIFOs flushed when going SLEEP state.
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
10.6 PATABLE Access 0x3E address used access PATABLE, which used selecting power control settings. expects eight data bytes after receiving address. programming PATABLE, controlled power ramp-up ramp-down achieved. Section page output power programming details. PATABLE 8-byte table that defines control settings each eight power values (selected 3-bit value FREND0.PA_POWER). table written read from lowest setting highest (7), byte time. index counter used control access table. This counter incremented each time byte read written table, lowest index when high. When highest value reached counter restarts access PATABLE either single byte burst access depending burst bit. When using burst access index counter will count when reaching counter will restart read/write controls whether access write access (R/W=0) read access (R/W=1). byte written PATABLE this value read then must high before read access order index counter back zero. Note that content PATABLE lost when entering SLEEP state, except first byte (index
Microcontroller Interface Configuration
typical system, CC2500 will interface microcontroller. This microcontroller must able Program CC2500 into different modes Read write buffered data Read back status information 4-wire SPI-bus configuration interface (SI, SCLK CSn) 11.1 Configuration Interface microcontroller uses four pins configuration interface (SI, SCLK CSn). described Section page 11.2 General Control Status Pins CC2500 dedicated configurable pins shared that output internal status information useful control software. These pins used generate interrupts MCU. Section page more details signals that programmed. dedicated pins called GDO0 GDO2. shared interface. default setting GDO1/SO 3-state output. selecting other programming options GDO1/SO will become generic pin. When low, will always function normal pin. synchronous asynchronous serial modes, GDO0 used serial data input while transmit mode. GDO0 also used on-chip analog temperature sensor. measuring voltage GDO0 with external ADC, temperature calculated. Specifications temperature sensor found Section page With default PTEST register setting (0x7F) temperature sensor output only available when frequency synthesizer enabled (e.g. MANCAL, FSTXON, states). necessary write 0xBF PTEST register analog temperature sensor IDLE state. Before leaving IDLE state, PTEST register should restored default value (0x7F). 11.3 Optional Radio Control Feature CC2500 optional controlling radio, reusing SCLK from interface. This feature allows simple three-pin control major states radio: SLEEP, IDLE, This optional functionality enabled with MCSM0.PIN_CTRL_EN configuration bit. State changes commanded follows: When high SCLK desired state according Table When goes state SCLK latched command strobe generated
SWRS040a Page
PRELIMINARY Data Sheet (Rev.1.2)
CC2500
internally according control coding. only possible change state with this functionality. That means that instance will restarted SCLK toggles. When SCLK normal functionality. control command strobes executed immediately, except SPWD strobe, which delayed until goes high.
SCLK
mode
mode
Function
Chip unaffected
SCLK/SI
Generates SPWD strobe Generates strobe Generates SIDLE strobe Generates strobe mode (wakes into IDLE SLEEP/XOFF)
Table Optional control coding
Data Rate Programming
data rate used when transmitting, data rate expected receive programmed MDMCFG3.DRATE_M MDMCFG4.DRATE_E configuration registers. data rate given formula below. formula shows, programmed data rate depends crystal frequency. DRATE_M rounded nearest integer becomes 256, increment DRATE_E DRATE_M=0. data rate from kbps kbps with minimum step size
RDATA
(256 DRATE
DRATE
XOSC
Data rate start [kbps]
Typical data rate [kbps]
Data rate stop [kbps]
Data rate step size [kbps]
3.17
1.2/2.4 19.6 38.4 76.8 153.6
3.17 6.35 12.7 25.4 50.8 101.6 203.1 406.3
0.0062 0.0124 0.0248 0.0496 0.0992 0.1984 0.3967 0.7935 1.5869
following approach used find suitable values given data rate:
6.35 12.7 25.4
DATA DRATE XOSC DATA DRATE XOSC DRATE
50.8 101.6 203.1 406.3
Table Data rate step size
Receiver Channel Filter Bandwidth
order meet different channel width requirements, receiver channel filter programmable. MDMCFG4.CHANBW_E MDMCFG4.CHANBW_M configuration registers control receiver channel filter bandwidth, which scales with crystal oscillator frequency. following formula gives relation between register settings channel filter bandwidth:
BWchannel
XOSC CHANBW
CC2500 supports following channel filter bandwidths:
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
MDMCFG4. CHANBW_M MDMCFG4.CHANBW_E
tolerance crystal accuracy should also subtracted from signal bandwidth. following example illustrates this: With channel filter bandwidth kHz, signal should stay within kHz, which kHz. Assuming 2.44 frequency frequency uncertainty both transmitting device receiving device, total frequency uncertainty 2.44 GHz, which kHz. whole transmitted signal bandwidth received within kHz, transmitted signal bandwidth should maximum kHz, which kHz.
Table Channel filter bandwidths [kHz] (assuming crystal) best performance, channel filter bandwidth should selected that signal bandwidth occupies most channel filter bandwidth. channel centre
Demodulator, Symbol Synchronizer Data Decision
CC2500 contains advanced highly configurable demodulator. Channel filtering frequency offset compensation performed digitally. generate RSSI level (see Section 17.3 more information) signal level channel estimated. Data filtering also included enhanced performance.
14.1 Frequency Offset Compensation When using FSK, GFSK modulation, demodulator will compensate offset between transmitter receiver frequency, within certain limits, estimating centre received data. This value available FREQEST status register. Writing value from FREQEST into FSCTRL0.FREQOFF frequency synthesizer automatically adjusted according estimated frequency offset. Note that frequency offset compensation supported modulation. 14.2 Synchronization synchronization algorithm extracts clock from incoming symbols. algorithm requires that expected data rate programmed described Section page Re-synchronization performed continuously adjust error incoming symbol rate. 14.3 Byte Synchronization Byte synchronization achieved continuous sync word search. sync word configurable field that automatically inserted start packet modulator transmit mode. demodulator uses this field find byte boundaries stream bits. sync word will also function system identifier, since only packets with correct predefined sync word will received. sync word detector correlates against user-configured 16-bit sync word. correlation threshold 15/16 bits match 16/16 bits match. sync word further qualified using preamble quality indicator mechanism described below and/or carrier sense condition. sync word programmed with SYNC1 SYNC0. order make false detections sync words less likely, mechanism called preamble quality indication (PQI) used qualify sync word. threshold value preamble quality must exceeded order detected sync word accepted. Section 17.2 page more details.
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Packet Handling Hardware Support
CC2500 built-in hardware support packet oriented radio protocols. transmit mode, packet handler will following elements packet stored FIFO: programmable number preamble bytes. byte synchronization (sync) word. duplicated give 4-byte sync word. Optionally whiten data with sequence. Optionally Interleave Forward Error Code data. Optionally compute checksum over data field. recommended setting 4-byte preamble 4-byte sync word except kbps data rate where recommended preamble length bytes.
Field name Description
CRC_OK
received data disabled) error received data
Link Quality Indicator estimates easily received signal demodulated
Table Received packet status byte (second byte appended after data) Note that register fields that control packet handling features should only altered when CC2500 IDLE state. 15.1 Data Whitening From radio perspective, ideal over data random free. This results smoothest power distribution over occupied bandwidth. This also gives regulation loops receiver uniform operation conditions data dependencies). Real world data often contain long sequences zeros ones. Performance then improved whitening data before transmitting, de-whitening receiver. With CC2500, this done automatically setting PKTCTRL0.WHITE_DATA=1. data, except preamble sync word, then XOR-ed with 9-bit pseudo-random (PN9) sequence before being transmitted shown Figure receiver end, data XOR-ed with same pseudorandom sequence. This way, whitening reversed, original data appear receiver. Data whitening only used when PKTCTRL0.CC2400_EN (default).
receive mode, packet handling support will de-construct data packet: Preamble detection. Sync word detection. Optional byte address check. Optionally compute check CRC. Optionally append status bytes (see Table Table with RSSI value, Link Quality Indication status.
Field name
Description
RSSI
RSSI value
Table Received packet status byte (first byte appended after data)
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Figure Data whitening mode Length byte constant programmable packet length Optional address byte Payload Optional byte
15.2 Packet Format format data packet configured consists following items (see Figure 11): Preamble Synchronization word
Optional data whitening Optionally encoded/decoded Optional CRC-16 calculation Address field Length field Sync word
Legend: Inserted automatically processed removed CRC-16 Optional user-provided fields processed processed removed Unprocessed user data (apart from and/or whitening)
Preamble bits (1010.1010)
Data field
bits
16/32 bits
bits
bits
bits
bits
Figure Packet format preamble pattern alternating sequence ones zeros (01010101.). minimum length preamble programmable. When enabling modulator will start transmitting preamble. When programmed number preamble bytes been transmitted, modulator will send sync word then data from FIFO data available. FIFO empty, modulator will continue send preamble bytes until first byte written FIFO. modulator will then send sync word then data bytes. number preamble bytes programmed with MDMCFG1.NUM_PREAMBLE value. synchronization word two-byte value SYNC1 SYNC0 registers. sync word provides byte synchronization incoming packet. one-byte sync word emulated setting SYNC1 value preamble pattern. also possible emulate sync word using MDMCFG2.SYNC_MODE=3 sync word will then repeated twice.
CC2500 supports both fixed packet length
protocols variable packet length protocols. Variable fixed packet length mode used packets bytes. longer packets, infinite packet length mode must used.
SWRS040a Page
PRELIMINARY Data Sheet (Rev.1.2)
CC2500
Fixed packet length mode selected setting PKTCTRL0.LENGTH_CONFIG=0. desired packet length PKTLEN register. variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, packet length configured first byte after sync word. packet length defined payload data, excluding length byte optional automatic CRC. PKTLEN register used maximum packet length allowed packet received with length byte with value greater than PKTLEN will discarded. With PKTCTRL0.LENGTH_CONFIG=2, packet length infinite transmission reception will continue until turned manually. infinite mode turned while packet being transmitted received. described next section, this used support packet formats with different length configuration than natively supported CC2500. 15.2.1 Arbitrary Length Field Configuration fixed length field reprogrammed during receive transmit. This opens possibility have different length field configuration than supported variable length packets. start reception, packet length large value. reads enough bytes interpret length field packet. Then PKTLEN value according this value. packet will occur when byte counter packet handler equal PKTLEN register. Thus, must able program correct length, before internal counter reaches packet length. utilizing infinite packet length option, arbitrary packet length available. start packet, infinite mode must active. side, PKTLEN register mod(length, 256). side reads enough bytes interpret length field packet sets PKTLEN register mod(length, 256). When less than bytes remains packet disables infinite packet length activates fixed length packets. When internal byte counter reaches PKTLEN value, transmission reception ends. Automatic appending/checking used setting PKTCTRL0.CRC_EN When example 600-byte packet transmitted, should following (see also Figure 12): PKTCTRL0.LENGTH_CONFIG=2 (10). Pre-program PKTLEN mod(600,256)=88. register
Transmit least bytes, example filling 64-byte FIFO times (384 bytes transmitted). PKTCTRL0.LENGTH_CONFIG=0 (00). transmission ends when packet counter reaches total bytes transmitted.
Internal byte counter packet handler counts from then starts again
Infinite packet length enabled
Fixed packet length enabled when less than bytes remains packet
bytes transmitted received
Length field transmitted received. PKTLEN value mod(600,256)
Figure Arbitrary length field configuration
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
15.3 Packet Filtering Receive Mode
CC2500 supports three different packet-filtering criteria: address filtering, maximum length filtering filtering.
15.3.1 Address Filtering Setting PKTCTRL1.ADR_CHK other value than zero enables packet address filter. packet handler engine will compare destination address byte packet with programmed node address ADDR register 0x00 broadcast address when PKTCTRL1.ADR_CHK=10 both 0x00 0xFF broadcast addresses when PKTCTRL1.ADR_CHK=11. received address matches valid address, packet received written into FIFO. address match fails, packet discarded receive mode restarted (regardless MCSM1.RXOFF_MODE setting). received address matches valid address when packet length infinite address filtering enabled, 0xFF will written into FIFO followed address byte then payload data. 15.3.2 Maximum Length Filtering variable packet length mode PKTLEN.PACKET_LENGTH register value used maximum allowed packet length. received length byte larger value than this, packet discarded receive mode restarted (regardless MCSM1.RXOFF_MODE setting). 15.3.3 Filtering filtering packet when check fails enabled with PKTCTRL1.CRC_AUTOFLUSH. auto flush function will flush entire FIFO check fails. After auto flushing FIFO, next state depends MCSM1.RXOFF_MODE setting. PKTCTRL0.CC2400_EN must (default) auto flush function work correctly. When using auto flush function, maximum packet length bytes variable packet length mode bytes fixed packet length mode. Note that maximum allowed packet length reduced bytes when PKTCTRL1.APPEND_STATUS enabled, make room FIFO status bytes appended packet. Since entire FIFO flushed when check fails, previously
received packet must read FIFO before receiving current packet. must read from current packet until been checked 15.4 Check There different implementations. PKTCTRL0.CC2400_EN selects between options. check different options. Refer also CC2500 Errata Note. 15.4.1 PKTCTRL0.CC2400_EN PKTCTRL0.CC2400_EN possible read back status different ways: PKTCTRL1.APPEND_STATUS=1 read CRC_OK flag second byte appended FIFO after packet data. This requires double buffering packet, i.e. entire packet content FIFO must completely read before possible check whether indication not. avoid reading entire FIFO, another solution PKTCTRL1.CRC_AUTOFLUSH feature. this feature enabled, entire FIFO will flushed check fails. GDOx_CFG=0x06 GDOx will asserted when sync word found. GDOx will de-asserted packet. When latter occurs should read number bytes FIFO from RXBYTES.NUM_RXBYTES status register. RXBYTES.NUM_RXBYTES=0 check failed FIFO flushed. RXBYTES.NUM_RXBYTES>0 check data read FIFO. 15.4.2 PKTCTRL0.CC2400_EN PKTCTRL0.CC2400_EN checked outlined Section 15.4.1 well reading CRC_OK flag available PKTSTATUS[7] register, LQI[7] status register from pins GDOx_CFG 0x07 0x15. PKTCTRL1.CRC_AUTOFLUSH data whitening cannot used when PKTCTRL0.CC2400_EN 15.5 Packet Handling Transmit Mode payload that transmitted must written into FIFO. first byte written must length byte when variable packet
SWRS040a Page
PRELIMINARY Data Sheet (Rev.1.2)
CC2500
length enabled. length byte value equal payload packet (including optional address byte). fixed packet length enabled, then first byte written FIFO interpreted destination address, this feature enabled device that receives packet. modulator will first send programmed number preamble bytes. data available FIFO, modulator will send two-byte (optionally 4-byte) sync word then payload FIFO. enabled, checksum calculated over data pulled from FIFO result sent extra bytes payload data. whitening enabled, length byte, payload data bytes will whitened. This done before optional FEC/Interleaver stage. Whitening enabled setting PKTCTRL0.WHITE_DATA=1. FEC/Interleaving enabled, length byte, payload data bytes will scrambled interleaver, encoded before being modulated. 15.6 Packet Handling Receive Mode receive mode, demodulator packet handler will search valid preamble sync word. When found, demodulator obtained both byte synchronism will receive first payload byte. FEC/Interleaving enabled, decoder will start decode first payload byte. interleaver will de-scramble bits before other processing done data. whitening enabled, data will dewhitened this stage. When variable packet length enabled, first byte length byte. packet handler stores this value packet length receives number bytes indicated length byte. fixed packet length used, packet handler will accept programmed number bytes. Next, packet handler optionally checks address only continues reception address matches. automatic check enabled, packet handler computes matches with appended checksum. payload, packet handler will optionally write extra packet status bytes that contain status, link quality indication RSSI value.
Modulation Formats
CC2500 supports amplitude, frequency phase shift modulation formats. desired modulation format MDMCFG2.MOD_FORMAT register.
Optionally, data stream Manchester coded modulator decoded demodulator. This option enabled setting MDMCFG2.MANCHESTER_EN=1. Manchester encoding supported same time using FEC/Interleaver option. 16.1 Frequency Shift Keying optionally shaped Gaussian filter with BT=1, producing GFSK modulated signal. frequency deviation programmed with DEVIATION_M DEVIATION_E values DEVIATN register. value exponent/mantissa form, resultant deviation given 16.2 Minimum Shift Keying When using MSK1, complete transmission (preamble, sync word payload) will modulated. Identical offset QPSK with half-sine shaping (data coding differ)
SWRS040a Page
xosc DEVIATION DEVIATION
symbol encoding shown Table
Format Symbol Coding
FSK\GFSK
Deviation Deviation
Table Symbol encoding modulation
PRELIMINARY Data Sheet (Rev.1.2)
CC2500
Phase shifts performed with constant transition time. fraction symbol period used change phase modified with DEVIATN.DEVIATION_M setting. This equivalent changing shaping symbol. modulation format implemented CC2500 inverts sync word data compared e.g. signal generators. 16.3 Amplitude Modulation supported amplitude modulation On-Off Keying (OOK) simply turns modulate respectively.
Received Signal Qualifiers Link Quality Information
CC2500 several qualifiers that used increase likelihood that valid sync word detected.
17.1 Sync Word Qualifier sync word detection enabled register MDMCFG2 CC2500 will start filling FIFO perform packet filtering described Section 15.3 before valid sync word been detected. sync word qualifier mode MDMCFG2.SYNC_MODE summarized Table Carrier sense Table described Section 17.4. Another preamble quality threshold qualifier optional termination timer. Section 19.7 page details. preamble quality estimator increases internal counter each time received that different from previous bit, decreases counter each time received that same last bit. counter saturates threshold configured with register field PKTCTRL1.PQT. threshold this counter used gate sync word detection. setting value zero, preamble quality qualifier sync word disabled. "Preamble Quality Reached" flag also observed pins status register PKTSTATUS.PQT_REACHED. This flag asserts when received signal exceeds PQT. 17.3 RSSI RSSI value estimate signal level chosen channel. This value based current gain setting chain measured signal level channel. mode, RSSI value read continuously from RSSI status register until demodulator detects sync word (when sync word detection enabled). that point RSSI readout value frozen until next time chip enters state. RSSI value with resolution. RSSI update rate depends receiver filter bandwidth (BWchannel defined Section AGCCTRL0.FILTER_LENGTH.
MDMCFG2. SYNC_MODE
Sync word qualifier mode
preamble/sync 15/16 sync word bits detected 16/16 sync word bits detected 30/32 sync word bits detected preamble/sync, carrier sense above threshold 15/16 carrier sense above threshold 16/16 carrier sense above threshold 30/32 carrier sense above threshold
Table Sync word qualifier mode 17.2 Preamble Quality Threshold (PQT) Preamble Quality Threshold (PQT) syncword qualifier adds requirement that received sync word must preceded with preamble with quality above programmed threshold.
RSSI
BWchannel FILTER LENGTH
Page
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
CC2500
PKTCTRL1.APPEND_STATUS enabled RSSI value sync word detection automatically added first byte appended after data. RSSI value read from RSSI status register complement number. following procedure used convert RSSI reading absolute power level (RSSI_dBm). Read RSSI status register Convert reading from hexadecimal number decimal number (RSSI_dec) RSSI_dec then RSSI_dBm (RSSI_dec 256)/2 RSSI_offset Else RSSI_dec then RSSI_dBm (RSSI_dec)/2 RSSI_offset Table provides typical values RSSI_offset. Figure shows typical plots RSSI readings function input power level different data rates.
Data rate [kbps]
RSSI_offset [decimal]
Table Typical RSSI_offset values
-10.0 -20.0 -30.0 RSSI readout [dBm] -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100.0 -110.0 -120.0 -120 -110 -100
Input [dBm] kbps kbps kbps kbps, reduced current kbps
Figure Typical RSSI value input power level some typical data rates asserted when RSSI increased with programmable number from RSSI sample next, de-asserted when RSSI decreased with same number This setting dependent absolute signal level thus useful detect signals environments with time varying noise floor.
17.4 Carrier Sense (CS) Carrier Sense flag used sync word qualifier CCA. flag based conditions, which individually adjusted: asserted when RSSI above programmable absolute threshold, deasserted when RSSI below same threshold (with hysteresis).
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Carrier Sense (CS) used sync word qualifier that requires signal level higher than threshold sync word search performed. signal also observed pins status register PKTSTATUS.CS. Other uses Carrier Sense include TX-IfCCA function (see Section 17.5 page optional fast termination (see Section 19.7 page 38). used avoid interference from e.g. WLAN. 17.4.1 Absolute Threshold absolute threshold related RSSI value given
THRRSSI MAGN TARGET CARRIER SENSE GAIN
MAX_DVGA_GAIN[1:0] MAX_LNA_GAIN[2:0] -94.5 -92.5 -87.5 -79.5 -76.5 -78.5 -73.5 -70.5 -78.5 -77.5 -67.5
Table Typical RSSI value threshold with default MAGN_TARGET kbps threshold high, i.e. only strong signals wanted, threshold should adjusted upwards first reducing MAX_LNA_GAIN value then MAX_DVGA_GAIN value. This will reduce power consumption receiver front end, since highest gain settings avoided. MAGN_TARGET setting compromise between blocker tolerance/selectivity sensitivity. value sets desired signal level channel into demodulator. Increasing this value reduces headroom blockers, therefore close-in selectivity.
maximum possible gain reduced using AGCCTRL2.MAX_LNA_GAIN AGCCTRL2.MAX_DVGA_GAIN register fields. CARRIER_SENSE_ABS_THR programmable steps from 7dB. Table Table show RSSI readout values threshold kbps kbps data rate respectively. default CARRIER_SENSE_ABS_THR MAGN_TARGET have been used. MAX_DVGA_GAIN[1:0] MAX_LNA_GAIN[2:0] -93.5 -91.5 -90.5 -84.5 -82.5 -90.5 -82.5 -78.5 -81.5 -78.5 -72.5
17.4.2 relative threshold relative threshold detects sudden changes measured signal level. This setting dependent absolute signal level thus useful detect signals environments with time varying noise floor. register field AGCCTRL1.CARRIER_SENSE_REL_THR used enable/disable relative select threshold RSSI change 17.5 Clear Channel Assessment (CCA) Clear Channel Assessment used indicate current channel free busy. current state viewable pins. MCSM1.CCA_MODE selects mode when determining CCA. When SFSTXON command strobe given while CC2500 state, state only entered clear channel requirements fulfilled. chip will
Table Typical RSSI value threshold with default MAGN_TARGET kbps
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
otherwise remain This feature called CCA. Four requirements programmed: Always (CCA disabled, always goes RSSI below threshold Unless currently receiving packet Both above (RSSI below threshold currently receiving packet) 17.6 Link Quality Indicator (LQI) Link Quality Indicator metric current quality received signal. PKTCTRL1.APPEND_STATUS enabled, value automatically appended each received packet. value also read from status register. calculated over symbols following sync word (first packet bytes). best used relative measurement link quality, since value dependent modulation format.
Forward Error Correction with Interleaving
18.1 Forward Error Correction (FEC)
CC2500 built support Forward Error Correction (FEC). enable this option, MDMCFG1.FEC_EN only supported fixed packet length mode (PKTCTRL0.LENGTH_CONFIG=0). employed data field word order reduce gross error rate when operating near sensitivity limit. Redundancy added transmitted data such that receiver restore original data presence some errors.
allows correct reception lower SNR, thus extending communication range. Alternatively, given SNR, using decreases error rate (BER). packet error rate (PER) related
input produces output bits; hence, effective data rate halved. 18.2 Interleaving Data received through radio channels will often experience burst errors interference time-varying signal strengths. order increase robustness errors spanning multiple bits, interleaving used when enabled. After de-interleaving, continuous span errors received stream will become single errors spread apart.
BER) packet length
lower used allow longer packets, higher percentage packets given length, transmitted successfully. Finally, realistic radio environments, transient time-varying phenomena will produce occasional errors even otherwise good reception conditions. will mask such errors and, combined with interleaving coded data, even correct relatively long periods faulty reception (burst errors). scheme adopted CC2500 convolutional coding, which bits generated based input bits most recent input bits, forming code stream able withstand certain number errors between each coding state (the m-bit window). convolutional coder rate code with constraint length m=4. coder codes
CC2500 employs matrix interleaving, which illustrated Figure on-chip interleaving de-interleaving buffers matrices. transmitter, data bits written into rows matrix, whereas sequence transmitted read from columns matrix rate convolutional coder. Conversely, receiver, received symbols written into columns matrix, whereas data passed onto convolutional decoder read from rows matrix.
When interleaving used least extra byte required trellis termination. addition, amount data transmitted over must multiple size interleaver buffer (two bytes). packet control hardware therefore automatically inserts extra bytes packet, that total length data interleaved even number. Note that these extra bytes invisible user, they removed before received packet enters FIFO. When interleaving used minimum data payload bytes.
SWRS040a Page
PRELIMINARY Data Sheet (Rev.1.2)
CC2500
Storing coded data Transmitting interleaved data Demodulator Receiving interleaved data Passing data decoder
Modulator
Data
Decoder Receiver
SPWD SWOR SLEEP SXOFF XOFF AUTOCAL= SFSTXON CALIBRATE CAL_ COMPLETE SFSTXON) RXOFF MODE 13,14,15 RXOFF MODE AUTOCAL= RXFIFO OVERFLOW RXOFF MODE AUTOCAL= OVERFLOW SFRX
Encoder
Data
Transmitter
Figure General principle matrix interleaving
Radio Control
SIDLE CAL_ COMPLETE MANCAL 3,4,5 SCAL IDLE
SFSTXON
WAKEUP
AUTOCAL= SFSTXON
SFSTXON FSTXON
SETTLING 9,10,11
TXOFF MODE=01
SFSTXON RXOFF MODE
RXOFF MODE TXOFF MODE 19,20
RXTX_ SETTLING
RXOFF MODE
TXOFF MODE
TXRX_ SETTLING
TXFIFO UNDERFLOW
TXOFF MODE AUTOCAL= TXOFF MODE AUTOCAL= CALIBRATE
UNDERFLOW
SFTX IDLE
Figure Complete radio control state diagram
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
CC2500 built-in state machine that used switch between different operation states (modes). change state done either using command strobes internal events such FIFO underflow.
simplified state diagram, together with typical usage current consumption, shown Figure page complete radio control state diagram shown Figure numbers refer state number readable MARCSTATE status register. This register primarily test purposes. 19.1 Power-On Start-Up Sequence When power supply turned system must reset. following sequences must followed: Automatic power-on reset (POR) manual reset. 19.1.1 Automatic power-on reset circuit included CC2500. minimum requirements stated Section must followed power-on reset function properly. internal powerup sequence completed when CHIP_RDYn goes low. CHIP_RDYn observed after pulled low. Section 10.1 more details CHIP_RDYn. When CC2500 reset completed chip will IDLE state crystal oscillator running. chip sufficient time crystal oscillator voltage regulator stabilize after power-on-reset, will immediately after taking low. taken before reset completed will first high, indicating that crystal oscillator voltage regulator stabilized, before going shown Figure
XOSC voltage regulator stabilized
SRES
default, IDLE state. manual powerup sequence follows (see Figure 17): SCLK=1 SI=0, avoid potential problems with control mode (see Section 11.3 page 23). Strobe high. Hold high least relative pulling Pull wait (CHIP_RDYn). Issue SRES strobe line. When goes again, reset complete chip IDLE state.
XOSC voltage regulator switched
Figure Power-on reset with SRES Note that above reset procedure only required just after power supply first turned user wants reset CC2500 after this, only necessary issue SRES command strobe. 19.2 Crystal Control crystal oscillator (XOSC) either automatically controlled always MCSM0.XOSC_FORCE_ON set. automatic mode, XOSC will turned SXOFF SPWD command strobes issued; state machine then goes XOFF SLEEP respectively. This only done from IDLE state. XOSC will turned when released (goes high). XOSC will automatically turned again when goes low. state machine will then IDLE state. interface must zero before interface ready used; described Section 10.1 page
XOSC voltage regulator stabilized
Figure Power-on reset
19.1.2 Manual Reset other global reset possibility CC2500 SRES command strobe. issuing this strobe, internal registers states
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
XOSC forced crystal will always stay even SLEEP state. Crystal oscillator start-up time depends crystal load capacitances. electrical specification crystal oscillator found Section page 19.3 Voltage Regulator Control voltage regulator digital core controlled radio controller. When chip enters SLEEP state, which state with lowest current consumption, voltage regulator disabled. This occurs after released when SPWD command strobe been sent interface. chip SLEEP state. Setting again will turn regulator crystal oscillator make chip enter IDLE state. When wake radio enabled, module will control voltage regulator described Section 19.5. 19.4 Active Modes received radio controller will then state indicated MCSM1.RXOFF_MODE setting. possible destinations are: IDLE FSTXON: Frequency synthesizer ready frequency. Activate with STX. Start sending preambles Start search packet
Similarly, when active chip will remain state until current packet been successfully transmitted. Then state will change indicated MCSM1.TXOFF_MODE setting. possible destinations same manually change state from vice versa using command strobes. radio controller currently transmit strobe used, current transmission will ended transition will done. radio controller when SFSTXON command strobes used, clear channel" function will used. channel clear, chip will remain MCSM1.CCA_MODE setting controls conditions clear channel assessment. Section 17.5 page details. SIDLE command strobe always used force radio controller IDLE state. 19.5 Wake Radio (WOR) optional Wake Radio (WOR) functionality enables CC2500 periodically wake from deep sleep listen incoming packets without interaction. When enabled, CC2500 will SLEEP state when released after SWOR command strobe been sent interface. oscillator must enabled before strobe used, clock source timer. on-chip timer will CC2500 into IDLE state then state. After programmable time chip goes back SLEEP state, unless packet received. Figure Section 19.7 details timeout works.
CC2500 active modes: receive
transmit. These modes activated directly using command strobes, automatically Wake Radio. frequency synthesizer must calibrated regularly. CC2500 manual calibration option (using SCAL strobe), three automatic calibration options, controlled MCSM0.FS_AUTOCAL setting: Calibrate when going from IDLE either FSTXON) Calibrate when going from either IDLE Calibrate every fourth time when going from either IDLE
calibration takes constant number XOSC cycles (see Table timing details). When activated, chip will remain receive mode until packet successfully received termination timer expires (see Section 19.7). Note: probability that false sync word detected reduced using PQT, maximum sync word length sync word qualifier mode describe Section After packet successfully
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
CC2500 signal that packet been received using pins. packet received, MCSM1.RXOFF_MODE will determine behaviour received packet. When read packet, chip back into SLEEP with SWOR strobe from IDLE state. FIFO will lose contents SLEEP state.
timer events, Event Event SLEEP state with activated, reaching Event will turn digital regulator start crystal oscillator. Event follows Event after programmed timeout. time between consecutive Event programmed with mantissa value given WOREVT1.EVENT0 WOREVT0.EVENT0, exponent value WORCTRL.WOR_RES. equation power XOSC enabled, clock used timer divided XOSC clock. When chip goes sleep state, oscillator will last valid calibration result. frequency oscillator locked main crystal frequency divided 750. 19.6 Timing
CC2500, such synthesizer calibration,
radio controller controls most timing
lock RT/TX turnaround times. Timing from IDLE IDLE constant, dependent auto calibration setting. RX/TX TX/RX turnaround times constant. calibration time constant 18739 clock periods. Table shows timing crystal clock cycles state transitions. Power time XOSC start-up times variable, within limits stated Table Note that frequency hopping spread spectrum multi-channel protocol calibration time reduced from approximately This explained Section 30.2.
Description XOSC periods crystal
Event
EVENT 5WOR XOSC
Event timeout programmed with WORCTRL.EVENT1. Figure shows timing relationship between Event timeout Event timeout.
IDLE calibration
2298 ~21037 2298 ~21037 ~18739 ~18739
88.4 88.4 21.5
timeout
State: SLEEP IDLE SLEEP IDLE
IDLE with calibration IDLE TX/FSTXON, calibration IDLE TX/FSTXON, with calibration switch
Event0
Event1
Event0
Event1
tEvent0 tEvent0 tEvent1 tEvent1
switch IDLE, calibration IDLE, with calibration Manual calibration
Figure Event Event relationship Refer Application Note AN038 CC1100/CC2500 Wake-on-Radio further details. 19.5.1 Oscillator Timing frequency low-power oscillator used functionality varies with temperature supply voltage. order keep frequency accurate possible, oscillator will calibrated whenever possible, which when XOSC running chip SLEEP state. When
Table State transition timing 19.7 Termination Timer
CC2500 optional functions automatic termination after programmable time. main this functionality wake-onradio (WOR), useful other applications. termination timer starts when state. timeout programmable with MCSM2.RX_TIME setting. When timer expires, radio controller will check condition staying condition met, will terminate. After timeout, condition will checked continuously.
SWRS040a Page
PRELIMINARY Data Sheet (Rev.1.2)
CC2500
programmable conditions are: MCSM2.RX_TIME_QUAL=0: Continue receive sync word been found MCSM2.RX_TIME_QUAL=1: Continue receive sync word been found preamble quality above threshold (PQT) terminates carrier sense when MCSM2.RX_TIME_RSSI function used, sync word found when using MCSM2.RX_TIME timeout function, chip will always back IDLE disabled back SLEEP enabled. Otherwise, MCSM1.RXOFF_MODE setting determines state when ends. Note that wake-on-radio (WOR) mode, state cleared latter case. This means that chip will automatically back SLEEP again IDLE, even e.g. address field packet match. therefore recommended always wake microcontroller sync word detection when using mode. This done selecting output signal (see Table page programmable output pins, programming microcontroller wake edgetriggered interrupt from this pin.
system expect transmission have started when enabling receiver, MCSM2.RX_TIME_RSSI function used. radio controller will then terminate first valid carrier sense sample indicates carrier (RSSI below threshold). Section 17.4 page details Carrier Sense. modulation, lack carrier sense only considered valid after eight symbol periods. Thus, MCSM2.RX_TIME_RSSI function used mode when distance between symbols less.
Data FIFO
CC2500 contains byte FIFOs, received data data transmitted. interface used read from FIFO write FIFO. Section 10.5 contains details FIFO access. FIFO controller will detect overflow FIFO underflow FIFO. When writing FIFO responsibility avoid FIFO overflow. FIFO overflow will result error FIFO content. Likewise, when reading FIFO must avoid reading FIFO past empty value, since FIFO underflow will result error data read FIFO. chip status byte that available while transferring address contains fill grade FIFO address read operation fill grade FIFO address write operation. Section 10.1on page contains more details this. number bytes FIFO FIFO also read from status registers RXBYTES.NUM_RXBYTES TXBYTES.NUM_TXBYTES respectively. received data byte written FIFO exact same time last byte FIFO read over interface, FIFO pointer properly updated last read byte duplicated. packet lengths less than bytes recommended wait until complete packet been received before reading FIFO. packet length larger than bytes must determine many bytes read from FIFO (RXBYTES.NUM_RXBYTES-1) following software routine used:
Read
RXBYTES.NUM_RXBYTES repeatedly rate guaranteed least twice that which bytes received until same value returned twice; store value
bytes remaining packet, read bytes from FIFO. Repeat steps until bytes remaining packet. Read remaining bytes from FIFO.
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
4-bit FIFOTHR.FIFO_THR setting used program threshold points FIFOs. Table lists FIFO_THR settings corresponding thresholds FIFOs. threshold value coded opposite directions FIFO FIFO. This gives equal margin overflow underflow conditions when threshold reached. flag will assert when number bytes FIFO equal higher than programmed threshold. flag used generate FIFO status signals that viewed pins (see Section page 46). Figure shows number bytes both FIFO FIFO when threshold flag toggles, case FIFO_THR=13. Figure shows flag respective FIFO filled above threshold, then drained below.
NUM_RXBYTES
FIFO_THR
Bytes FIFO
Bytes FIFO
(0000) (0001) (0010) (0011) (0100) (0101) (0110) (0111) (1000) (1001) (1010) (1011) (1100) (1101) (1110) (1111)
Table FIFO_THR settings corresponding FIFO thresholds
Overflow margin
FIFO_THR=13
NUM_TXBYTES
bytes
Figure FIFO_THR=13 number bytes FIFO (GDOx_CFG=0x00 GDOx_CFG=0x02
FIFO_THR=13
Underflow margin
bytes TXFIFO
RXFIFO
Figure Example FIFOs threshold
Frequency Programming
frequency programming CC2500 designed minimize programming needed channel-oriented system. system with channel numbers, desired channel spacing programmed with MDMCFG0.CHANSPC_M MDMCFG1.CHANSPC_E registers. channel spacing registers mantissa exponent respectively. base start frequency frequency word located FREQ2, FREQ1 FREQ0 registers. This word will typically centre lowest channel frequency that used. desired channel number programmed with 8-bit channel number register, CHANNR.CHAN, which multiplied channel offset. resultant carrier frequency given
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
carrier XOSC FREQ CHAN (256 CHANSPC CHANSPC
With crystal maximum channel spacing kHz. e.g. channel spacing solution channel spacing select each third channel CHANNR.CHAN. preferred frequency programmed with FSCTRL1.FREQ_IF register. frequency given
Note that SmartRF® Studio software automatically calculates optimum FSCTRL1.FREQ_IF register setting based channel spacing channel filter bandwidth. frequency programming register altered when frequency synthesizer running, synthesizer give undesired response. Hence, frequency programming should only updated when radio IDLE state.
XOSC FREQ
completely integrated on-chip. 22.1 Self-Calibration characteristics will vary with temperature supply voltage changes, well desired operating frequency. order ensure reliable operation, CC2500 includes frequency synthesizer self-calibration circuitry. This calibration should done regularly, must performed after turning power before using frequency channel). number XOSC cycles completing calibration given Table page calibration initiated automatically manually. synthesizer automatically calibrated each time synthesizer turned each time synthesizer turned off. This configured with MCSM0.FS_AUTOCAL register setting. manual mode, calibration initiated when SCAL command strobe activated IDLE mode. Note that calibration values maintained sleep mode, calibration still valid after waking from sleep mode (unless supply voltage temperature changed significantly). check that lock user program register IOCFGx.GDOx_CFG 0x0A lock detector output available GDOx interrupt positive transition GDOx means that lock. alternative user read register FSCAL1. lock register content different from 0x3F. Refer also CC2500 Errata Note. more robust operation source code could include check that recalibrated until lock achieved does lock first time.
Voltage Regulators
CC2500 contains several on-chip linear voltage regulators, which generate supply voltage needed low-voltage modules. These voltage regulators invisible user, viewed integral parts various modules. user must however make sure that absolute maximum ratings required voltages Table Table exceeded. voltage regulator
digital core requires decoupling capacitor. external
Setting turns voltage regulator digital core starts crystal oscillator. interface must before using serial interface (setup time given Table 16).
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
chip programmed enter power-down mode, (SPWD strobe issued), power will turned after goes high. power crystal oscillator will turned again when goes low. voltage regulator output should only used driving CC2500.
Output Power Programming
output power level from device levels programmability, illustrated Figure Firstly, special PATABLE register hold eight user selected output power settings. Secondly, 3-bit FREND0.PA_POWER value selects PATABLE entry use. This two-level functionality provides flexible power ramp ramp down start transmission. power settings PATABLE from index FREND0.PA_POWER value used. power ramping start packet turned setting FREND0.PA_POWER then program desired output power index PATABLE. Table contains recommended PATABLE settings various output levels frequency bands. Section 10.6 page PATABLE programming details. PATABLE must programmed burst mode want write other entries than PATABLE[0].
PATABLE(7)[7:0] PATABLE(6)[7:0] PATABLE(5)[7:0] PATABLE(4)[7:0] PATABLE(3)[7:0] PATABLE(2)[7:0] PATABLE(1)[7:0] PATABLE(0)[7:0] Index into PATABLE(7:0) Settings PA_POWER used during ramp-up start transmission ramp-down transmission, modulation. uses this setting.
PA_POWER[2:0] FREND0 register
SmartRF® Studio software should used obtain optimum PATABLE settings various output powers.
Figure PA_POWER PATABLE
Default power setting
Output power, typical [dBm]
Current consumption, typical [mA]
0xC6
-11.8
11.1
Table Output power current consumption default PATABLE setting
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Output power, typical, +25°C, [dBm] PATABLE value Current consumption, typical [mA]
(-55 less)
0x00 0x50 0x44 0xC0 0x84 0x81 0x46 0x93 0x55 0x8D 0xC6 0x97 0x6E 0x7F 0xA9 0xBB 0xFE
10.2 10.1 10.0 10.1 11.7 10.8 12.2 11.1 12.2 14.1 15.1 16.2 17.7 21.2
Table Optimum PATABLE settings various output power levels
Selectivity
Figure Figure show typical selectivity performance (adjacent alternate rejection).
Selectivity [dB]
-0.8 -0.6 -0.4 -0.2
Frequency offset [MHz]
Figure Typical selectivity kbps. frequency 273.9 kHz. MDMCFG2.DEM_DCFILT_OFF
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Selectivity [dB] -0.8 -0.6 -0.4 -0.2 offse
Figure Typical selectivity kbps. frequency 273.9 kHz. MDMCFG2.DEM_DCFILT_OFF
Selectivity [dB]
Frequency offset [MHz]
Figure Typical selectivity kbps. frequency 177.7 kHz. MDMCFG2.DEM_DCFILT_OFF
Selectivity [dB]
Frequency offset [MHz]
Figure Typical selectivity kbps. frequency kHz. MDMCFG2.DEM_DCFILT_OFF
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Selectivity [dB] Frequency offset [MHz]
Figure Typical selectivity kbps. frequency 307.4 kHz. MDMCFG2.DEM_DCFILT_OFF
Crystal Oscillator
crystal frequency range 26-27 must connected between XOSC_Q1 XOSC_Q2 pins. oscillator designed parallel mode operation crystal. addition, loading capacitors (C81 C101) crystal required. loading capacitor values depend total load capacitance, specified crystal. total load capacitance seen between crystal terminals should equal crystal oscillate specified frequency. crystal oscillator circuit shown Figure Typical component values different values given Table crystal oscillator amplitude regulated. This means that high current used start oscillations. When amplitude builds current reduced what necessary maintain approximately signal swing. This ensures fast start-up, keeps drive level minimum. crystal should within specification order ensure reliable start-up (see Section page 10).
XOSC_Q1 XOSC_Q2
C101
parasitic
parasitic capacitance constituted input capacitance stray capacitance. Total parasitic capacitance typically
XTAL C101
Figure Crystal oscillator circuit
Component
CL=13
CL=16
C101
Table Crystal oscillator component values
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
26.1 Reference Signal chip alternatively operated with reference signal from instead crystal. This input clock either fullswing digital signal VDD) sine wave maximum peak-peak amplitude. reference signal must connected XOSC_Q1 input. sine wave must connected XOSC_Q1 using serial capacitor. XOSC_Q2 line must left unconnected. C101 omitted when using reference signal.
External Match
balanced input output CC2500 share common pins designed simple, low-cost matching balun network printed circuit board. receive- transmit switching CC2500 front-end controlled dedicated on-chip function, eliminating need external RX/TXswitch. passive external components combined with internal RX/TX switch/termination circuitry ensures match both mode. Although CC2500 balanced input/output, chip connected single-ended antenna with external cost capacitors inductors. passive matching/filtering network connected CC2500 should have following differential impedance seen from RFport (RF_P RF_N) towards antenna: Zout ensure optimal matching CC2500 differential output highly recommended follow CC2500EM reference designs closely possible. Gerber files reference designs available download from Chipcon websites.
General Purpose Test Output Control Pins
three digital output pins GDO0, GDO1 GDO2 general control pins configured with IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG IOCFG2.GDO3_CFG respectively. Table shows different signals that monitored pins. These signals used interrupt MCU. GDO1 same interface, thus output programmed this will only valid when high. default value GDO1 3-stated, which useful when interface shared with other devices. default value GDO0 135-141 clock output (XOSC frequency divided 192). Since XOSC turned power-onreset, this used clock systems with only crystal. When running, change clock frequency writing IOCFG0.GDO0_CFG. on-chip analog temperature sensor enabled writing value (0x80h) IOCFG0.GDO0_CFG register. voltage GDO0 then proportional temperature. Section page temperature sensor specifications.
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
GDOx_CFG[5:0]]
(0x00) (0x01) (0x02) (0x03) (0x04) (0x05) (0x06) (0x07) (0x08) (0x09) (0x0A) (0x0B) (0x0C) (0x0D) (0x0E) (0x0F) (0x10) (0x11) (0x12) (0x13) (0x14) (0x15) (0x16) (0x17) (0x18) (0x19) (0x1A) (0x1B) (0x1C) (0x1D) (0x1E) (0x1F) (0x20) (0x21) (0x22) (0x23) (0x24) (0x25) (0x26) (0x27) (0x28) (0x29) (0x2A) (0x2B) (0x2C) (0x2D) (0x2E) (0x2F) (0x30) (0x31) (0x32) (0x33) (0x34) (0x35) (0x36) (0x37) (0x38) (0x39) (0x3A) (0x3B) (0x3C) (0x3D) (0x3E) (0x3F)
Description Associated with FIFO: Asserts when FIFO filled above RXFIFO_THR. De-asserts when FIFO drained below RXFIFO_THR. Associated with FIFO: Asserts when FIFO filled above RXFIFO_THR packet reached. De-asserts when FIFO empty. Associated with FIFO: Asserts when FIFO filled above TXFIFO_THR. De-asserts when FIFO below TXFIFO_THR. Associated with FIFO: Asserts when FIFO full. De-asserts when FIFO drained below TXFIFO_THR. Asserts when FIFO overflowed. De-asserts when FIFO been flushed. Asserts when FIFO underflowed. De-asserts when FIFO flushed. Asserts when sync word been sent received, de-asserts packet. will de-assert when optional address check fails FIFO overflows. will de-assert FIFO underflows. Asserts when packet been received with De-asserts when first byte read from FIFO. Only valid PKTCTRL0.CC2400_EN Preamble Quality Reached. Asserts when above programmed value. Clear channel assessment. High when RSSI level below threshold (dependent current CCA_MODE setting) Lock detector output. lock lock detector output positive transition constantly logic high. check lock lock detector output should used interrupt MCU. Serial Clock. Synchronous data synchronous serial mode. Data falling edge read rising edge SERIAL_CLK when GDOx_INV=0. Serial Synchronous Data Output (DO). Used synchronous serial mode. must read rising edge SERIAL_CLK when GDOx_INV=0. Data falling edge CC2500. Serial transparent Data Output. Used asynchronous serial mode. Carrier sense. High RSSI level above threshold. CRC_OK. last comparison matched. Cleared when entering/restarting mode. Only valid PKTCTRL0.CC2400_EN Reserved used test. Reserved used test. Reserved used test. Reserved used test. Reserved used test. Reserved used test. RX_HARD_DATA[1]. used together with RX_SYMBOL_TICK alternative serial output. RX_HARD_DATA[0]. used together with RX_SYMBOL_TICK alternative serial output. Reserved used test. Reserved used test. Reserved used test. PA_PD. Note: PA_PD will have same signal level SLEEP states. control external RX/TX switch applications where SLEEP state used recommended address (0x2F). LNA_PD. Note: LNA_PD will have same signal level SLEEP states. control external RX/TX switch applications where SLEEP state used recommended address (0x2F). RX_SYMBOL_TICK. used together with RX_HARD_DATA alternative serial output. Reserved used test. Reserved used test. Reserved used test. Reserved used test. Reserved used test. Reserved used test. WOR_EVNT0 WOR_EVNT1 Reserved used test. Reserved used test. Reserved used test. CHIP_RDY Reserved used test. XOSC_STABLE Reserved used test. GDO0_Z_EN_N. When this output GDO0 configured input (for serial data). High impedance (3-state) (HW1 achieved with _INV signal). used control external LNA/PA RX/TX switch. CLK_XOSC/1 CLK_XOSC/1.5 CLK_XOSC/2 CLK_XOSC/3 CLK_XOSC/4 CLK_XOSC/6 CLK_XOSC/8 Note: There pins, only CLK_XOSC/n selected output CLK_XOSC/12 time. CLK_XOSC/n monitored pins, other pins must configured values less than 0x30. GDO0 default value CLK_XOSC/192. CLK_XOSC/16 CLK_XOSC/24 CLK_XOSC/32 CLK_XOSC/48 CLK_XOSC/64 CLK_XOSC/96 CLK_XOSC/128 CLK_XOSC/192
Table GDOx signal selection
PRELIMINARY Data Sheet (Rev.1.2) SWRS040a Page
CC2500
Asynchronous Synchronous Serial Operation
Several features modes operation have been included CC2500 provide backward compatibility with previous Chipcon products other existing communication systems. systems, recommended built-in packet handling features, they give more robust communication, significantly offload microcontroller simplify software development. 29.1 Asynchronous operation backward compatibility with systems already using asynchronous data transfer from other Chipcon products, asynchronous transfer also included CC2500. When asynchronous transfer enabled, several support mechanisms that included CC2500 will disabled, such packet handling hardware, buffering FIFO asynchronous transfer mode does allow data whitener, interleaver FEC. Only FSK, GFSK supported asynchronous transfer. Setting PKTCTRL0.PKT_FORMAT enables asynchronous transparent (serial) mode. GDO0 used data input data). Data output GDO0, GDO1 GDO2. must control start stop transmit receive with STX, SIDLE strobes. CC2500 modulator samples level asynchronous input times faster than programmed data rate. timing requirement asynchronous stream that error period must less than eighth programmed data rate. 29.2 Synchronous serial operation Setting PKTCTRL0.PKT_FORMAT enables synchronous serial operation mode. this operational mode data must encoded (MDMCFG2.MANCHESTER_EN=0). synchronous serial operation mode, data transferred wire serial interface. CC2500 provides clock that used data data input line sample data data output line. Data input data) GDO0 pin. This will automatically configured input when active. data output pins; this IOCFG0.GDO0_CFG, IOCFG1.GDO1_CFG IOCFG2.GDO2_CFG fields. Preamble sync word insertion/detection active, dependent sync mode MDMCFG2.SYNC_MODE. preamble sync word disabled, other packet handler features should also disabled. must then handle preamble sync word insertion detection software. preamble sync word insertion/detection left packet handling features used. CC2500 will insert detect preamble sync word will only provide/get data payload. This equivalent recommended FIFO operation mode.
System considerations Guidelines
30.1 Regulations International regulations national laws regulate radio receivers transmitters. Short Range Devices (SRDs) license free operation allowed operate 2.45 bands worldwide. most important regulations (Europe), CFR47 part 15.247 15.249 (USA), ARIB STD-T66 (Japan). summary most important aspects these regulations found Application Note AN032 regulations license-free transceiver operation band, available from Chipcon websites. Please note that compliance with regulations dependent complete system performance. customer's responsibility ensure that system complies with regulations.
SWRS040a Page
PRELIMINARY Data Sheet (Rev.1.2)
CC2500
30.2 Frequency Hopping Channel Systems Multiapproximately smaller blanking interval than solution 30.3 Wideband Modulation Spread Spectrum Using
2.400 2.4835 band shared many systems both industrial, office home environments. therefore recommended frequency hopping spread spectrum (FHSS) multi-channel protocol because frequency diversity makes system more robust with respect interference from other systems operating same frequency band. FHSS also combats multipath fading.
CC2500 highly suited FHSS multichannel systems agile frequency synthesizer effective communication interface. Using packet handling support data buffering also beneficial such systems these features will significantly offload host controller.
Charge pump current, current capacitance array calibration data required each frequency when implementing frequency hopping CC2500. There ways obtaining calibration data from chip: Frequency hopping with calibration each hop. calibration time approximately Fast frequency hopping without calibration each done calibrating each frequency startup saving resulting FSCAL3, FSCAL2 FSCAL1 register values memory. Between each frequency hop, calibration process then replaced writing FSCAL3, FSCAL2 FSCAL1 register values corresponding next frequency. turn time approximately calibration single frequency startup. Next write FSCAL3[5:4] disable charge pump calibration. After writing FSCAL3[5:4] strobe STX) with MCSM0.FS_AUTOCAL each frequency hop. That current capacitance calibration done charge pump current calibration. When charge pump current calibration disabled calibration time reduced from approximately approximately There trade between blanking time memory space needed storing calibration data non-volatile memory. Solution above gives shortest blanking interval, requires more memory space store calibration values. Solution gives
Digital modulation systems under part 15.247 includes GFSK modulation. maximum peak output power (+30 dBm) allowed bandwidth modulated signal exceeds kHz. addition, peak power spectral density conducted antenna shall greater than band. Operating high data rates high frequency separation, CC2500 suited systems targeting compliance with digital modulation systems defined part 15.247. external power amplifier needed increase output above dBm. 30.4 Data Burst Transmissions high maximum data rate CC2500 opens burst transmissions. average data rate link (e.g. kbps), realized using higher over-the-air data rate. Buffering data transmitting bursts high data rate (e.g. kbps) will reduce time active mode, hence also reduce average current consumption significantly. Reducing time active mode will reduce likelihood collisions with other systems, e.g. WLAN. 30.5 Continuous Transmissions data streaming applications CC2500 opens continuous transmissions kbps effective data rate. modulation done with up-converter with I/Qsignals coming from closed loop PLL, there limitation length transmission. (Open loop modulation used some transceivers often prevents this kind continuous data streaming reduces effective data rate.) 30.6 Crystal Drift Compensation CC2500 very fine frequency resolution (see Table This feature used compensate frequency offset drift. frequency offset between `external' transmitter receiver measured CC2500 read back from
SWRS040a Page
PRELIMINARY Data Sheet (Rev.1.2)
CC2500
FREQEST status register described Section 14.1. measured frequency offset used calibrate frequency using `external' transmitter reference. That received signal device will match receiver's channel filter better. same centre frequency transmitted signal will match `external' transmitter's signal. 30.7 Spectrum Efficient Modulation achieved antenna topology, Figure HC-49 type crystal used CC2500EM reference design. Note that crystal package strongly influences price. size constrained design smaller, more expensive, crystal used. 30.9 Battery Operated Systems
CC2500 also possibility Gaussian shaped (GFSK). This spectrum-shaping feature improves adjacent channel power (ACP) occupied bandwidth. `true' systems with abrupt frequency shifting, spectrum inherently broad. making frequency shift `softer', spectrum made significantly narrower. Thus, higher data rates transmitted same bandwidth using GFSK.
30.8 Cost Systems CC2500 provides kbps multichannel performance without external filters, very cost system made. differential antenna will eliminate need balun, biasing
Antenna
power applications, SLEEP state with crystal oscillator core switched should used when CC2500 active. possible leave crystal oscillator core running SLEEP state start-up time critical. functionality should used power applications. 30.10 Increasing Output Power some applications necessary extend link range. Adding external power amplifier most effective doing this. power amplifier should inserted between antenna balun, switches needed disconnect mode. Figure
Filter
Balun
CC2500
switch
switch
Figure Block diagram CC2500 usage with external power amplifier
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Configuration Registers
configuration CC2500 done programming 8-bit registers. configuration data based selected system parameters most easily found using SmartRF® Studio software. Complete descriptions registers given following tables. After chip reset, registers have default values shown tables. There Command Strobe Registers, listed Table Accessing these registers will initiate change internal state mode. There normal 8-bit Configuration Registers, listed Table Many these registers test purposes only, need written normal operation CC2500. There also Status registers, which listed Table These registers, which
Address Strobe Name Description
read-only, contain information about status CC2500. FIFOs accessed through 8-bit register. Write operations write FIFO, while read operations read from FIFO. During address transfer while writing register FIFO, status byte returned. This status byte described Table page Table summarizes address space. address given adding base address left burst read/write bits top. Note that burst different meaning base addresses above below 0x2F.
0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x38 0x39 0x3A 0x3B 0x3C 0x3D
SRES SFSTXON SXOFF SCAL SIDLE SWOR SPWD SFRX SFTX SWORRST SNOP
Reset chip. Enable calibrate frequency synthesizer MCSM0.FS_AUTOCAL=1). (with CCA): wait state where only synthesizer running (for quick turnaround). Turn crystal oscillator. Calibrate frequency synthesizer turn (enables quick start). SCAL strobed IDLE state without setting manual calibration mode (MCSM0.FS_AUTOCAL=0) Enable Perform calibration first coming from IDLE MCSM0.FS_AUTOCAL=1. IDLE state: Enable Perform calibration first MCSM0.FS_AUTOCAL=1. state enabled: Only channel clear. Exit turn frequency synthesizer exit Wake-On-Radio mode applicable. Start automatic polling sequence (Wake-on-Radio) described Section 19.5. Enter power down mode when goes high. Flush FIFO buffer. Only issue IDLE, TXFIFO_UNDERFLOW RXFIFO_OVERFLOW states. Flush FIFO buffer. Only issue IDLE, TXFIFO_UNDERFLOW RXFIFO_OVERFLOW states. Reset real time clock. operation. used strobe commands bytes simpler software.
Table Command strobes
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Address Register Description Preserved SLEEP state Details page number
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E
IOCFG2 IOCFG1 IOCFG0 FIFOTHR SYNC1 SYNC0 PKTLEN PKTCTRL1 PKTCTRL0 ADDR CHANNR FSCTRL1 FSCTRL0 FREQ2 FREQ1 FREQ0 MDMCFG4 MDMCFG3 MDMCFG2 MDMCFG1 MDMCFG0 DEVIATN MCSM2 MCSM1 MCSM0 FOCCFG BSCFG AGCTRL2 AGCTRL1 AGCTRL0 WOREVT1 WOREVT0 WORCTRL FREND1 FREND0 FSCAL3 FSCAL2 FSCAL1 FSCAL0 RCCTRL1 RCCTRL0 FSTEST PTEST AGCTEST TEST2 TEST1 TEST0
GDO2 output configuration GDO1 output configuration GDO0 output configuration
FIFO FIFO thresholds Sync word, high byte Sync word, byte Packet length Packet automation control Packet automation control Device address Channel number Frequency synthesizer control Frequency synthesizer control Frequency control word, high byte Frequency control word, middle byte Frequency control word, byte Modem configuration Modem configuration Modem configuration Modem configuration Modem configuration Modem deviation setting Main Radio Control State Machine configuration Main Radio Control State Machine configuration Main Radio Control State Machine configuration Frequency Offset Compensation configuration Synchronization configuration control control control High byte Event timeout byte Event timeout Wake Radio control Front configuration Front configuration Frequency synthesizer calibration Frequency synthesizer calibration Frequency synthesizer calibration Frequency synthesizer calibration oscillator configuration oscillator configuration Frequency synthesizer calibration control Production test test Various test settings Various test settings Various test settings
Table Configuration registers overview
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Address Register Description Details page number
0x30 (0xF0) 0x31 (0xF1) 0x32 (0xF2) 0x33 (0xF3) 0x34 (0xF4) 0x35 (0xF5) 0x36 (0xF6) 0x37 (0xF7) 0x38 (0xF8) 0x39 (0xF9) 0x3A (0xFA) 0x3B (0xFB)
PARTNUM VERSION FREQEST RSSI MARCSTATE WORTIME1 WORTIME0 PKTSTATUS VCO_VC_DAC TXBYTES RXBYTES
CC2500 part number
Current version number Frequency Offset Estimate Demodulator estimate Link Quality Received signal strength indication Control state machine state High byte timer byte timer Current GDOx status packet status Current setting from calibration module Underflow number bytes FIFO Overflow number bytes FIFO
Table Status registers overview
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
Write Single byte +0x00 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Burst +0x40 Single byte +0x80 IOCFG2 IOCFG1 IOCFG0 FIFOTHR SYNC1 SYNC0 PKTLEN PKTCTRL1 PKTCTRL0 ADDR CHANNR FSCTRL1 FSCTRL0 FREQ2 FREQ1 FREQ0 MDMCFG4 MDMCFG3 MDMCFG2 MDMCFG1 MDMCFG0 DEVIATN MCSM2 MCSM1 MCSM0 FOCCFG BSCFG AGCCTRL2 AGCCTRL1 AGCCTRL0 WOREVT1 WOREVT0 WORCTRL FREND1 FREND0 FSCAL3 FSCAL2 FSCAL1 FSCAL0 RCCTRL1 RCCTRL0 FSTEST PTEST AGCTEST TEST2 TEST1 TEST0 SRES SFSTXON SXOFF SCAL SIDLE SWOR SPWD SFRX SFTX SWORRST SNOP PATABLE FIFO SRES SFSTXON SXOFF SCAL SIDLE SWOR SPWD SFRX SFTX SWORRST SNOP PATABLE FIFO PARTNUM VERSION FREQEST RSSI MARCSTATE WORTIME1 WORTIME0 PKTSTATUS VCO_VC_DAC TXBYTES RXBYTES Read Burst +0xC0
PATABLE FIFO
PATABLE FIFO
Table address space
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Command Strobes, Status registers (read only) multi byte registers
configuration registers, burst access possible
Page
CC2500
31.1 Configuration Register Details Registers with preserved values sleep state 0x00: IOCFG2 GDO2 output configuration
Field Name Reset Description
Reserved
(0x29) Invert output, i.e. select active high Default CHIP_RDY (see Table page 47).
GDO2_INV GDO2_CFG[5:0]
0x01: IOCFG1 GDO1 output configuration
Field Name Reset Description
GDO_DS
(0x2E)
high output drive strength pins. Invert output, i.e. select active high Default 3-state (see Table page
GDO1_INV GDO1_CFG[5:0]
0x02: IOCFG0 GDO0 output configuration
Field Name Reset Description
TEMP_SENSOR_ENABLE
(0x3F)
Enable analog temperature sensor. Write other register bits when using temperature sensor. Invert output, i.e. select active high Default CLK_XOSC/192 (see Table page 47).
GDO0_INV GDO0_CFG[5:0]
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
0x03: FIFOTHR FIFO FIFO thresholds
Field Name Reset Description
Reserved FIFO_THR[3:0]
(0111)
Write compatibility with possible future extensions threshold FIFO FIFO. threshold exceeded when number bytes FIFO equal higher than threshold value. Setting (0000) (0001) (0010) (0011) (0100) (0101) (0110) (0111) (1000) (1001) (1010) (1011) (1100) (1101) (1110) (1111) Bytes FIFO Bytes FIFO
0x04: SYNC1 Sync word, high byte
Field Name Reset Description
SYNC[15:8]
(0xD3)
16-bit sync word
0x05: SYNC0 Sync word, byte
Field Name Reset Description
SYNC[7:0]
(0x91)
16-bit sync word
0x06: PKTLEN Packet length
Field Name Reset Description
PACKET_LENGTH
(0xFF)
Indicates packet length when fixed length packets enabled. variable length packets used, this value indicates maximum length packets allowed.
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
0x07: PKTCTRL1 Packet automation control
Field Name Reset Description
PQT[2:0]
(000)
Preamble quality estimator threshold. preamble quality estimator increases internal counter each time received that different from previous bit, decreases counter each time received that same last bit. counter saturates threshold this counter used gate sync word detection. When PQT=0 sync word always accepted.
Reserved CRC_AUTOFLUSH
Enable automatic flush FIFO when This requires that only packet FIFO that packet length limited FIFO size.
PKTCTRL0.CC2400_EN must (default) autoflush function work correctly.
APPEND_STATUS When enabled, status bytes will appended payload packet. status bytes contain RSSI values, well flag. Controls address check configuration received packages. Setting (00) (01) (10) (11) Address check configuration address check Address check, broadcast Address check, (0x00) broadcast Address check, (0x00) (0xFF) broadcast
ADR_CHK[1:0]
(00)
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040a
Page
CC2500
0x08: PKTCTRL0 Packet automation control
Field Name Reset Description
Reserved WHITE_DATA
Turn data whitening Whitening Whitening Data whitening only used when PKTCTRL0.CC2400_EN (default).
PKT_FORMAT[1:0]
(00)
Format data Setting (00) (01) Packet format Normal mode, FIFOs Serial Synchronous mode, used backwards compatibility. Data GDO0 Random mode; sends random data using generator. Used test. Works normal mode, setting (00), Asynchronous transparent mode. Data GDO0 Data either pins
(10)
(11) CC2400_EN
Enable CC2400 support. same implementation CC2400.
PKTCTRL1.CRC_AUTOFLUSH must PKTCTRL0.CC2400_EN PKTCTRL0.WHITE_DATA must PKTCTRL0.CC2400_EN
CRC_EN calculation check enabled disabled LENGTH_CONFIG[1:0] (01) Configure packet length Setting (00) (01) (10) (11) Packet length configuration Fixed length packets, length configured PKTLEN register Variable length packets, packet length configured first byte after sync word Enable infinite length packets Reserved
0x09: ADDR Device address
Field Name Reset Description
DEVICE_ADDR[7:0]
(0x00)
Address used packet filtration. Optional broadcast addresses (0x00) (0xFF).<br
Other recent searches
SN74HC244 - SN74HC244 SN74HC244 Datasheet
SN54HC244 - SN54HC244 SN54HC244 Datasheet
SHD116036 - SHD116036 SHD116036 Datasheet
SHD116036B - SHD116036B SHD116036B Datasheet
S30VT80 - S30VT80 S30VT80 Datasheet
RP336LU - RP336LU RP336LU Datasheet
RP336LD - RP336LD RP336LD Datasheet
IPB120N06S4-H1 - IPB120N06S4-H1 IPB120N06S4-H1 Datasheet
IPI120N06S4-H1 - IPI120N06S4-H1 IPI120N06S4-H1 Datasheet
IPP120N06S4-H1 - IPP120N06S4-H1 IPP120N06S4-H1 Datasheet
EN8273A - EN8273A EN8273A Datasheet
LA5771MP - LA5771MP LA5771MP Datasheet
1N5400 - 1N5400 1N5400 Datasheet
1N5408 - 1N5408 1N5408 Datasheet
Privacy Policy | Disclaimer
© 2013 Datasheets.org.uk