CA3282
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CA3282
Octal Side Power Driver with Serial Control
CA3282 logic controlled, eight channel octal power driven. serial peripheral interface (SPI) utilized CA3282 serial synchronous compatible with Intersil CDP68HC05, equivalent, microcomputers. shown Block Diagram CA3282 each open drain NDMOS output drivers individual protection overvoltage over-current. Each output channel separate output latch control with fault unlatch diagnostic feedback. Under normal conditions, each output driver low, saturation state. Comparators diagnostic circuitry monitor output drivers determine saturation condition exists. comparator senses fault, respective output driver unlatched. addition, over current protection provided with current limiting each output, independent diagnostic feedback loop. CA3282 fabricated Power BiMOS process, intended automotive other applications having wide range temperature electrical stress conditions. particularly suited driving lamps, relays, solenoids applications where operating power, high breakdown voltage, high output current high temperatures required. CA3282 supplied lead plastic package with lead forms either vertical surface mount.
June 1998
Features
Output Current Drive Capability Outputs Equal 0.625A Each Output Individually Each Maximum Total Outputs High Voltage Power BiMOS Outputs Open Drain NDMOS Drivers Individual Output Latch Over-Current Limit Protection 1.05A Over-Voltage Clamp Protection High Speed CMOS Logic Control Quiescent Current Controlled Interface Individual Fault Unlatch Feedback Common Reset Line Operating Temperature Range -40oC 125oC
Applications
Automotive Industrial Systems Solenoids, Relays Lamp Drivers Logic Controlled Drivers Robotic Controls
Ordering Information
PART NUMBER CA3282AS1 CA3282AS2 TEMP. RANGE(oC) PACKAGE LEAD FORM Plastic Staggered Vertical Plastic Surface Mount Z15.05A Z15.05B
Pinout
CA3282 (SIP) VIEW
OUTPUT OUTPUT OUTPUT OUTPUT RESET
MISO MOSI
Block Diagram
OUTPUT
NOTE: HEAT SINK INTERNALLY CONNECTED GROUND (VSS)
MOSI MISO RESET
INTERFACE CIRCUIT
SHIFT REGISTER
OUTPUT LATCH CURRENT LIMIT
OUTPUT OUTPUT OUTPUT OUTPUT
CONTROL LOGIC
DIAGNOSTIC CIRCUITRY
DRIVERS THRU
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. Rights Reserved
File Number
2767.6
CA3282
Absolute Maximum Ratings
Output Voltage, (Note (Clamp) Output Load Current, ILOAD (Per Output, Individual) Output Load Current, ILOAD (All Outputs Equal IOUT) 0.625A Output Load Current, ILOAD (Max. Total Outputs 5.0A Logic Supply, Input Voltage, .-0.7
Thermal Information
Thermal Resistance (Typical, Note Plastic Heat Sink Infinite Heat Sink Power Dissipation JA(oC/W) JC(oC/W)
Operating Conditions
Ambient Temperature Range -40oC 125oC Junction Temperature Range -40oC 150oC
125oC Heat Sink 0.56W Above 125oC Heat Sink .Derate Linearly 22mW/oC 125oC w/Infinite Heat Sink. 8.33W Above 125oC w/Infinite Heat Sink Derate Linearly 333mW/oC Maximum Storage Temperature Range -55oC 150oC Maximum Lead Temperature (Soldering, 10s). 265oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: MOSFET Output Drain internally clamped with Drain-to-Gate zener diode that turns-on MOSFET; holding Drain Output Clamp Voltage, VOC. measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER Quiescent Supply Current, Quiescent Supply Current, Output Clamping Voltage Output Clamping Energy Output Leakage Current
-40oC 125oC, Unless Otherwise Specified SYMBOL LEAK TEST CONDITIONS Outputs 0.5A Load Output Outputs ILOAD 0.5A, Output Programmed ILOAD 0.5A, Output Output Programmed 1.05 1000 UNITS
Output Resistance Output Current Limit Turn-On Delay Turn-Off Delay Fault Reference Voltage Fault Reset Delay (After High Transition) Output Voltage LOGIC INPUTS
rDS(ON) LIMIT tPHL tPLH VOREF VOFF
ILOAD 0.5A (Note Output Programmed VOUT 500mA, Reactive Load 500mA, Reactive Load Output Programmed Fault Detected VOREF Figure Output Programmed OFF, Output Floating
(MOSI, RESET) VTVT+ (MISO) 1.6mA 0.8mA 1.3V 0.2V VTVDD 5.5V, 0.2VDD 0.85 0.3VDD 0.6VDD 0.7VDD 2.25
Threshold Voltage Falling Edge Threshold Voltage Rising Edge Hysteresis Voltage Input Current Input Capacitance LOGIC OUTPUT
Output Voltage Output HIGH Voltage
CA3282
Electrical Specifications
PARAMETER Output Three State Leakage Current Output Capacitance -40oC 125oC, Unless Otherwise Specified (Continued) SYMBOL COUT TEST CONDITIONS 5.25V, Held High VDD, Held High UNITS
Serial Peripheral Interface Timing
PARAMETER Operating Frequency Enable Lead Time Enable Time Clock HIGH Time Clock Time Data Setup Time Data Hold Time Enable Time Disable Time Data Valid Time Output Data Hold Time Rise Time (MISO Output) Rise Time Inputs (SCK, MOSI, Fall Time (MISO Output) Fall Time Inputs (SCK, MOSI, NOTES:
(See Figure SYMBOL fOPER (10) (11) (12) (12) (13) (13) tLEAD tLAG twSCK
TEST CONDITIONS
D.C.
Note <100 <100
UNITS
twSCK
tDIS trSO trSI tfSO tfSI 70%, 200pF 70%, 200pF 20%, 200pF 20%, 200pF
Refer Figure IOUT current VSAT voltage. Typical rDS(ON) values given -40oC, 25oC, 105oC 125oC temperatures. Maximum Operating Frequency typically greater than 10MHz application limited primarily external input rise/fall times MISO output loading.
Timing Diagrams
(CPOL CPHA
INTERNAL STROBE DATA CAPTURE
FIGURE DATA CLOCK TIMING DIAGRAM
CA3282 Timing Diagrams
(INPUT) (INPUT) LAST TRANSMITTED (13) (12)
(Continued)
MISO (OUTPUT)
HIGH
(10)
(11)
FAULT-INDUCED TURN-OFF
MOSI (INPUT)
DRIVER OUTPUT
tPHL tPLH
FIGURE
TIMING DIAGRAM
RESET
MOSI
MISO
OUTPUTS
FAULTS
RESET
FIGURE BYTE TIMING DIAGRAM WITH ASYNCHRONOUS RESET
Signal Descriptions
Power Output Drivers, Output Output input output bits corresponding Output thru Output transmitted received most significant (MSB) first bus. outputs provided with current limiting voltage sense functions fault indication protection. nominal load current these outputs 500mA, with current limiting minimum 1.05A. on-chip clamp circuit capable handling 500mA provided each output clamping inductive loads. RESET Active reset input. When this input line low, shift register output latches configured turn
output drivers. power clear function implemented connecting this with external resistor, with external capacitor. case, this must left floating. Active chip enable. Data transferred from shift register outputs rising edge this signal. falling edge loads shift register with output voltage sense bits coming from output stages. output driver MISO enabled when this low. must logic prior first serial clock (SCK) must remain until after last (eighth) serial clock cycle. level also activates internal disable circuit used unlatching output states that fault mode
CA3282
sensed saturation condition. high forces MISO high impedance state. Also, when high, octal driver ignores MOSI signals. SCK, MISO, MOSI Serial Peripheral Interface (SPI) section this data sheet. (GND) Positive negative power supply lines. Serial Peripheral Interface (SPI) Serial Peripheral Interface (SPI) utilized CA3282 serial synchronous control data transfers. Clock (SCK), which generated microcomputer, active only during data transfers. systems using CDP68HC05 family microcomputers, inactive clock polarity determined CPOL microcomputer's control register. CPOL used conjunction with clock phase bit, CPHA produce desired clock data relationship between microcomputer octal driver. CPHA general selects clock edge which captures data allows change states. CA3282, CPOL must logic zero CPHA logic one. Configured this manner, MISO (output) data will appear with every rising edge SCK, MOSI (input) data will latched into shift register with every falling edge SCK. Also, steady state value inactive serial clock, SCK, will level. Timing diagrams serial peripheral interface shown Figure Signal Descriptions MOSI (Master Out/Slave Serial data input. Data bytes shifted this pin, most significant (MSB) first. data passed directly shift register which turn controls latches output drivers. logic this will program corresponding output logic will turn OFF. MISO (Master In/Slave Out) Serial data output. Data bytes shifted this pin, most significant (MSB) first. This serial output from shift register three stated when high. high data this indicates that corresponding output high. this data indicates that output low. Comparing serial output bits with previous input bits, microcomputer implements diagnostic data supplied CA3282. Serial clock input. This signal clocks shift register MOSI (input) data will latched into shift register every falling edge SCK. phase bit, CPHA, polarity bit, CPOL, must respectively microcomputer's control register. Serial Peripheral Interface (SPI) protocol. Each channel independently controlled output latch common RESET line that disables eight outputs. Byte timing with asynchronous reset shown Figure circuit receives 8-bit serial data means serial input (MOSI), stores this data internal register control output drivers. serial output (MISO) provides 8-bit diagnostic data representing voltage level driver output. This allows microcomputer diagnose condition output drivers. device selected when chip enable (CE) line low. When (CE) high, device deselected serial output (MISO) placed threestate mode. device shifts serial data rising edge serial clock (SCK), latches data falling edge. rising edge chip enable (CE), input data from shift register latched output drivers. falling edge chip enable (CE) transfers output drivers fault information back shift register. output drivers have voltage rated current, monitored comparator saturation condition, which case output driver with fault becomes unlatched diagnostic data sent microcomputer MISO line. typical microcomputer interface circuit shown Figure Also, CA3282 cascaded with another CA3282 octal driver. Shift Register shift register both serial parallel inputs outputs. Serial output input data simultaneously transferred from bus. parallel outputs latched into output latch CA3282 data transfer. parallel inputs diagnostic data into shift register beginning data transfer cycle.
CDP68HC05C4 MICROCOMPUTER PORT MOSI MISO RESET MOSI MISO
CA3282
RESET
FIGURE TYPICAL MICROCOMPUTER INTERFACE WITH CA3282
Output Latch output latch holds input data from shift register which used activate outputs. latch circuit cleared fault condition protect overloaded outputs), RESET signal.
Functional Descriptions
CA3282 operating power, high voltage, high current, octal power driver featuring eight channels open drain NDMOS output drivers. drivers have saturation voltage output short circuit protection, suited driving resistive inductive loads such lamps, relays solenoids. Data transmitted device serially using
CA3282
Output Drivers output drivers provide active output 500mA nominal with current limiting 1.05A allow high inrush currents. addition, each output provided with voltage clamp circuit limit inductive transients. Each output driver also monitored comparator saturation condition. output voltage output exceeds saturation voltage limit, fault condition assumed latch driving this output reset, turning output off. output comparators, which also provide diagnostic feedback data shift register, contain internal pull-down current which will cause cell indicate output voltage output programmed output open circuited. High Transition When three state MISO enabled. falling edge diagnostic data from output voltage comparators will latched into shift register. output high, logic will loaded into that shift register. output low, logic zero will loaded. During time that low, data bytes controlling output drivers shifted MOSI most significant (MSB) first. logic zero this will program corresponding output logic will turn OFF. High Transition When last data been shifted into CA3282, should pulled high. rising edge shift register data latched into output latch outputs activated with data. internal 150µs delay timer will start this rising edge compensate high inrush currents lamps inductive loads. During this period, outputs will protected only analog current limiting circuits since resetting output latches fault conditions will inhibited during this time. This allows device handle inrush currents immediately after turn When 150µs delay elapsed, output voltages sensed comparators saturation outputs latched off. serial clock input (SCK) should during transitions avoid false clocking shift register. input gated that input ignored when high. Detecting Fault Conditions Fault conditions checked follows. Clock control byte wait approximately 150µs allow outputs settle. Clock same control byte note diagnostic data output MISO pin. diagnostic bits should identical data clocked differences will indicate fault corresponding outputs. example, output programmed clocking zero, corresponding diagnostic that output one, indicating driver output still high, then short circuit overload condition have caused output unlatch. Alternatively, output programmed clocking one, diagnostic that output
CURRENT AMPERES (IOUT)
shows zero, then probable cause open circuit resulting floating output.
rDS(ON) 0.48 CURRENT AMPERES (IOUT) rDS(ON) 0.54 rDS(ON) 0.67 rDS(ON) 0.78
SATURATION VOLTAGE (VSAT)
FIGURE CA3282 TYPICAL OUTPUT DRIVER rDS(ON) CHARACTERISTICS CURRENT SATURATION VOLTAGE, VSAT -40oC 125oC JUNCTION TEMPERATURE
CURRENT LIMITING
-40oC 25oC 105oC 125oC
SATURATION VOLTAGE (VSAT)
FIGURE CA3282 TYPICAL OUTPUT DRIVER rDS(ON) CHARACTERISTICS CURRENT SATURATION VOLTAGE, VSAT -40oC 125oC JUNCTION TEMPERATURE
Dissipation Multiple Outputs
CA3282 Octal Power Driver multiple Output Drivers requires special consideration with regard maximum current dissipation ratings. While each output maximum current specification consistent with device structure, such devices chip simultaneously rated same high level peak current. total combined current dissipation chip must adjusted maximum allowable ratings, given simultaneous multiple output conditions.
CA3282
CA3282, maximum positive output current rating when output When outputs rating reduced 0.625A because total maximum current limited given application, output drivers chip have different level loading. discussion here intended provide relatively simple methods determine maximum dissipation current ratings general solution and, special solution, when switched outputs have same current loading. General Solution general equation dissipation should specify that total power dissipation package significant elements dissipation chip. However, Power BiMOS Circuits very little dissipation needed control logic predriver circuits chip. over-all chip dissipation primarily dissipation losses each channel where current, output current resistance, NMOS channel resistance, rDS(ON) each output driver. such, total dissipation, output drivers
Equation Equation expressed
(EQ.
(EQ.
Integrated Circuit packages have directly definable case temperature because heat spread thru lead frame Board which effective heat sink. Calculation Example CA3282, 3oC/W worst case junction temperature, application design solution, should exceed 150oC. given application, Equation determines dissipation, Assume package mounted heat sink having thermal resistance 6oC/W and, given application, dissipation, Assume operating ambient temperature, 100oC. calculated Junction-to-Ambient thermal resistance
9oC/W
(EQ.
This expression sums dissipation, each output driver without regard uniformity dissipation each channel. dissipation loss NMOS channel
(EQ.
solution junction temperature Equation
100oC 9oC/W 127oC
Calculation Example Using CA3282 maximum Junction-to-Ambient Thermal Resistance, value 45oC/W external heat sink) worst case Junction Temperature, 150oC have application design solution maximum ambient temperature dissipation. example; Using Equation assuming device dissipation, maximum allowable Ambient Temperature, from Equation calculated follows:
150oC 1.0W 45oC/W 105oC
where current, determined output load when channel turned channel resistance, rDS(ON) function circuit design, level gate voltage chip temperature. Refer Electrical Specifications values worse case channel resistance. temperature rise package dissipation product on-chip dissipation, package Junction-to-Case thermal resistance, determine junction temperature, given case (heat sink tab) temperature, linear heat flow solution
(EQ.
Equal Current Loading Solution Where given application equal current loading output drivers, equal rDS(ON) temperature conditions assumed. such, convenient method show rating boundaries substitute dissipation Equation into junction temperature Equation outputs that with equal currents, where have following solution dissipation:
(EQ.
(EQ.
Since this solution relates only package, further consideration must given practical heat sink. equation linear heat flow assumes that Junction-toAmbient thermal resistance, thermal resistance from Junction-to-Case thermal resistance from Case (heat sink)-to-Ambient, Junction-toAmbient thermal resistance, thermal paths from chip junction ambient temperature (TA) environment expressed
(EQ.
(EQ.
CA3282
number output drivers conducting from (i.e., output drivers conducting, Maximum temperature, dissipation current ratings must observed. drain current case temperature plotted value from provided drain currents remain equal. curve Figure illustrates boundary limits temperature dissipation. Figure shows maximum current outputs with equal current plotted versus Case Temperature, Boundary conditions relate Absolute Maximum Ratings defined data sheet.
DISSIPATION WATTS AMBIENT TEMPERATURE (oC) CA3282 WITH HEAT SINK 45oC/W) CA3282 WITH EXT. 6oC/W HEAT SINK 9oC/W) CA3282 WITH INFINITE HEAT SINK 3oC/W)
FIGURE DISSIPATION DERATING CURVE
MAX. DRIVE CURRENT, OUTPUTS (WITH EQUAL CURRENT)
MAX. CURRENT LIMITED (0.625A TOTAL CURRENT) IMAX DISSIPATION LIMITED
rDS(ON) THERMAL RESISTANCE, 3oC/W
CASE TEMPERATURE (oC)
FIGURE CURRENT CASE (TAB) TEMPERATURE, OUTPUTS WITH EQUAL CURRENT
CA3282 Single-In-Line Plastic Packages (SIP)
-XSEE DETAIL
Z15.05A (JEDEC MO-048 ISSUE
LEAD PLASTIC SINGLE-IN-LINE PACKAGE STAGGERED VERTICAL LEAD FORM INCHES SYMBOL 0.172 0.024 0.014 0.778 0.684 0.416 0.182 0.031 0.024 0.798 0.694 0.426 MILLIMETERS 4.37 0.61 0.36 19.76 17.37 10.57 4.62 0.79 0.61 20.27 17.63 10.82
-YL1
TERMINAL
TERMINAL
0.010(0.25) 0.024(0.61) LEADS
0.110 0.050 0.200 0.169 0.700 0.057 0.150 0.690 0.148 0.065 0.152 0.080 0.063 0.176 0.710
2.79 1.27 5.08 4.29 17.78 1.45 3.81 17.53 3.76 1.65 3.86 2.03 Rev. 4/98 1.60 4.47 18.03
0.015(0.38)
DETAIL
NOTES: Refer series symbol list, JEDEC Publication Dimensioning Tolerancing ANSI Y14.5M-1982. number terminals. Controlling dimension: INCH.
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
CA3282 Single-In-Line Plastic Packages (SIP)
Z15.05B
LEAD PLASTIC SINGLE-IN-LINE PACKAGE SURFACE MOUNT "GULLWING" LEAD FORM INCHES SYMBOL
MILLIMETERS 4.37 0.61 0.46 19.76 17.37 10.57 4.62 0.79 0.61 20.27 17.63 10.82 2.79 1.27 17.78 1.45 1.66 2.49 1.60 2.03 2.74
0.172 0.024 0.018 0.778 0.684 0.416
0.182 0.031 0.024 0.798 0.694 0.426
SURFACES
0.110 0.050 0.700 0.057 0.065 0.098 0.148 0.065 0.152 0.080 3.76 1.65 0.063 0.080 0.108
0.010
0.004 0.008 (NOTE
LEAD TIPS
3.86 2.03 Rev. 11/97
HEADER BOTTOM
NOTES: Dimensioning Tolerancing ANSI Y14.5M 1982. number terminals. lead surfaces within 0.004 inch each other. lead more than 0.004 inch above below header plane, Datum).
BOTTOM VIEW
Controlling dimension: INCH.
0.814 0.407 0.150
LAND PATTERN
0.130
0.700 0.662 0.774
0.050
0.030
0.350 0.700
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