ARM920TTM ISO7816
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Incorporates ARM920TARM® Thumb® Processor
MIPS MHz, Memory Management Unit 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer In-circuit Emulator including Debug Communication Channel Mid-level Implementation Embedded Trace Macrocell (256-ball Package Only) Power: VDDCORE 24.4 Normal Mode, Standby Mode Additional Embedded Memories Bytes SRAM 128K Bytes External Interface (EBI) Supports SDRAM, Static Memory, Burst Flash, Glueless Connection CompactFlash® NAND Flash/SmartMediaSystem Peripherals Enhanced Performance: Enhanced Clock Generator Power Management Controller On-chip Oscillators with PLLs Very Slow Clock Operating Mode Software Power Optimization Capabilities Four Programmable External Clock Signals System Timer Including Periodic Interrupt, Watchdog Second Counter Real-time Clock with Alarm Interrupt Debug Unit, Two-wire UART Support Debug Communication Channel Advanced Interrupt Controller with 8-level Priority, Individually Maskable Vectored Interrupt Sources, Spurious Interrupt Protected Seven External Interrupt Sources Fast Interrupt Source Four 32-bit Controllers with Programmable Lines, Input Change Interrupt Open-drain Capability Each Line 20-channel Peripheral Controller (PDC) Ethernet 10/100 Base-T Media Independent Interface (MII) Reduced Media Independent Interface (RMII) Integrated 28-byte FIFOs Dedicated Channels Receive Transmit Full Speed Mbits second) Host Double Port Dual On-chip Transceivers (Single Port Only 208-lead PQFP Package) Integrated FIFOs Dedicated Channels Full Speed Mbits second) Device Port On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs Multimedia Card Interface (MCI) Automatic Protocol Control Fast Automatic Data Transfers Memory Card-compliant, Supports Memory Cards Three Synchronous Serial Controllers (SSC) Independent Clock Frame Sync Signals Each Receiver Transmitter Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) Support ISO7816 T0/T1 Smart Card Hardware Handshaking RS485 Support, IrDA Kbps Full Modem Control Lines USART1 Master/Slave Serial Peripheral Interface (SPI) 16-bit Programmable Data Length, External Peripheral Chip Selects 3-channel, 16-bit Timer/Counters (TC) Three External Clock Inputs, Multi-purpose Pins Channel Double Generation, Capture/Waveform Mode, Up/Down Capability Two-wire Interface (TWI) Master Mode Support, 2-wire Atmel EEPROMs Supported IEEE 1149.1 JTAG Boundary Scan Digital Pins Power Supplies 1.65V 1.95V VDDCORE, VDDOSC VDDPLL 3.0V 3.6V VDDIOP (Peripheral I/Os) VDDIOM (Memory I/Os)Available 208-lead PQFP 256-ball Package
ARM920TTMbased Microcontroller AT91RM9200
Rev. 1768E-ATARM-30-Sep-05
Description
AT91RM9200 complete system-on-chip built around ARM920T Thumb processor. incorporates rich system application peripherals standard interfaces order provide single-chip solution wide range compute-intensive applications that require maximum functionality minimum power consumption lowest cost. AT91RM9200 incorporates high-speed on-chip SRAM workspace, low-latency External Interface (EBI) seamless connection whatever configuration off-chip memories memory-mapped peripherals required application. incorporates controllers synchronous DRAM (SDRAM), Burst Flash Static memories features specific circuitry facilitating interface NAND Flash/SmartMedia Compact Flash. Advanced Interrupt Controller (AIC) enhances interrupt handling performance ARM920T processor providing multiple vectored, prioritized interrupt sources reducing time taken transfer interrupt handler. Peripheral Controller (PDC) provides channels serial peripherals, enabling them transfer data from off-chip memories without processor intervention. This reduces processor overhead when dealing with transfers continuous data streams.The AT91RM9200 benefits from generation which includes dual pointers that simplify significantly buffer chaining. Parallel (PIO) controllers multiplex peripheral input/output lines with generalpurpose data I/Os maximum flexibility device configuration. input change interrupt, open drain capability programmable pull-up resistor included each line. Power Management Controller (PMC) keeps system power consumption minimum selectively enabling/disabling processor various peripherals under software control. uses enhanced clock generator provide selection clock signals including slow clock kHz) optimize power consumption performance times. AT91RM9200 integrates wide range standard interfaces including Full Speed Host Device Ethernet 10/100 Base-T Media Access Controller (MAC), which provides connection extensive range external peripheral devices widely used networking layer. addition, provides extensive peripherals that operate accordance with several industry standards, such those used audio, telecom, Flash Card, infrared Smart Card applications. complete offer, AT91RM9200 benefits from integration wide range debug features including JTAG-ICE, dedicated UART debug channel (DBGU) embedded real time trace. This enables development debug applications, especially those with real-time constraints.
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
Block Diagram
Bold arrows Figure 2-1. AT91RM9200 Block Diagram
NRST JTAGSEL NTRST Reset Test JTAG Scan
Instruction Cache bytes Data Cache bytes
indicate master-to-slave dependency.
TST0-TST1
ARM920T Core
E
TSYNC TCLK TPS0 TPS2 TPK0 TPK15
IRQ0-IRQ6 PCK0-PCK3 PLLRCB PLLRCA XOUT
Fast SRAM bytes
Address Decoder Abort Status
CompactFlash NAND Flash SmartMedia
PLLB PLLA Peripheral Bridge System Timer Peripheral Controller Fast 128K bytes
Misalignment Detector Arbiter
SDRAM Controller
XIN32 XOUT32 DRXD DTXD
Memory Controller
DBGU
Static Memory Controller
PIOA/PIOB/PIOC/PIOD Controller FIFO Host FIFO Transceiver
Burst Flash Controller
D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15/A18-A22 A16/BA0 A17/BA1 NCS0/BFCS NCS1/SDCS NCS2 NCS3/SMCS NRD/NOE/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS-CAS SDWE SDA10 BFRDY/SMOE BFCK BFAVD BFBAA/SMWE BFOE BFWE A23-A24 A25/CFRNW NWAIT NCS4/CFCS NCS5/CFCE1 NCS6/CFCE2 NCS7 D16-D31 HDMA HDPA HDMB HDPB
Transceiver
Device FIFO ETXCK-ERXCK-EREFCK ETXEN-ETXER ECRS-ECOL ERXER-ERXDV ERX0-ERX3 ETX0-ETX3 EMDC EMDIO EF100 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TCLK3 TCLK4 TCLK5 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5
MCCK MCCDA MCDA0-MCDA3 MCCDB MCDB0-MCDB3 RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DSR1 DTR1 DCD1 RXD2 TXD2 SCK2 RTS2 CTS2 RXD3 TXD3 SCK3 RTS3 CTS3 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK
Ethernet 10/100
USART0 USART1 SSC1 SSC0
USART2
SSC2
USART3
Timer Counter
Timer Counter
TWCK
1768E-ATARM-30-Sep-05
This section presents features each block.
ARM920T Processor
ARM9TDMITM-based ARM® Architecture instruction sets ARM® High-performance 32-bit Instruction Thumb® High Code Density 16-bit Instruction 5-Stage Pipeline Architecture: Instruction Fetch Instruction Decode Execute Data Memory Register Write 16-Kbyte Data Cache, 16-Kbyte Instruction Cache Virtually-addressed 64-way Associative Cache words line Write-though write-back operation Pseudo-random Round-robin replacement Low-power implementation Write Buffer 16-word Data Buffer 4-address Address Buffer Software Control Drain Standard ARMv4 Memory Management Unit (MMU) Access permission sections Access permission large pages small pages specified separately each quarter pages embedded domains Entry Instruction Entry Data 16-, 32-bit Data Instructions Data
Debug Test
Integrated Embedded In-Circuit-Emulator Debug Unit Two-pin UART Debug Communication Channel Chip Register Embedded Trace Macrocell: ETM9 Rev2a Medium Level Implementation Half-rate Clock Mode
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
Four Pairs Address Comparators Data Comparators Eight Memory Decoder Inputs Counters Sequencer 18-byte FIFO IEEE1149.1 JTAG Boundary Scan Digital Pins
Boot Program
Default Boot Program stored ROM-based products Downloads runs application from external storage media into internal SRAM Downloaded code size depends embedded SRAM size Automatic detection valid application Bootloader supporting wide range non-volatile memories DataFlash® connected NPCS0 Two-wire EEPROM 8-bit parallel memories NCS0 Boot Uploader case valid program detected external supporting several communication media Serial communication DBGU (XModem protocol) Device Port (DFU Protocol)
Embedded Software Services
Compliant with ATPCS Compliant with AINSI/ISO Standard Compiled ARM/Thumb Interworking Entry Service Tempo, Xmodem DataFlash services Sine tables
Reset Controller
reset input lines (NRST NTRST) providing, respectively: Initialization User Interface registers (defined user interface each peripheral) and: Sample signals needed bootup Compel processor fetch next instruction address zero. Initialization embedded controller.
Memory Controller
Programmable Arbiter handling four Masters Internal shared ARM920T, PDC, Host Port Ethernet Masters
1768E-ATARM-30-Sep-05
Each Master assigned priority between Address Decoder provides selection Eight external 256-Mbyte memory areas Four internal 1-Mbyte memory areas 256-Mbyte embedded peripheral area Boot Mode Select Option Non-volatile Boot Memory internal external Selection made sampled reset Abort Status Registers Source, Type parameters access leading abort saved Misalignment Detector Alignment checking data accesses Abort generation case misalignment Remap command Provides remapping internal SRAM place boot
External Interface
Integrates three External Memory Controllers: Static Memory Controller SDRAM Controller Burst Flash Controller Additional logic NAND Flash/SmartMedia CompactFlash support Optimized External Bus: 32-bit Data 26-bit Address Bus, 64-Mbytes addressable Chip Selects, each reserved eight Memory Areas Optimized multiplexing reduce latencies External Memories Configurable Chip Select Assignment: Burst Flash Controller Static Memory Controller NCS0 SDRAM Controller Static Memory Controller NCS1 Static Memory Controller NCS3, Optional NAND Flash/SmartMedia Support Static Memory Controller NCS4 NCS6, Optional CompactFlash Support Static Memory Controller NCS7
Static Memory Controller
External memory mapping, 512-Mbyte address space Chip Select Lines 16-bit Data Remap Boot Memory Multiple Access Modes supported Byte Write Byte Select Lines
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
different Read Protocols each Memory Bank Multiple device adaptability Compliant with Module Programmable Setup Time Read/Write Programmable Hold Time Read/Write Multiple Wait State Management Programmable Wait State Generation External Wait Request Programmable Data Float Time
SDRAM Controller
Numerous configurations supported Address Memory Parts SDRAM with four Internal Banks SDRAM with 32-bit Data Path Programming facilities Word, half-word, byte access Automatic page break when Memory Boundary been reached Multibank Ping-pong Access Timing parameters specified software Automatic refresh operation, refresh rate programmable Energy-saving capabilities Self-refresh Low-power Modes supported Error detection Refresh Error Interrupt SDRAM Power-up Initialization software Latency clocks (CAS Latency Supported) Auto Precharge Command used
3.10
Burst Flash Controller
Multiple Access Modes supported Asynchronous Burst Mode Byte, Half-word Word Read Accesses Asynchronous Mode Half-word Write Accesses Adaptability different device speed grades Programmable Burst Flash Clock Rate Programmable Data Access Time Programmable Latency after Output Enable Adaptability different device access protocols interfaces Burst Read Protocols: Clock Control Address Advance Signal Controlled Address Advance Multiplexed separate address data buses
1768E-ATARM-30-Sep-05
Continuous Burst Page Mode Accesses supported
3.11
Peripheral Controller (PDC)
Generates transfers to/from peripherals such DBGU, USART, SSC, Twenty channels Master Clock cycle needed transfer from memory peripheral Master Clock cycles needed transfer from peripheral memory
3.12
Advanced Interrupt Controller
Controls interrupt lines (nIRQ nFIQ) ARM® Processor Thirty-two individually maskable vectored interrupt sources Source reserved Fast Interrupt Input (FIQ) Source reserved system peripherals (ST, RTC, PMC, DBGU.) Source Source control thirty embedded peripheral interrupts external interrupts Programmable Edge-triggered Level-sensitive Internal Sources Programmable Positive/Negative Edge-triggered High/Low Level-sensitive External Sources 8-level Priority Controller Drives Normal Interrupt processor Handles priority interrupt sources Higher priority interrupts served during service lower priority interrupt Vectoring Optimizes Interrupt Service Routine Branch Execution 32-bit Vector Register interrupt source Interrupt Vector Register reads corresponding current Interrupt Vector Protect Mode Easy debugging preventing automatic operations General Interrupt Mask Provides processor synchronization events without triggering interrupt
3.13
Power Management Controller
Optimizes power consumption whole system Embeds controls: Main Oscillator Slow Clock Oscillator (32.768Hz) Phase Locked Loops (PLLs) Dividers Clock Prescalers Provides: Processor Clock Master Clock Clocks, UHPCK UDPCK, respectively Host Port Device Port
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
Programmable automatic switch-off Device suspend conditions thirty peripheral clocks four programmable clock outputs PCK0 PCK3 Four operating modes: Normal Mode, Idle Mode, Slow Clock Mode, Standby Mode
3.14
System Timer
Period Interval Timer, 16-bit programmable counter Watchdog Timer, 16-bit programmable counter Real-time Timer, 20-bit free-running counter Interrupt Generation event
3.15
Real Time Clock
power consumption Full asynchronous design hundred year calendar Programmable Periodic Interrupt Alarm update parallel load Control alarm update Time/Calendar Data
3.16
Debug Unit
System peripheral facilitate debug Atmel's ARM®-based systems Composed following functions Two-pin UART Debug Communication Channel (DCC) support Chip Registers Two-pin UART Implemented features 100% compatible with standard Atmel USART Independent receiver transmitter with common programmable Baud Rate Generator Even, Odd, Mark Space Parity Generation Parity, Framing Overrun Error Detection Automatic Echo, Local Loopback Remote Loopback Channel Modes Interrupt generation Support channels with connection receiver transmitter Debug Communication Channel Support Offers visibility COMMRX COMMTX signals from Processor Interrupt generation Chip Registers Identification device revision, sizes embedded memories, peripherals
1768E-ATARM-30-Sep-05
3.17
Controller
programmable Lines Fully programmable through Set/Clear Registers Multiplexing peripheral functions Line each Line (whether assigned peripheral used general purpose I/O) Input change interrupt Glitch filter Multi-drive option enables driving open drain Programmable pull each line data status register, supplies visibility level time Synchronous output, provides Clear several lines single write
3.18
Host Port
Compliance with Open specification Compliance with V2.0 Full-speed Low-speed Specification Supports both Low-speed Mbps Full-speed Mbps devices Root integrated with downstream ports embedded transceivers Supports power management Operates master Memory Controller
3.19
Device Port
V2.0 full-speed compliant, Mbits second Embedded V2.0 full-speed transceiver Embedded dual-port endpoints Suspend/Resume logic Ping-pong mode (two memory banks) isochronous bulk endpoints general-purpose endpoints Endpoint Endpoint bytes, ping-pong mode Endpoint Endpoint bytes, ping-pong mode Endpoint Endpoint bytes, ping-pong mode
3.20
Ethernet
Compatibility with IEEE Standard 802.3 Mbits second data throughput capability Full- half-duplex operation RMII interface physical layer Register interface address, status control registers interface, operating master Memory Controller Interrupt generation signal receive transmit completion 28-byte transmit 28-byte receive FIFOs
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
Automatic generation transmitted frames Address checking logic recognize four 48-bit addresses Supports promiscuous mode where valid frames copied memory Supports physical layer management through MDIO interface
3.21
Serial Peripheral Interface
Supports communication with serial external devices Four chip selects with external decoder support allow communication with peripherals Serial memories, such DataFlash 3-wire EEPROMs Serial peripherals, such ADCs, DACs, Controllers, Controllers Sensors External co-processors Master slave serial peripheral interface 16-bit programmable data length chip select Programmable phase polarity chip select Programmable transfer delays between consecutive transfers between clock data chip select Programmable delay between consecutive transfers Selectable mode fault detection Connection channel optimizes data transfers channel receiver, channel transmitter Next buffer support
3.22
Two-wire Interface
Compatibility with standard two-wire serial memory One, three bytes slave address Sequential Read/Write operations
3.23
USART
Programmable Baud Rate Generator 9-bit full-duplex synchronous asynchronous serial communications stop bits Asynchronous Mode stop bits Synchronous Mode Parity generation error detection Framing error detection, overrun error detection MSB- LSB-first Optional break generation detection by-16 over-sampling receiver frequency Optional hardware handshaking RTS-CTS Optional modem signal management DTR-DSR-DCD-RI Receiver time-out transmitter timeguard Optional Multi-drop Mode with address generation detection
1768E-ATARM-30-Sep-05
RS485 with driver control signal ISO7816, Protocols interfacing with smart cards NACK handling, error counter with repetition iteration limit IrDA modulation demodulation Communication 115.2 Kbps Test Modes Remote Loopback, Local Loopback, Automatic Echo Connection Peripheral Controller (PDC) channels Offers buffer transfer without processor intervention
3.24
Serial Synchronous Controller
Provides serial synchronous communication links used audio telecom applications Contains independent receiver transmitter common clock divider Interfaced with channels reduce processor overhead Offers configurable frame sync data length Receiver transmitter programmed start automatically detection different event frame sync signal Receiver transmitter include data signal, clock signal frame synchronization signal
3.25
Timer Counter
Three 16-bit Timer Counter Channels Wide range functions including: Frequency Measurement Event Counting Interval Measurement Pulse Generation Delay Timing Pulse Width Modulation Up/down Capabilities Each channel user-configurable contains: Three external clock inputs Five internal clock inputs multi-purpose input/output signals Internal interrupt signal global registers that three Channels
3.26
MultiMedia Card Interface
Compatibility with MultiMedia Card Specification Version Compatibility with Memory Card Specification Version Cards clock rate Master Clock divided Embedded power management slow down clock rate when used
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
Supports slots slot MultiMedia Card cards) Memory Card Support stream, block multi-block data read write Connection Peripheral Controller (PDC) channel Minimizes processor intervention large buffer transfers
1768E-ATARM-30-Sep-05
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
AT91RM9200 Product Properties
Power Supplies
AT91RM9200 five types power supply pins: VDDCORE pins. They power core, including processor, memories peripherals; voltage ranges from 1.65V 1.95V, 1.8V nominal. VDDIOM pins. They power External Interface lines; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDIOP pins. They power Peripheral lines transceivers; voltage ranges from 3.0V 3.6V, 3.3V nominal. VDDPLL pins. They power cells; voltage ranges from 1.65V 1.95V, 1.8V nominal. VDDOSC pin. They power both oscillators; voltage ranges from 1.65V 1.95V, 1.8V nominal. double power supplies VDDIOM VDDIOP identified Table page Table page These supplies enable user power device differently interfacing with memories interfacing with peripherals. Ground pins common power supplies, except VDDPLL VDDOSC pins. these pins, GNDPLL GNDOSC provided, respectively.
Pinout
AT91RM9200 available packages: 208-lead PQFP, 31.2 31.2 lead pitch 256-ball BGA, ball pitch product features 256-ball package extended compared 208-lead PQFP package. features that available only with 256-ball package are: Parallel Controller Eport with outputs multiplexed Controller second Host transceiver, opening capabilities embedded Host.
1768E-ATARM-30-Sep-05
4.2.1 Table 4-1.
Number
208-lead PQFP Package Pinout AT91RM9200 Pinout 208-lead PQFP Package
Signal Name
PC24 PC25 PC26 PC27 PC28 PC29 VDDIOM PC30 PC31 PC10 PC11 PC12 PC13 PC14 PC15 VDDCORE VDDIOM VDDPLL PLLRCA GNDPLL XOUT VDDOSC GNDOSC XOUT32 XIN32
Number
Signal Name
VDDPLL PLLRCB GNDPLL VDDIOP PA10 PA11 PA12 PA13 VDDIOP PA14 PA15 PA16 PA17 VDDCORE PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26
Number
Signal Name
PA27 PA28 VDDIOP PA29 PA30 PA31/BMS PB10 PB11 PB12 VDDIOP PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 JTAGSEL
Number
Signal Name
NTRST VDDIOP TST0 TST1 NRST VDDCORE PB23 PB24 PB25 PB26 PB27 PB28 PB29 HDMA HDPA VDDIOP VDDIOM A0/NBS0 A1/NBS2/NWR2 SDA10
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
Table 4-1.
Number
AT91RM9200 Pinout 208-lead PQFP Package (Continued)
Signal Name
VDDIOM VDDCORE A16/BA0 A17/BA1
Number
Signal Name
VDDIOM NCS0/BFCS NCS1/SDCS NCS2 NCS3/SMCS NRD/NOE/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE
Number
Signal Name
SDWE VDDIOM VDDCORE
Number
Signal Name
VDDIOM PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23
Note:
Shaded cells define pins powered VDDIOM.
4.2.2
Mechanical Overview 208-lead PQFP Package Figure shows orientation 208-lead PQFP package. detailed mechanical description given section Mechanical Characteristics. Figure 4-1. 208-lead PQFP Pinout (Top View)
1768E-ATARM-30-Sep-05
4.2.3 Table 4-2.
256-ball Package Pinout AT91RM9200 Pinout 256-ball Package
Signal Name JTAGSEL PB20 PB17 PD11 VDDIOP PA31/BMS VDDIOP PA23 PA19 PA14 VDDIOP PA13 PD13 PB18 PB21 PD12 PB10 VDDIOP PA24 PA17 PA15 PA11 PA12 PD15 Signal Name PD14 PB22 PB19 PD10 PB13 PB12 PA20 PA18 VDDCORE TST1 VDDIOP VDDIOP VDDIOP PB14 VDDIOP PA22 PA21 PA16 PA10 NRST NTRST TST0 Signal Name PB15 PA29 PA26 PA25 PD16 PB23 PB25 PB24 VDDCORE PB16 PB11 PA30 PA28 PLLRCB PD19 PD17 PB26 PD18 PB27 PA27 Signal Name XIN32 PD23 PD20 PD22 PD21 VDDIOP VDDPLL VDDIOP GNDPLL XOUT32 PD25 PD27 PD24 PD26 PB28 PB29 GNDOSC VDDOSC VDDPLL GNDPLL HDPA HDMA VDDIOP VDDIOM XOUT
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
Table 4-2.
AT91RM9200 Pinout 256-ball Package (Continued)
Signal Name HDPB HDMB VDDIOP PC10 PC15 VDDCORE PLLRCA VDDIOM A1/NBS2/NWR2 NCS1/SDCS PC13 PC14 A0/NBS0 Signal Name SDA10 NRD/NOE/CFOE PC28 PC31 PC30 PC11 PC12 VDDIOM NWR0/NWE/CFWE SDCKE Signal Name PC26 PC27 VDDIOM VDDIOM NCS3/SMCS NWR3/NBS3/ CFIOW VDDIOM PC17 VDDIOM PC24 PC29 VDDIOM VDDCORE A17/BA1 VDDIOM NCS2 Signal Name NWR1/NBS1/ CFIOR SDWE VDDCORE PC19 PC21 PC23 PC25 VDDCORE A16/BA0 NCS0/BFCS SDCK PC16 PC18 PC20 PC22
Note:
Shaded cells define pins powered VDDIOM.
4.2.4
Mechanical Overview 256-ball Package Figure page shows orientation 256-ball Package. detailed mechanical description given section Mechanical Characteristics.
1768E-ATARM-30-Sep-05
Figure 4-2.
256-ball Pinout (Top View)
Peripheral Multiplexing Lines
AT91RM9200 features four controllers: PIOA PIOB, multiplexing lines peripheral set. PIOC, multiplexing data bits several External Interface control signals. Using PIOC pins increases number general-purpose lines available prevents 32-bit memory access. PIOD, available 256-ball package option only, multiplexing outputs peripheral Eport. Each Controller controls lines. Each line assigned peripheral functions, tables following paragraphs define lines peripherals multiplexed Controllers columns "Function" "Comments" have been inserted user's comments; they used track pins defined application. column "Reset State" indicates whether line resets mode peripheral mode. equal "I/O", line resets input with pull-up enabled that device maintained static state soon NRST asserted. result, corresponding line register PIO_PSR (Peripheral Status Register) resets low. signal name "Reset State" column, line assigned this function corresponding PIO_PSR resets high. This case pins controlling memories, either address lines chip selects, that require driven soon NRST raises. Note that pull-up resistor also enabled this case. Table page Table page Table page Table page
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
4.3.1 Table 4-3. Controller Multiplexing Multiplexing Controller
Controller Line PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral MISO MOSI SPCK NPCS0 NPCS1 NPCS2 NPCS3 ETXCK/EREFCK ETXEN ETX0 ETX1 ECRS/ECRSDV ERX0 ERX1 ERXER EMDC EMDIO TXD0 RXD0 SCK0 CTS0 RTS0 RXD2 TXD2 SCK2 TWCK MCCK MCCDA MCDA0 DRXD DTXD Peripheral PCK3 PCK0 IRQ4 IRQ5 PCK1 TXD3 RXD3 PCK2 MCCDB MCDB0 MCDB1 MCDB2 MCDB3 TCLK0 TCLK1 TCLK2 IRQ6 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 IRQ3 PCK1 IRQ2 IRQ1 TCLK3 TCLK4 TCLK5 CTS2 RTS2 Reset State Function Application Usage Comments
1768E-ATARM-30-Sep-05
4.3.2 Table 4-4.
Controller Multiplexing Multiplexing Controller
Controller Application Usage Reset State EF100 Function Comments
Line PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29
Peripheral DTR1 TXD1 RXD1 SCK1 DCD1 CTS1 DSR1 RTS1 PCK0 IRQ0
Peripheral RTS3 CTS3 SCK3 MCDA1 MCDA2 MCDA3 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5 ETX2 ETX3 ETXER ERX2 ERX3 ERXDV ECOL ERXCK
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
4.3.3 Controller Multiplexing Controller multiplexing only peripheral lines used. Selecting Peripheral Controller effect. Table 4-5. Multiplexing Controller
Controller Line PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Peripheral BFCK BFRDY/SMOE BFAVD BFBAA/SMWE BFOE BFWE NWAIT A25/CFRNW NCS4/CFCS NCS5/CFCE1 NCS6/CFCE2 NCS7 Peripheral Reset State NCS4 NCS5 NCS6 NCS7 Function Application Usage Comments
1768E-ATARM-30-Sep-05
4.3.4
Controller Multiplexing
Controller multiplexes pure output signals peripheral connections, particular from EMAC interface EPort peripheral connections. Controller available only 256-ball package option AT91RM9200. Table 4-6. Multiplexing Controller
Controller Line PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 NPCS1 NPCS2 NPCS3 RTS0 RTS1 RTS2 RTS3 DTR1 Peripheral ETX0 ETX1 ETX2 ETX3 ETXEN ETXER DTXD PCK0 PCK1 PCK2 PCK3 TSYNC TCLK TPS0 TPS1 TPS2 TPK0 TPK1 TPK2 TPK3 TPK4 TPK5 TPK6 TPK7 TPK8 TPK9 TPK10 TPK11 TPK12 TPK13 TPK14 TPK15 Peripheral Reset State Function Application Usage Comments
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
4.3.5 Name Description Table gives details name classified peripheral. Table 4-7.
Name
Description List
Function Power Type Active Level Comments
VDDIOM VDDIOP VDDPLL VDDCORE VDDOSC GNDPLL GNDOSC
Memory Lines Power Supply Peripheral Lines Power Supply Oscillator Power Supply Core Chip Power Supply Oscillator Power Supply Ground Ground Oscillator Ground
Power Power Power Power Power Ground Ground Ground
3.0V 3.6V 3.0V 3.6V 1.65V 1.95V 1.65V 1.95V 1.65V 1.95V
Clocks, Oscillators PLLs XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 PCK3 Main Crystal Input Main Crystal Output 32KHz Crystal Input 32KHz Crystal Output Filter Filter Programmable Clock Output JTAG NTRST JTAGSEL Test Clock Test Data Test Data Test Mode Select Test Reset Signal JTAG Selection ETSYNC TCLK TPS0 TPS2 TPK0 TPK15 Trace Synchronization Signal Trace Clock Trace Pipeline Status Trace Packet Port Reset/Test NRST TST0 TST1 Microcontroller Reset Test Mode Select Input Input on-chip pull-up, Schmitt trigger Must tied normal operation, Schmitt trigger Output Output Output Output Input Input Output Input Input Input Schmitt trigger Internal Pull-up, Schmitt trigger Tri-state Internal Pull-up, Schmitt trigger Internal Pull-up, Schmitt trigger Schmitt trigger Input Output Input Output Input Input Output
1768E-ATARM-30-Sep-05
Table 4-7.
Name
Description List (Continued)
Function Memory Controller Type Active Level Comments
Boot Mode Select Debug Unit
Input
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
Debug Receive Data Debug Transmit Data
IRQ0 IRQ6
External Interrupt Inputs Fast Interrupt Input
Input Input
PA31 PB29 PC31 PD27
Parallel Controller Parallel Controller Parallel Controller Parallel Controller
Pulled-up input reset Pulled-up input reset Pulled-up input reset Pulled-up input reset
Data Address
Output
Pulled-up input reset reset
NCS0 NCS7 NWR0 NWR3 NWAIT NBS0 NBS3
Chip Select Lines Write Signal Output Enable Read Signal Upper Byte Select Lower Byte Select Write Enable Wait Signal Byte Mask Signal
Output Output Output Output Output Output Output Input Output CompactFlash Support
reset reset reset reset reset reset reset
reset
CFCE1 CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS
CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash Read CompactFlash Write CompactFlash Read Write CompactFlash Chip Select
Output Output Output Output Output Output Output
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Table 4-7.
Name
Description List (Continued)
Function Type NAND Flash/SmartMedia Support Active Level Comments
SMCS SMOE SMWE
NAND Flash/SmartMedia Chip Select NAND Flash/SmartMedia Output Enable NAND Flash/SmartMedia Write Enable SDRAM Controller
Output Output Output
SDCK SDCKE SDCS SDWE SDA10
SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Column Signal SDRAM Address Line
Output Output Output Output Output Output Output Burst Flash Controller High
BFCK BFCS BFAVD BFBAA BFOE BFRDY BFWE
Burst Flash Clock Burst Flash Chip Select Burst Flash Address Valid Burst Flash Address Advance Burst Flash Output Enable Burst Flash Ready Burst Flash Write Enable
Output Output Output Output Output Input Output Multimedia Card Interface High
MCCK MCCDA MCDA0 MCDA3 MCCDB MCDB0 MCDB3
Multimedia Card Clock Multimedia Card Command Multimedia Card Data Multimedia Card Command Multimedia Card Data USART
Output
SCK0 SCK3 TXD0 TXD3 RXD0 RXD3 RTS0 RTS3 CTS0 CTS3 DSR1 DTR1 DCD1
Serial Clock Transmit Data Receive Data Ready Send Clear Send Data Ready Data Terminal Ready Data Carrier Detect Ring Indicator
Output Input Output Input Input Output Input Input
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Table 4-7.
Name
Description List (Continued)
Function Device Port Type Active Level Comments
Device Port Data Device Port Data Host Port
Analog Analog
HDMA HDPA HDMB HDPB
Host Port Data Host Port Data Host Port Data Host Port Data Ethernet
Analog Analog Analog Analog
EREFCK ETXCK ERXCK ETXEN ETX0 ETX3 ETXER ERXDV ECRSDV ERX0 ERX3 ERXER ECRS ECOL EMDC EMDIO EF100
Reference Clock Transmit Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Carrier Sense Data Valid Receive Data Receive Error Carrier Sense Collision Detected Management Data Clock Management Data Input/Output Force Mbits/sec.
Input Input Input Output Output Output Input Input Input Input Input Input Output Output Synchronous Serial Controller High
RMII only only only
ETX0 ETX1 only RMII only only RMII only ERX0 ERX1 only RMII
only only
RMII only
Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync Timer/Counter
Output Input
TCLK0 TCLK5 TIOA0 TIOA5 TIOB0 TIOB5
External Clock Input Line Line
Input
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Table 4-7.
Name
Description List (Continued)
Function Type Active Level Comments
MISO MOSI SPCK NPCS0 NPCS1 NPCS3
Master Slave Master Slave Serial Clock Peripheral Chip Select Peripheral Chip Select Two-Wire Interface
Output
TWCK
Two-wire Serial Data Two-wire Serial Clock
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Peripheral Identifiers
AT91RM9200 embeds wide range peripherals. Table defines peripheral identifiers AT91RM9200. peripheral identifier required control peripheral interrupt with Advanced Interrupt Controller control peripheral clock with Power Management Controller. Table 4-8.
Peripheral
Peripheral Identifiers
Peripheral Mnemonic SYSIRQ PIOA PIOB PIOC PIOD SSC0 SSC1 SSC2 EMAC Parallel Controller Parallel Controller Parallel Controller Parallel Controller USART USART USART USART Multimedia Card Interface Device Port Two-wire Interface Serial Peripheral Interface Synchronous Serial Controller Synchronous Serial Controller Synchronous Serial Controller Timer/Counter Timer/Counter Timer/Counter Timer/Counter Timer/Counter Timer/Counter Host Port Ethernet Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 Peripheral Name Advanced Interrupt Controller External Interrupt
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4.4.1 System Interrupt System Interrupt wired-OR interrupt signals coming from: Memory Controller Debug Unit System Timer Real-Time Clock Power Management Controller clock these peripherals cannot controlled Peripheral only used within Advanced Interrupt Controller. 4.4.2 External Interrupts external interrupt signals, i.e., Fast Interrupt signal Interrupt signals IRQ0 IRQ6, dedicated Peripheral However, there clock control associated with these peripheral IDs.
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Product Memory Mapping
first level address decoding performed Memory Controller, i.e., implementation Advanced System (ASB) with additional features. Decoding splits bytes address space into areas 256M bytes. areas directed that associates these areas external chip selects NCS7. area reserved addressing internal memories, second level decoding provides bytes internal memory area. area reserved peripherals provides access Advanced Peripheral (APB). Other areas unused performing access within them provides abort master requesting such access.
4.5.1
External Memory Mapping External Memory Mapping
256M Bytes 256M Bytes 256M Bytes 256M Bytes 0x0000 0000
0x0FFF FFFF
Figure 4-3.
Internal Memories Chip Select Chip Select Chip Select Chip Select Chip Select Chip Select Chip Select Chip Select SDRAMC CompactFlash NAND Flash/SmartMedia
0x1000 0000
0x1FFF FFFF
0x2000 0000
0x2FFF FFFF
0x3000 0000
0x3FFF FFFF
0x4000 0000 256M Bytes 256M Bytes 256M Bytes 256M Bytes 256M Bytes
0x4FFF FFFF
0x5000 0000
0x5FFF FFFF
0x6000 0000
0x6FFF FFFF
0x7000 0000
0x7FFF FFFF
0x8000 0000
0x8FFF FFFF 0x9000 0000
256M Bytes 1,536 bytes
0xEFFF FFFF
Undefined (Abort)
256M Bytes
0xF000 0000
0xFFFF FFFF
Peripherals
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4.5.2 4.5.2.1 Internal Memory Mapping Internal AT91RM9200 integrates high-speed, 16-Kbyte internal SRAM. After reset until Remap Command performed, SRAM only accessible address 0x20 0000. After Remap, SRAM also available address 0x0. 4.5.2.2 Internal AT91RM9200 integrates 128-Kbyte Internal ROM. time, mapped address 0x10 0000. also accessible address after reset before Remap Command tied high during reset. 4.5.2.3 Host Port AT91RM9200 integrates Host Port Open Host Controller Interface (OHCI). registers this interface directly accessible mapped like standard internal memory address 0x30 0000. Figure 4-4. Internal Memory Mapping
0x0000 0000 Internal Memory Area
0x000F FFFF
MBytes
0x0010 0000
0x001F FFFF
Internal Memory Area Internal Internal Memory Area Internal SRAM Internal Memory Area Host Port
MBytes
0x0020 0000 256Mbytes
0x002F FFFF
MBytes
0x0030 0000
0x003F FFFF 0x0040 0000
MBytes
Undefined Area (Abort)
0x0FFF FFFF
252M bytes
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4.5.3 4.5.3.1
Peripheral Mapping System Peripherals Mapping System Peripherals mapped bytes address space, between addresses 0xFFFF F000 0xFFFF FFFF. Each peripheral bytes. Figure 4-5. System Peripherals Mapping
Peripheral Name 0xFFFF F000
0xFFFF F1FF
Size
Advanced Interrupt Controller
bytes/128 registers
0xFFFF F200
DBGU
0xFFFF F3FF
Debug Unit
bytes/128 registers
0xFFFF F400 PIOA Controller bytes/128 registers
0xFFFF F5FF
0xFFFF F600 PIOB Controller bytes/128 registers
0xFFFF F7FF
0xFFFF F800 PIOC Controller bytes/128 registers
0xFFFF F9FF
0xFFFF FA00 PIOD Controller bytes/128 registers
0xFFFF FBFF
0xFFFF FC00
0xFFFF FCFF
Power Management Controller
bytes/64 registers
0xFFFF FD00
0xFFFF FDFF
System Timer
bytes/64 registers
0xFFFF FE00
0xFFFF FEFF
Real-time Clock
bytes/64 registers
0xFFFF FF00
0xFFFF FFFF
Memory Controller
bytes/64 registers
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4.5.3.2 User Peripherals Mapping User Peripherals mapped upper 256M bytes address space, between addresses 0xFFFA 0000and 0xFFFE 3FFF. Each peripheral 16-Kbyte address space. Figure 4-6. User Peripherals Mapping
Peripheral Name
0xF000 0000
Size
Reserved
0xFFF9 FFFF
0xFFFA 0000
0xFFFA 3FFF
TC0, TC1,
Timer/Counter
Bytes
0xFFFA 4000
0xFFFA 7FFF 0xFFFA 8000
TC3, TC4,
Timer/Counter
Bytes
Reserved
0xFFFA FFFF
0xFFFB 0000
0xFFFB 3FFF
Device Port
Bytes
0xFFFB 4000
0xFFFB 7FFF
Multimedia Card Interface
Bytes
0xFFFB 8000
0xFFFB BFFF
Two-Wire Interface
Bytes
0xFFFB C000
0xFFFB FFFF
EMAC
Ethernet
Bytes
0xFFFC 0000
0xFFFC 3FFF
USART0
Universal Synchronous Asynchronous Receiver Transmitter Universal Synchronous Asynchronous Receiver Transmitter Universal Synchronous Asynchronous Receiver Transmitter Universal Synchronous Asynchronous Receiver Transmitter Serial Synchronous Controller
Bytes
0xFFFC 4000
0xFFFC 7FFF
USART1
Bytes
0xFFFC 8000
0xFFFC BFFF
USART2
Bytes
0xFFFC C000
0xFFFC FFFF
USART3
Bytes
0xFFFD 0000
0xFFFD 3FFF
SSC0
Bytes
0xFFFD 4000
0xFFFD 7FFF
SSC1
Serial Synchronous Controller
Bytes
0xFFFD 8000
0xFFFD BFFF 0xFFFD C000
SSC2
Serial Synchronous Controller
Bytes
Reserved
0xFFFD FFFF
0xFFFE 0000
0xFFFE 3FFF 0xFFFE 4000
Serial Peripheral Interface
Bytes
Reserved
0xFFFE FFFF
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4.6.1
Peripheral Implementation
USART USART describes features allowing management Modem Signals DTR, DSR, details, "Modem Mode" page 435. AT91RM9200, only USART1 implements these signals, named DTR1, DSR1, DCD1 RI1. USART0, USART2 USART3 implement modem signals. Only (RTS0 CTS0, RTS2 CTS2, RTS3 CTS3, respectively) implemented these USARTs other features. Thus, programming USART0, USART2 USART3 Modem Mode lead unpredictable results. these USARTs, commands relating Modem Mode have effect status bits relating status modem signals never activated.
4.6.2
Timer Counter Timer Counter described with five generic clock inputs, TIMER_CLOCK1 TIMER_CLOCK5. AT91RM9200, these clock inputs connected Master Clock (MCK), Slow Clock (SLCK) divisions Master Clock. details, "Clock Control" page 488. Table gives correspondence between Timer Counter clock inputs clocks AT91RM9200. Each Timer Counter displays same configuration. Table 4-9. Timer Counter Clocks Assignment
Clock MCK/2 MCK/8 MCK/32 MCK/128 SLCK
Clock Input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5
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ARM920T Processor Overview
Overview
ARM920T cached processor member ARM9Thumb® family high-performance 32-bit system-on-a-chip processors. provides complete high performance subsystem including: ARM9TDMI RISC integer 16-Kbyte instruction 16-Kbyte data caches Instruction data memory management units (MMUs) Write buffer AMBA(Advanced Microprocessor Architecture) interface Embedded Trace Macrocell (ETM) interface ARM9TDMI core within ARM920T executes both 32-bit 16-bit Thumb instruction sets. ARM9TDMI processor Harvard architecture device, implementing five-stage pipeline consisting Fetch, Decode, Execute, Memory Write stages. ARM920T processor incorporates coprocessors: CP14 Controls software access debug communication channel CP15 System Control Processor, providing additional registers that used configure control caches, MMU, protection system, clocking mode other system options main features ARM920T processor are: ARM9TDMI®-based, ARM® Architecture Instruction Sets High-performance 32-bit Instruction Thumb High Code Density 16-bit Instruction 5-Stage Pipeline Architecture Instruction Fetch Instruction Decode Execute Data Memory Access Register Write 16-Kbyte Data Cache, 16-Kbyte Instruction Cache Virtually-addressed 64-way Associative Cache Words Line Write-though Write-back Operation Pseudo-random Round-robin Replacement Low-power Implementation Write Buffer 16-word Data Buffer 4-address Address Buffer Software Control Drain
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Standard ARMv4 Memory Management Unit (MMU) Access Permission Sections Access Permission Large Pages Small Pages Specified Separately Each Quarter Pages Embedded Domains 64-entry Instruction 64-entry Data 16-, 32-bit Data Instructions Data
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Block Diagram
ARM920T Internal Functional Block Diagram
Figure 5-1.
ARM920T
Instruction Cache Instruction Instruction Physical Address
Instruction Modified Virtual Address
Instruction Virtual Address Interface
Instruction
ARM9TDMI
CP15
Interface
Memory Controller
Data Virtual Address
Data
Write Buffer
Data Modified Virtual Address
Data Physical Address
Data Cache
Data Data Index
Write Back
Write Back Physical Address
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5.3.1
ARM9TDMI Processor
Instruction Type Instructions either bits state) bits Thumb state).
5.3.2
Data Types ARM9TDMI supports byte (8-bit), half-word (16-bit) word (32-bit) data types. Words must aligned four-byte boundaries half-words two-byte boundaries. Unaligned data access behavior depends which instruction used particular location.
5.3.3
ARM9TDMI Operating Modes ARM9TDMI, based architecture v4T, supports seven processor modes: User: Standard program execution state FIQ: Designed support high-speed data transfer channel processes IRQ: Used general-purpose interrupt handling Supervisor: Protected mode operating system Abort mode: Implements virtual memory and/or memory protection System: privileged user mode operating system Undefined: Supports software emulation hardware coprocessors Mode changes made under software control, brought about external interrupts exception processing. Most application programs will execute User Mode. nonuser modes, known privileged modes, entered order service interrupts exceptions access protected resources.
5.3.4
ARM9TDMI Registers ARM9TDMI processor core consists 32-bit datapath associated control logic. That datapath contains general-purpose registers, coupled full shifter, Arithmetic Logic Unit multiplier. time, registers visible user. remainder synonyms used speed exception processing. Register Program Counter (PC) used instructions reference data relative current instruction. holds return address after subroutine call. used software convention) stack pointer. Table 5-1.
User System Mode
ARM9TDMI Modes Register Layout
Supervisor Mode Undefined Mode Interrupt Mode Fast Interrupt Mode
Abort Mode
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Table 5-1.
User System Mode
ARM9TDMI Modes Register Layout (Continued)
Supervisor Mode R13_SVC R14_SVC Undefined Mode R13_UNDEF R14_UNDEF Interrupt Mode R13_IRQ R14_IRQ Fast Interrupt Mode R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ
Abort Mode R13_ABORT R14_ABORT
CPSR
CPSR SPSR_SVC
CPSR SPSR_ABO
CPSR SPSR_UND
CPSR SPSR_IRQ
CPSR SPSR_FIQ
Mode-specific banked registers
Registers unbanked registers, thus each them refers same 32-bit physical register processor modes. They general-purpose registers, with special uses managed architecture, used wherever instruction allows general-purpose register specified. Registers banked registers. This means that each them depends current processor mode. further details, Architecture Reference Manual, Rev. DDI0100E. 5.3.4.1 Modes Exception Handling exceptions have banked registers R13. After exception, holds return address exception processing. This address used both return after exception processed address instruction that caused exception. banked across exception modes provide each exception handler with private stack pointer. fast interrupt mode also banks registers that interrupt processing begin without need save these registers.
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seventh processing mode, System Mode, does have banked registers. uses User Mode registers. System Mode runs tasks that require privileged processor mode allows them invoke classes exceptions. 5.3.4.2 Status Registers other processor states held status registers. current operating processor status Current Program Status Register (CPSR). CPSR holds: four flags (Negative, Zero, Carry, Overflow), interrupt disable bits (one each type interrupt), indicate Thumb execution five bits encode current processor mode five exception modes also have Saved Program Status Register (SPSR) which holds CPSR task immediately before exception occurred. 5.3.4.3 Exception Types
ARM9TDMI supports five types exceptions privileged processing mode each
type. types exceptions are: fast interrupt (FIQ) normal interrupt (IRQ) memory aborts (used implement memory protection virtual memory) attempted execution undefined instruction software interrupt (SWIs) Exceptions generated internal external sources. More than exception occur same time. When exception occurs, banked version SPSR exception mode used save state. return after handling exception, SPSR moved CPSR moved This done ways: data-processing instruction with S-bit set, destination Load Multiple with Restore CPSR instruction (LDM) 5.3.5 Instruction Overview instruction divided into: Branch instructions Data processing instructions Status register transfer instructions Load Store instructions Coprocessor instructions Exception-generating instructions instructions executed conditionally. Every instruction contains 4-bit condition code field (bits[31:28]). further details, ARM920T Technical Reference Manual, Rev. DDI0151C.
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Table gives instruction mnemonic list. Table 5-2.
Mnemonic
SMULL SMLAL LDRSH LDRSB LDRH LDRB LDRBT LDRT
Instruction Mnemonic List
Operation
Move Subtract Reverse Subtract Compare Test Logical Logical Exclusive Multiply Sign Long Multiply Signed Long Multiply Accumulate Move Status Register Branch Branch Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move Coprocessor Load Coprocessor
Mnemonic
UMULL UMLAL STRH STRB STRBT STRT SSWPB
Operation
Coprocessor Data Processing Move with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Clear Logical (inclusive) Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch Link Software Interrupt Store Word Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor
5.3.6
Thumb Instruction Overview Thumb instruction re-encoded subset instruction set. Thumb instruction divided into: Branch instructions Data processing instructions Load Store instructions Load Store multiple instructions Exception-generating instruction Thumb mode, eight general-purpose registers available, that same physical registers when executing instructions. Some Thumb instructions also access Program Counter (ARM Register 15), Link Register (ARM Register
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Stack Pointer (ARM Register 13). Further instructions allow limited access register further details, ARM920T Technical Reference Manual, Rev. DDI0151C. Table gives Thumb instruction mnemonic list. Table 5-3.
Mnemonic
LDRH LDRB LDRSH LDMIA PUSH
Thumb Instruction Mnemonic List
Operation
Move Subtract Compare Test Logical Logical Exclusive Logical Shift Left Arithmetic Shift Right Multiply Branch Branch Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register stack STRH STRB LDRSB STMIA Branch Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Register from stack
Mnemonic
Operation
Move with Carry Subtract with Carry Compare Negated Negate Clear Logical (inclusive) Logical Shift Right Rotate Right
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CP15 Coprocessor
Coprocessor System Control Coprocessor CP15, used when special features used with ARM9TDMI such On-chip Memory Management Unit (MMU) Instruction and/or Data Cache Write buffer control these features, CP15 provides additional registers. Table 5-4. Table 5-4.
Register Notes:
CP15 Registers
Name Register Control Translation Table Base Domain Access Control Reserved Fault Status Fault Address Cache Operations
Access Read-only Read/Write Read/Write Read/Write None Read/Write Read/Write Write-only Write-only Read/Write Read/Write None None Read/Write None None
Operations
cache lockdown lockdown Reserved Reserved FCSE PID(2) Reserved Test configuration
TLB: Translation Lookaside Buffer FCSE PID: Fast Context Switch Extension Process Identifier
5.4.1
CP15 Register Access (Move Coprocessor from Register) instruction (Move Register from Coprocessor) instruction
CP15 registers only accessed privileged mode
Other instructions (CDP, LDC, STC) cause undefined instruction exception. instruction used write register CP15. instruction used read value CP15 register. assembler code these instructions
MCR/MRC{cond} p15, opcode_1, CRn, CRm, opcode_2.
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MCR, instructions pattern shown below:
Cond
opcode_1
opcode_2
CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. value dependent CP15 register used. details, refer CP15 specific register behavior. opcode_2[7:5] Determines specific coprocessor operation code. default, Rd[15:12]: Register Defines register whose value transferred coprocessor. chosen, result unpredictable. CRn[19:16]: Coprocessor Register Determines destination coprocessor register. opcode_1[23:20]: Coprocessor Code Defines coprocessor specific code. Value CP15. Instruction instruction instruction Cond [31:28]: Condition
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Memory Management Unit (MMU)
ARM920T processor implements enhanced architecture provide translation access permission checks instruction data address ports ARM9TDMI core. controlled from single two-level page tables stored main memory, providing single address translation protection scheme. Independently, instruction data TLBs locked flushed. Table 5-5. Mapping Details
Mapping Size byte bytes bytes byte Access Permission Section separated subpages separated subpages Tiny Page Subpage Size bytes byte
Mapping Name Section Large Page Small Page Tiny Page
5.5.1
Domain domain collection sections pages. ARM920T supports domains. Access domains controlled Domain Access Control register. details, refer "CP15 Register Domain Access Control Register" page
5.5.2
Faults generates alignment faults, translation faults, domain faults permission faults. Alignment fault checking affected whether enabled not. access controls detect conditions that produce these faults. fault result memory access, aborts access signals fault core.The stores status address fault registers (only faults generated data access). does store fault information about faults generated instruction fetch. memory system abort during line fetches, memory accesses translation table access.
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Caches, Write Buffers Physical Address
ARM920T includes Instruction Cache (ICache), Data Cache (DCache), write buffer Physical Address (PA) reduce effect main memory bandwidth latency performance. ARM920T implements separate 16-Kbyte Instruction 16-Kbyte Data Caches. caches write buffer controlled CP15 Register (Control), CP15 Register (Cache Operations) CP15 Register (Cache Lockdown).
5.6.1
Instruction Cache (ICache) ARM920T includes 16-Kbyte Instruction Cache (ICache). ICache lines bytes, arranged 64-way associative cache. Instruction access subject permission translation checks. ICache enabled with disabled, instructions fetched threats cachable. protection checks made physical address flat-mapped modified virtual address. When ICache disabled, cache contents ignored instruction fetches appear AMBA bus. reset, ICache entries invalidated ICache disabled. best performance, ICache should enabled soon possible after reset. ICache enabled writing CP15 Register disabled writing this bit. more details, "CP15 Register Control" page ICache organized eight segments, each containing lines with each line made words.The position line within segment called index numbered from line cache identified index segment. index independent (Modified Virtual Address), segment bit[7:5] MVA.
5.6.2
Data Cache (DCache) Write Buffer ARM920T includes 16-Kbyte data cache (DCache). DCache lines bytes, arranged 64-way associative cache, uses MVAs translated CP15 Register from ARM9DTMI core.
5.6.2.1
DCache DCache organized eight segments, each containing lines with each line made eight words.The position line within segment called index number from Write Buffer hold words data four separate addresses. DCache Write Buffer operations closely connected their configuration each section page descriptor translation table. data accesses subject permission translation checks. Data accesses aborted cannot cause linefill data access AMBA interface.
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Write-though Operation When cache occurs data access, cache line that contains data updated contains value. data also immediately written main memory. When cache occurs data access, cache line marked dirty, meaning that contents up-to-date with those main memory.
Write-back Operation
5.6.2.2
Write Buffer ARM920T incorporates 16-entry write buffer avoid stalling processor when writes external memory performed. When store occurs, data, address other details written write buffer high speed. write buffer then completes store main memory speed (typically slower than speed). parallel, ARM9TDMI processor execute further instructions full speed.
5.6.2.3
Physical Address RAM) ARM920T implements Physical Address RAM) perform write-backs from data cache. physical address lines held data cache stored memory, removing need address translation when evicting line from cache. When line written into data cache, physical address written into RAM. this line written back main memory, read physical address used AMBA interface perform write-back. 16-Kbyte DCache, organized eight segments with: rows segments bits rows
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5.7.1
ARM920T User Interface
CP15 Register Code Cache Type
Access: Read-only Register contains specific hardware information. contents read accesses determined opcode_2 field value. Writing Register unpredictable. 5.7.1.1 Code
code register accessed reading register with opcode_2 field contents code shown below:
SRev
archi
PNumber
Layout
LayoutRev[3:0]: Revision Contains processor revision number PNumber[15:4]: Processor Part Number 0x920 value ARM920T processor. archi[19:16]: Architecture Details implementor architecture code. value means ARMv4T architecture. SRev[23:20]: Specification Revision Number value; specification revision number used distinguished variants same primary part. imp[31:24]: Implementor Code 0x41 means Ltd.
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5.7.1.2 Cache Type Cache Type register accessed reading register with opcode_2 field Cache Type register contains information about size architecture caches.
ctype
DSize
ISize
ISize[11:0]: Instruction Cache Size Indicates size, line length associativity instruction cache. DSize[23:12]: Data Cache Size Indicates size, line length associativity data cache. S[24]: Cache Indicates cache unified separate instruction data caches. this field indicates separate Instruction Data caches. ctype[28:25]: Cache Type Defines cache type.
details bits DSize ISize, refer ARM920T Technical Reference Manual, Rev. DDI0151C.
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5.7.2
CP15 Register Control
Access: Read/Write CP15 Register Control Register, contains control bits ARM920T.
M[0]: Enable disabled. enabled. A[1]: Alignment Fault Enable Fault checking disabled. Fault checking enabled. C[2]: DCache Enable DCache disabled. DCache enabled. B[7]: Endianness Little endian mode. endian mode. S[8]: System Protection Modifies protection system. further details, ARM920T Technical Reference Manual, Rev. DDI0151C. R[9]: Protection Modifies protection system. further details, ARM920T Technical Reference Manual, Rev. DDI0151C. I[12]: ICache Control ICache disabled. ICache enabled.
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V[13]: Base Location Exception Register address means 0x00000000. High address means 0xFFFF0000. RR[14]: Round Robin Replacement Random replacement. Round robin replacement. Clocking Mode[31:30] bits)
Clocking mode Fast Synchronous Reserved Asynchronous
5.7.3
CP15 Register
Access: Read/Write CP15 Register Translation Table Base (TTB) Register, defines first-level translation table.
Pointer
Pointer
Pointer
Pointer[31:14] Points first-level translation table base. Read returns currently active first-level translation table. Write sets pointer first-level table written value. non-defined bits should zero when written unpredictable when read.
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5.7.4
CP15 Register Domain Access Control Register
Access: Read/Write Register Domain Access Control Register, defines domain's access permission. accesses priory controlled through domains. Each field Register associated with domain.
Named Domain Access 2-bit field value allows domain access described table below.
Value Access access Client Reserved Manager Description access generates domain fault Users domain (execute programs, access data), domain access permission controlled domain access. Reserved Controls behavior domain, checking domain access permission done
5.7.5
CP15 Register Reserved
access (Read Write) this register causes unpredictable behavior.
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5.7.6 CP15 Register Fault Status Register Access: Read/Write Reading Register Fault Status Register (FSR), returns source last data fault, indicating domain type access being attempted when data abort occurred. addition, virtual address which caused data abort written into Fault Address Register (CP15 Register Writing Register Fault Status Register (FSR), sets value data written. This useful debugger restore value FSR.
Domain
Status
Status[3:0]: Fault Type Indicates fault type. status field encoded when data abort occurs. interpretation Status field dependant domain field associated with data abort (stored FAR). Domain[7:4]: Domain Indicates domain (D15 being accessed when fault occurred.
non-defined bits should zero when written unpredictable when read.
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5.7.7
CP15 Register Fault Address Register
Access: Read/Write Register Fault Address Register (FAR), contains (Modified Virtual Address) access being attempted when last fault occurred. only updated data faults, prefetch faults. ability write provided allow debugger restore previous state.
FAR[31:0]: Fault Address reading: returns value FAR. holds virtual address access which attempted when fault occurred. writing: sets value written data. This useful debugger restore value FAR. 5.7.8 CP15 Register Cache Operation Register
Access: Write-only CP15 Register Cache Operation Register, used manage Instruction Cache (ICache) Data Cache (DCache). function each cache operation selected opcode_2 fields instruction used write CP15 Register Table 5-6.
Function Wait Interrupt Invalidate ICache Invalidate ICache single entry (using MVA) Invalidate DCache Invalidate DCache single entry (using MVA) Invalidate ICache DCache Clean DCache singe entry (using MVA) Clean DCache single entry (using index) Drain write buffer Prefetch ICache line (using MVA) Clean Invalidate DCache entry (using MVA) Clean Invalidate DCache entry (using index)
Cache Functions
Data format format format Index format format format Index format opcode_2
AT91RM9200
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AT91RM9200
Function Details Wait interrupt Stops execution low-power state until interrupt occurs. Invalidate cache line lines) marked invalid, cache hits occur that line until re-allocated address. Clean Applies write-back data caches. cache line contains stored data that been written main memory, written main memory immediately. Drain write buffer Stops execution until data write buffer been stored main memory. Prefetch memory cache line specified virtual address loaded into cache. operation carried single cache line identifies line using data transferred instruction. data interpreted using formats:
format index format
Below details CP15 Register Cache Function Register, format.
mva[31:5]: Modified Virtual Address non-defined bits should zero when written unpredictable when read.
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Below details CP15 Register Cache Function Register, Index format:
index
index[31:26]: Line Determines cache line. set[7:5]: Segment Determines cache segment.
non-defined bits should zero when written unpredictable when read.
Writing other opcode_2 values values unpredictable. Reading from CP15 Register unpredictable.
AT91RM9200
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AT91RM9200
5.7.9 CP15 Register Operations Register Access: Write-only CP15 Register Translation Lookaside Buffer (TLB) Operations Register, used manage instruction TLBs data TLBs. operation selected opcode_2 fields instruction used write CP15 Register Table 5-7.
Function Invalidate Invalidate single entry (using MVA) Invalidate Invalidate single entry (using MVA) Invalidate both Instruction Data
Operations
Data format format opcode_2
Below details CP15 Register operation format single entry.
mva[31:10]: Modified Virtual Address non-defined bits should zero when written unpredictable when read.
Writing other opcode_2 values values unpredictable. Reading from CP15 Register unpredictable.
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5.7.10
CP15 Register Cache Lockdown Register
Access: Read/Write CP15 Register Cache Lockdown Register, reset. Cache Lockdown Register allows software control which cache line ICache DCache loaded linefill. prevents lines ICache DCache from being evicted during linefill, locking them into cache. Reading from CP15 Register returns value Cache Lockdown Register that base pointer cache segments. Only bits[31:26] returned; others unpredictable. Writing CP15 Register updates Cache Lockdown Register with both base current victim pointers cache segments.
Table 5-8.
Function
Cache Lockdown Functions
Data Base Victim Base Base Victim Base opcode_2
Read DCache lockdown base Write DCache victim lockdown base Read ICache lockdown base Write ICache victim lockdown base
index
index[31:26]: Victim Pointer Current victim pointer that specifies cache line used victim next linefill.
non-defined bits should zero when written unpredictable when read.
AT91RM9200
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AT91RM9200
5.7.11 CP15 Register Lockdown Register Access: Read/Write CP15 Register Lockdown Register, reset. There TLSB Lockdown Register each TLBs; value opcode_2 determines which register access: opcode_2 register opcode_2 register
Table 5-9.
Function
Lockdown Functions
Data lockdown lockdown lockdown lockdown Opcode_2
Read lockdown Write lockdown Read lockdown Write lockdown
Base
Victim
Base[31:26]: Base replacement strategy only uses entries numbered from base Victim field provided that range. Victim[25:20]: Victim Counter Specifies entry (line) being overwritten. P[0]: Preserved entry invalidated. entry protected. cannot invalidated during Invalidate instruction. Refer "CP15 Register Operations Register" page
non-defined bits should zero when written unpredictable when read. 5.7.12 CP15 Registers Reserved
access (Read Write) these registers causes unpredictable behavior.
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5.7.13
CP15 Register FCSE Register
Access: Read/Write CP15 Register Fast Context Switch Extension (FCSE) Process Identifier (PID) Register, reset. Reading from CP15 Register returns FCSE value. Writing CP15 Register sets FCSE PID. FCSE sets mapping between ARM9TDMI cache memories. addresses issued ARM9TDMI range Mbytes translated FCSE PID.
FCSEPID
FCSEPID[31:25]: FCSE FCSE modifies behavior ARM920T memory system. This modification allows multiple programs ARM. 4-GB virtual address divided into process blocks Mbytes each. Each process block contain program that been compiled address range 0x00000000 0x01FFFFFF. each process blocks, runs from address i*0x20000000 address i*0x20000000 0x01FFFFFF. further details, ARM920T Technical Reference Manual, Rev. DDI0151C.
non-defined bits should zero when written unpredictable when read. 5.7.14 CP15 Register Reserved
access (Read Write) these registers causes unpredictable behavior. 5.7.15 CP15 Register Test Configuration Register
CP15 Register Test Configuration Register, used test purposed. access (write read) this register causes unpredictable behavior.
AT91RM9200
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AT91RM9200
Debug Test Features (DBG Test)
Overview
AT91RM9200 features number complementary debug test capabilities. common JTAG/ICE (In-Circuit Emulator) port used standard debugging functions such downloading code single-stepping through programs. E(Embedded Trace Macrocell) provides more sophisticated debug features such address data comparators, half-rate clock mode, counters, sequencer FIFO. Debug Unit provides two-pin UART that used upload application into internal SRAM. manages interrupt handling internal COMMTX COMMRX signals that trace activity Debug Communication Channel. dedicated debug test input/output pins give direct access these capabilities from PC-based test environment. Features Debug Test Features are: Integrated Embedded In-Circuit-Emulator Debug Unit Two-pin UART Debug Communication Channel Chip Register Embedded Trace Macrocell: ETM9 Rev2a Medium Level Implementation Half-rate Clock Mode Four Pairs Address Comparators Data Comparators Eight Memory Decoder Inputs Counters Sequencer 18-byte FIFO IEEE1149.1 JTAG Boundary Scan Digital Pins
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Block Diagram
Figure 6-1. AT91RM9200 Debug Test Block Diagram
NTRST ICE/JTAG JTAGSEL
Boundary Port
TPK0-TPK15 TPS0-TPS2 TSYNC ARM920T TCLK
ARM9TDMI
E
DTXD DBGU DRXD
Reset Test
TST0-TST1 NRST TAP: Test Access Port
AT91RM9200
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AT91RM9200
6.3.1
Application Examples
Debug Environment Figure page shows complete debug environment example. ICE/JTAG interface used standard debugging functions such downloading code single-stepping through program. Trace Port interface used tracing information. software debugger running personal computer provides user interface configuring Trace Port interface utilizing ICE/JTAG interface. Figure 6-2. AT91RM9200-based Application Debug Trace Environment Example
Host Debugger
ICE/JTAG Interface
Trace Port Interface
ICE/JTAG Connector
Trace Connector RS232 Connector
AT91RM9200
Terminal
AT91RM9200-based Application Board
Test Environment
Figure below shows test environment example. Test vectors sent interpreted tester. this example, "board under test" designed using many JTAG compliant devices. These devices connected together form single scan chain.
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Figure 6-3.
AT91RM9200-based Application IEEE1149.1 Test Environment Example
Test Adaptor Tester
JTAG Interface
ICE/JTAG Connector
Chip
Chip
AT91RM920
Chip
AT91RM9200-based Application Board Under Test
Debug Test Description
Debug Test List
Function Reset/Test Type Active Level
Table 6-1.
Name
NRST TST0 TST1
Microcontroller Reset Test Mode Select Test Mode Select JTAG
Input Input Input
NTRST JTAGSEL
Test Clock Test Data Test Data Test Mode Select Test Reset Signal JTAG Selection E(available only package)
Input Input Output Input Input Input
TSYNC TCLK TPS0- TPS2 TPK0 TPK15
Trace Synchronization Signal Trace Clock Trace Pipeline Status Trace Packet Port Debug Unit
Output Output Output Output
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
DRXD DTXD
AT91RM9200
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AT91RM9200
6.6.1
Functional Description
Test Mode Pins dedicated pins (TST1, TST0) used define test mode device. user must make sure that these pins both tied level ensure normal operating conditions. Other values associated these pins manufacturing test reserved.
6.6.2
Embedded In-Circuit Emulator ARM9TDMI Embedded In-Circuit Emulator supported ICE/JTAG port. connected host computer interface. Debug support implemented using ARM9TDMI core embedded within ARM920T. internal state ARM920T examined through ICE/JTAG port which allows instructions serially inserted into pipeline core without using external data bus. Therefore, when debug state, store-multiple (STM) inserted into instruction pipeline. This exports contents ARM9TDMI registers. This data serially shifted without affecting rest system. There scan chains inside ARM920T processor which support testing, debugging, programming Embedded ICE. scan chains controlled ICE/JTAG port. Embedded mode selected when JTAGSEL low. possible switch directly between JTAG operations. chip reset must performed (NRST NTRST) after JTAGSEL changed. test reset input embedded (NTRST) provided separately facilitate debug boot program. further details Embedded In-Circuit-Emulator, ARM920T Technical Reference Manual, Ltd, 0151C.
6.6.3
Debug Unit Debug Unit provides two-pin (DXRD TXRD) UART that used several debug trace purposes offers ideal means in-situ programming solutions debug monitor communication. Moreover, link with Peripheral Controller channels provides packet handling these tasks with processor time reduced minimum. Debug Unit also manages interrupt handling COMMTX COMMRX signals that come from trace activity Debug Communication Channel. Debug Unit used upload application into internal SRAM. activated boot program when valid application detected. specific register, Debug Unit Chip Register, informs about product version internal configuration. AT91RM9200 Debug Unit Chip value 0x09290781, 32-bit width. further details Debug Unit, "Debug Unit (DBGU)" page 321. further details Debug Unit Boot program, "Boot Program" page
6.6.4
Embedded Trace Macrocell AT91RM9200 features Embedded Trace Macrocell (ETM), which closely connected ARM9TDMI Processor. Embedded Trace standard mid-level implementation contains following resources: Four pairs address comparators
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data comparators Eight memory decoder inputs counters sequencer Four external inputs external output 18-byte FIFO Embedded Trace Macrocell AT91RM9200 works half-rate clock mode thus integrates clock divider. This assures that maximum frequency trace port signals exceed half ARM920T clock speed. Embedded Trace Macrocell input output resources used AT91RM9200. Embedded Trace real-time trace module with capability tracing ARM9TDMI instruction data. Embedded Trace debug features only accessible AT91RM9200 package. further details Embedded Trace Macrocell, ETM9 (Rev2a) Technical Reference Manual, Ltd. -DDI 0157E. 6.6.4.1 Trace Port Trace Port made following pins: TSYNC synchronization signal (Indicates start branch sequence trace packet port.) TCLK Trace Port clock, half-rate ARM920T processor clock. TPS0 TPS2 indicate processor state each trace clock edge. TPK0 TPK15 Trace Packet data value. trace packet information (address, data) associated with processor state indicated TPS. Some processor states have additional data associated with Trace Packet Port (i.e. failed condition code instruction). packet 8-bits wide, packets output cycle.
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AT91RM9200
Figure 6-4. ETM9 Block
TPS-TPS0 ARM920T Tracker Trace Control FIFO TPK15-TPK0 TSYNC
Trace Enable, View Data
Controller
Trigger, Sequencer, Counters
Scan Chain ETM9
6.6.4.2
Implementation Details This section gives overview Embedded Trace resources. further details, Embedded Trace Macrocell Specification, Ltd. -IHI 0014H.
Three-state Sequencer sequencer three possible next states (one dedicated itself others) change every clock cycle. sate transition controlled with internal events. user needs multiple-stage trigger schemes, trigger event based sequencer state. Address Comparator single mode, address comparators compare either instruction address data address against user-programmed address. range mode, address comparators arranged pairs form virtual address range resource. Details address comparator programming are: first comparator programmed with range start address. second comparator programmed with range address. resource matches address within following range: (address range start address) (address range address) Unpredictable behavior occurs address comparators configured same way. Data Comparator Each full address comparator associated with specific data comparator. data comparator used observe data only when load store operations occur. data comparator both value register mask register, therefore possible compare only certain bits preprogrammed value against data bus.
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Memory Decoder Inputs eight memory decoder inputs connected custom address decoders. address decoders divide memory into regions on-chip SRAM, on-chip ROM, peripherals. address decoders also optimize ETM9 trace trigger. Table 6-2.
Description SRAM SRAM NCS0-NCS7 NCS0-NCS7 User Peripheral System Peripheral
EMemory Inputs Layout
Region Internal Internal Internal Internal External External Internal Internal Access type Data Fetch Data Fetch Data Fetch Data Data start_address 0x00000000 0x00000000 0x00100000 0x00100000 0x10000000 0x10000000 0xF0000000 0xFFFFF000 end_address 0x000FFFFF 0x000FFFFF 0x001FFFFF 0x001FFFFF 0x8FFFFFFF 0x8FFFFFFF 0xFFFFEFFF 0xFFFFFFFF
FIFO 18-byte FIFO used store data tracing. FIFO used separate pipeline status from trace packet. FIFO used buffer trace packets. FIFO overflow detected embedded trace macrocell when FIFO full when FIFO less bytes than user-programmed number. further details, ETM9 (Rev2a) Technical Reference Manual, Ltd. 0157E. Half-rate Clocking Mode ETM9 implemented half-rate mode that allows both rising falling edge data tracing trace clock. half-rate mode implemented maintain signal clock integrity high speed systems Mhz). Figure 6-5. Half-rate Clocking Mode
ARM920T Clock
Trace Clock
TraceData
Half-rate Clocking Mode
Care must taken choice trace capture system needs support half-rate clock functionality.
AT91RM9200
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AT91RM9200
6.6.4.3 Application Board Restriction TCLK signal needs with care, some timing parameters required. Refer AT91RM9200 "JTAG/ICE Timings" page "ETimings" page 648. specified target system connector Mictor connector. connector must oriented application board described below Figure 6-6. view shown from above with trace connector mounted near edge board. This allows Trace Port Analyzer minimize physical intrusiveness interconnected target. Figure 6-6. Mictor Connector Orientation
AT91RM9200-based Application Board
1Chamfer
6.6.5
IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent device packaging technology. IEEE 1149.1 JTAG Boundary Scan enabled when JTAGSEL high. SAMPLE, EXTEST BYPASS functions implemented. debug mode, processor responds with non-JTAG chip that identifies processor system. This IEEE 1149.1 JTAG-compliant. possible switch directly between JTAG operations. chip reset must performed (NRST NTRST) after JTAGSEL changed. Boundary Scan Descriptor Language (BSDL) files provided testing. Each BSDL file dedicated specific packaging.
6.6.5.1
JTAG Boundary Scan Register Boundary Scan Register (BSR) contains bits which correspond active pins associated control signals. Each AT91RM9200 input corresponding Boundary Scan Register observability. Each AT91RM9200 output corresponding 2-bit register BSR. OUTPUT contains data which forced pad. CTRL into high impedance.
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Each AT91RM9200 input/output corresponds 3-bit register BSR. OUTPUT contains data that forced pad. INPUT facilitates observability data applied pad. CTRL selects direction pad. Table 6-3.
Number NWE/NWR0 NUB/NWR1/NBS1 NBS3 SDCKE SDCKE/RAS/CAS/WE/SDA10 Output Output Output Output Output Output Output OUTPUT OUTPUT OUTPUT CTRL OUTPUT OUTPUT OUTPUT Output OUTPUT INPUT NCS0/BFCS NCS[1:0]/NOE/NRD/NUB/ NWR1/NBS1/BFCS/SDCS NCS1/SDCS NCS2 NCS[2:3]/NBS3 NCS3 NOE/NRD Output Output Output Output Output Output Output PC9/A25/CFRNW PC8/A24 PC7/A23
JTAG Boundary Scan Register
Name A[19:16]/BA0/BA1 A[22:20]/NWE/NWR0 Type Output Output Output Output Output Output Associated Cells OUTPUT CTRL OUTPUT CTRL OUTPUT OUTPUT INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL OUTPUT CTRL OUTPUT OUTPUT CTRL OUTPUT OUTPUT INPUT
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Table 6-3.
Number OUTPUT OUTPUT INPUT D[15:12] OUTPUT CTRL INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT D[11:8] OUTPUT CTRL INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT D[7:4] OUTPUT CTRL INPUT OUTPUT INPUT OUTPUT INPUT OUTPUT INPUT D[3:0] OUTPUT CTRL INPUT
JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT
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Table 6-3.
Number
JTAG Boundary Scan Register (Continued)
Name Type OUTPUT INPUT PC16/D16 OUTPUT CTRL INPUT PC17D17 OUTPUT CTRL INPUT PC18/D18 OUTPUT CTRL INPUT PC19/D19 OUTPUT CTRL INPUT PC20/D20 OUTPUT CTRL INPUT PC21/D21 OUTPUT CTRL INPUT PC22/D22 OUTPUT CTRL INPUT PC23/D23 OUTPUT CTRL INPUT PC24/D24 OUTPUT CTRL INPUT PC25/D25 OUTPUT CTRL INPUT PC26/D26 OUTPUT CTRL Associated Cells INPUT
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Table 6-3.
Number PC15 PC14 PC13/NCS7 PC12/NCS6/CFCE2 PC11/NCS5/CFCE1 PC10/NCS4/CFCS PC31/D31 PC30/D30 PC29/D29 PC28/D28 PC27/D27
JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL
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Table 6-3.
Number
JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT PC0/BCFK OUTPUT CTRL INPUT PC1/BFRDY/SMOE OUTPUT CTRL INPUT PC2/BFAVD OUTPUT CTRL INPUT PC3/BFBAA/SMWE OUTPUT CTRL INPUT PC4/BFOE OUTPUT CTRL INPUT PC5/BFWE OUTPUT CTRL INPUT PC6/NWAIT OUTPUT CTRL INPUT PA0/MISO/PCK3 OUTPUT CTRL INPUT PA1/MOSI/PCK0 OUTPUT CTRL INPUT PA2/SPCK/IRQ4 OUTPUT CTRL INPUT PA3/NPCS0/IRQ5 OUTPUT CTRL
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AT91RM9200
Table 6-3.
Number PA7/ETXCK/EREFCK/PCK2 PA6/NPCS3/RXD3 PD6/DTXD PD5/ETXER PD4/ETXEN PD3/ETX3 PD2/ETX2 PD1/ETX1 PD0/ETX0 PA5/NPCS2/TXD3 PA4/NPCS1/PCK1
JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL
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Table 6-3.
Number
JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT PA8/ETXEN/MCCDB OUTPUT CTRL INPUT PA9/ETX0/MCDB0 OUTPUT CTRL INPUT PA10/ETX1/MCDB1 OUTPUT CTRL INPUT PA11/ECRS/ECRSDV/MCDB2 OUTPUT CTRL INPUT PA12/ERX0/MCDB3 OUTPUT CTRL INPUT PA13/ERX1/TCLK0 OUTPUT CTRL INPUT PA14/ERXER/TCLK1 OUTPUT CTRL INPUT PA15/EMDC/TCLK2 OUTPUT CTRL INPUT PA16/EMDIO/IRQ6 OUTPUT CTRL INPUT PA17/TXD0/TIOA0 OUTPUT CTRL INPUT PA18/RXD0/TIOB0 OUTPUT CTRL
AT91RM9200
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AT91RM9200
Table 6-3.
Number PA29/MCDA0/TCLK5 PA28/MCCDA/TCLK4 PA27/MCCK/TCLK3 PA26/TWCK/IRQ1 PA25/TWD/IRQ2 PA24/SCK2/PCK1 PA23/TXD2/IRQ3 PA22/RXD2/TIOB2 PA21/RTS0/TIOA2 PA20/CTS0/TIOB1 PA19/SCK0/TIOA1
JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL
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Table 6-3.
Number
JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT PA30/DRXD/CTS2 OUTPUT CTRL INPUT PA31/DTXD/RTS2 OUTPUT CTRL INPUT PB0/TF0/RTS3 OUTPUT CTRL INPUT PB1/TK0/CTS3 OUTPUT CTRL INPUT PB2/TD0/SCK3 OUTPUT CTRL INPUT PB3/RD0/MCDA1 OUTPUT CTRL INPUT PB4/RK0/MCDA2 OUTPUT CTRL INPUT PB5/RF0/MCDA3 OUTPUT CTRL INPUT PB6/TF1/TIOA3 OUTPUT CTRL INPUT PB7/TK1/TIOB3 OUTPUT CTRL INPUT PB8/TD1/TIOA4 OUTPUT CTRL
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AT91RM9200
Table 6-3.
Number PD9/PCK2/TPS0 PD8/PCK1/TCLK PD7/PCK0/TSYNC PB16/RK2/ERX3 PB15/RD2/ERX2 PB14/TD2/ETXER PB13/TK2/ETX3 PB12/TF2/ETX2 PB11/RF1/TIOB5 PB10/RK1/TIOA5 PB9/RD1/TIOB4
JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL
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Table 6-3.
Number
JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT PD10/PCK3/TPS1 OUTPUT CTRL INPUT PD11/TPS2 OUTPUT CTRL INPUT PD12/TPK0 OUTPUT CTRL INPUT PB17/RF2/ERXDV OUTPUT CTRL INPUT PB18/RI1/ECOL OUTPUT CTRL INPUT PB19/DTR1/ERXCK OUTPUT CTRL INPUT PB20/TXD1 OUTPUT CTRL INPUT PB21/RXD1 OUTPUT CTRL INPUT PB22/SCK1 OUTPUT CTRL INPUT PD13/TPK1 OUTPUT CTRL INPUT PD14/TPK2 OUTPUT CTRL
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AT91RM9200
Table 6-3.
Number PD20/NPCS3/TPK8 PD19/NPCS2/TPK7 PD18/NPCS1/TPK6 PD17/TD2/TPK5 PD16/TD1/TPK4 PB27/PCK0 PB26/RTS1 PB25/DSR1/EF100 PB24/CTS1 PB23/DCD1 PD15/TD0/TPK3
JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL
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Table 6-3.
Number
JTAG Boundary Scan Register (Continued)
Name Type Associated Cells INPUT PD21/RTS0/TPK9 OUTPUT CTRL INPUT PD22/RTS1/TPK10 OUTPUT CTRL INPUT PD23/RTS2/TPK11 OUTPUT CTRL INPUT PD24/RTS3/TPK12 OUTPUT CTRL INPUT PD25/DTR1/TPK13 OUTPUT CTRL INPUT PD26/TPK14 OUTPUT CTRL INPUT PD27/TPK15 OUTPUT CTRL INPUT PB28/FIQ OUTPUT CTRL INPUT PB29/IRQ0 OUTPUT CTRL A0/NLB/NBS0 A[3:0]/NLB/NWR2/NBS0 /NBS2 A1/NWR2/NBS2 A[7:4] Output Output Output Output Output Output Output Output OUPUT CTRL OUTPUT OUTPUT OUTPUT OUTPUT CTRL OUTPUT
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AT91RM9200
Table 6-3.
Number
JTAG Boundary Scan Register (Continued)
Name A[11:8] SDA10 A[15:12] A16/BA0 A17/BA1 Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Associated Cells OUTPUT OUTPUT OUTPUT CTRL OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT CTRL OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT
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6.6.6
AT91RM9200 Code Register
Access: Read-only
VERSION
PART NUMBER
PART NUMBER
PART NUMBER
MANUFACTURER IDENTITY
MANUFACTURER IDENTITY
VERSION[31:28]: Product Version Number JTAGSEL low. JTAGSEL high. PART NUMBER[27:14]: Product Part Number 0x5b02. MANUFACTURER IDENTITY[11:1] 0x01f. [0]: Required IEEE Std. 1149.1
AT91RM9200 Code value 0x15b0203f (JTAGSEL High). AT91RM9200 Code value 0x05b0203f (JTAGSEL Low).
AT91RM9200
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AT91RM9200
Boot Program
Overview
Boot Program capable downloading application AT91RM9200-based system. integrates Bootloader boot Uploader assure correct information download. Bootloader activated first. looks sequence eight valid exception vectors DataFlash connected SPI, EEPROM connected Two-wire Interface (TWI) 8-bit memory device connected external interface (EBI). these vectors must Bbranch load register instructions except sixth instruction. This vector used store information, such size image download type DataFlash device. valid sequence found, code downloaded into internal SRAM. This followed remap jump first address SRAM. valid vector sequence found, boot Uploader started. initializes Debug Unit serial port (DBGU) Device Port. then waits transaction downloads piece code into internal SRAM Device Firmware Upgrade (DFU) protocol XMODEM protocol DBGU. After download, branches application entry point first address SRAM. main features Boot Program are: Default Boot Program stored ROM-based products Downloads runs application from external storage media into internal SRAM Downloaded code size depends embedded SRAM size Automatic detection valid application Bootloader supporting wide range non-volatile memories DataFlash® connected NPCS0 Two-wire EEPROM 8-bit parallel memories NCS0 Boot Uploader case valid program detected external supporting several communication media Serial communication DBGU (XModem protocol) Device Port (DFU Protocol)
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Flow Diagram
Boot Program implements algorithm presented Figure 7-1. Figure 7-1. Boot Program Algorithm Flow Diagram
Device Setup
DataFlash Boot
Download from DataFlash
Bootloader
Timeout
EEPROM Boot
Download from EEPROM
Timeout
Parallel Boot
Download from 8-bit Device
DBGU Serial Download Download DFU* protocol *DFU Device Firmware Upgrade
Boot Uploader
AT91RM9200
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AT91RM9200
Bootloader
Boot Program started from address 0x0000_0000 (ARM reset vector) when on-chip boot mode selected (BMS high during reset, only devices with integrated). first operation search valid program off-chip non-volatile memories. valid application found, this application loaded into internal SRAM executed branching address 0x0000_0000 after remap. This application application code secondlevel Bootloader. optimize downloaded application code size, Boot Program embeds several functions that reused application. Boot Program linked address 0x0010_0000 internal mapped both 0x0000_0000 0x0010_0000 after reset. call functions relative does absolute addresses. vectors present both addresses, 0x0000_0000 0x0010_0000. access functions ROM, structure containing chip descriptor function entry points defined fixed address ROM. valid application detected, debug serial port device port must connected allow upload. specific application provided Atmel (DFU uploader) loads application into internal SRAM through USB. load application through debug serial port, terminal application (HyperTerminal) running Xmodem protocol required. Figure 7-2. Remap Action after Download Completion
Internal SRAM 0x0020_0000 REMAP
Internal 0x0010_0000
Internal 0x0000_0000
Internal SRAM 0x0000_0000
After reset, code internal mapped both addresses 0x0000_0000 0x0010_0000:
100000 100004 100008 10000c 100010 100014 100018 10001c ea00000b e59ff014 e59ff014 e59ff014 e59ff014 00001234 e51fff20 e51fff20 0x2c00ea00000bB0x2c
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7.3.1
Valid Image Detection Bootloader software looks valid application analyzing first bytes corresponding exception vectors. These bytes must implement instructions either branch load with relative addressing. sixth vector, offset 0x14, contains size image download DataFlash parameters. user must replace this vector with vector.
Figure 7-3.
Opcode
Figure 7-4.
Opcode
Offset bits)
Unconditional instruction: bits Load with relative addressing instruction: I==1 P==1 offset added (U==1) subtracted (U==0) W==1 7.3.1.1 Example example valid vectors:
ea00000b e59ff014 e59ff014 e59ff014 e59ff014 00001234 e51fff20 e51fff20 [PC,-0xf20] [PC,-0xf20] 0x2c [PC,20] [PC,20] [PC,20] [PC,20]
Code size 4660 bytes
download mode (DataFlash, EEPROM 8-bit memory device with integrated), size image load into SRAM contained location sixth vector. Thus user must replace this vector correct vector application.
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7.3.2 Structure Vector exception vector used store information needed Boot downloader. This information described below. Figure 7-5. Structure vector
DataFlash page size Reserved bytes blocks download
Number pages
first eight bits contain number blocks download. size block bytes, allowing download 128K bytes. bits determine DataFlash page number. DataFlash page number 2(Nb pages) last bits contain DataFlash page size. Table 7-1.
Device AT45DB011B AT45DB021B AT45DB041B AT45DB081B AT45DB161B AT45DB321B AT45DB642 AT45DB1282
DataFlash Device
Density Mbit Mbits Mbits Mbits Mbits Mbits Mbits Mbits Page Size (bytes) 1056 1056 Number pages 1024 2048 4096 4096 8192 8192 16384
7.3.2.1
Example following vector contains information describe AT45DB642 DataFlash which contains 11776 bytes download. Vector 0x0841A017 Size download: 0x17 bytes 11776 bytes Number pages (1101b): Number DataFlash pages 8192 DataFlash page size(000010000100000b) 1056 download EEPROM 8-bit external memory, only size downloaded decoded.
1768E-ATARM-30-Sep-05
7.3.3
Bootloader Sequence Boot Program performs device initialization followed download procedure. unsuccessful, upload done debug serial port.
7.3.3.1
Device Initialization Initialization follows steps described below: setup PLLB initialized generate clock necessary Device. register located Power Management Controller (PMC) determines frequency main oscillator thus correct factor PLLB. Table defines crystals supported Boot Program. Table 7-2.
4.433619 6.144 7.864320 12.0 16.0
Crystals Supported Software Auto-detection (MHz)
3.2768 4.9152 12.288 17.734470 3.6864 6.5536 9.8304 13.56 18.432 3.84 5.24288 7.159090 10.0 14.31818 20.0 7.3728 11.05920 14.7456
Stacks setup each mode Main oscillator frequency detection Interrupt controller setup variables initialization Branch main function 7.3.3.2 Download Procedure download procedure checks valid boot several devices. first device checked serial DataFlash connected NPCS0 SPI, followed serial EEPROM connected 8-bit parallel memory connected NCS0 External Interface.
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
7.3.3.3 Serial DataFlash Download Boot Program supports Atmel DataFlash devices. Table summarizes parameters include vector devices. DataFlash Status Register that determines parameters required access device. Thus, compatible with future design DataFlash, parameters coded vector Figure 7-6. Serial DataFlash Download
Start
Send status command
status
Serial DataFlash Download
Read first instructions bytes). Decode sixth vector
vectors (except vector Branch instruction
Read DataFlash into internal SRAM. (code size read vector
Restore reset value peripherals. perform REMAP jump downloaded application
1768E-ATARM-30-Sep-05
7.3.3.4
Serial Two-wire EEPROM Download Generally, serial EEPROMs have identification code. bootloader checks acknowledgment first read. device address two-wire must 0x0. bootloader supports devices listed Table 7-3. Table 7-3. Supported EEPROM Devices
Device AT24C16A AT24C164 AT24C32 AT24C64 AT24C128 AT24C256 AT24C512 Size Kbits Kbits Kbits Kbits Kbits Kbits Kbits Organization bytes page write bytes page write bytes page write bytes page write bytes page write bytes page write bytes page write
Figure 7-7.
Serial Two-Wire EEPROM Download
Start
Send Read command
8-bits parallel memory Download Device
Only Device with integrated
Memory Uploader
Only Device without integrated
Read first instructions bytes). Decode sixth vector
vectors (except vector Branch instruction
Read Two-Wire EEPROM into internal SRAM (code size read vector
Restore reset value peripherals. perform REMAP jump downloaded application
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
7.3.3.5 8-bit Parallel Flash Download (Applicable Devices with EBI) Eight-bit parallel Flash download supported product integrates External Interface (EBI). 8-bit memory devices supported when NCS0 configured 8-bit data width supported bootloader. Figure 7-8. 8-bit Parallel Flash Download
Start
Setup memory controller
Read first instructions bytes). Read size sixth vector
vectors (except vector Branch instruction
Memory uploader
Read external memory into internal SRAM (code size read vector
Restore reset value peripherals. perform REMAP jump downloaded application
1768E-ATARM-30-Sep-05
Boot Uploader
valid boot device been found during Bootloader sequence, initialization serial communication devices (DBGU device ports) performed. Initialization DBGU serial port (115200 bauds, Xmodem protocol start Initialization Device Port protocol start Download application boot Uploader performs Xmodem protocols upload application into internal SRAM address 0x0020_0000. Boot Program uses piece internal SRAM variables stacks. prevent upload error, size application upload must less than SRAM size minus bytes. After download, peripheral registers reset, interrupts disabled remap performed. After remap, internal SRAM address 0x0000_0000 internal address 0x0010_0000. instruction setting just after remap command. This instruction fetched pipe before doing remap executed just after. This fetch cycle executes downloaded image.
7.4.1 7.4.1.1
External Communication Channels DBGU Serial Port upload performed through DBGU serial port initialized 115200 Baud, DBGU sends character (0x43) start Xmodem protocol. terminal performing this protocol used send application file target. size binary file send depends SRAM size embedded product (Refer microcontroller datasheet determine SRAM size embedded microcontroller). cases, size binary file must lower than SRAM size because Xmodem protocol requires some SRAM memory work.
7.4.1.2
Xmodem Protocol Xmodem protocol supported 128-byte length block. This protocol uses character CRC-16 guarantee detection maximum error. Xmodem protocol with accurate provided both sender receiver report successful transmission. Each block transfer looks like: <SOH><blk #><255-blk #><-128 data bytes-><checksum> which: <SOH> <blk binary number, starts increments wraps 0FFH (not <255-blk complement blk#. <checksum> bytes CRC16 Figure shows transmission using this protocol.
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
Figure 7-9. Xmodem Transfer Example
Host Data[128] Data[128] Data[100] Device
7.4.1.3
Device Port clock necessary Device port. been programmed earlier device initialization with PLLB configuration.
7.4.1.4
Protocol allows upgrade firmware devices. algorithm part specification. more details, refer "USB Device Firmware Upgrade Specification, Rev. 1.0". There four distinct steps when carrying firmware upgrade: Enumeration: device informs host capabilities. Reconfiguration: host device agree initiate firmware upgrade. Transfer: host transfers firmware image device. Status requests employed maintain synchronization between host device. Manifestation: Once device reports host that completed reprogramming operations, host issues reset device executes upgraded firmware. Figure 7-10. Protocol
Host Prepare upgrade Device
reset mode activated Download this firmware Prepare exit mode reset
1768E-ATARM-30-Sep-05
Hardware Software Constraints
software limitations Boot Program are: downloaded code size less than SRAM size embedded product. device address EEPROM must bus. code always downloaded from device address 0x0000_0000 (DataFlash, EEPROM) address 0x0000_0000 internal SRAM (after remap). downloaded code must position-independent linked address 0x0000_0000. hardware limitations Boot Program are: DataFlash must connected NPCS0 SPI. 8-bit parallel Flash must connected NCS0 EBI. Boot Program initializes DBGU pins multiplexed common both 208lead PQFP 256-ball packages, this case meaning PIOA. Using external clock source possible main oscillator enabled Boot ROM. drivers several PIOs alternate functions communicate with devices. Care must taken when these PIOs used application. devices connected could unintentionally driven boot time, electrical conflicts between output pins connected devices appear. assure correct functionality, recommended plug critical devices other pins boot external 16-bit parallel memory setting BMS. Table contains list pins that driven during Boot Program execution. These pins driven during boot sequence period about correct boot program found. download through takes about bytes rate (100 Kbits/s). DataFlash driven SPCK signal MHz, time download bytes reduced Before performing jump application internal SRAM, PIOs peripherals used Boot Program their reset state. Table 7-4.
Used MOSI(1) SPCK
Pins Driven during Boot Program Execution
(DataFlash) (EEPROM)
NPCS0 TWD(1)
TWCK(1) Note:
"Peripheral Multiplexing Lines" page
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
Embedded Software Services
Overview
embedded software service independent software object that drives device resources frequently implemented tasks. object-oriented approach software provides easy access services build applications. AT91 service several purposes: gives software examples dedicated AT91 devices. used several AT91 device families. offers interface software stored ROM. main features software services are: Compliant with ATPCS Compliant with ANSI/ISO Standard Compiled ARM/Thumb Interworking Entry Service Tempo, Xmodem DataFlash services Sine tables
8.2.1 8.2.1.1
Service Definition
Service Structure Structure Definition service structure defined header files. This structure composed data members pointers functions (methods) similar class definition. There protection data access methods access. However, some functions used customer application other services considered public methods. Similarly, other functions invoked them. They considered private methods. This also valid data.
8.2.1.2
Methods service structure, pointers functions supposed initialized default standard functions. Only default standard functions reside ROM. Default methods overloaded custom application methods. Methods declare static variables invoke global variables. methods invoked with pointer service structure. method access update service data without restrictions. Similarly, there polling methods. fact, there method start functionality read give example), method status read achieved?), callback, initialized start method. Thus, using service, client application carries synchronous read starting read polling status, asynchronous read specifying callback when starting read operation.
1768E-ATARM-30-Sep-05
8.2.1.3
Service Entry Point Each AT91 service, except Entry Service (see 8.3.2 "ROM Entry Service" page 103), defines function named AT91F_Open_<Service>. only entry point defined service. Even functions AT91F_Open_<Service> compared with object constructors, they constructors that they initiate service structure they allocate Thus customer application must allocate
Example
Allocation service structure AT91S_Pipe pipe; Opening service AT91PS_Pipe pPipe AT91F_OpenPipe(&pipe,
Method pointers service structure initialized default methods defined AT91 service. Other fields service structure initialized default values with arguments function AT91F_Open_<Service>. summary, application must know what service structure where function AT91F_Open_<Service> default function AT91F_Open_<Service> redefined application comprised application-defined function. 8.2.2 8.2.2.1 Using Service Opening Service entry point service established initializing service structure. open function associated with each service structure, except Entry Service (see 8.3.2 "ROM Entry Service" page 103). Thus, only functions AT91F_Open_<service> visible from user side. Access service methods made function pointers service structure. function AT91F_Open_<service> least argument: pointer service structure that must allocated elsewhere. returns pointer base service structure pointer this service structure. function AT91F_Open_<service> initializes data members method pointers. function pointers service structure service's functions. advantage this method offer single entry point service. methods service initialized open function each member overloaded. 8.2.2.2 Overloaqding Method Default methods defined services provided ROM. These methods adapted project requirement. possible overload default methods methods defined project. method pointer function. This pointer initialized function AT91F_Open_<Service>. overload several methods service, function pointer must updated method.
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
possible overload just method service methods service. this latter case, functionality service user-defined, still works same data structure.
Note: Calling default function AT91F_Open_<Service> ensures that methods data initialized.
This done writing function My_OpenService(). This Open function must call library-defined function AT91F_Open_<Service>, then update several function pointers: Table 8-1. Overloading Method with Overloading Open Service Function
Overloading AT91F_ChildMethod My_ChildMethod My_ChildMethod will replace AT91F_ChildMethod char My_ChildMethod Overloading Open Service Method Defined obj_service.c ROM) char AT91F_MainMethod char AT91F_ChildMethod Init service with default methods AT91PS_Service AT91F_OpenService( AT91PS_Service pService) pService->data pService->MainMethod =AT91F_MainMethod; return pService; Opening service AT91PS_Service pService My_OpenService(&service); Allocation service structure AT91S_Service service; AT91PS_Service My_OpenService( AT91PS_Service pService) AT91F_OpenService(pService); Overloading ChildMethod default value pService->ChildMethod= My_ChildMethod; return pService;
Default service behavior Defined embedded_services.h typedef struct _AT91S_Service char data; char (*MainMethod) char (*ChildMethod) AT91S_Service, AT91PS_Service;
1768E-ATARM-30-Sep-05
This also done directly overloading method after AT91F_Open_<Service> method: Table 8-2. Overloading Method without Overloading Open Service Function.
Overloading AT91F_ChildMethod My_ChildMethod My_ChildMethod will replace AT91F_ChildMethod char My_ChildMethod Allocation service structure Defined obj_service.c ROM) char AT91F_MainMethod char AT91F_ChildMethod Init service with default methods AT91PS_Service AT91F_OpenService( AT91PS_Service pService) pService->data pService->MainMethod =AT91F_MainMethod; return pService; Overloading ChildMethod default value pService->ChildMethod= My_ChildMethod; Opening service AT91PS_Service pService AT91F_OpenService(&service); AT91S_Service service;
Default service behavior Defined embedded_services.h typedef struct _AT91S_Service char data; char (*MainMethod) char (*ChildMethod) AT91S_Service, AT91PS_Service;
AT91RM9200
1768E-ATARM-30-Sep-05
AT91RM9200
8.3.1
Embedded Software Services
Definition Several AT91 products embed ROM. most cases, integrates bootloader several services that speed application reduce application code size. When software fixed ROM, address each object (function, constant, table, etc.) must related customer application. This done providing address table linker. each version ROM, address table must provided client applications must recompiled. Embedded Software Services offer another solution access objects stored ROM. each embedded service, customer application requires only address Service Entry Point (see 8.2.1.3 "Service Entry Point" page 100). Even these services have only entry point (AT91F_Open_<Service> function), they must specified linker. Embedded Software Services solve this problem providing dedicated service: Entry Service. goal this product-dedicated service provide just address access functionalities.
8.3.2
Entry Service Entry Service product structure named AT91S_RomBoot. Some members this structure point open functions services stored (function AT91F_Open_<Service>) also Sine Arrays. Thus, only address AT91S_RomBoot published.
Table 8-3.
Initialization Entry Service with Open Service Method
Memory Space AT91S_TempoStatus AT91F_OpenCtlTempo( AT91PS_CtlTempo pCtlTempo, void const *pTempoTimer AT91S_TempoStatus AT91F_CtlTempoCreate AT91PS_CtlTempo pCtrl, AT91PS_SvcTempo pTempo)
Application Memory Space Init Entry Service AT91S_RomBoot const *pAT91; pAT91 AT91C_ROM_BOOT_ADDRESS; Allocation service structure AT91S_CtlTempo tempo; Call Service Open method pAT91->OpenCtlTempo(&tempo, tempo methods tempo.CtlTempoCreate(&tempo,
application obtains address Entry Service initializes instance AT91S_RomBoot structure. obtain Open Service Method another service stored ROM, application uses appropriate member AT91S_RomBoot structure. address AT91S_RomBoot found beginning ROM, after exception vectors.
1768E-ATARM-30-Sep-05
8.3.3 8.3.3.1
Tempo Service Presentation Tempo Service allows single hardware system timer support several software timers running concurrently. This works object notifier. There objec
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