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EP9302 Data Sheet
ARM920T Processor Kbyte Instruction Cache Kbyte Data Cache Linux®, Microsoft® Windows® enabled System
High Speed ARM9 Systemon-Chip Processor with MaverickCrunch
6-channel Serial Audio Interface (I2S) 2-channel low-cost Serial Audio Interface (AC'97) Internal Peripherals Direct Memory Access (DMA) Channels Real-time Clock with software Trim Dual controls clock domains Watchdog Timer general purpose 16-bit timers general purpose 32-bit timer 40-bit Debug Timer Interrupt Controller Boot Package 208-pin LQFP
MaverickCrunchMath Engine Floating point, integer signal processing instructions Optimized digital music compression decompression algorithms Hardware interlocks allow in-line coding MaverickKeyIDs 32-bit unique used compliance 128-bit random Integrated Peripheral Interfaces 16-bit SDRAM Interface banks 16-bit SRAM FLASH Serial EEPROM Interface 1/10/100 Mbps Ethernet UARTs Two-port Full Speed Host (OHCI) Mbits second) IrDA Interface Serial Peripheral Interface (SPI) Port
COMMUNICATIONS PORTS
Serial Audio Interface
Peripheral
USER INTERFACE
MaverickCrunch
UARTs IrDA
Channel
Clocks Timers
ARM920T
MaverickKeyHosts
D-Cache 16KB
I-Cache 16KB
Interrupts GPIO
Processor
Bridge
Ethernet
Boot
SRAM Flash
Unified SDRAM
MEMORY STORAGE
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OVERVIEW
EP9302 ARM920T-based system-on-a-chip design with large peripheral targeted variety applications: Industrial controls Digital media servers Integrated home media gateways Digital audio jukeboxes Streaming audio players Set-top boxes Point-of-sale terminals Thin clients Biometric security systems fleet management systems Educational toys Industrial computers Industrial hand-held devices Voting machines Medical equipment
ARM920T microprocessor core with separate Kbyte, 64-way set-associative instruction data caches augmented MaverickCrunchcoprocessor enabling faster than real-time compression audio CDs. MaverickKeyunique hardware programmed solution growing concern over secure content commerce. With Internet security playing important role delivery digital media such books music, traditional software methods quickly becoming unreliable. MaverickKey unique provide OEMs with method utilizing specific hardware such those assigned SDMI (Secure Digital Music Initiative) other authentication mechanism. high-performance 1/10/100 Mbps Ethernet Media Access Controller (EMAC) included along with external interfaces SPI, AC'97 audio. two-port Full Speed Host (OHCI) Mbits second), UARTs, analog voltage measurement Analog Digital Converter (ADC) included well. EP9302 high-performance, low-power RISCbased single-chip computer built around ARM920T microprocessor core with maximum operating clock rate (184 industrial conditions). core operates from supply, while operates with power usage between (dependent speed).
EP9302 series ARM920T-based devices. Other members family have different peripheral sets, coprocessors package configurations.
Table Change History
Revision
Date
June 2004 July 2004 Initial Release. Update data. data.
Changes
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EP9302 High Speed ARM9 System-on-Chip Processor with MaverickCrunch
Table Contents
Processor Core ARM920T MaverickCrunchMath Engine MaverickKeyUnique General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH) Ethernet Media Access Controller (MAC) Serial Interfaces (SPI, '97) 12-bit Analog-to-Digital Converter (ADC) Universal Asynchronous Receiver/Transmitters (UARTs) Dual Port Host Two-Wire Interface With EEPROM Support Real-Time Clock with Software Trim Clocking Timers Interrupt Controller Dual Drivers General Purpose Input/Output (GPIO) Reset Power Management Hardware Debug Interface 12-Channel Controller Internal Boot
Electrical Specifications
Absolute Maximum Ratings Recommended Operating Conditions Characteristics
Timings
Memory Interface Ethernet Interface Audio Interface AC'97 JTAG
LQFP Package Outline
LQFP Pinout
Acronyms Abbreviations Units Measurement ORDERING INFORMATION
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List Figures
Figure Timing Diagram Drawing Figure SDRAM Load Mode Register Cycle Timing Measurement Figure SDRAM Burst Read Cycle Timing Measurement Figure SDRAM Burst Write Cycle Timing Measurement Figure SDRAM Auto Refresh Cycle Timing Measurement Figure Static Memory Multiple Word Read Cycle Timing Measurement Figure Static Memory Multiple Word Write Cycle Timing Measurement Figure Static Memory Multiple Word Read Cycle Timing Measurement Figure Static Memory Multiple Word Write Cycle Timing Measurement Figure Static Memory Burst Read Cycle Timing Measurement Figure Static Memory Single Read Wait Cycle Timing Measurement Figure Static Memory Single Write Wait Cycle Timing Measurement Figure Static Memory Turnaround Cycle Timing Measurement Figure Ethernet Timing Measurement Figure Single Transfer Timing Measurement Figure Microwire Frame Format, Single Transfer Figure Format with SPH=1 Timing Measurement Figure Inter-IC Sound (I2S) Timing Measurement Figure Configuration Timing Measurement Figure Transfer Function Figure JTAG Timing Measurement
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EP9302 High Speed ARM9 System-on-Chip Processor with MaverickCrunch
List Tables
Table Change History Table General Purpose Memory Interface Assignments Table Ethernet Media Access Controller Assignments Table Audio Interfaces Assignment Table 12-bit Analog-to-Digital Converter Assignments Table Universal Asynchronous Receiver/Transmitters Assignments Table Dual Port Host Assignments Table Two-Wire Port with EEPROM Support Assignments Table Real-Time Clock with Assignments Table Clocking Assignments Table Interrupt Controller Assignment Table Dual Assignments Table M.General Purpose Input/Output Assignment Table Reset Power Management Assignments Table Hardware Debug Interface Table List Numerical Order Number Table Descriptions Table Multiplex Usage Information
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EP9302 High Speed ARM9 System-on-Chip Processor with MaverickCrunch
Processor Core ARM920T
ARM920T Harvard architecture processor with separate Kbyte instruction data caches with 8word line length unified memory. processor utilizes five-stage pipeline consisting fetch, decode, execute, memory write stages. features include: (32-bit) Thumb (16-bit compressed) instruction sets 32-bit Advanced Micro-Controller Architecture (AMBA) Kbyte Instruction Cache with lockdown Kbyte Data Cache (programmable write-through write-back) with lockdown Linux®, Microsoft® Windows® other operating systems Translation Look Aside Buffers with Data Instruction Entries Programmable Page Sizes Kbyte, Kbyte, Kbyte Independent lockdown Entries
provide OEMs with method utilizing specific hardware such those assigned SDMI (Secure Digital Music Initiative) other authentication mechanism. Both specific 32-bit well 128-bit random programmed into EP9302 through laser probing technology. These then used match secure copyrighted content with target device EP9302 powering, then deliver copyrighted information over secure connection. addition, secure transactions benefit also matching device server IDs. MaverickKey provide level hardware security required today's Internet appliances.
General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH)
EP9302 features unified memory address model where memory devices accessed over common address/data bus. Memory accesses performed Processor bus. SRAM memory controller supports 16-bit devices accommodates internal boot concurrently with 16-bit SDRAM memory. banks 16-bit SDRAM internal port connected Processor Address data shared between SDRAM, SRAM, ROM, FLASH memory Both NAND FLASH memory supported
Table General Purpose Memory Interface Assignments
MaverickCrunchMath Engine
MaverickCrunch Engine mixed-mode coprocessor designed primarily accelerate math processing required rapidly encode digital audio formats. accelerates single double precision integer floating point operations plus integer multiply-accumulate (MAC) instruction that considerably faster than ARM920T's native instruction. ARM920T coprocessor interface utilized thereby sharing memory interface instruction stream. Hardware forwarding interlock allows handle looping addressing while MaverickCrunch handles computation. Features include: IEEE-754 single double precision floating point 64-bit integer multiply compare Integer 32-bit input with 72-bit accumulate Integer Shifts Floating point to/from integer conversion Sixteen 64-bit register files Four 72-bit accumulators
Mnemonic
SDCLK SDCLKEN SDCSn[3:0] RASn CASn SDWEn CSn[7:6] CSn[3:0] AD[25:0] DA[15:0] DQMn[1:0]
Description
SDRAM Clock SDRAM Clock Enable SDRAM Chip Selects SDRAM SDRAM SDRAM Write Enable Chip Selects Address 25-0 Data 15-0 SDRAM Output Enables Data Masks SRAM Write Strobe SRAM Read Strobe SRAM Wait Input
MaverickKeyUnique
MaverickKey unique hardware programmed solution growing concern over secure content commerce. With Internet security playing important role delivery digital media such books music, traditional software methods quickly becoming unreliable. MaverickKey unique
WAITn
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Ethernet Media Access Controller (MAC)
subsystem compliant with ISO/TEC 802.3 topology single shared medium with several stations. Multiple MII-compliant PHYs supported. Features include: Supports 1/10/100 Mbps transfer rates home small-business large-business applications Interfaces off-chip through industry standard Media Independent Interface (MII)
Table Ethernet Media Access Controller Assignments
Table Audio Interfaces Assignment
Name
SCLK1 SFRM1
Normal Mode Description
Clock
Mode Description
Serial Clock
AC'97 Mode Description
Clock Frame Clock Serial Input Serial Output
Frame Clock Frame Clock Serial Input Serial Output Master Clock)
SSPRX1 Serial Input SSPTX1 Serial Output
Mnemonic
MDIO RXCLK MIIRXD[3:0] RXDVAL RXERR TXCLK MIITXD[3:0] TXEN TXERR
Description
Management Data Clock Management Data Receive Clock Receive Data Receive Data Valid Receive Data Error Transmit Clock Transmit Data Transmit Enable Transmit Error Carrier Sense Collision Detect
ARSTn
AC'97 Reset
AC'97 Reset AC'97 Clock AC'97 Frame Clock AC'97 Serial Input
Master Clock Serial Clock Frame Clock Serial Input
ABITCLK AC'97 Clock ASYNC ASDI ASDO AC'97 Frame Clock AC'97 Serial Input AC'97 Serial Output
AC'97 Serial Output Serial Output
12-bit Analog-to-Digital Converter (ADC)
block consists 12-bit Analog Digital converter with analog input multiplexer. multiplexer select measure battery voltage other miscellaneous voltages external measurement pins. Features include: external pins measurement Internal battery measurement Measurement input range: ADC-conversion-complete interrupt signal
Serial Interfaces (SPI, '97)
Serial Peripheral Interface (SPI) port configured master slave, supporting National Semiconductor®, Motorola® Texas Instruments® signaling protocols. AC'97 port supports multiple codecs multichannel audio output with single stereo input. port supports stereo audio. These ports multiplexed that port will take over either AC'97 pins pins. Normal Mode: Port AC'97 Port Mode: AC'97 Port Port AC'97 Mode: Port Port
Note: output AC'97 ports same time.
Table 12-bit Analog-to-Digital Converter Assignments
Mnemonic
ADC[0] (Ym, 135) ADC[1] (sXp, 134) ADC[2] (sXm, 133) ADC[3] (sYp, 132) ADC[4] (sYm, 131)
Description
External Analog Measurement Input External Analog Measurement Input External Analog Measurement Input External Analog Measurement Input External Analog Measurement Input
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Universal Asynchronous Receiver/Transmitters (UARTs)
16550-compatible UARTs supplied. provides asynchronous HDLC (High-level Data Link Control) protocol support full duplex transmit receive. HDLC receiver handles framing, address matching, checking, control-octet transparency, optionally passes host packet. HDLC transmitter handles framing, generation, control-octet transparency. host must assemble frame memory before transmission. HDLC receiver transmitter UART FIFOs buffer data streams. second UART provides IrDA® compatibility. UART1 supports modem rates 115.2 Kbps, supports HDLC includes byte FIFO receive byte FIFO transmit. Interrupts generated modem status change. UART2 contains IrDA encoder operating either slow Kbps), medium (0.576 1.152 Mbps), fast Mbps) data rates. also byte FIFO receive byte FIFO transmit.
Table Universal Asynchronous Receiver/Transmitters Assignments
Supports both speed (1.5 Mbps) full speed Mbps) device connections Root integrated with downstream ports Transceiver buffers integrated, over-current protection ports Supports power management Operates master Open host controller initializes master transfer with bus: Fetches endpoint descriptors transfer descriptors Accesses endpoint data from system memory Accesses communication area Writes status retire transfer descriptor
Table Dual Port Host Assignments
Mnemonic
USBp[2,0] USBm[2,0]
Name Description
Positive signals Negative Signals
Note:
USBm[1] USBp[1] bonded out.
Two-Wire Interface With EEPROM Support
two-wire interface provides communication control EEPROM devices. EPROM Controller download device configuration information upon chip reset.
Table Two-Wire Port with EEPROM Support Assignments
Mnemonic
TXD0 RXD0 CTSn DSRn DCDn DTRn RTSn EGPIO[0] TXD1 SIROUT RXD1 SIRIN
Name Description
UART1 Transmit UART1 Receive UART1 Clear Send Transmit Enable UART1 Data Ready Data Carrier Detect UART1 Data Terminal Ready UART1 Ready Send UART1 Ring Indicator UART2 Transmit IrDA Output UART2 Receive IrDA Input
Mnemonic
EECLK EEDATA
Name Description
EEPROM Two-Wire Interface Clock EEPROM Two-Wire Interface Data
Alternative Usage
General Purpose General Purpose
Real-Time Clock with Software Trim
software trim feature real time clock (RTC) provides software controlled digital compensation 32.768 crystal oscillator. This compensation accurate 1.24 sec/month.
Table Real-Time Clock with Assignments
Dual Port Host
Open Host Controller Interface (Open HCI) provides full speed serial communications ports baud rate Mbits/sec. devices (printer, mouse, camera, keyboard, etc.) hubs connected host "tieredstart" topology. This includes following feature:
Mnemonic
RTCXTALI RTCXTALO
Name Description
Real-Time Clock Oscillator Input Real-Time Clock Oscillator Output
Compliance with specification Compliance with Open specification
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Clocking
Processor Peripheral Clocks operate from single 14.7456 crystal. Real Time Clock operates from 32.768 crystal oscillator.
Table Clocking Assignments
Software supported priority mask FIQs IRQs
Table Interrupt Controller Assignment
Mnemonic
INT[3] INT[1:0]
Name Description
External Interrupts
Note:
INT[2] bonded out.
Mnemonic
XTALI XTALO VDD_PLL GND_PLL
Name Description
Main Oscillator Input Main Oscillator Output Main Oscillator Power Main Oscillator Ground
Dual Drivers
pins assigned specifically drive external LEDs.
Table Dual Assignments
Timers
Watchdog Timer insures proper operation requiring periodic attention prevent reset-on-timeout. 16-bit timers operate free running down-counters periodic timers fixed interval interrupts have range 0.03 4.27 seconds. 32-bit timer, plus 6-bit prescale counter, range 0.03 73.3 hours. 40-bit debug timer, plus 6-bit prescale counter, range 12.7 days.
Mnemonic
GRLED REDLED
Name Description
Green
Alternative Usage
General Purpose General Purpose
General Purpose Input/Output (GPIO)
EGPIO FGPIO pins each configured individually output, input interrupt input. There pins that alternatively used input, output, open-drain pins, support interrupts. These pins are: Ethernet MDIO Both Outputs EEPROM Clock Data HGPIO[5:2] CGPIO[0] pins alternatively used inputs only: CTSn, DSRn DCDn Interrupt Lines pins alternatively used outputs only: RTSn ARSTn
Table General Purpose Input/Output Assignment
Interrupt Controller
interrupt controller allows interrupts generate Interrupt Request (IRQ) Fast Interrupt Request (FIQ) signal processor core. Thirty-two hardware priority assignments provided assisting vectoring, levels provided vectoring. This allows time critical interrupts processed shortest time possible. Internal interrupts programmed active high active level sensitive inputs. GPIO pins programmed interrupts programmed active high level sensitive, active level sensitive, rising edge triggered, falling edge triggered, combined rising/falling edge triggered. Supports interrupts from variety sources (such UARTs, GPIO ADC) Routes interrupt sources either ARM920T's (Fast IRQ) inputs Three dedicated off-chip interrupt lines operate active high level sensitive interrupts GPIO lines maybe configured generate interrupts
Mnemonic
EGPIO[15:0] FGPIO[3:1]
Name Description
Expanded General Purpose Input Output Pins with Interrupts Expanded General Purpose Input Output Pins with Interrupts
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Reset Power Management
chip reset through PRSTn through open drain common reset pin, RSTOn. Clocks managed peripheral-by-peripheral basis turned conserve power. processor clock dynamically adjustable from (184 industrial conditions).
Table Reset Power Management Assignments
12-Channel Controller
module contains separate channels. these used peripheral-to-memory memory-to-peripheral access. these dedicated memory-to-memory transfers. Each channel connected 16-bit request bus. request collection requests, Serial Audio UARTs. Each channel used independently dedicated request signal. each channel, source destination addressing independently programmed increment, decrement, stay same value. addresses physical, virtual addresses.
Mnemonic
PRSTn RSTOn
Name Description
Power Reset User Reset In/Out Open Drain Preserves Real Time Clock value
Internal Boot
Internal Kbyte allows booting from FLASH memory, UART.
Hardware Debug Interface
JTAG interface allows ARM's Multi-ICE other in-circuit emulators.
Table Hardware Debug Interface
Mnemonic
TRSTn
Name Description
JTAG Clock JTAG Data JTAG Data JTAG Test Mode Select JTAG Port Reset
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Electrical Specifications
Absolute Maximum Ratings
(All grounds voltages with respect
Parameter Symbol
RVDD CVDD VDD_PLL VDD_ADC (Note
3.96 2.16 2.16 3.96 RVDD+0.3 +125
Unit
Power Supplies
Total Power Dissipation Input Current Pin, (Except supply pins) Output current pin, Digital Input voltage Storage temperature
(Note
-0.3
Note:
Includes power generated and/or output loading. power supply pins maximum values listed "Recommended Operating Conditions", below. ambient temperatures above total power dissipation must limited less than Watts.
WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
Recommended Operating Conditions
(All grounds voltages with respect
Parameter Symbol
RVDD CVDD VDD_PLL VDD_ADC FCLK FCLK HCLK HCLK
1.65 1.65
1.80 1.80
1.94 1.94
Unit
Power Supplies
Operating Ambient Temperature Commercial Operating Ambient Temperature Industrial Processor Clock Speed Commercial Processor Clock Speed Industrial System Clock Speed Commercial System Clock Speed Industrial
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Characteristics
CVDD VDD_PLL 1.8; RVDD grounds voltages with respect unless otherwise noted)
Parameter
High level output voltage level output voltage High level input voltage level input voltage High level leakage current level leakage current Iout Iout (Note (Note (Note (Note (Note
Symbol
0.85 RVDD 0.65 RVDD -0.3
0.15 RVDD 0.35 RVDD
Unit
Parameter Power Supply Pins (Outputs Unloaded)
Power Supply Current: Low-Power Mode Supply Current CVDD VDD_PLL Total RVDD CVDD VDD_PLL Total RVDD
Unit
Note:
open drain pins, high level output voltage dependent external load. inputs that include internal pull-ups pull-downs, must externally driven proper operation (See Table page 37). input driven, should tied power ground, depending particular function. driven programmed input, should tied power ground through resistor.
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Timings
Timing Diagram Conventions
This data sheet contains more timing diagrams. following explains components used these diagrams. variations clearly labelled when they occur. Therefore, additional meaning should attached unless specifically stated.
Clock High High/Low High Change Valid Undefined/Invalid Valid High Impedance State Bus/Signal Omission
Figure Timing Diagram Drawing
Timing Conditions
Unless specified otherwise, following conditions true timing measurements. CVDD VDD_PLL 1.8V RVDD grounds Logic Logic Output loading Timing reference levels Processor Clock (HCLK) programmable user. frequency typically between industrial conditions).
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Memory Interface
Figure through Figure define timings associated with phases SDRAM. following table contains values timings each SDRAM modes.
Parameter
SDCLK high time SDCLK time SDCLK rise/fall time Signal delay from SDCLK rising edge time Signal hold from SDCLK rising edge time DQMn delay from SDCLK rising edge time DQMn hold from SDCLK rising edge time valid setup SDCLK rising edge time valid hold from SDCLK rising edge time
Symbol
tclk_high tclk_low tclkrf tDQd tDQh tDAs tDAh
(tHCLK) (tHCLK)
Unit
SDRAM Load Mode Register Cycle
tclk_low tclk_high
tclkrf SDCLK
SDCSn
RASn
CASn
SDWEn
DQMn
OP-Code
Figure SDRAM Load Mode Register Cycle Timing Measurement
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SDRAM Burst Read Cycle
tclk_low SDCLK
tclk_high
tclkrf SDCSn
RASn
CASn
SDWEn tDQd DQMn tDQh
tDAs tDAh
Figure SDRAM Burst Read Cycle Timing Measurement
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SDRAM Burst Write Cycle
tclk_low SDCLK SDCSn
tclk_high
tclkrf
RASn
CASn
SDWEn
DQMn
Figure SDRAM Burst Write Cycle Timing Measurement
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SDRAM Auto Refresh Cycle
tclk_low SDCLK
tclk_high
tclkrf SDCSn
RASn
CASn
SDWEn
Note: Chip select shown illustrate multiple devices being into auto refresh access
Figure SDRAM Auto Refresh Cycle Timing Measurement
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Static Memory 32-bit Read 8-bit External
Parameter
setup assert time assert Address transition time Address assert time Address assert time transition deassert time hold from deassert time assert time assert assert delay time deassert deassert delay time assert DQMn assert delay time deassert DQMn deassert delay time setup transition time setup time transition transition hold time deassert transition hold time
Symbol
tADs tAD1 tAD2 tAD3 tAD4 tADh tRDpwL tRDd tRDh tDQMd tDQMh tDAs1 tDAs2 tDAh1 tDAh2
tHCLK tHCLK (WST1 tHCLK (WST1 tHCLK (WST1 tHCLK (WST1 tHCLK tHCLK WST1 tHCLK
Unit
DQMn DAh1 DAs1 DAs1 DAs2
DAh1
Figure Static Memory Multiple Word Read Cycle Timing Measurement
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Static Memory 32-bit Write 8-bit External
Parameter
setup assert time deassert transition time hold from deassert time hold from deassert time assert delay time assert time deassert time DQMn assert delay time DQMn assert time DQMn deassert time DQMn deassert transition time
Symbol
tADs tADd tADh tCSh tWRd tWRpwL tWRpwH tDQMd tDQMpwL tDQMpwH tDAh
tHCLK tHCLK tHCLK tHCLK tHCLK (WST1 tHCLK tHCLK (WST1 tHCLK tHCLK
Unit
DQMn
Figure Static Memory Multiple Word Write Cycle Timing Measurement
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Static Memory 32-bit Read 16-bit External
Parameter
setup assert time assert transition time transition deassert time hold from deassert time assert time assert delay time deassert delay time DQMn assert delay time DQMn deassert delay time ADsetup time setup time transition transition hold time deassert transition hold time
Symbol
tADs tADd1 tADd2 tADh tRDpwL tRDd tRDh tDQMd tDQMh tDAs1 tDAs2 tDAh1 tDAh2
tHCLK tHCLK (WST1 tHCLK (WST1 tHCLK tHCLK WST1 tHCLK
Unit
tADs
tADd1
tADd2
tADh
tRDd tRDpwl tDQMd tDQMh
tRDh
DQMn
tDAs1
tDAh1
tDAs2
tDAh2
WAIT
Figure Static Memory Multiple Word Read Cycle Timing Measurement
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Static Memory 32-bit Write 16-bit External
Parameter
setup assert time deassert transition time hold from deassert time hold from deassert time assert delay time assert time deassert time DQMn assert delay time DQMn assert time DQMn deassert time DQMn deassert transition time DQMn deassert transition time
Symbol
tADs tADd tADh tCSh tWRd tWRpwL tWRpwH tDQMd tDQMpwL tDQMpwH tDAh1 tDAh2
tHCLK tHCLK tHCLK tHCLK tHCLK (WST1 tHCLK tHCLK (WST1 tHCLK tHCLK tHCLK
Unit
tADs
tADd
tADh
tWRd tWRpwL tWRpwH tWRpwL tCSh
tDQMd DQMn tDQpwL tDQpwH tDAh1 tDAh2 tDQpwL
WAIT
Figure Static Memory Multiple Word Write Cycle Timing Measurement
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Static Memory Burst Read Cycle
Parameter
assert Address transition time Address assert time hold from deassert time assert time assert delay time assert time DQMn assert delay time DQMn assert time setup time setup time transition transition hold time deassert transition hold time
Symbol
tADd1 tADd2 tADh tCSpw tRDd tRDpw tDQMd tDQMpw tDAs1 tDAs2 tDAh1 tDAh2
tHCLK (WST1 tHCLK (WST2 tHCLK tHCLK ((WST1 4(WST2 tHCLK ((WST1 4(WST2 tHCLK ((WST1 4(WST2 tHCLK
Unit
Note:
These characteristics valid when Page Mode Enable (Burst Mode) set. User's Guide details.
tADd1
tADd2
tADd2
tADh
tCSpw
tRDd tDQMd tRDpw
DQMn
tDQMpw tDAh1 tDAh1 tDAh1 tDAh2
tDAs1 WAIT tDAs1 tDAs1 tDAs2
Figure Static Memory Burst Read Cycle Timing Measurement
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Static Memory Single Read Wait Cycle
Parameter
assert WAIT time WAIT assert time WAIT deassert delay time
Symbol
tWAITd tWAITpw tCSnd
tHCLK (WST1-2) tHCLK tHCLK
tHCLK tHCLK
Unit
DQMn
WAIT
tWAITd
tWAITpw
tCSnd
Figure Static Memory Single Read Wait Cycle Timing Measurement
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Static Memory Single Write Wait Cycle
Parameter
WAIT deassert delay time assert WAIT time WAIT assert time WAIT deassert delay time
Symbol
tWRd tWAITd tWAITpw tCSnd
tHCLK tHCLK (WST1 tHCLK tHCLK
tHCLK tHCLK tHCLK
Unit
DQMn
AITd WAIT tCSnd
AITpw
Figure Static Memory Single Write Wait Cycle Timing Measurement
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Static Memory Turnaround Cycle
Parameter
CSnX deassert CSnY assert time
Symbol
tBTcyc
tHCLK (IDCY+1)
Unit
Note:
represent chip select numbers.
tBTcyc
CSn0
CSn1
DQMn
WAIT
Figure Static Memory Turnaround Cycle Timing Measurement
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Ethernet Interface
Parameter Symbol Mbit mode
Mbit mode
Mbit mode
Mbit mode
Mbit mode
Mbit mode
Unit
TXCLK cycle time TXCLK high time TXCLK time TXCLK signal transition delay time TXCLK rise/fall time RXCLK cycle time RXCLK high time RXCLK time RXDVAL RXERR setup time RXDVAL RXERR hold time RXCLK rise/fall time cycle time high time time rise/fall time MDIO setup time (STA sourced) MDIO hold time (STA sourced) MDIO signal transition delay time (PHY sourced)
tTX_per tTX_high tTX_low tTXd tTXrf tRX_per tRX_high tRX_low tRXs tRXh tRXrf tMDC_per tMDC_high tMDC_low tMDCrf tMDIOs tMDIOh tMDIOd
Station device that contains IEEE 802.11 conforming Medium Access Control (MAC) physical layer (PHY) interface wireless medium. Ethernet physical layer interface.
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tTX_high TXCLK MII_TXD[3:0]/ TXEN/ TXERR tTXd tTX_per
tTX_low
tTXrf
tRXrf RXCLK MII_RXD[3:0]/ RXDVAL/ RXERR tRXh tRXs
tRX_low
tRX_high
tRX_per
tMDCrf MDIO (Sourced STA) tMDC_high tMDC_low tMDIOs tMDIOh
tMDC_per
MDIO (Sourced PHY)
tMDIOd
Figure Ethernet Timing Measurement
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Audio Interface
following table contains values timings each modes.
Parameter
SCLK cycle time SCLK high time SCLK time SCLK rise/fall time Data from master valid delay time Data from master setup time Data from master hold time Data from slave valid delay time Data from slave setup time Data from slave hold time
Symbol
tclk_per tclk_high tclk_low tclkrf tDMd tDMs tDMh tDSd tDSs tDSh
tspix_clk (tspix_clk) (tspix_clk)
Unit
Note:
tspix_clk programmable user.
Texas Instruments' Synchronous Serial Format
tclk_per clk_high SCLK tclk_low SFRM SSPTXD/ SSPRXD tclkrf
bits
Figure Single Transfer Timing Measurement
Microwire
clk_hig
clk_per
clkrf
SCLK
clk_low
SFRM
SSPTXD
8-bit control SSPRXD
bits output data
Figure Microwire Frame Format, Single Transfer
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Motorola
tclk_per tclk_high SCLK (SPO=0) tclk_low SCLK (SPO=1) tDMs SSPTXD from master tDMd tDSd SSPRXD from slave SFRM tDSs tDSh tDMh tclkrf
Figure Format with SPH=1 Timing Measurement
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EP9302 High Speed ARM9 System-on-Chip Processor with MaverickCrunch
Inter-IC Sound
Parameter
SCLK cycle time SCLK high time SCLK time SCLK rise/fall time SCLK LRCLK assert delay time LRCLK from SCLK assert hold time SCLK deassert setup time from SCLK deassert hold time SCLK assert delay time from SCLK assert hold time
Symbol
tclk_per tclk_high tclk_low tclkrf tLRd tLRh tSDIs tSDIh tSDOs tSDOh
Unit
tclk_per tclk_high SCLK tLRs LRCLK tSDOs SDO/SDI tSDIs
Figure Inter-IC Sound (I2S) Timing Measurement
tclk_low
tclkrf
tLRh
tSDOh tSDIh
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EP9302 High Speed ARM9 System-on-Chip Processor with MaverickCrunch
AC'97
Parameter
ABITCLK input cycle time ABITCLK input high time ABITCLK input time ABITCLK input rise time ABITCLK input fall time ASDI setup ABITCLK falling ASDI hold after ABITCLK falling ASDI input rise/fall time ABITCLK rising ASDO ASYNC valid, ASYNC ASDO rise time, ASYNC ASDO fall time,
Symbol
tclk_per tclk_high tclk_low tclkr tclkf trfin trout tfout
81.4
Unit
tclk_per ABITCLK tclkrf
tclk_high tclk_low
tclkrf
trfin
ASDI
ASDO
trout/tfout
rfout
ASYNC trfout rout trfout fout
Figure Configuration Timing Measurement
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EP9302 High Speed ARM9 System-on-Chip Processor with MaverickCrunch
Parameter
Resolution Integral non-linearity Offset error Full scale error Maximum sample rate Channel switch settling time Noise (RMS) typical Note: ADIV ADIV ADIV ADIV
Comment
missing codes Range
Value
counts (approximate) 0.01% 0.2% 3750
Units
Samples second Samples second
ADIV refers KeyTchClkDiv register. ADIV means input clock module equal external 14.7456 clock divided ADIV means input clock module equal external 14.7456 clock divided
61A8
0000 FFFF
9E58 Vref/2 Vref
Converter Transfer Function (approximately ±25,000 counts)
Figure Transfer Function
Using ADC: This state-machine based conversion engine that automates conversion process. initiator conversion read access TSXYResult register CPU. data returned from reading this register contains result well status indicating state ADC. However, this peripheral requires delay between each successful conversion issue next conversion command, else returned value successive samples reflect analog input. Since state state machine returned through same channel used initiate conversion process, there must delay inserted after every complete conversion. Note that reading TSXYResult during conversion will affect result ongoing process. following recommended procedure safely polling from software: Read TSXYResult register into local variable initiate conversion. value local variable then repeat step Delay long enough meet maximum sample rate shown above. Mask local variable with 0xFFFF remove extraneous data. signed mode used, sign extend lower halfword. Return sampled value.
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EP9302 High Speed ARM9 System-on-Chip Processor with MaverickCrunch
JTAG
Parameter
clock period clock high time clock time clock rising setup time Clock rising hold time JTAG port clock output JTAG port high impedance valid output JTAG port valid output high impedance
Symbol
tclk_per tclk_high tclk_low tJPs tJPh tJPco tJPzx tJPxz
Units
tclk_per tclk_high tJPzx tJPco tJPxz tclk_low tJPs tJPh
Figure JTAG Timing Measurement
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EP9302 High Speed ARM9 System-on-Chip Processor with MaverickCrunch
LQFP Package Outline
2.19 208-Pin LQFP 1.40-mm Body)
29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 0.17 (0.007) 0.27 (0.011)
27.80 (1.094) 28.20 (1.110)
29.60 (1.165) 30.40 (1.197)
0.50 (0.0197)
Indicator
0.45 (0.018) 0.75 (0.030)
1.35 (0.053) 1.45 (0.057)
1.00 (0.039)
0.09 (0.004) 0.20 (0.008) 1.40 (0.055) 1.60 (0.063) 0.05 (0.002) 0.15 (0.006)
NOTES: Dimensions millimeters, controlling dimension millimeter. Package body dimensions include mold protrusion, which 0.25 (0.010 in). identification either dimple. Package dimensions smaller than bottom dimensions 0.20 (0.008 in). `lead width with plating' dimension does include total allowable dambar protrusion 0.08 maximum material condition). Ejector marks molding present every package. Drawing above does reflect exact package count.
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LQFP Pinout
following table shows LQFP pinout. VDD_core CVDD. VDD_ring RVDD. means that connected.
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List
following Low-Profile Quad Flat Pack (LQFP) assignment table sorted order pin.
Table List Numerical Order Number
Number
Name
CSn[7] CSn[6] CSn[3] CSn[2] CSn[1] AD[25] vdd_ring gnd_ring AD[24] SDCLK AD[23] vdd_core gnd_core SDWEn SDCSn[3] SDCSn[2] SDCSn[1] SDCSn[0] vdd_ring gnd_ring RASn CASn DQMn[1] DQMn[0] AD[22] AD[21] vdd_ring gnd_ring DA[15] AD[7] DA[14] AD[6] DA[13] vdd_core gnd_core
Number
Name
AD[5] DA[12] AD[4] DA[11] AD[3] vdd_ring gnd_ring DA[10] AD[2] DA[9] AD[1] DA[8] AD[0] vdd_ring gnd_ring vdd_ring gnd_ring AD[15] DA[7] vdd_core gnd_core AD[14] DA[6] AD[13] DA[5] AD[12] DA[4] AD[11] vdd_ring gnd_ring DA[3] AD[10] DA[2]
Number
Name
AD[9] DA[1] AD[8] DA[0] DSRn DTRn vdd_ring gnd_ring BOOT[1] BOOT[0] gnd_ring EECLK EEDAT ASYNC vdd_core gnd_core ASDO SCLK1 SFRM1 SSPRX1 SSPTX1 GRLED RDLED vdd_ring gnd_ring INT[3] INT[1] INT[0] RTSn USBm[0]
Number
Name
USBp[0] ABITCLK CTSn RXD[0] RXD[1] vdd_ring gnd_ring TXD[0] TXD[1] CGPIO[0] gnd_core PLL_GND XTALI XTALO PLL_VDD vdd_core gnd_ring vdd_ring RSTOn PRSTn CSn[0] gnd_core vdd_core gnd_ring vdd_ring ADC[4] ADC[3] ADC[2] ADC[1] ADC[0] ADC_VDD RTCXTALI RTCXTALO ADC_GND EGPIO[11]
Number
Name
EGPIO[10] EGPIO[9] EGPIO[8] EGPIO[7] EGPIO[6] EGPIO[5] EGPIO[4] EGPIO[3] gnd_ring vdd_ring EGPIO[2] EGPIO[1] EGPIO[0] ARSTn TRSTn ASDI USBm[2] USBp[2] WAITn EGPIO[15] gnd_ring vdd_ring EGPIO[14] EGPIO[13] EGPIO[12] gnd_core vdd_core FGPIO[3] FGPIO[2] FGPIO[1] gnd_ring vdd_ring TXERR
Number
Name
TXEN MIITXD[0] MIITXD[1] MIITXD[2] MIITXD[3] TXCLK RXERR RXDVAL MIIRXD[0] MIIRXD[1] MIIRXD[2] gnd_ring vdd_ring MIIRXD[3] RXCLK MDIO AD[16] AD[17] gnd_core vdd_core HGPIO[2] HGPIO[3] HGPIO[4] HGPIO[5] gnd_ring vdd_ring AD[18] AD[19] AD[20] SDCLKEN
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following section focuses EP9302 signals from viewpoints usage characteristics, multiplexing usage. first table (Table summary EP9302 signals. second table (Table illustrates signal multiplexing configuration options. Table summary EP9302 signals, which illustrates type pull type any). symbols used table defined follows. (Note: blank means Applicable (NA) Pull Type, Pull (NP).) Under Type column: Analog
Power Ground input only input/output output driver output driver 12mA 12mA output driver text description additional information about bi-directional pins. Under Pull Type Column: Resistor pull RVDD supply Resistor pull down RGND supply
Table Descriptions
Name TRSTn BOOT[1:0] XTALI XTALO VDD_PLL GND_PLL RTCXTALI RTCXTALO WAITn AD[25:0] DA[15:0] CSn[3:0] CSn[7:6] DQMn[1:0] SDCLK SDCLKEN SDCSn[3:0] RASn CASn SDWEn ADC[4:0] VDD_ADC GND_ADC Block JTAG JTAG JTAG JTAG JTAG System EBUS EBUS EBUS EBUS EBUS EBUS EBUS EBUS SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM Type Pull Type JTAG clock USBm[2, JTAG data TXD0 JTAG data RXD0 JTAG test mode select CTSn JTAG reset DSRn Boot mode select DTRn Main oscillator input RTSn Main oscillator output TXD1 Main oscillator power, 1.8V RXD1 Main oscillator ground oscillator input MDIO oscillator output RXCLK SRAM Write strobe MIIRXD[3:0] SRAM Read strobe RXDVAL SRAM Wait RXERR Shared Address TXCLK Shared Data in/out MIITXD[3:0] Chip select TXEN Chip select TXERR Shared data mask SDRAM clock SDRAM clock enable GRLED SDRAM chip selects RDLED SDRAM EECLK SDRAM EEDAT SDRAM write enable ABITCLK External Analog Measurement Input ASYNC power, 3.3V ASDI ground ASDO Name Description USBp[2,
Table Descriptions (Continued)
Block UART1 UART1 UART1 UART1 UART1 UART1 UART2 UART2 EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC EMAC EEPROM EEPROM AC97 AC97 AC97 AC97 Type 12ma 12ma Pull Type Description positive signals negative signals Transmit Receive Clear send transmit enable Data ready Data Carrier Detect Data Terminal Ready output Ready send Transmit IrDA output Receive IrDA input Management data clock Management data input/output Receive clock Receive data Receive data valid Receive data error Transmit clock Transmit data Transmit enable Transmit error Carrier sense Collision detect Green EEPROM Two-wire Interface clock EEPROM Two-wire Interface data AC97 clock AC97 frame sync AC97 Primary input AC97 output
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Table Descriptions (Continued)
Name ARSTn SCLK1 SFRM1 SSPRX1 SSPTX1 INT[3], INT[1:0] PRSTn RSTOn EGPIO[15:0] FGPIO[3:1] HGPIO[5:2] CGPIO[0] CVDD RVDD CGND RGND Block AC97 SPI1 SPI1 SPI1 SPI1 Syscon Syscon GPIO GPIO GPIO GPIO Power Power Ground Ground Type I/O, I/O, I/O, I/O, I/O, I/O, Pull Type AC97 reset clock Frame Clock input output External interrupts Power reset User Reset open drain Enhanced GPIO GPIO Port GPIO Port GPIO Port Digital power, 1.8V Digital power, 3.3V Digital ground Digital ground Description
Table illustrates signal multiplexing configuration options.
Table Multiplex Usage Information
Physical Name
EGPIO[0] EGPIO[1] EGPIO[3] EGPIO[4] EGPIO[5] EGPIO[6] EGPIO[7] EGPIO[8] EGPIO[9] EGPIO[10] EGPIO[11] EGPIO[12] EGPIO[13] EGPIO[14] EGPIO[15] ABITCLK ASYNC ASDO ASDI ARSTn SCLK1 SFRM1 SSPTX1 SSPRX1
Description
Ring Indicator Input clock monitor HDLC Clock Transmit Data Receive Data Transmit Data Request Acknowledge Request Acknowledge Receive Data PWM1 Output Device active present Serial clock Frame Clock Transmit Data Receive Data Master clock Serial clock Frame Clock Transmit Data Receive Data
Multiplex signal name
CLK1HZ HDLCCLK1 SDO1 SDI1 SDO2 DREQ0 DACK0 DEOT0 DREQ1 DACK1 DEOT1 SDI2 PWMOUT1 DASP SCLK LRCK SDO0 SDI0 MCLK SCLK LRCK SDO0 SDI0
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Acronyms Abbreviations
following tables list abbreviations acronyms used this data sheet.
Term
AMBA ATAPI CODEC
Term
OHCI
Definition
Open Host Controller Interface Ethernet PHYsical layer interface Programmed Reduced Instruction Computer Secure Digital Music Initiative Synchronous Dynamic Serial Peripheral Interface Static Random Access Memory Station device that contains IEEE 802.11 conforming Medium Access Control (MAC) physical layer (PHY) interface wireless medium Thin Film Transistor Translation Lookaside Buffer Universal Serial
Definition
Analog-to-Digital Converter RISC Alternative SDMI Advanced Micro-controller Architecture SDRAM Packet Interface COder DECoder SRAM Cyclic Redundancy Check Digital-to-Analog Converter Direct-Memory Access
EEPROM Electronically Erasable Programmable Read Only Memory EMAC EBUS FIFO FLASH GPIO HDLC IEEE IrDA JTAG LFSR Ethernet Media Access Controller External Memory First First Fast Interrupt Request Flash memory General Purpose High-level Data Link Control Interface Inter-IC Sound Integrated Circuit In-Circuit Emulator Integrated Drive Electronics Institute Electronics Electrical Engineers Infrared Data Association Standard Interrupt Request International Standards Organization Joint Test Action Group Linear Feedback Shift Register Media Independent Interface Memory Management Unit
Units Measurement
Symbol Unit Measure
degree Celsius Hertz cycle second Kilobits second Kilobyte KiloHertz 1000 Megabits second MegaHertz 1,000 KiloHertz microAmpere 10-6 Ampere microsecond 1,000 nanoseconds 10-6 seconds milliAmpere 10-3 Ampere millisecond 1,000 microseconds 10-3 seconds milliWatt 10-3 Watts nanosecond 10-9 seconds picoFarad 10-12 Farads Volt Watt
Kbps Kbyte Mbps
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ORDERING INFORMATION
order numbers device are: EP9302-CQ EP9302-CQZ EP9302-IQ EP9302-IQZ 208-pin LQFP 208-pin LQFP 208-pin LQFP 208-pin LQFP
Lead Free Lead Free
EP9302
Lead Material: Lead Free Part Number Product Line: Embedded Processor Package Type: pin, Profile Quad Flat Pack Temperature Range: Commercial Extended Operating Version Industrial Operating Version
Note:
Cirrus Logic Internet site http://www.cirrus.com find contact information your local sales representative.
Contacting Cirrus Logic Support
product questions inquiries contact Cirrus Logic Sales Representative. find nearest www.cirrus.com
IMPORTANT NOTICE "Preliminary" product information describes products that production, which full characterization data available. Cirrus Logic, Inc. subsidiaries ("Cirrus") believe that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). Customers advised obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgment, including those pertaining warranty, patent infringement, limitation liability. responsibility assumed Cirrus this information, including this information basis manufacture sale items, infringement patents other rights third parties. This document property Cirrus furnishing this information, Cirrus grants license, express implied under patents, mask work rights, copyrights, trademarks, trade secrets other intellectual property rights. Cirrus owns copyrights associated with information contained herein gives consent copies made information only within your organization with respect Cirrus integrated circuits other products Cirrus. This consent does extend other copying such copying general distribution, advertising promotional purposes, creating work resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS DESIGNED, AUTHORIZED WARRANTED AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO BODY, LIFE SUPPORT PRODUCTS OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS COMPONENTS PERSONAL AUTOMOTIVE SAFETY SECURITY DEVICES). INCLUSION CIRRUS PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK CIRRUS DISCLAIMS MAKES WARRANTY, EXPRESS, STATUTORY IMPLIED, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, WITH REGARD CIRRUS PRODUCT THAT USED SUCH MANNER. CUSTOMER CUSTOMER'S CUSTOMER USES PERMITS CIRRUS PRODUCTS CRITICAL APPLICATIONS, CUSTOMER AGREES, SUCH USE, FULLY INDEMNIFY CIRRUS, OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS OTHER AGENTS FROM LIABILITY, INCLUDING ATTORNEYS' FEES COSTS, THAT RESULT FROM ARISE CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, Cirrus Logic logo designs trademarks Cirrus Logic, Inc. other brand product names this document trademarks service marks their respective owners. Microsoft Windows registered trademarks Microsoft Corporation. Microwire trademark National Semiconductor Corp. National Semiconductor registered trademark National Semiconductor Corp. Texas Instruments registered trademark Texas Instruments, Inc. Motorola registered trademark Motorola, Inc. LINUX registered trademark Linus Torvalds.
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