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Switching Power supply with HIP4080A - Switching Power supply with HIP4080A
power mosfet ic 12 volts for audio amplifier - power mosfet ic 12 volts for audio amplifier
h-bridge gate drive ic - h-bridge gate drive ic
AN9404 - AN9404
Author: George Danz
HIP4080A, HIGH FREQUENCY H-BRIDGE DRIVER
HIP4080A member HIP408X family High Frequency H-Bridge Driver ICs. simplified application diagram HIP4080A shown Figure HIP408X family H-Bridge driver provide ability operate from 10VDC 80VDC busses driving H-Bridges, operating class-D switch-mode, whose switch elements comprised power N-channel MOSFETs. HIP408X family, packaged both SOIC DIPs, provide peak gate current drive 2.5A. HIP4080A includes undervoltage protection, which sends continuous gate turn-off pulse gate outputs when voltage falls below nominal 8.25 volts. startup sequence HIP4080A initiated when voltage returns above nominal 8.75 volts. course, must state enabled. startup sequence turns both side outputs, BLO, that bootstrap capacitors both sides H-bridge fully charged. During this time gate outputs held continuously insure that shoot-through occur during nominal 400ns boot-strap refresh period. boot strap refresh period outputs respond normally state input control signals. combination bootstrap charge-pumping techniques used power circuitry which drives upper halves H-Bridge. bootstrap technique supplies high instantaneous current needed turning power devices, while charge pump provides enough current "maintain" bias voltage upper driver sections MOSFETs. Since voltages upper bias supply "float" along with source terminals upper power switches, design this family provides voltage capability upper bias supply terminals 95VDC. HIP4080A drive lamp loads automotive industrial applications shown Figure When inductive loads switched, flyback diodes must placed around loads protect MOSFET switches. Many applications utilize full bridge topology. These voice coil motor drives, stepper brush motors, audio amplifiers even power supply inverters used uninterruptable power supplies, just name few. above, voice coil motor drives audio amplifiers take advantage built-in comparator available HIP4080A. Using output comparator some positive feedback, hysteresis control, popular with voice coil motor drivers, implemented shown Figure
1-888-INTERSIL 321-724-7143 Copyright
figure, back from comparator output, OUT, positive input comparator, IN+. Capacitor, integrates direction satisfy reference current signal input comparator sums this current reference with signal proportional load current through resistor, which comes from differential amplifier, bias voltage (represents half bias voltage maximum rail rail voltage comparator amplifier, biases comparator's terminal through amplifier, A1's, positive summing junction.
FIGURE HIP4080A SIMPLIFIED APPLICATION DIAGRAM
FIGURE HIP4080A LAMP SWITCH DRIVER, DUAL HIGH/ SWITCHES AUTOMOTIVE INDUSTRIAL CONTROLS
Intersil Corporation 1999
Application Note 9404
When current flowing either direction load, output exactly reference input, would also have request zero current from bridge. bridge would still switch this case, because positive feedback connection HIP4080A internal comparator. frequency oscillation output will function amount hysteresis gain, R3/R1 size capacitor, capacitor, made larger, steady-state frequency bridge will become smaller. beyond scope this application note provide full analysis. valuable characteristic hysteresis control that error becomes smaller (i.e. reference feedback signals match) frequency increases. Usually this occurs when load current small minimum. When error signal large, frequency becomes very small, perhaps even advantage this that when currents largest, switching losses minimum, when switching losses largest, current component small. HIP408X family devices fabricated using proprietary Intersil process which allows this family switch frequencies over 500kHz. Therefore HIP408X family ideal Voice coil motor, class-D audio amplifier, DC-DC converters high performance stepmotor control applications. provide accurate dead-time control twin purposes shoot-through avoidance duty-cycle maximization, resistors tied pins HDEL LDEL provide precise delay matching upper lower propagation delays, which typically only 55ns. HIP408X family H-bridge drivers enough voltage margin applied SELV classification operation 42.0V) applications most Automotive applications where "load dump" capability over required. This capability makes HIP408X family more cost-effective solution driving Nchannel power MOSFETs than either discrete solutions other solutions relying transformer- opto-coupling gatedrive techniques shown Figure HIP4080A differs from HIP4081A regarding function pins truth table which governs switching function ICs. HIP4080A, pins labeled HEN, OUT, IN-, respectively. HIP4081A, pins labeled (B-side high input), (B-side input), (A-side input) (A-side high input), respectively. HIP4081A's inputs individually control each four power MOSFETs, pairs (excepting shoot-through case). HIP4080A provides internal comparator "high enable.HEN" pin. comparator used provide logic signal switch appropriate MOSFETs within H-bridge, facilitate "Hysteresis" control illustrated later. enables (when high) disables (when low) A-side B-side upper MOSFETs. With held low, possible switch only lower H-bridge MOSFETs. When high both upper lower MOSFETs H-bridge switched. input also PWM-switched with inputs used only direction control, thereby minimizing switching losses.
block diagram HIP4080A relating driving A-side H-Bridge shown Figure blocks associated with each side H-Bridge identical, B-side shown simplicity. bias voltage terminals, HIP4080A should tied together. They were separated within HIP4080A avoid possible ground loops internal Tieing them together providing decoupling capacitor from common tie-point greatly improves noise immunity. Input Logic HIP4080A accepts inputs which control output state power MOSFET H-bridge provides comparator output pin, OUT, which provide compensation hysteresis. DIS, "Disable," disables gate drive H-bridge MOSFETs regardless command states input pins, IN+, HEN. state bias voltage, VDD, also disable gate drive discussed introduction. HEN, "High Enable," enables disables gate drive high side MOSFETs. high level "enables" high side gate drive further determined states comparator input pins, since pins control which diagonal pair MOSFETs gated. Upper drive "modulated" through while drive diagonally opposing lower MOSFETs continuous. simultaneously modulate both upper lower drivers, continuously held high while modulating pins. Modulating only upper switches nearly halve switching losses both driver lower MOSFETs. power dissipation saved high switching frequencies significant. Table summarizes input control logic. input sensitivity input pins best described "enhanced TTL" levels. Inputs which fall below 1.0V above 2.5V recognized, respectively, level high level inputs. comparator inputs have common mode input voltage range 1.0V -1.5V, whereas offset voltage less than 5mV. more information comparator specifications, Intersil Data Sheet HIP4080A, File Number 3658.
TABLE INPUT LOGIC TRUTH TABLE
Application Note 9404
FIGURE HYSTERESIS MODE SWITCHING
HIGH VOLTAGE 95VDC UNDERVOLTAGE CHARGE PUMP LEVEL SHIFT LATCH DRIVER TURN-ON DELAY (PIN
+12VDC BIAS SUPPLY
FIGURE HIP4080A BLOCK DIAGRAM
Application Note 9404
Propagation Delay Control Propagation delay control major feature HIP4080A. identical sub-circuits within delay commutation power MOSFET gate turn-on signals both sides H-bridge. gate turn-off signals delayed. Propagation delays related leveltranslation function (see section Level-Translation) cause both upper on/off propagation delays longer than lower on/off propagation delays. Four delay sub-circuits needed fully balance H-bridge delays, upper delay control lower gate control. Users tailor side high side commutation delay times placing resistor from HDEL pin. Similarly, resistor connected from LDEL controls high side side commutation delay times lower power switches. HDEL resistor controls both upper commutation delays LDEL resistor controls lower commutation delays. Each resistors sets current which inversely proportional created delay. delay added falling edge "off" pulse associated with MOSFET which being commutated off. When delay complete, "on" pulse initiated. This effect "delaying" commanded pulse amount delay, thereby creating dead-time. Proper choice resistor values connected from HDEL LDEL provides means matching commutation dead times whether commutating high high. Values resistors ranging from 200k recommended. Figure shows delays obtainable function resistor values used.
upper power MOSFET source connections. This voltage much when bias supply voltage only (the bias supply voltage voltages must exceed 95VDC). order minimize power dissipation level-shifter circuit, important minimize width pulses translated because power dissipation proportional product switching frequency pulse energy joules. pulse energy turn equal product voltage magnitude, translation pulse current translation pulse duration. provide reliable, noise free pulse requires nominal current pulse magnitude approximately 3mA. translated pulses then "latched" maintain "on" "off" state until another level-translation pulse comes along latch opposite state. Very reliable operation obtained with pulse widths approximately 80ns. switching frequency even 1.0MHz, with 80VDC potential, power developed leveltranslation circuit will less than 0.08W.
Charge Pump Circuits
There charge pump circuits HIP4080A, each upper logic driver circuits. Each charge pump uses switched capacitor doubler provide about 30µA 50µA gate load current. sourcing current charging capability drops floating supply voltage increases. Eventually gate voltage approaches level internal zener clamp, which prevents voltage from exceeding about 15V, safe gate voltage rating most commonly available MOSFETs.
Each four output drivers comprised bipolar high speed transistors both sourcing sinking gate charge from MOSFET switches. addition, sink driver incorporates parallel-connected n-channel MOSFET enable gate power switch gate-source voltage brought completely propagation delays through gate driver sub-circuits while driving 500pF loads typically less than 10ns. Nevertheless, gate driver design nearly eliminates gate driver shoot-through which significantly reduces power dissipation.
successfully apply HIP4080A designer should address following concerns: General Bias Supply Design Issues Upper Bias Supply Circuit Design Bootstrap Bias Supply Circuit Design General Bias Supply Design Issues bias supply design simple. designer must first establish desired gate voltage turning power switches. most power MOSFETs, increasing gatesource voltage beyond yields little reduction switch drain-source voltage drop.
FIGURE MINIMUM DEAD-TIME RESISTANCE
lower power MOSFET gate drive signals from propagation delay control circuits amplification circuits which described more detail under section "Driver Circuits". upper power MOSFET gate drive signals directed first Level-Translation circuits before going upper power MOSFET "Driver Circuits". Level-Translation circuit communicate "on" "off" pulses from Propagation Delay sub-circuit upper logic gate drive sub-circuits which "float" potential
Application Note 9404
Overcharging power switch's gate-source capacitance also delays turn-off, increases MOSFET switching losses increases energy switched gate driver HIP4080A, which increases dissipation within HIP4080A. Overcharging MOSFET gate-source capacitance also lead "shoot-through" where both upper lower MOSFETs single bridge find themselves simultaneously, thereby shorting high voltage supply. Values close optimum supplying VCC, although HIP4080A will operate 15V. Lower Bias Supply Design Since most applications identical MOSFETs both upper lower power switches, bias supply requirements with respect driving MOSFET gates will also identical. case switching frequencies driving upper lower MOSFETs differ, sets calculations must done; upper switches lower switches. bias current budget upper lower switches will each calculation. Always keep mind that lower bias supply must supply current upper gate drive logic circuits well lower gate drive circuits logic circuits. This fact that side bias supplies (VCC /VDD) charge bootstrap capacitors charge pumps, which maintain voltage across upper power switch's gate-source terminals. Good layout practice capacitor bypassing technique avoids transient voltage dips bias power supply HIP4080A. Always place (equivalent series resistance) ceramic capacitor adjacent connected between bias terminals common terminal, value range 0.22µF 0.5µF usually sufficient. Minimize effects Miller feedback keeping source gate return leads from MOSFETs HIP4080A short. This also reduces ringing, minimizing length inductance these connections. Another minimize inductance gate charge/discharge path, addition minimizing path length, outbound gate lead directly "over" source return lead. Sometimes source return leads made into small "ground plane" back side board making possible outbound gate lead top" board. This minimizes "enclosed area" loop, thus minimizing inductance this loop. also adds some capacitance between gate source which shunts some Miller feedback effect. Upper Bias Supply Circuit Design Before discussing bootstrap circuit design detail, worth mentioning that possible operate HIP4080A without bootstrap circuit altogether. Even bootstrap capacitor, which functions supply reservoir charge rapidly turning MOSFETs optional some cases. situations where very slow turn-on MOSFETs tolerable, consider omitting some bootstrap components. Applications such driving relays lamp loads, where MOSFETs switched infrequently switching losses low, provide opportunities boot strapless operation. Generally, loads with resistance inductance possible candidates. Operating HIP4080A without bootstrap diode and/or capacitor will severely slow gate turn-on. Without bootstrap capacitor, gate current only comes from internal charge pump. peak charge pump current only about 30µA 50µA. gate voltage waveform, when operating without bootstrap capacitor, will appear similar dotted line shown Figure bootstrap capacitor value approximately equal equivalent MOSFET gate capacitance used, upper bias supply (labeled "bootstrap voltage" Figure will drop approximately half when gate turned larger bootstrap capacitance used, smaller instantaneous drop bootstrap supply voltage when upper MOSFET turned
GATE INITIATION SIGNAL BOOT STRAP VOLTAGE (XHB XHS) GATE VOLTAGE (XHO XHS)
Although recommended, employ bootstrap capacitor without bootstrap diode. this case charge pump used charge capacitor whose value should much larger than equivalent gate-source capacitance driven MOSFET. value bootstrap capacitance about times greater than equivalent MOSFET gatesource capacitance usually sufficient. Provided that sufficient time elapses before turning MOSFET again, bootstrap capacitor will have chance recharge voltage value that bootstrap capacitor prior turning MOSFET. Assuming series resistance bootstrap change path, output frequency should allow sufficient refresh time. bootstrap capacitor times larger than equivalent gate-source capacitance driven MOSFET prevents drop bootstrap supply voltage from exceeding bias supply voltage during turn-on MOSFET. When operating without bootstrap diode time required replenish charge bootstrap capacitor will same time would take charge equivalent gate capacitance from This because charge lost bootstrap capacitor exactly equal charge transferred gate capacitance during turn-on. Note that very first time that bootstrap capacitor charged takes
Application Note 9404
much longer since capacitor must charged from With bootstrap diode, initial charging bootstrap supply almost instantaneous, since charge required comes from low-side bias supply. Therefore, before upper MOSFETs initially gated, time must allowed upper bootstrap supply reach full voltage. Without bootstrap diode, this initial "charge" time excessive. switching cycle assumed begin when upper MOSFET gated then bootstrap capacitor will undergo charge withdrawal when source driver connects equivalent gate-source capacitance MOSFET. After this initial "dump" charge, quiescent current drain experienced bootstrap supply infinitesimal. fact, quiescent supply current more than offset charge pump current. charge pump continuously supplies current bootstrap supply eventually would charge bootstrap capacitor MOSFET gate capacitance back initial value prior beginning switching cycle. problem that "eventually" fast enough when switching frequency greater than hundred Bootstrap Bias Supply Circuit Design high frequency applications bootstrap components, both diodes capacitors, required. Therefore, must familiar with bootstrap capacitor sizing proper choice bootstrap diode. Just after switch cycle begins charge transfer from bootstrap capacitor gate capacitance complete, voltage bootstrap capacitor lowest that will ever during switch cycle. charge lost bootstrap capacitor will very nearly equal charge transferred equivalent gate-source capacitance MOSFET shown Equation
soon upper MOSFET turned off, voltage phase terminal (the source terminal upper MOSFET) begins descent toward negative rail high voltage bus. When phase terminal voltage becomes less than voltage, refreshing (charging) bootstrap capacitor begins. long phase voltage below refreshing continues until bootstrap voltages equal. off-time upper MOSFET dependent gate control input signals, never shorter than dead-time delay setting, which resistors connecting HDEL LDEL VSS. bootstrap capacitor fully charged time upper MOSFET turns again, incomplete refreshing occurs. designer must insure that dead-time setting consistent with size bootstrap capacitor order guarantee complete refreshing. Figure illustrates circuit path refreshing bootstrap capacitor.
4080 HIGH SIDE DRIVE HIGH VOLTAGE VBUS "B-SIDE" H-BRIDGE
SIDE DRIVE LOWER MOSFET
+VBIAS (12VDC) "B-SIDE" H-BRIDGE
where: VBS1= Bootstrap voltage immediately before turn-on VBS2 Bootstrap voltage immediately after turn-on Bootstrap Capacitance Gate charge transferred during turn-on Were internal charge pump, voltage bootstrap capacitor gate capacitor (because upper MOSFET turned would eventually drain down zero bootstrap diode leakage current very small supply current associated with level-shifters upper gate driver sub-circuits. switch-mode, switching frequency equal reciprocal period between successive turn-on turnoff) pulses. Between turn-on gate pulses exists turn-off pulse. Each time turn-off pulse issued upper MOSFET, bootstrap capacitor that MOSFET begins "refresh" cycle. refresh cycle ends when upper MOSFET turned again, which varies depending frequency duty cycle. duty cycle approaches 100%, available "off-time", tOFF approaches zero. Equation shows relationship between tOFF, fPWM duty cycle.
SUPPLY BYPASS CAPACITOR
NOTE: Only "A-side" H-bridge Shown Simplicity. Arrows Show Bootstrap Charging Path. FIGURE BOOTSTRAP CAPACITOR CHARGING PATH
bootstrap charging discharging paths should kept short, minimizing inductance these loops mentioned section, "Lower Bias Supply Design". Bootstrap Circuit Design Example Equation describes relationship between gate charge transferred MOSFET upon turn-on, size bootstrap capacitor change voltage across bootstrap capacitor which occurs result turn-on charge transfer. effects reverse leakage current associated with bootstrap diode bias current associated with upper gate drive circuits also affect bootstrap capacitor sizing. instant that upper MOSFET turns source voltage begins rapidly rise, bootstrap diode becomes rapidly reverse biased resulting reverse recov-
Application Note 9404
charge which further depletes charge bootstrap capacitor. completely model total charge transferred during turn-on upper MOSFETs, these effects must accounted for, shown Equation
diode recovered charge used rather than maximum value, voltage droop bootstrap supply will only about 0.5V
Power Dissipation Thermal Design
(EQ.3) model power dissipated HIP4080A lumping losses into static losses dynamic (switching) losses. static losses bias current losses upper lower sections include currents when switching. quiescent current approximately 9mA. Therefore with bias supply, static power dissipation slightly over 100mW. dynamic losses associated with switching power MOSFETs much more significant divided into following categories: Voltage Gate Drive (charge transfer) High Voltage Level-shifter (V-I) Losses High Voltage Level-shifter (charge transfer)
where: Bootstrap diode reverse leakage current IQBS Upper supply quiescent current Bootstrap diode reverse recovered charge Turn-on gate charge transferred fPWM operating frequency VBS1 Bootstrap capacitor voltage just after refresh VBS2 Bootstrap capacitor voltage just after upper turn Bootstrap capacitance From practical standpoint, bootstrap diode reverse leakage upper supply quiescent current negligible, particularly since HIP4080A's internal charge pump continuously sources minimum about 30µA. This current more than offsets leakage supply current components, which fixed function switching frequency. higher switching frequency, lower charge effect contributed these components their effect bootstrap capacitor sizing negligible, shown Equation Supply current bootstrap diode recovery charge component increases with switching frequency generally negligible. Hence need fast recovery diode. Diode recovery charge information usually found most vendor data sheets. example, choose Intersil IRF520R power MOSFET, data book states gate charge, 12nC typical 18nC maximum, both 12V. Using maximum value 18nC maximum charge should have transfer will less than 18nC. Suppose General Instrument UF4002, 100V, fast recovery, miniature plastic rectifier used. data sheet gives reverse recovery time 25ns. Since recovery current waveform approximately triangular, recovery charge approximated taking product half peak reverse current magnitude peak) recovery time duration (25ns). this case recovery charge should 12.5nC. Since internal charge pump offsets possible diode leakage upper drive circuit bias currents, these sources discharge current bootstrap capacitor will ignored. bootstrap capacitance required example above calculated shown Equation using Equation
18nC 12.5nC -12.0 11.0
practice, high voltage level-shifter charge transfer losses small compared gate drive charge transfer losses. more significant voltage gate drive charge transfer losses caused movement charge equivalent gate-source capacitor each MOSFETs comprising H-bridge. loss function (switching) frequency, applied bias voltage, equivalent gate-source capacitance minute amount CMOS gate charge internal HIP4080A. voltage charge transfer losses given Equation
high voltage level-shifter power dissipation much more difficult evaluate, although equation which defines simple shown Equation difficulty arises from fact that level-shift current pulses, IOFF perfectly phase with voltage upper MOSFET source terminals, VSHIFT propagation delays within These time-dependent source voltages "phase" voltages) further dependent gate capacitance driven MOSFETs type load (resistive, capacitive inductive) which determines rapidly MOSFETs turn example, level-shifter IOFF pulses come latched upper logic circuits before phase voltage even moves. result, little level-shift power dissipation result from pulse, whereas IOFF pulse have significant power dissipation associated with since phase voltage generally remains high throughout duration iOFF pulse. (EQ.
Therefore bootstrap capacitance 0.033µF will result less than 1.0V droop voltage across bootstrap capacitor during turn-on period either upper MOSFETs. typical values gate charge bootstrap
Application Note 9404
Lastly, there power dissipated within charge transfer capacitance between upper driver circuits VSS. Since charge transfer phenomena, closely resembles form Equation except that capacitance much smaller than equivalent gatesource capacitances associated with power MOSFETs. other hand, voltages associated with level-shifting function much higher than voltage changes experienced gate MOSFETs. relationship shown Equation
turers data sheet. Notice that MOSFET data sheet usually gives value units charge (usually nanocoulombs) different drain-source voltages. Choose drain-source voltage closest particular voltage interest. Simply substituting actual MOSFETs capacitors, doesn't yield correct average current because Miller capacitance will accounted for. This because drains don't switch using test circuit shown Figure Also gate capacitance devices using represent maximum values which only data sheet will provide.
power associated with each high voltage tubs HIP4080A derived from Equation quite small, extremely small capacitance associated with these tubs. "tub" isolation area which surrounds isolates high side circuits from ground referenced circuits important point users that power dissipated linearly related switching frequency square applied voltage. capacitance Equation varies with applied voltage, VSHIFT, making solution difficult, phase shift IOFF pulses with respect phase voltage, VSHIFT, Equation difficult measure. Even Equation easy measure. Hence Equation through Equation calculate total power dissipation best difficult. equations however, allow users understand significance that MOSFET choice, switching frequency voltage play determining power dissipation. This knowledge lead corrective action when power dissipation becomes excessive. Fortunately, there easy method which used measure components power dissipation rather than calculating them, except tiny "tub capacitance" component.
HDEL LDEL 100K
GATE LOAD CAPACITANCE
FIGURE VOLTAGE POWER DISSIPATION TEST CIRCUIT
Power Dissipation, Easy
average power dissipation associated with gate connected MOSFETs easily measured using signal generator, averaging millimeter voltmeter. Voltage Power Dissipation sets measurements required. first uses circuit Figure evaluates voltage power dissipation components. These components include MOSFET gate charge internal CMOS charge transfer losses shown Equation well quiescent bias current losses associated with losses calculated very simply calculating product bias voltage current measurements performed using circuit shown Figure measurement purposes, phase terminals (AHS BHS) both phases both tied chip common, terminal, along with lower source terminals, BLS. Capacitors equal equivalent gate-source capacitance MOSFETs connected from each gate terminal VSS. value capacitance chosen comes from MOSFET manufac-
voltage charge transfer switching currents shown Figure Figure does include quiescent bias current component, which bias current which flows when switching disabled. quiescent bias current component approximately 10mA. Therefore quiescent power loss would 120mW. Note that bias current given switching frequency grows almost proportionally load capacitance, current directly proportional switching frequency, previously suggested Equation
VOLTAGE BIAS CURRENT (mA) 1000 SWITCHING FREQUENCY (kHz) 10,000 3,000 1,000
FIGURE VOLTAGE BIAS CURRENT (LESS QUIESCENT COMPONENT) FREQUENCY GATE LOAD CAPACITANCE
Application Note 9404
High Voltage Power Dissipation high voltage power dissipation component largely comprised high voltage level-shifter component described Equation difficulties associated with time variance IOFF pulses level shift voltage, VSHIFT, under integrand Equation avoided. completeness, total loss must include small leakage current component, although latter usually smaller compared level-shifter component. high voltage power loss calculation product high voltage voltage level, VBUS, average high voltage current, IBUS, measured circuit shown Figure Averaging meters should used make measurements. measures quiescent leakage current well switching component. Notice that current increases somewhat with applied voltage. This finite output resistance level-shift transistors Layout Issues fast switching, high frequency systems, poor layout result problems. crucial consider layout. HIP4080A pinout configuration encourages tight layout placing gate drive output terminals strategically along right side chip (pin upper left-hand corner). This provides short gate source return leads connecting with power MOSFETs. Minimize series inductance gate drive loop running lead going gate MOSFETs from over return lead from MOSFET sources back using double-sided possible. board separates traces provides small amount capacitance well reducing loop inductance reducing encircled area gate drive loop. benefit that gate drive currents voltages much less prone ringing which similarly modulate drain current MOSFET. following table summarizes some layout problems which occur corrective action take.
Layout Problems Effects
Bootstrap circuit path should also short minimize series inductance that cause voltage bootstrap capacitor ring, slowing down refresh causing overvoltage bootstrap bias supply. compact power circuit layout (short circuit path between upper/lower power switches) minimizes ringing phase lead(s) keeping voltages from ringing excessively below terminal which cause excessive charge extraction from substrate possible malfunction Excessive gate lead lengths cause gate voltage ringing subsequent modulation drain current, thereby amplifying Miller Effect.
PROBLEM EFFECT Inductance cause voltage bootstrap capacitor ring, slowing down refresh and/or causing overvoltage bootstrap bias supply. cause ringing phase lead(s) causing ring excessively below terminal causing excessive charge extraction from substrate possible malfunction cause gate voltage ringing subsequent modulation drain current impairs effectiveness sink driver from minimizing miller effect when opposing switch being rapidly turned
100K VBUS (0VDC 80VDC)
GATE LOAD CAPACITANCE
FIGURE HIGH VOLTAGE LEVEL-SHIFT CURRENT TEST CIRCUIT
1000 LEVEL-SHIFT CURRENT (µA) 1000 SWITCHING FREQUENCY (kHz)
Bootstrap circuit path long
Lack tight power circuit layout (long circuit path between upper/ lower power switches)
FIGURE HIGH VOLTAGE LEVEL-SHIFT CURRENT FREQUENCY VOLTAGE
Figure shows that high voltage level-shift current varies directly with switching frequency. This result should surprising, since Equation rearranged show current function frequency, which reciprocal switching period, 1/T. test circuit Figure
Excessive gate lead lengths
Application Note 9404 Quick Help Table
quick help table been included help locate solutions problems have applying HIP4080A.
Application Demonstration Board
Intersil developed demonstration board allow fast prototyping numerous types applications. board also tailored used characterizing HIP4080A HIP4081A devices under actual operating conditions. Figure Figure show schematic silkscreen indicating component placement, respectively, HIP408X demo board. Note that board used evaluate either HIP4080A HIP4081A, simply changing jumpers. board incorporates CD4069UB "buffer" inputs HIP4080A input terminals IN2. Normally polarities should opposite polarity obtain proper H-Bridge operation. MOSFETs PWM-ed, then JMPR3 should removed opened). Also terminal should driven, insure JMPR1 open. Specific recommendations working with HIP4081A will discussed corresponding section application note HIP4081A. JMPR5 should always removed order implement power reset circuit described data sheet HIP4080A, File Number 3178. Resistors well capacitor, required. Consistent with good design practice, +12V bias supply bypassed capacitors terminals directly). Capacitor 4.7µF tantalum, designed bypass whole PCB, whereas 0.22µF, designed bypass HIP4080A. bootstrap capacitors, high voltage bypass capacitors 0.1µF, 100V ceramic. Ceramic used here because inductance required these capacitors application. bootstrap diodes fast recovery (tRR 200ns), 100V, minimize charge loss from bootstrap capacitors when diodes become reverse-biased. MOSFETs supplied with demo board Intersil IRF520, 100V, device. Since gate charge approximately 12nC, gate resistors, through R24, have been employed deliberately slow down turn-on turn-off these switches. Finally, provide adjustment dead-time. These 500k normally 100k, which will result dead-time approximately 50ns. Resistors, shunt resistors (0.1, wirewound) used provide current-limiting signal, desired. These replaced with wire jumpers required. Finally, space been provided filter reactors, filter capacitors, provide filtering switching components from appearing output terminals facilitate placement user-defined ICs, such op-amps, comparators, etc., space fourteen standard width been reserved left side demo board. output terminations optional locations wired holes which used mount application-specific components, easing process building working amplifiers motor controls audio amplifiers.
chip bias voltages cause power MOSFETs exhibit ex(VCC VDD) cessive RDSON, possibly overheating them. Below about function properly. High chip bias voltag- voltages above about 12V. (VCC VDD) charge pump limiter will begin operate, turn drawing heavier current. Above 16V, breakdown occur. Bootstrap capacitor(s) small cause insufficient soft charge delivery MOSFETs turn-on causing MOSFET overheating. Charge pump will pump charge, possibly quickly enough avoid excessive switching losses. Dead time need increased order allow sufficient bootstrap refresh time. alternative decrease bootstrap capacitance. Smaller values RGATE reduces turn-on/ times cause excessive problems. Incorporating series gate resistor with anti-parallel diode solve problem dead time, reducing shoot-through tendency. Increases switching losses MOSFET heating. anti-parallel diode mentioned above backwards, turn-off time increased, turn-on time not, possibly causing shoot-through fault. Reduces "refresh" time well dead time, with increased shoot-through tendency. increasing HDEL LDEL resistors (don't exceed 250k). Reduce voltage, switching frequency, choose MOSFET with lower gate capacitance reduce bias voltage below 12V). Shed some voltage gate switching losses HIP4080A placing small amount series resistance leads going MOSFET gates, thereby transferring some losses resistors. Check that terminal tied inadvertently.
Bootstrap capacitor(s) large
Dead time small
Lower MOSFETs turn upper MOSFETs don't
CONTROL LOGIC SECTION
DRIVER SECTION HIP4080A/81A
JMPR1 CD4069UB OUT/BLI
HEN/BHI OUT/BLI IN+/ALI IN-/AHI HDEL LDEL
Application Note 9404
CD4069UB JMPR4 IN-/AHI
NOTES: DEVICE CD4069UB COM. +12V. COMPONENTS R30, R31, SUPPLIED. REFER APPLICATION NOTE HELP DETERMINING JMPR1 JMPR4 JUMPER LOCATIONS.
FIGURE HIP4080A EVALUATION BOARD SCHEMATIC
Application Note 9404
JMPR1 JMPR2 JMPR3 JMPR4
FIGURE HIP4080A EVALUATION BOARD SILKSCREEN
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries. information regarding Intersil Corporation products, site http://www.intersil.com
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