AN703 Si9110
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Designing DC/DC Converters with Si9110 Switchmode Controller
James Blanc
distributed power systems battery-powered equipment, advantages over bipolar technology pulse-width modulation (PWM) controllers significant. First, using BiC/DMOS power process, high-voltage DMOS transistor integrated with CMOS controller serve pre-regulator stage. This reduces number external components permitting power controller interface directly power bus. second advantage speed. Bipolar controllers made fast, only with significant increase supply current. Logic gate delays readily achievable using 5-mm CMOS, comparator propagation delays 100-ns range, supply current maintained below does speed translate into power supply performance? answer first reliability second power density. delay time long between sensing overcurrent condition power switch turn-off switch, then peak current values reach excessive levels switch fails. well-designed power supply should tolerate continuous short circuit output. accomplish this with slow controller extra protection circuitry oversized switching transistor heatsink required. that costs money. Power supply density (often expressed output power watts divided volume cubic inches) steadily been increasing over past years. increasing switching frequency, size magnetics filter capacitors been reduced, allowing smaller less expensive power supplies built. increase switching frequency 100- 500-kHz range still
achieve high reliability requires that current limit delay time kept under approximately first BiC/DMOS switchmode controller meet these requirements Si9110. 500-kHz rating maximum switching frequency fully usable, thanks high-speed current limit comparator efficient output driver stage, which essentially eliminates shoot-through current found bipolar totem-pole circuits. DMOS transistor input pre-regulator breakdown voltage rating which provides ample headroom operation from typical voltages distributed power systems (where frequently encountered). appeal such distributed power processing systems their flexibility reliability. bussing power higher voltage, smaller conductors used, well fewer connector pins power where needed-on circuit card. on-card power supply then provide voltages needed that part system. power voltage usually chosen enough eliminate need safety agency approvals, battery connected through diode power provide emergency back-up. distributed power approach employed telecom systems, large minicomputers, other applications where reliability primary concern. illustrate some performance capabilities this BiC/DMOS switchmode controller 15-W forward converter design presented. converter provides +5-V ±12-V outputs from 36-V input range. This permits power supply operate from 12-V 24-V batteries, from 28-V aircraft power source. Before describing forward converter example, instructive review operation each Si9110 switchmode controller's functional blocks.
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Functional Description Pre-regulator
BiC/DMOS power integrated circuit process used integrate high-voltage (120-V rated) lateral DMOS transistor with CMOS controller. using implant shift gate threshold negative value, shown Figure transistor made operate depletion-mode device. This eliminates need pull-up voltage above turn device amplifier voltage reference used implement linear regulator, shown Figure CMOS circuitry thus protected from transients which appear input power bus.
Depletion Mode MOSFET Characteristics
some applications useful turn pre-regulator after start-up. This easily accomplished using auxiliary winding transformer develop bootstrap supply voltage. After converter starts, output feeds (VCC), amplifier pulls gate MOSFET -VIN rail. Thus, -VCC, device turned off.
Oscillator
ring inverters internal capacitors forms oscillator circuit, shown Figure This circuit requires only resistor external capacitor) program frequency. internal capacitance charged towards through ROSC. When capacitor voltage reaches VCC/2, CMOS logic threshold, inverter INV1 changes state (from high low), INV2 output goes from high output. capacitor, provides positive feedback ensure stable operation without frequency jitter. also causes "bump" ramp until INV2 turn discharge switch, terminate cycle.
Enhancement Mode MOSFET Characteristics
-VCC Figure
Vth2
Vth1
Depletion mode MOSFET Characteristics
0-120
+VIN
Cbypass -VIN Figure
Cbypass
Internal Circuitry
regulator/Start Circuit Oscillator Waveforms
Oscillator synchronization achieved prematurely terminating each clock cycle using positive going pulse capacitively coupled onto oscillator ramp voltage. pulse forces INV1 change states, discharges cycle repeats. internal flip-flop blanks output during every other clock cycle, switch duty ratio limited maximum 50%. Therefore, oscillator frequency SYNC pulse repetition rate must times switching frequency,
ROSC Internal Control Logic
Free running VCC/2 With External Sync VCC/2 Input Sync Pulse Sync Pulse 21.5 INV1 Discharge INV2 21.5
INV3
Figure
Si9110 Oscillator Circuit Operation
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Error Amplifier
bias resistor connected from (BIAS) (-VIN) programs current sources analog portion current-mode controller including error amplifier, current-mode current-limit comparators, voltage reference. Si9110 data sheet guarantees performance these functions value bias current possible change performance characteristics these functions changing bias current, Appendix explains this accomplished. error amplifier circuit employs PMOS transistors differential input stage achieve high input impedance typically minimum). This input impedance, combined with 1-kW small-signal output impedance, enables amplifier used with feedback compensation, unlike transconductance error amplifiers. amplifier source sink 0.140 seen from output stage equivalent circuit Figure Yes, transistor used here. Most controller CMOS, process allows flexibility using bipolar devices where they advantageous. error amplifier unity gain stable with typical bandwidth phase margin. Bias current values from have been tested, error amplifier does remain stable over this range. Actually, bandwidth phase margin increase somewhat IBIAS increased above Higher bias currents may, therefore, useful when compensating higher frequency converters (above kHz).
Voltage Reference
buried zener with merged temperature compensating diode (patent pending) used achieve stability 0.25 mV/_C. Si9110 voltage reference trimmed plus minus with bias current This voltage varies about IBIAS varied from reference accuracy must guaranteed, IBIAS should circuits employing external reference secondary side, such those used with optically coupled feedback, Si9111 economical approach. voltage reference provides bias point input error amplifier where accuracy more than sufficient. reference accuracy only difference between Si9110 Si9111.
Comparators
delay time current-limit current-mode comparators modeled current source charging internal nodal capacitance, shown Figure current-mode comparator intentionally made four times slower than current-limit comparator. many circuits, this permits elimination filter current-sense circuit, which used prevent false trips leading edge current spike. After comparator outputs goes high, there additional gate propagation delay before output driver begin switching.
IBIAS IBIAS -VIN Compensation (Pin IBIAS
Output MOSFET Gate) Cnode VCC/2 IBIAS) 4.25 IBIAS)
Figure
Error Amplifier Output Stage
Figure
Current limit Comparator Delay (Equivalent Circuit Model)
total current-limit delay output versus IBIAS shown Figure equal delay time Siliconix
IBIAS decreases IBIAS operating frequency increased, IBIAS
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increased speed current limiting reduce minimum MOSFET pulse width. IBIAS increased, however, current-limit trip voltage also increases. Figure shows trip voltage established varies with IBIAS. current sense resistor IBIAS determine peak value switch current. Since this current limiting very fast, trip level current usually well above maximum normal operating current factor This prevents false trips still protects MOSFET switch from exceeding pulse current ratings. characteristics shown Figure n-channel (turn-off) peak drive current about higher than that p-channel (turn-on) device. Although on-resistance (rDS(on)) output drive specified, usually saturation current (where DID/DVDS very small) determines switching speed. This vertical load line capacitive loads. other words, MOSFET gate capacitance appears short circuit across driver's output.
MOSFET Driver
driver circuit CMOS inverter whose typical
(ns)
IBIAS (mA) Figure Current limit Comparator Delay Bias Current
IBIAS Trip Voltage Current Limit Comparator negative temp coefficient. positive temp coefficient. IBIAS
Figure
IBIAS (mA) Current Limit Trip Voltage Programmed Bias Current
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Output n-Channel (Turn-OFF Drive)
p-Channel (Turn-ON Drive) -100 -150 -200
-VIN
Figure
Output Drive Characteristics
CMOS driver fast enough effectively eliminate cross-conduction current during switching transitions, least when Above this level, small amount cross conduction occurs. Therefore, greatest gate drive efficiency (approaching 100%) achieved keeping gate drive power given
Pgate where MOSFET gate charge switching frequency supply voltage
charging current output disabled until reaches lockout voltage (typically requires less than current during this time, since largest component supply current usually gate drive (see Appendix When reaches output enabled MOSFET begins switching. supply current increases charges more slowly until reaches pre-regulator voltage (8.5 much current drawn from VCC, instance supply other circuitry, possible that converter will prevented from starting. oscillate starts loads down pin, shuts off, then repeats this cycle.
Forward Converter Shutdown Logic
shutdown logic employs flip-flop disable output drive. Both SHUTDOWN RESET inputs have internal current-source pull-ups (equal IBIAS), they left open when unused. long SHUTDOWN input held low, output OFF. RESET input hard wired -VIN (through normally closed reset button desired), input SHUTDOWN will latch output "off" state. will remain until power recycled reset button pushed).
Specifications
Input Voltage: Output Voltages Minimum Load (mA) Maximum Load 0.310 0.310 Regulation Ripple (mVp-p)
Undervoltage Lockout
During start-up, depletion transistor charges capacitance connected with typical Siliconix
Efficiency: Full Load: typical, minimum Load: typical, minimum Switching Frequency
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Circuit Description
forward converter schematic shown Figure block diagram Si9110/Si9111 controller appears Figure easy reference. circuit employs TL431C voltage reference/amplifier drive opto-isolator, This maintains galvanic isolation between input output voltages. Since reference needed secondary side, external controller necessary have precision reference primary side. voltage reference Si9111 specified ±10%, which accurate enough establish bias point collector current galvanic isolation required, then feedback circuitry replaced voltage divider network, input output grounds must tied together. this configuration, reference accuracy controller limits accuracy output voltages, Si9110 with reference should specified. identical other respects. SMP25N06 switching transistor (Q1) 25-A, 60-V MOSFET T0-220 package. breadboard operated without heatsink even with power supply output shorted. Three secondaries transformer, provide isolated voltages output inductors wound common core. This reduces size cost compared separate output chokes, well improves response dynamic loads. same core size used transformer output inductor, only difference being required inductor sustain flux. transformer does require since winding, resets core flux zero during "off" time
1N4148
(Core 1811PL00-3C8) N3=13 (#26)
1N5822
(Core 1811PA250-3C8) turns strands #26) (1.5
+VIN (9-36 VDC)
(#32)
1N5822 2200
turns (#32)
COMMON
1N5811 strands #26) N4=30 (#32) N5=30 (#32) 1N5811 0.018 SMP25N06 6N135 1N5811 1N5811
turns
(#32)
(0.310 COMMON (0.310
+VIN COMP VREF SENSE BIAS -VIN DSCH
Feedback Isolation Circuit
Feedback Circuit Non-Isolated Supply
Si9111
TL431C
39.2
Figure
Multiple Output Forward Converter
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Error Amplifier VREF Clock fOSC) BIAS +VIN Current Sources Internal Circuits Comparator Current-mode Comparator OUTPUT COMP DISCHARGE
-VIN
Undervoltage Comparator
SENSE
SHUTDOWN RESET
Pre-regulator/Startup Figure Si9110/Si9111 Block Diagram
Forward Converter Principle
Secondary Voltage
operating principle forward converters illustrated Figure When switch, input voltage applied across primary winding, example, input voltage minus voltage drop across equal then turn applied across primary. Since same magnetic flux links windings, volts/turn constant Faraday's -N(df/dt)]. Therefore, equals equal filter cut-off frequency well below switching frequency, that average value pulsed secondary voltage appears output. equal duty ratio, neglecting diode drops, given 0.385
di/dt Drain Current
Figure
Forward Converter Operating Principle
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control loop will force duty ratio value required make regulated output equal duty ratio equals 0.385, secondary voltages given designs that tolerate shorted outputs indefinite period. short removed, then converter returns normal operation.
(30) (0.385) 11.5
Measured Circuit Performance
Figure shows power supply efficiency varies with load. Under low-line condition (VIN full load efficiency 77%. higher input voltages, conduction losses MOSFET sense resistor reduced, permitting full-load efficiency exceed 80%. High efficiency light loads permitted CMOS controller's supply current. only 20.7 required Si9111. circuit operation VIN= with load illustrated waveforms Figure control voltage ac-coupled shown above current sense voltage. downward slope slope compensation resistor connected between Slope compensation explained below section loop analysis References When +5-V output shorted ground, waveforms appear Figure error amplifier output, goes positive rail, current-mode comparator would allow duty ratio increase 50%. However, faster current-limit comparator trips about duty ratio limited less than 10%.
This ideal case. diode drops cause duty ratio higher, very close (The measured value 12.1 When turns off, free-wheeling diodes CR3, CR5, carry inductor currents. Again, diode drops neglected, each output voltage appears across corresponding inductor winding. Since volts turn must constant each winding number turns must proportional output voltage. Therefore, number turns inductance each winding cannot arbitrarily assigned they individual output chokes. ratio turns must integer multiple secondary windings. this case, integer amount inductance then determined core gap, specified inductance 1000 turns; 1000 turns used, giving inductance inductor determined from
1000
Therefore, current slope during "on" time (referred primary side given
0.275 A/mS
Efficiency
This current ramp sensed give voltage ramp input Si9111. current-mode comparator changes states turns MOSFET switch when this sense voltage exceeds control voltage, from output error amplifier. Thus, peak inductor current controlled cycle-by-cycle basis. same current sense signal also compared internally-generated reference current-limit comparator. This comparator made four times faster than current-mode comparator minimize delay time required turn MOSFET when overcurrent condition exists. Such dual-threshold current sensing enables power supply
Figure
Percent Efficiency Load Current
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V/div) V/div)
(pin (500 mV/div) VSENSE (500 mV/div) A/div)
(pin (500 mV/div) A/div)
Loads:
0.25 Forward Converter Waveforms
Figure
Figure
Forward Converter Waveforms with Output Shorted (VIN
RDIV
Current Proportional Control Voltage
VREF
Voltage Current Converter
Control Voltage
Figure
Power Converter with Current-mode Control
Control Loop Analysis Current-Mode Control
Current-mode control switching power converters offers several advantages over voltage-mode control. reliability improvement offered fast cycle-by-cycle current limiting discussed above. second major advantage current programming improved dynamic response regulator loop while same time requiring simpler error amplifier compensation.
basic objective current-mode control make power stage behave voltage-to-current converter (transconductance amplifier), shown Figure regulate output voltage, feedback loop employed. control voltage, generated error amplifier which compares output voltage precision reference, just voltage-mode control.
There several methods implementing transconductance power amplifier function-all them employ inner current feedback control loop.
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most common method uses constant frequency clock peak current sensing, shown Figure clock pulse initiates turn-on MOSFET switch, current ramps output inductor. This current, reflected through transformer turns ratio, sensed resistor MOSFET source produce voltage analog inductor current. When voltage ramp reaches control voltage, current-mode comparator sets latch turns switch. this inner current control loop programs inductor current proportion control voltage. achieve same loop bandwidth current-programmed power converter, voltage-mode converter requires error amplifier with compensation shown Figure 17a.
ROSC +VIN
RSENSE
Figure
Voltage-to-Current Converter
Current-mode control requires fewer compensation components, shown Figure 17b, error amplifier simpler transfer function. simplified compensation elimination double pole output filter, which must compensated double zero inner current-programmed loop were perfect, then inductor would behave controlled current source, power stage would single-pole system. This doesn't happen. What does occur splitting poles. shifted down frequency approximately which dominant low-frequency pole. second pole voltage regulator loop occurs unity gain crossover frequency, wC/2p, inner current-control loop. inner current-control loop less gain than voltage loop more bandwidth.[1] wide bandwidth current loop enables power converter respond more rapidly step changes load current, even small-signal loop bandwidth same. must realized that step load changes large signal perturbations between different small-signal operating points. With inductor current controlled parameter, wideband current loop changes more rapidly between operating points load current. measured response step change load given Figure switch current output voltage recover steady-state within about five switching cycles. Voltage-mode control generally yields response which slower factor
Output Voltage from Power Stage VREF
GAIN (dB)
Control Voltage Modulator FREQUENCY
Figure 17a. Error Amplifier Compensation Maximum Bandwidth Using Voltage-Mode Control
GAIN (dB)
Output Voltage from Power Stage VREF
Control Voltage Modulator
FREQUENCY
Figure 17b. Error Amplifier Compensation Maximum Bandwidth Using Current-Mode Control
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A/div)
(500 mV/div) V/div)
Figure Step Load Response
Small-Signal Analysis
very concise presentation small-signal analysis current-mode control loops found Reference that paper, Y-parameter model, shown here Figure developed current-programmed power stages since Y-parameters give output current unit control voltage input. inner current loop demonstrated stable, long slope compensation employed 0.5, therefore, current loop absorbed into power stage model. This advantage allowing analyze stability only (voltage) control loop.
derivations will presented here, resulting control-to-output voltage transfer function buck regulator shown Figure frequency value inverse output admittance, Y22. measure effectively current programming makes power stage behave current source and, consequently, depends heavily upon gain inner current loop. More inductance yields higher current loop gain larger R22. Smaller causes frequency gain diminished, since appears parallel with load, also decreases low-frequency pole same factor. this case, simply sense resistance value buck-derived converters, ratio voltage current-mode comparator input inductor current, accounts current amplifier gains current transformer ratios. second pole wC/2p depends upon switching frequency, amount slope compensation, duty ratio operating point (remember that this small-signal analysis variations around operating point); does depend load current. easy work through calculations form table, shown Figure voltage-control loop bandwidth, fvc, phase margin, calculated full load three different input voltages. same symbols used reference with exceptions that current ramp slopes referenced current-mode comparator input. result same long current scale factor, taken into account.
Figure Y-parameter Model Current-mode Regulators
(R22
(dB)
Figure
Small-signal Control Output Transfer Function Current-programmed Buck Regulators
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0.59 0.78 0.88 (R22 Figure 15-W Forward-converter Stability Analysis Ramp Slope: VCC/2 TS/2 RSLOPE (V/ms) 0.044 0.089 0.158 1.16 (Hz) (krad/s)
(kHz) 15.76 15.77 15.85
(deg)
(17.5dB) (17dB) (17dB)
(33.7) (31.4) (31.2)
VCC/2
TS/2 RDIV RSLOPE
Current Proportional Control Voltage
ROSC VREF
Voltage Current Converter
Control Voltage
Figure Implementation Slope Compensation Using Si9110.
forward converter transformer-isolated derivative buck regulator. Therefore, Y-parameter model buck regulator applies here, values used must reflected through transformer turns ratios. resulting circuit parameters 0.31 0.31
Slope compensation achieved feeding oscillator ramp voltage into inverting input error amplifier, shown Figure amount slope compensation given RSLOPE
0.071 V/ms 0.83 (1000
This calculation does take into account effect ripple feedback upon slope compensation. buck regulator, during "on" time switch, output ripple voltage ramping upward capacitor ESR. This ramp voltage amplified inverted error amplifier provide additional slope compensation. lower capacitors used, this effect diminished. film ceramic filter capacitors, ripple also phase shifted, since ripple voltage determined more than ESR. Siliconix
20.3
1500
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slope compensation parameter, given n=1+ (10)
where current ramp slope (times sense resistance) during tON, which calculated from
GAIN (dB)
2pRfbCf
Power Stage
Error
20.3
(11)
15.8
buck converter, simply equal sense resistance. conduction parameter measure into continuous conduction converter operating. full load (20.3 (0.83) 4.86 (12)
Conditions: Full Load
Figure Bode Plot Small-signal Loop Gain
This converter operates heavily into continuous conduction mode fairly high current-loop gain. output resistance parameter (13)
error amplifier gain remains constant
Rdiv
(15)
23.5
which varies with both input voltage load. frequency, power stage low-frequency pole (R22 (14)
between point where open-loop gain error amplifier takes over. This occurs AOL1 BW/A1M, where error amplifier bandwidth. gain loop decreased unity below poles wC/2p, AOL1 each contribute significant phase shift. voltage loop crossover frequency calculated from (16)
low-frequency gain power stage (R22 RL)/R2C high-frequency pole given wS/pnDi. Once gain power stage been determined plotted, shown Figure objective establish values error amplifier compensation provide good loop bandwidth phase margin. Some typical "rule-of-thumb" numbers bandwidth sixth fifth switching frequency phase margin 60_. series network feedback error gives pole origin zero RfbCfb.
feedback divider resistor, first arbitrarily chosen (This non-isolated configuration. analysis optical-isolator circuit, Appendix achieve kHz, calculated from Equation This requires Rdiv standard capacitance value then chosen such that falls somewhat below 0.018 places zero, about
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phase margin, ideal current-mode converter 90_. Phase lags poles wC/2p AOL1 diminish phase margin according
90_-tan-1 -tan-1
(17)
where transformer efficiency
more accurate analysis should account zero capacitor ESR. tantalum capacitors used here (type 550D from Sprague) will cause zero approximately kHz. This will just about cancel pole wC/2p, increase phase margin. Higher will cause extra zero fall below fVC, loop bandwidth will increased somewhat.
(16.1)
/0.99
45.8
electrical conditions parameter, given 0.145 Ke2f2Bm2 10-4
Magnetics Design Transformer Core Selection
core selection method used here employs core geometry parameter, proposed McLyman.[3] cores were chosen both transformer coupled inductor, another design approach using toroids recommended applications requiring either lower profile resilience thermal shock that toroids provide. Begin calculating output power transformer. (18)
where
Waveform Factor forward converter) Operating Frequency Maximum Flux Density (0.15 tesla chosen)
0.145(
)2(105)2(0.15)2
10-4
6525
where
Finally, core geometry,
Output Voltage Diode Drop Output Current V)(1.5 2(12 V)(0.31 16.1 (19)
(24)
where percent regulation (use 45.8 10-3 cm-5 (6525) (25)
apparent power, single-ended forward converter
This calculation based upon assumed window utilization factor, 0.4. This difficult achieve using small cores. Assuming window area, core geometry adjusted Siliconix
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Kg(new) (0.4/0.25) (3.5 10-3) 10-3 Bmax (27) closest core number 1811PL00 from Ferroxcube, which 10-3 cm5. toroidal cores which most nearly meet transformer requirements numbers T8-16-8 T10-20-5 from TDK. Their Kg's 0.007456 0.007536 cm5, respectively. Bmax
(28)
where
Transformer Winding Design (First Iteration)
Refer Figure nomenclature used here. number primary turns calculated from Faraday's Law, which states that -N(df /dt).
Cross-sectional Area Core Bmax Maximum Flux Density MOSFET On-time (tON
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Design Dmax 0.475 calculated from
Inductor Core Selection
power handling capability core independent number windings used. simplest approach refer outputs winding assume that
(rDS(ON) RSENSE)
PO/VO (PO/h) W/0.8) (0.475) (30) (31) Therefore, (4/2)(5 A)10-5 (8.2 (4.75 (0.15 (0.433 10-4 turns (32)
operate well into continuous conduction choose 2L/RTS
(0.08 0.10)
This ball park number; acceptable, However, larger, larger core required same core losses.
Calculate secondary turns follows: peak inductor current, maximum load,
[(Vp) (NS/Np)
IO(MAX)
(36)
0.475, then 8.07. (Assume diode drop Schottky diodes fast recovery diodes.) Eight turns close enough. find number turns 12-V secondary. During off-time, output voltages appear across each coupled inductor winding, which must have same turns ratios transformer secondaries. Therefore, (34)
approximately given tOFF
(37)
maximum occurs maximum where 0.11, tOFF D)10 (38)
gives 18.5 turns; turns give 11.65 turns give 12.35 Another option This will more closely achieve desired turns ratios, copper losses will greatly increased. Remember that number turns doubled, then copper cross section must halved. Resistance, copper losses, increase factor four. doesn't matter that 12-V output bit, then
inductor energy storage requirement (LI2) mH)(3.75)2
electrical conditions Siliconix
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0.145 (PO) (Bm)2 10-4 0.145 (15) (0.3)2 10-4 19.6 10-6 1811 core with standard value (160, 250, mH/103). toroid, number 55206 molypermalloy powder core, which 0.007274 cm5. core chosen here. (0.00275) 10-3 0.25 (43)
core geometry requirement
Inductor Winding Design
(E)2 (232 mJ)2 (19.6 10-6) (42) transformer design left with which causes 12-V output about 12.35 mH/1000 turns used, (8/1000)2 (0.4) 25.6
0.00275
regulation. Adjust this window utilization,
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This gives (25.6 (1.67) (10-5) (45) inductors used. Calculations made based upon some reasonable assumptions, results give desired outcome (such fractional turn saturated core). Then choices must made which consistent with requirements application. choice made here output voltages close possible transformer secondary turns primary turns found from VO/D (NS/Np) (47) 0.475 (53) (54)
which still well into continuous conduction (Kcrit buck converters). could done this way, make output come closer some other turns ratios. gives: (5.5/13)30 11.99 mH/1000 turns gives (13/1000)2 (0.25) maximum flux density found from (48) 0.28 (49) (46)
9.67 turns turns that converter will continue regulate down Again, apportioning copper according power level (and equally split between primary secondary) gives following winding configuration. Winding Turns Wire Size Strands AWG26 Strand AWG32 Strand AWG26 Strand AWG32 Strand AWG32
(3.75 (13) (0.433 10-4)
Saturation occurs above 3000 gauss, this flux level acceptable. Apportion window area according output power each winding. Total copper area 0.25 where 0.285 total window area. copper cross section winding (0.25) (0.285 cm2) turns (1.5 (50)
Primary RESET
2.74 10-3 strands AWG26 magnet wire, which copper area (1.28 10-3 cm2) (2.56 10-3 cm2) (51) winding, (0.25) (0.285 cm2) turns (0.31 (52)
primary RESET windings were wound together (multifilar) over bobbin, followed output. ±12-V windings were wound bifilar over winding.
Prototyping Hints
schematic parts list provide sufficient information enable operator switching power supply. Parasitic inductances capacitances, which appear schematic, cause major differences performance. number layout iterations reduced (down with experience) following guidelines followed. ground plane. However, assume that ground plane impedance zero that ignore need good component placement. Every component cannot placed near every other component. Know which components should grouped closely together when close proximity unnecessary. Siliconix
0.59 10-3 strand AWG30, which 0.507 10-3 cm2.
Transformer Winding Design (Revisited)
shown above analysis, transformer inductor designs interdependent when coupled
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Keep loop areas small where current changes rapidly. Loop inductance proportional loop area. Inductive voltage spikes proportional inductance, i.e, Ldi/dt. example, loop from through primary, back bottom carries current which undergoes high rate change. Reducing this loop area reduces noise input power lines. Other examples loops defined each secondary winding corresponding output rectifiers. Cross regulation 12-V outputs worsened inductance these loops. Conversely, inductance loop defined CR3, critical. parasitic inductance series with inductor little consequence. Keep noise-sensitive nodes away from noise generators. drain voltage changes rapidly. trace between (primary) (drain) runs adjacent feedback input (pin then noise capacitively coupled into feedback. noise current proportional parasitic capacitance Cdv/dt. Injected noise currents worse when driving point impedance high. Pins switchmode controller such high-impedance nodes. much noise injection causes random instability control loop. Following these guidelines reduces headaches well costly design time. Using BiC/DMOS controllers reduces component count failure rates dc/dc converters distributed power systems.
References
Middlebrook, R.D., "Topics Multiple-Loop Regulators Current-Mode Programming," IEEE Power Electronics Specialists Conference, Record, 716-732 (IEEE Publication 85CH2117-0). Hsu, al., "Modelling Analysis Switching DC-to-DC Converters Constant-Frequency Current-Programmed Mode," IEEE Power Electronics Specialist Conference, 1979 Record, 284-301, (IEEE Publication 79CH1461-3 AES). McLyman, Col. "Magnetic Core Selection Transformers Inductors," Marcel Dekker,1982.
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Appendix
Proper operation Si9110 requires that programming resistor, RBIAS, connected from -VIN, which assumed here ground. This resistor programs internal current sources analog portion control circuitry. value bias current depends upon parameters, RBIAS, shown circuit provided Figure characteristic curve PMOS follows familiar square proportional squared). However, over region interest, between curve closely approximated straight line, shown Figure This line defined slope point intersection with X-axis (3.5 intersection this curve with load line defined RBIAS determines value IBIAS. load line Figure identifies conditions which specified data sheet. When RBIAS IBIAS pre-regulator used continuously, forward converter example above, then nominal value 1-MW bias resistor gives IBIAS This lowest value recommended. high end, much performance improvement terms comparator speed obtained IBIAS above (see Figure
Bias Current
(Pin VBIAS RBIAS
ISOURCE
(Pin VBIAS -VGS
Figure Internal Current Source Programming
RBIAS
25.6
DVSD
Figure
Programmable Current Regulator Characteristics
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Appendix
supply current requirements controller specified operating frequency, with load being driven. many cases, useful circuit designer determine supply current requirements needed drive specific MOSFET given frequency. Si9110 been well characterized this regard. Equation provides quick calculation supply current drawn Si9110. forward converter example, supply current should Voltage reference Oscillator logic (1.5 mA)/kHz Analog circuitry Gate drive 1500 Total supply current 1860 measured value
Appendix
gain error amplifier plus feedback isolation circuit
(CTR)
1000
IBIAS
Each explanation.
components
straightforward
(0.07) 1180
voltage reference requires constant current which neither frequency load dependent. typical value CMOS circuitry only uses power when change logic state occurs. Therefore, quiescent current requirements oscillator logic gates proportional switching frequency. proportionality constant typically kHz. analog circuitry (error amplifier comparators) utilizes constant-current sources which programmed bias resistor connected from ground. Setting RBIAS equal programs bias current this current, internally generated voltage reference levels (for undervoltage lockout, VREF, VCL) have best compensation over temperature. This also value which data sheet parameters guaranteed. output drive current typically largest component ICC. drive stage been designed minimize shoot-through current output inverter. Thus, current requirement calculated Igate CLVCCfS. MOSFET gate capacitive load, non-linear one. Therefore, MOSFET manufacturers specify total gate charge required turn MOSFET this case, Qg(on) where switching frequency.
which approximately equal gain non-isolated feedback circuit analyzed above. TL431C voltage reference with accuracy equal were both chosen establish current much greater than input bias current which causes amplifier behave integrator with high gain, thus ensuring accuracy output voltage. causes gain remain constant R9/R7 above crossover frequency,1/(2pR9C10). minimum current transfer ratio (CTR) 0.07. defined ratio output current anode current optical isolator. small-signal variation current equal output voltage divided R10. output voltage equal output current times R11. Therefore, gain from output output given CTR(R11/R10). chosen establish operating current given approximately VREF
Likewise, establishes operating point approximately chosen last achieve desired overall gain.
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