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Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
Funk ABSTRACT Both buffered unbuffered CMOS B-series gates, inverters, high-current products available from Each product classification application advantages appropriate logic-system designs. Many CMOS suppliers have concentrated promoting buffered B-series products, with applications literature focusing attributes buffered types. This practice left imbalance understanding application both buffered unbuffered gates. some instances, customers using unbuffered products when they best choice intended application. This application report offers clarification relative merits buffered unbuffered CMOS devices. This application report acquired from Harris Semiconductor Corporation edited reformatted December 2001. This application report adapted from AN6558.1, published Harris (1992), which, turn, adapted from ICAN-6558, published (1983). Standard Linear Logic
Contents Background Definitions Buffered CMOS Unbuffered CMOS Examples Output Impedance Noise Immunity Comparisons Gain Bandwidth Output Oscillation Slow Inputs Input Capacitance Applications Guidance Gate, Inverter, Driver Products
Trademarks property their respective owners.
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List Figures Buffered (CD4001B) Unbuffered (CD4001UB) Two-Input Gates Schematic Diagrams Buffered Unbuffered Two-Input Gates Constant Output Impedance Buffered Gate Variable Output Impedance Unbuffered Two-Input Gate (The Resistors Represent Impedance n-Channel Transistor) Voltage Transfer Characteristics Buffered Two-Input Gate (CD4001B) Voltage Transfer Characteristics Unbuffered Two-Input Gate (CD4001UB) With Output Voltages Linear-Gain Test Circuit Typical Linear-Mode Gain Buffered Unbuffered Two-Input Gates Buffered Output Oscillation Slow Input Input Capacitance Buffered Two-Input Gate (CD4001B) Input Capacitance Unbuffered Two-Input Gate (CD4001UB) List Tables Comparison Buffered Unbuffered Gate Characteristics Characteristics Buffered Unbuffered Gates Input-Voltage Specifications Applications Buffered Unbuffered CMOS Gates Inverters COS/MOS Buffered Unbuffered Gate, Inverter, Driver Types
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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Background
Historically, most CMOS gates, inverters, high-current products were unbuffered exhibited good logic-system performance, speed, noise immunity, quasi-linear characteristics wide variety applications. scope CMOS products broadened additional manufacturers began making them, buffered gate inverter products became available. While initial buffered products were confined functions, buffered NAND gates were introduced with same generic 4000A-series designations original, widely used, unbuffered gates. Users were surprised noninterchangeability devices applications where speed, noise immunity, output impedance, linear gain-bandwidth characteristics were critical. benefit CMOS users have available definitions designations both buffered unbuffered B-series CMOS devices determined JEDEC CMOS Standardizing Committee under cognizance JC40.2 JEDEC Committee EIA. official JEDEC definitions repeated following paragraphs, along with detailed explanations examples. Comparisons user-oriented characteristics buffered unbuffered gates also reviewed.
Definitions
Buffered CMOS
buffered CMOS device which output impedance independent valid input logic conditions, both preceding present, said have buffered output buffered CMOS device. such products designated suffix
Unbuffered CMOS
Devices that meet B-series specifications, except that logical outputs buffered specifications VDD, respectively, marked with designation, including (but limited 4001UB, 4007UB, 4009UB, 4011UB, 4041UB, 4049UB, 4069UB. official JEDEC definitions applicable primarily gates, inverters, high-current (inverting) drivers, such specific types listed previously. Noninverting gates drivers, well medium-scale integrated circuit (MSI) large-scale integrated circuit (LSI types are, definition, types. There special analog types that also types because they conform standards, except that they have special analog circuitry. Examples parts that have buffered unbuffered significance 4016B, 4046B, 4051B, 4052B, 4053B, 4067B, 4097B, 4066B, 4511B, 4528B. Logic examples buffered unbuffered two-input gates shown Figure Note that buffered logic implemented either two-input function, followed inverters input inverters, followed two-input NAND gate output buffer. uses latter logic configuration, which advantage optimizing device noise immunity negating effect stacked devices input. This characteristic especially significant three- four-input gates where three four PMOS NMOS transistors stacked series input. this case, inputs have effective offset threshold reduced input noise immunity.
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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Output Output Buffered CD4001B Output
Unbuffered CD4001UB
92CS-28330
Figure Buffered (CD4001B) Unbuffered (CD4001UB) Two-Input Gates
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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Figure schematic representation buffered unbuffered two-input gates. improved four-diode-input gate-oxide protection circuit shown inputs.
Output
Buffered
Output
Unbuffered
92CS-28331
Figure Schematic Diagrams Buffered Unbuffered Two-Input Gates
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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Examples
Examination performance characteristics both buffered unbuffered two-input gates reveals electrical characteristics, output impedance noise immunity, which types differentiated JEDEC standard specifications.
Output Impedance Buffered Output
Figure shows buffered output stage shows transistor switched with channel resistance, which same value switch closed switch closed.
Switch
Switch
92CS-28332
Figure Constant Output Impedance Buffered Gate
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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Unbuffered Output
Figure shows unbuffered two-input gate n-channel switches appropriate on-channel resistances. Note that stacked p-channel switches designed resistance R/2, that output impedance when both logic inputs [see Figure 4(b)]. Figure 4(a), output impedance negative supply terminal (usually ground) input logic state input high. Figure 4(c) shows condition when unbuffered gate output impedance both logic inputs high, hence, variable output impedance unbuffered gate. four-input gate, this variable R/4. maximum output resistance buffered unbuffered gates Thus, minimum specifications buffered unbuffered gates identical.
Inputs High Inputs Inputs High High
Output
Output
Output
Input Low, Input High
Both Inputs
Both Inputs High
92CM-28333
Figure Variable Output Impedance Unbuffered Two-Input Gate (The Resistors Represent Impedance n-Channel Transistor)
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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Noise Immunity
second JEDEC-defined difference between buffered unbuffered CMOS gates inverters) difference input noise-immunity characteristics.
Buffered Gate
buffered two-input gate voltage-transfer characteristics square shaped because gain three CMOS stages from input output (see Figure Figure shows that noise voltage inputs ±1.5 will have little discernible effect output voltage; i.e., noise immunity logic states optimally high noise margin,
25°C
VOUT
92CS-28334
Figure Voltage Transfer Characteristics Buffered Two-Input Gate (CD4001B)
Unbuffered Gate
Figure shows rounded voltage transfer characteristics two-input unbuffered gate. Also evident shift transfer curve different logic input states. Compare these curves those Figure effects nonbuffered inputs, well gain differences, evident. rounded characteristics require noise-immunity specification well reduced noise margin,
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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25°C
VOUT
VOUT
92CS-28335
25°C
VOUT
VOUT
92CS-28336
Figure Voltage Transfer Characteristics Unbuffered Two-Input Gate (CD4001UB) With Output Voltages
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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previous definitions gate characteristics illustrate JEDEC definitions buffered unbuffered characteristics relative variable output impedance noise-immunity performance. Inverters high-current drivers also defined buffered types unbuffered (UB) types virtue squared rounded transfer characteristics Figures respectively. Even though both types have single NMOS single PMOS output transistor, rounded transfer characteristic unbuffered inverters makes them types virtue
Reduced noise-immunity performance, where rating applicable Varying output impedance, function input voltage change along rounded portion transfer curve
Comparisons
Table1 shows qualitative comparisons user-oriented performance characteristics buffered unbuffered CMOS gates, inverters, drivers. Table Comparison Buffered Unbuffered Gate Characteristics
CHARACTERISTICS Propagation delay Noise immunity/margin Output impedance output transition time gain Output oscillation slow inputs Input capacitance BUFFERED GATE Slow Excellent Constant High UNBUFFERED GATE Fast Good Variable High
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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Table quantitative comparison performance characteristics, with explanations propagation delay, noise immunity, output impedance, output transition time. Table Characteristics Buffered Unbuffered Gates
CHARACTERISTICS Noise immunity/margin Two-input gate Typical output impedance ±0.4 Three-input gate Four-input gate Two-, three-, four-input gates BUFFERED GATES Susceptible Average Peak UNBUFFERED GATES susceptible
Typical propagation delay
Noise margin
Typical output transition time gain bandwidth Output oscillation slow inputs Typical input capacitance
Propagation Delay
Propagation delay times Table applicable two-, three-, four-input NAND gates.
Noise Immunity
Table shows detailed data-sheet input-voltage specifications buffered unbuffered gates. From test conditions Table user-oriented noise immunity noise-margin data Table derived. Also, refer Figures voltage-transfer characteristics that illustrate reason different input-voltage-specification requirements buffered unbuffered devices.
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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Table Input-Voltage Specifications
CHARACTERISTICS Buffered Input voltage Unbuffered 13.5 13.5 Buffered Input voltage Unbuffered 12.5 LIMITS UNIT
NOTES: Noise-immunity voltage specification limit. Noise-margin voltage computed Noise-margin voltage (VDD (VDD VIH)
Output Impedance
output impedance, refer Figures accompanying descriptions constant output impedance buffered gates variable output impedance unbuffered gates. Note that both buffered unbuffered two-, three-, four-input gates designed meet same maximum output impedance; output current ratings (IOL IOH) have same minimum limit data sheets.
Output Transition Time
time required CMOS output transfer high transfer constant buffered gates, varies according input logic states unbuffered gates. Output transition time varies function driving source resistance output, which state dependent, indicated Figure well device output capacitance, which dependent both device size input logic state. Because variable output capacitance, output transition-time variations linear function output resistance. Table shows, two-, three-, four-input unbuffered gates exhibit two-to-one difference output transition time, even though output resistance four-to-one variation four-input gate.
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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Gain Bandwidth
CMOS linear-mode gain measured both buffered unbuffered two-input gates using test circuit Figure Figure shows typical linear-mode gain difference between buffered unbuffered two-input gates. While absolute performance depends device type (inverters two-, three-, four-input gates) test configurations, Figure defines approximately three-to-one difference linear-mode performance between buffered unbuffered gates.
Sine-Wave Generator Source
CD4001
Meter
92CS-28338
Figure Linear-Gain Test Circuit
Gain
Frequency Typical CD4001B Linear Gain
Gain Frequency Typical CD4001UB Linear Gain
92CS-28339
2800
Figure Typical Linear-Mode Gain Buffered Unbuffered Two-Input Gates
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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Output Oscillation Slow Inputs
high linear-mode gain buffered CMOS devices lead undesirable oscillation outputs when input ramps excess approximately 1-ms duration. Figure shows this effect when approximately noise within device bandwidth input signal amplified through device tend develop cycles oscillation between positive negative rails under operation. contrast, unbuffered gates tend oscillate unless noise voltage present within bandwidth device. input ramp 100-ms duration create oscillation laboratory tests unbuffered gates.
Noise Ramp
Input (also applicable
Transition Begins
Output
92CS-28340
Figure Buffered Output Oscillation Slow Input
Input Capacitance
Figures show dynamic input capacitance buffered unbuffered two-input gates, respectively. large transistor geometry unbuffered gate responsible higher peak input capacitance (Miller effect) linear switching range. longer dwell this linear region also tends broaden Miller capacitance and, therefore, increases effective average input capacitance. Buffered gates inverters rated maximum input capacitance unit load (7.5 JEDEC standard); unbuffered gates inverters rated unit loads maximum). High-current unbuffered drivers, such CD4049UB, rated unit loads (22.5 maximum).
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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25°C
92CS-28341
Figure Input Capacitance Buffered Two-Input Gate (CD4001B)
25°C
92CS-28342
Figure Input Capacitance Unbuffered Two-Input Gate (CD4001UB)
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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Applications Guidance
Table summarizes preferred application areas both buffered unbuffered B-series devices. This information based buffered unbuffered CMOS device characteristics listed Table combined with author's experience familiarity with application areas indicated. information given general guidance allow designer key-in specific performance characteristics either device type. data provided this application report derived from standardized products whose circuit designs were implemented match performance between gate types closely possible. example, device sizes were selected assure matched output drive. addition, process layout rules followed designs devices identical, improved gate-oxide protection circuitry devices. Table Applications Buffered Unbuffered CMOS Gates Inverters
APPLICATION High-speed systems High-noise environments, low-speed systems Ultra-low-frequency systems, inputs <1-kHz sine wave ramps with excluding Schmitt triggers Gate applications requiring constant output impedance, such R-2R conversion Linear amplification High frequency, moderate gain frequency, high gain Preferred Preferred Preferred Preferred Preferred BUFFERED UNBUFFERED Preferred
Applies gates inverter designs astable monostable multivibrators with
Gate, Inverter, Driver Products
Table list small-scale integrated (SSI) products presently production Refer data sheets detailed product information. Table COS/MOS Buffered Unbuffered Gate, Inverter, Driver Types
BUFFERED CD4001B CD4002B CD4010B CD4011B CD4012B CD4023B CD4025B CD4050B CD4068B CD4071B CD4072B CD4073B CD4075B CD4078B CD4081B CD4082B UNBUFFERED CD4001UB CD4007UB CD4009UB CD4011UB CD4041UB CD4049UB CD4069UB
Understanding Buffered Unbuffered CD4xxxB Series Device Characteristics
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