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Implementing Digital Filters
Author: Amar Palacherla Microchip Technology Inc.
THEORY OPERATION
Digital filters most cases assume following form relationship between output input sequences.
INTRODUCTION
This application note describes implementation various digital filters using PIC17C42, first member Microchip's generation 8-bit microcontrollers. PIC17C42 very high speed 8-bit microcontroller with instruction cycle time input clock). Even though PIC17C42 8-bit device, it's high speed efficient instruction allows implementation digital filters practical applications. Traditionally digital filters have been implemented using expensive Digital Signal Processors (DSPs). system normally slave processor being controlled either 8-bit 16-bit microcontroller. Where sampling rates high (especially mechanical control systems), single chip solution possible using PIC17C42. This application note provides examples implementing digital filters. Example code order Infinite Impulse Response (IIR) filters given. following type filters implemented: Pass High Pass Band Pass Band Stop (notch) filter
above equation basically states that present output weighted past inputs past outputs. case filters, weighted constants case filters, least constants zero. case IIR, above formula rewritten terms transform
This application note does explain design filter. Filter design theory well established beyond scope this application note. assumed that filter designed according desired specifications. desired digital filters designed using either standard techniques using commonly available digital filter design software packages. Finite Impulse Response (FIR) filters have many advantages over filters, much more resource intensive (both terms execution time RAM). other hand, filters quite attractive implementing with PIC17C42 resources. Especially where phase information important, filters good choice (FIR filters have linear phase response). various forms used realizing digital filters (like, Direct form, Direct form, Cascade form, Parallel, Lattice structure, etc.) Direct form used this application note. easy understand simple macros built using these structures.
above equation further rewritten difference equation format follows:
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Realization above equation called Direct Form structure. example, case second order structure, gives following difference equations: multiplier routine also provided. This routine implemented straight line code speed considerations. order filter implemented Pass Filter with specifications shown Table
EQUATION EQUATION
above difference equations represented shown Figure
TABLE FILTER CONSTANTS
BAND1 Lower Band Edge Upper Band Edge Nominal Gain Nominal Ripple Maximum Ripple Ripple Sampling Frequency 0.01 0.00906 0.07830 BAND2 0.05 0.04601 -26.75
FIGURE
X(n)
ORDER DIRECT FORM STRUCTURE (TRANSPOSED)
Y(n)
Pass Filter designed using digital filter design package (DFDPby Atlanta Signal Processors Inc.). filter package produces filter constants structure shown Table Table shows filter co-efficients that obtained above Pass filter specification.
TABLE FILTER CO-EFFICIENTS
Stage Co-efficients
-0.133331 0.147827
structure shown Figure cascaded attain higher order filter. example, stages cascaded together, Order Filter obtained. This way, output stage becomes input second stage. Multiple order filters thus implemented cascading order filter structure shown Figure
0.167145 0.765900
0.285431 0.698273
0.462921 0.499908
0.285431 0.698273
IMPLEMENTATION
order Filter implemented cascading structures shown Figure output (output each filter stage) computed direct implementation Equation Equation Since each stage similar algorithmically, implemented macro using Microchip's, Assembler/Linker PIC17C42. This Macro (labelled BIQUAD) called twice implementing order filter. output stage directly input second stage without scaling. Scaling required depending particular application. user modify code very easily without penalty speed. Also, saturation arithmetic used. Overflows avoided limiting input sequence amplitude. numbers assumed bits format decimal points, sign bit). Thus user must scale sign extend input sequence accordingly. example, input from 12-bit converter, user must sign extend 12-bit input one. BIQUAD macro generic macro used filters whether Pass, High Pass, Band Pass Band Stop. general purpose 16x16
above filter co-efficients stage) quantized format (i.e they multiplied 32768) saved program memory (starting label _coeff_lpass). constants both stages read into data memory using TLRD TABLRD instructions Initialization Routine (labelled initFilter). user read coefficients only stage time save some expense speed. sample order Pass Filter tested analyzing impulse response filter. impulse signal input filter. This simulated forcing input filter large quantity (say 7F00h) first input sample, zeros from sample onwards. output sequence filter's impulse response captured into PICMASTER's (Microchip's Universal In-Circuit Emulator) real-time trace buffer. This captured data from PICMASTER saved file analyzed. Analysis done using MathCadfor Windows® Analysis program from Burr-Brown (DSPLAYTM). Fourier Transform this impulse response filter should display filter's frequency response, this case being Pass type. plots impulse response frequency response shown Figure Figure Figure
MathCad trademark MathSoft, Inc. DSPLAY trademark Burr-Brown DFDP trademark Atlanta Signal Processing Inc. Windows registered trademark Microsoft Corporation.
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FIGURE IMPULSE RESPONSE CAPTURED FROM PICMASTER
Impulse Response 8000 -6000 -4000 -Magnitude 2000 -2000 -4000 -Time *0.5 (mSec)
PERFORMANCE
resource requirements filter implementations using PIC17C42 given Table These numbers used determine whether higher order filter executed real-time. same information used determine highest sampling rate possible.
FILTER APPLICATIONS
Digital filters find applications many areas especially those involving processing real world signals. some applications like systems automobile, digital filtering becomes must. this case elimination noise (especially glitches false readings sensors) very critical thus becomes requirement digital signal processing.
FIGURE
SPECTRUM COMPUTED FROM IMPULSE RESPONSE
FREQUENCY RESPONSE
TABLE RESOURCE REQUIREMENTS
Timing (Cycles)(1) Filter Stages*775
-500 -400 -Magnitude
Program Memory (locations)(1) Filter Stages*68 (File Registers) Filter Stages*16
-200 -100
Note above numbers include initialization routine.
FIGURE
MAGNITUDE SPECTRUM IMPULSE RESPONSE
Frequency Response
FREQUENCY/512 (kHz) Magnitude (dB)
Frequency/512 (kHz)
Digital filters also needed Process Control where notch filters pass filters desired because signals from sensors transmitted over long lines, especially very noisy environment. these cases, typically notch filter (centering used. cases eliminating background noise, band stop filter (e.g., used. sample code given this application note used design feedback control system's digital compensator. example, typical Motor's digital compensator (like dead-beat compensator) second order same filter structure that implemented this application note.
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TABLE RESOURCE REQUIREMENTS
Filter Order Cycles 1566 2341 3116 3891 Real Time (@16 MHz) 197.75 391.5 585.25 779.0 972.75 Maximum Sampling 5.05 2.55 1.28 Program Memory(1)
Note above numbers include initialization routine.
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Please check Microchip latest version source code. Microchip's Worldwide Address: www.microchip.com; Bulletin Board Support: MCHIPBBS using CompuServe® (CompuServe membership required).
APPENDIX IIR.LS0T
MPASM 01.40 Released IIR.ASM 1-16-1997 14:48:37 PAGE
OBJECT CODE VALUE 00001 00002 00003 00004 00005 00001 00002 00264 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00945 00021 00022 00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 00015 00016 00017 00018 00019 00020 00021 00022 00023 00024 00025 00026 00027 00028
LINE SOURCE TEXT
TITLE LIST
"Digital Filter Using PIC17C42" P=17C42, columns=120,WRAP,
#include <p17c42.inc> LIST ;P17C42.INC Standard Header File, Version 1.03 Microchip Technology, Inc. LIST #define #define #define #define true false TRUE FALSE
#define #define _INC _NO_INC _LOW _HIGH
00000001 00000000 00000000 00000001
#include <17c42.mac> LIST #include <17c42iir.mac> LIST PIC17C42 MACRO ;Macro Bi-Quad Filter order Direct Form (Transposed) Type Filter co-efficients assumed equal difference equations each cascade section given Y(n) B0*D(n) B1*D(n-1) B2*D(n-2) D(n) X(n) A1*D(n-1) A2*D(n-2) where X(n) input sample, Y(n) output filter Filter Co-efficients above difference equations only section order Direct_Form Filter structure (IIR) NOTE possible design above structures such that co-efficients this case, Y(n) B0*[D(n) D(n-2)] B2*[D(n) D(n-2)] This way, multiplication avoided order filter implemented, output structure should input cascade section
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00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 00051 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 Timing (WORST CASE) 59+4*179 Cycles (194 Mhz) Program Memory locations sample filters designed that B0=B2 This saves multiplication B0_EQUALS_B2 TRUE Parameters BIQUAD Macro Filter Constants D(n), D(n-1), D(n-2), filter stage BIQUAD MACRO Compute Ax2*D(n-2) MOVFP16 Dn_2,AARG D(n-2) multiplier MOVFP16 Ax2,BARG multiplicand call DblMult (ACCd,ACCc) A2*D(n-2) product output section Save result Accumulator ADD32 DPX,ACC Compute A1*D(n-1) MOVFP16 Dn_1,AARG AARG D(n-2) multiplier MOVFP16 Ax1,BARG BARG multiplicand call DblMult (ACCd,ACCc) A1*D(n-1) Compute A1*D(n-1) A2*D(n-2) output previous section multiplications already done, simply perform previously obtained multiplication results ADD32 DPX,ACC A1*D(n-1) A2*D(n-2) (output section) save upper bits D(n) from accumulator left shift result adjust decimal point after Q15*Q15 multiplication rlcf ACC+B1,w rlcf ACC+B2,w movwf rlcf ACC+B3,w decimal adjust mult movwf Dn+B1 Compute [D(n) D(n-2)] B0_EQUALS_B2 ADD16ACC Dn_2,Dn,AARG AARG D(n-2) multiplier Bx0,BARG BARG multiplicand call DblMult (ACCd,ACCc) B2*[D(n)+D(n-2)] MOVPF32 DPX,ACC MOVFP16 #else MOVFP16 Bx0,BARG
00000001
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00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00023 00024 00025 00026 00027 00028 00029 00030 00031 00032 00033 00034 00035 00036 00037 00038 00039 00040 00041 00042 00043 00044 00045 00046 00047 00048 00049 00050 MOVFP16 call MOVPF32 MOVFP16 MOVFP16 DPX,ACC Bx2,BARG Dn_2,AARG call DblMult ADD32 DPX,ACC Dn,AARG DblMult B0*D(n)
B2*D(n-2)
#endif Shift down D(n-1) D(n-2) after D(n-2) usage longer required. This next iteration D(n-2) equal present D(n-1) movfp Dn_1,AARG+B0 movpf AARG+B0,Dn_2 Shift down D(n-1) movfp Dn_1+B1,AARG+B1 movpf AARG+B1,Dn_2+B1 AARG D(n-1) multiplier MOVFP16 Bx1,BARG BARG multiplicand
call DblMult (ACCd,ACCc) B1*D(n-1) Compute Output B1*D(n-1) B2*D(n-2) B0*D(n) B1*D(n-1) B0*[D(n) D(n-2)] Since multiplications already done, simply perform addition ADD32 DPX,ACC B1*D(n-1) B2*D(n-2) B0*D(n) Shift down D(n) D(n-1) that next iteration, D(n-1) present D(n) MOV16 Dn,Dn_1 Shift down D(n) D(n-1) ENDM LIST Second Order Direct Form Filter code given below, order Elliptic Lowpass Filter implemented. Other order filters implemented taking following example code basis. Program: IIR.ASM Revision Date: 1-13-97 Compatibility with MPASMWIN 1.40 specifications filter Sampling Frequency Filter Type Order Elliptic Lowpass Filter Band1 Band2 Lower Band Edge Upper Band Edge Nominal Gain Nominal Ripple 0.01 0.05 ;Maximum Ripple 0.00906 0.04601
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00051 00052 00053 00054 00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 Ripple 0.07830 -26.75 Filter Co-efficients above specifications filter computed follows Section -0.133331 0.167145 0.285431 0.462921 0.285431 Section 0.147827 0.765900 0.698273 0.499908 0.698273 Performance (WORST Case): Cycles Filter Stages*775 2*775+16 1566 Cycles uSec) each sample. Initialization time after reset counted Timing measured with B0_EQUALS_B2 TRUE (see BIQUAD Macro explanation) Program Memory FilterStages (BIQUAD Memory filter co-efficients) multiplier 16+2*(63+5)+274 locations (excluding initialization) usage file registers usage/each additional stage file regs This time less than (500 uSec), which means real time filtering possible CBLOCK BB0,BB1,BB2,BB3 ENDC CBLOCK 0x18 DPX,DPX1,DPX2,DPX3 arithmetic accumulator AARG,AARG1,BARG,BARG1 multiply arguments ENDC CBLOCK Dn1, Dn1_Hi Dn1_1, Dn1_1_Hi Dn1_2, Dn1_2_Hi Dn2, Dn2_Hi Dn2_1, Dn2_1_Hi
00000000
00000018 0000001C
00000020 00000022 00000024 00000026 00000028
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0000002A 00117 00118 00119 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 Dn2_2, Dn2_2_Hi ENDC CBLOCK A11, A12, B10, B11, B12, A21, A22, B20, B21, B22, ENDC CBLOCK bits input stream bits filter output A11_Hi A12_Hi B10_Hi B11_Hi B12_Hi A21_Hi A22_Hi B20_Hi B21_Hi B22_Hi
0000002C 0000002E 00000030 00000032 00000034 00000036 00000038 0000003A 0000003C 0000003E
Section Filter Co-efficients
Section Filter Co-efficients
00000040 00000042 00000044
ACC, ACC1, ACC2, ACC3 accumulator computations ENDC FltStage .set NumCoeff (5*FltStage) Co-eff stage LPASS .set TRUE HPASS .set FALSE BPASS .set FALSE select desired filter type BSTOP .set FALSE SIGNED TRUE This `TRUE' signed multiplication `FALSE' unsigned. Test Program Pass Filter start call movlw movwf movlw movwf initFilter 0x00 0x7f X+BB1 0x0000
00000002 0000000A 00000001 00000001 00000000 00000000 00000000 00000001
0000 0000 0000 0001 0002 0003 0004 0005 0005 0006 0007 0007 0008 0009 000A 000B
E00D B000 0140 B07F 0141
initial X(0) 0x7f00 test impulse response
E022 A442 AE43 0000 2940 2941 C005
000C C00C
000D
NextPoint call IIR_Filter tlwt _LOW,Y tracePoint tablwt _HIGH,0,Y+BB1 clrf X(n) clrf X+BB1, simulating Impulse goto NextPoint self goto self initFilter
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00183 00184 00185 00186 00187 00188 00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 00233 00234 00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 first read Filter Co-efficients from Prog. Data LPASS movlw movwf movlw movwf HPASS movlw movwf movlw movwf BPASS movlw movwf movlw movwf BSTOP movlw movwf movlw movwf
000D 000E 000F 0010
B0C1 010D B001 010E
_coeff_lpass TBLPTRL HIGH _coeff_lpass TBLPTRH
#endif
_coeff_hpass TBLPTRL HIGH _coeff_hpass TBLPTRH
#endif
_coeff_bpass TBLPTRL HIGH _coeff_bpass TBLPTRH
#endif
_coeff_bstop TBLPTRL HIGH _coeff_bstop TBLPTRH
#endif movlw movwf FSR0 ALUSTA,FS0 ALUSTA,FS1
0011 0012 0013 0014
B02C 0101 8404 8D04
0015 0016 0017 0017 0018 0019 001A
B00A A92C A000 AB00 170A C017
001B 001C 001D 001E 001E 001F 0020
B020 0101 B00C 2900 170A C01E
0021 0002
0022
auto increment Read Filter Co-efficients from Program Memory movlw NumCoeff tablrd _LOW,_INC,A11 garbage NextCoeff tlrd _LOW,INDF0 tablrd _HIGH,_INC,INDF0 decfsz WREG, goto NextCoeff Initialize "Dn"s zero movlw movwf FSR0 movlw 6*FltStage NextClr clrf INDF0, decfsz WREG, goto NextClr return Cascade Section IIR_Filter Compute D(n) X(n) A1*D(n-1) A2*D(n-2) Since filter constants computated format, X(n) must multiplied 2**15 then added other terms.
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0022 0023 0024 0025 0026 0027 0028 0029 002A 002B 8804 1941 1940 290A 190A 0145 6A40 0146 6A41 0147 00249 00250 00251 00252 00253 00254 00255 00256 00257 00258 00259 00260 00261 00262 00263 00264 Move Input accumulator after proper scaling ALUSTA,C rrcf X+BB1, rrcf clrf WREG, Scale input rrcf WREG, movwf ACC+BB1 movfp X,WREG movwf ACC+BB2 movfp X+BB1,WREG movwf ACC+BB3 scaled input X*(2**15) Biquad filter section BIQUAD Compute Ax2*D(n-2) MOVFP16 Dn1_2,AARG MOVFP MOVFP
D(n-2) multiplier
002C 7C24 002D 7D25
Dn1_2+B0,AARG+B0 move A(B0) B(B0) Dn1_2+B1,AARG+B1 move A(B1) B(B1) multiplicand move A(B0) B(B0) move A(B1) B(B1)
MOVFP16 A12,BARG MOVFP MOVFP A12+B0,BARG+B0 A12+B1,BARG+B1
002E 7E2E 002F 7F2F 0030 E0AF
call DblMult (ACCd,ACCc) A2*D(n-2) product output section Save result Accumulator ADD32 DPX,ACC MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC DPX+B0,WREG ACC+B0, DPX+B1,WREG ACC+B1, DPX+B2,WREG ACC+B2, DPX+B3,WREG ACC+B3, lowest byte lowest byte byte byte byte byte byte byte into save b(B0) into save b(B1) into save b(B2) into save b(B3)
0031 0032 0033 0034 0035 0036 0037 0038
6A18 0F44 6A19 1145 6A1A 1146 6A1B 1147
Compute A1*D(n-1) MOVFP16 MOVFP MOVFP MOVFP16 MOVFP MOVFP Dn1_1,AARG Dn1_1+B0,AARG+B0 Dn1_1+B1,AARG+B1 A11,BARG A11+B0,BARG+B0 A11+B1,BARG+B1 AARG D(n-2) multiplier move A(B0) B(B0) move A(B1) B(B1) BARG multiplicand move A(B0) B(B0) move A(B1) B(B1)
0039 7C22 003A 7D23
003B 7E2C 003C 7F2D 003D E0AF
call DblMult (ACCd,ACCc) A1*D(n-1) Compute A1*D(n-1) A2*D(n-2) output previous section multiplications already done, simply perform previously obtained multiplication results ADD32 DPX,ACC A1*D(n-1) A2*D(n-2)
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003E 003F 0040 0041 0042 0043 0044 0045 6A18 0F44 6A19 1145 6A1A 1146 6A1B 1147 MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC DPX+B0,WREG ACC+B0, DPX+B1,WREG ACC+B1, DPX+B2,WREG ACC+B2, DPX+B3,WREG ACC+B3, (output section) lowest byte into lowest byte save b(B0) byte into byte save b(B1) byte into byte save b(B2) byte into byte save b(B3)
0046 0047 0048 0049 004A
1A45 1A46 0120 1A47 0121
save upper bits D(n) from accumulator left shift result adjust decimal point after Q15*Q15 multiplication rlcf ACC+B1,w rlcf ACC+B2,w movwf rlcf ACC+B3,w decimal adjust mult movwf Dn1+B1 Compute [D(n) D(n-2)] B0_EQUALS_B2 ADD16ACC movfp addwf movwf movfp addwfc movwf MOVFP16 MOVFP MOVFP Dn1_2,Dn1,AARG Dn1_2+B0,WREG Dn1+B0,w AARG+B0 Dn1_2+B1,WREG Dn1+B1,w AARG+B1 B10,BARG B10+B0,BARG+B0 B10+B1,BARG+B1 BARG multiplicand move A(B0) B(B0) move A(B1) B(B1) (ACCd,ACCc) B2*[D(n)+D(n-2)] AARG D(n-2) multiplier
004B 004C 004D 004E 004F 0050
6A24 0E20 011C 6A25 1021 011D
0051 7E30 0052 7F31 0053 E0AF
call DblMult MOVPF32 DPX,ACC MOVPF MOVPF MOVPF MOVPF DPX+B0,ACC+B0 DPX+B1,ACC+B1 DPX+B2,ACC+B2 DPX+B3,ACC+B3
0054 0055 0056 0057
5844 5945 5A46 5B47
move move move move
A(B0) A(B1) A(B2) A(B3)
B(B0) B(B1) B(B2) B(B3)
#else MOVFP16 MOVFP16 call MOVPF32 MOVFP16 MOVFP16 call ADD32 B10,BARG Dn1,AARG DblMult DPX,ACC Bx2,BARG Dn1_2,AARG DblMult DPX,ACC
B0*D(n)
B2*D(n-2)
#endif Shift down D(n-1) D(n-2) after D(n-2) usage longer required. This next iteration D(n-2) equal present D(n-1)
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0058 0059 005A 005B 7C22 5C24 7D23 5D25 00265 00266 00267 00268 movfp movpf movfp movpf MOVFP16 MOVFP MOVFP Dn1_1,AARG+B0 AARG+B0,Dn1_2 Dn1_1+B1,AARG+B1 AARG+B1,Dn1_2+B1 B11,BARG B11+B0,BARG+B0 B11+B1,BARG+B1 Shift down D(n-1) AARG D(n-1) multiplier BARG multiplicand move A(B0) B(B0) move A(B1) B(B1)
005C 7E32 005D 7F33
005E E0AF
call DblMult (ACCd,ACCc) B1*D(n-1) Compute Output B1*D(n-1) B2*D(n-2) B0*D(n) B1*D(n-1) B0*[D(n) D(n-2)] Since multiplications already done, simply perform addition ADD32 DPX,ACC B1*D(n-1) B2*D(n-2) B0*D(n) MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC DPX+B0,WREG ACC+B0, DPX+B1,WR ACC+B1, DPX+B2,WREG ACC+B2, DPX+B3,WREG ACC+B3, lowest byte lowest byte byte byte byte byte byte byte into save b(B0) into save b(B1) into save b(B2) into save b(B3)
005F 0060 0061 0062 0063 0064 0065 0066
6A18 0F44 6A19 1145 6A1A 1146 6A1B 1147
Shift down D(n) D(n-1) that next iteration, D(n-1) present D(n) MOV16 Dn1,Dn1_1 Shift down D(n) D(n-1) MOVFP MOVWF MOVFP MOVWF Dn1+B0,WREG Dn1_1+B0 Dn1+B1,WREG Dn1_1+B1 byte into move b(B0) byte into move b(B1)
0067 0068 0069 006A
6A20 0122 6A21 0123
Biquad filter section BIQUAD Compute Ax2*D(n-2) MOVFP16 Dn2_2,AARG MOVFP MOVFP MOVFP16 MOVFP MOVFP Dn2_2+B0,AARG+B0 Dn2_2+B1,AARG+B1 A22,BARG A22+B0,BARG+B0 A22+B1,BARG+B1
D(n-2) multiplier move A(B0) B(B0) move A(B1) B(B1) multiplicand move A(B0) B(B0) move A(B1) B(B1)
006B 7C2A 006C 7D2B
006D 7E38 006E 7F39 006F E0AF
call DblMult (ACCd,ACCc) A2*D(n-2) product output section Save result Accumulator ADD32 DPX,ACC
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0070 0071 0072 0073 0074 0075 0076 0077 6A18 0F44 6A19 1145 6A1A 1146 6A1B 1147 MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC DPX+B0,WREG ACC+B0, DPX+B1,WREG ACC+B1, DPX+B2,WREG ACC+B2, DPX+B3,WREG ACC+B3, lowest byte lowest byte byte byte byte byte byte byte into save b(B0) into save b(B1) into save b(B2) into save b(B3)
Compute A1*D(n-1) MOVFP16 MOVFP MOVFP MOVFP16 MOVFP MOVFP Dn2_1,AARG Dn2_1+B0,AARG+B0 Dn2_1+B1,AARG+B1 A21,BARG A21+B0,BARG+B0 A21+B1,BARG+B1 AARG D(n-2) multiplier move A(B0) B(B0) move A(B1) B(B1) BARG multiplicand move A(B0) B(B0) move A(B1) B(B1)
0078 7C28 0079 7D29
007A 7E36 007B 7F37 007C E0AF
007D 007E 007F 0080 0081 0082 0083 0084
6A18 0F44 6A19 1145 6A1A 1146 6A1B 1147
call DblMult (ACCd,ACCc) A1*D(n-1) Compute A1*D(n-1) A2*D(n-2) output previous section multiplications already done, simply perform previously obtained multiplication results ADD32 DPX,ACC A1*D(n-1) A2*D(n-2) (output section) MOVFP DPX+B0,WREG lowest byte into ADDWF ACC+B0, lowest byte save b(B0) MOVFP DPX+B1,WREG byte into ADDWFC ACC+B1, byte save b(B1) MOVFP DPX+B2,WREG byte into ADDWFC ACC+B2, byte save b(B2) MOVFP DPX+B3,WREG byte into ADDWFC ACC+B3, byte save b(B3) save upper bits D(n) from accumulator left shift result adjust decimal point after Q15*Q15 multiplication rlcf ACC+B1,w rlcf ACC+B2,w movwf rlcf ACC+B3,w decimal adjust mult movwf Dn2+B1 Compute [D(n) D(n-2)] B0_EQUALS_B2 ADD16ACC Dn2_2,Dn2,AARG movfp addwf movwf movfp addwfc movwf Dn2_2+B0,WREG Dn2+B0,w AARG+B0 Dn2_2+B1,WREG Dn2+B1,w AARG+B1 BARG multiplicand AARG D(n-2) multiplier
0085 0086 0087 0088 0089
1A45 1A46 0126 1A47 0127
008A 008B 008C 008D 008E 008F
6A2A 0E26 011C 6A2B 1027 011D
MOVFP16 B20,BARG
DS00540C-page
1997 Microchip Technology Inc.
AN540
0090 7E3A 0091 7F3B 0092 E0AF MOVFP MOVFP B20+B0,BARG+B0 B20+B1,BARG+B1 move A(B0) B(B0) move A(B1) B(B1) (ACCd,ACCc) B2*[D(n)+D(n-2)]
call DblMult MOVPF32 DPX,ACC MOVPF MOVPF MOVPF MOVPF DPX+B0,ACC+B0 DPX+B1,ACC+B1 DPX+B2,ACC+B2 DPX+B3,ACC+B3
0093 0094 0095 0096
5844 5945 5A46 5B47
move move move move
A(B0) A(B1) A(B2) A(B3)
B(B0) B(B1) B(B2) B(B3)
#else MOVFP16 MOVFP16 call MOVPF32 MOVFP16 MOVFP16 call ADD32 B20,BARG Dn2,AARG DblMult DPX,ACC Bx2,BARG Dn2_2,AARG DblMult DPX,ACC
B0*D(n)
B2*D(n-2)
0097 0098 0099 009A
7C28 5C2A 7D29 5D2B
#endif Shift down D(n-1) D(n-2) after D(n-2) usage longer required. This next iteration D(n-2) equal present D(n-1) movfp Dn2_1,AARG+B0 movpf AARG+B0,Dn2_2 Shift down D(n-1) movfp Dn2_1+B1,AARG+B1 movpf AARG+B1,Dn2_2+B1 AARG D(n-1) multiplier MOVFP16 MOVFP MOVFP B21,BARG B21+B0,BARG+B0 B21+B1,BARG+B1 BARG multiplicand move A(B0) B(B0) move A(B1) B(B1)
009B 7E3C 009C 7F3D
009D E0AF
call DblMult (ACCd,ACCc) B1*D(n-1) Compute Output B1*D(n-1) B2*D(n-2) B0*D(n) B1*D(n-1) B0*[D(n) D(n-2)] Since multiplications already done, simply perform addition ADD32 DPX,ACC B1*D(n-1) B2*D(n-2) B0*D(n) MOVFP ADDWF MOVFP ADDWFC MOVFP ADDWFC MOVFP ADDWFC DPX+B0,WREG ACC+B0, DPX+B1,WREG ACC+B1, DPX+B2,WREG ACC+B2, DPX+B3,WREG ACC+B3, lowest byte lowest byte byte byte byte byte byte byte into save b(B0) into save b(B1) into save b(B2) into save b(B3)
009E 009F 00A0 00A1 00A2 00A3 00A4 00A5
6A18 0F44 6A19 1145 6A1A 1146 6A1B 1147
Shift down D(n) D(n-1) that next iteration, D(n-1) present D(n) MOV16 Dn2,Dn2_1 Shift down D(n) D(n-1) MOVFP MOVWF Dn2+B0,WREG Dn2_1+B0 byte into move b(B0)
00A6 6A26 00A7 0128
1997 Microchip Technology Inc.
DS00540C-page
AN540
00A8 6A27 00A9 0129 00269 00270 00271 00272 00273 00274 00275 00276 00277 00278 00279 00280 00281 00282 00178 00283 00284 00285 00286 00287 00288 00289 00290 00291 00292 00293 00294 00295 00296 00297 00298 00299 00300 00301 00302 00303 00304 00305 00306 00307 00308 00309 00310 00311 00312 00313 00314 00315 00316 00317 00318 00319 00320 00321 00322 00323 MOVFP MOVWF Dn2+B1,WREG Dn2_1+B1 byte into move b(B1)
filter output computed Save Upper Bits Accumulator into after adjusting decimal point MOV16 MOVFP MOVWF MOVFP MOVWF return Output Y(n) computed SIGNED/UNSIGNED Flag Before Including 17c42MPY.mac #include <17c42MPY.mac> LIST Pass Filter Co-efficients ELLIPTIC LOWPASS FILTER FILTER ORDER Sampling frequency 2.000 KiloHertz BAND BAND LOWER BAND EDGE .00000 .60000 UPPER BAND EDGE .50000 1.00000 NOMINAL GAIN 1.00000 .00000 NOMINAL RIPPLE .01000 .05000 MAXIMUM RIPPLE .00906 .04601 RIPPLE .07830 -26.74235 A(I,1) A(I,2) B(I,0) B(I,1) B(I,2) -.133331 .167145 .285431 .462921 .285431 .147827 .765900 .698273 .499908 .698273 _coeff_lpass data data data data data data data data data data co-efficients Cascade section -A11 -A12 co-efficients Cascade section -A21 -A22 ACC+BB2,Y ACC+BB2+B0,WREG Y+B0 ACC+BB2+B1,WREG Y+B1 byte into move b(B0) byte into move b(B1)
00AA 00AB 00AC 00AD
6A46 0142 6A47 0143
00AE 0002
01C1 01C1 01C2 01C3 01C4 01C5 01C6 01C7 01C8 01C9 01CA
1111 EA9B 2489 3B41 2489 ED14 9DF7 5961 3FFD 5961
4369 -5477 9353 15169 9353 -4844 -25097 22881 16381 22881
DS00540C-page
1997 Microchip Technology Inc.
AN540
00324 00325 00326 00327 00328 00329 00330 00331 00332 00333 00334 00335 00336 00337 00338 00339 00340 00341 00342 00343 00344 00345 00346 00347 00348 00349 00350 00351 00352 00353 00354 00355 00356 00357 00358 00359 00360 00361 00362 00363 00364 00365 00366 00367 00368 00369 00370 00371 00372 00373 00374 00375 00376 00377 00378 00379 00380 00381 00382 00383 00384 00385 00386 00387 00388 00389 High Pass Filter Co-efficients ELLIPTIC HIGHPASS FILTER FILTER ORDER Sampling frequency 2.000 KiloHertz BAND BAND LOWER BAND EDGE .00000 .50000 UPPER BAND EDGE .40000 1.00000 NOMINAL GAIN .00000 1.00000 NOMINAL RIPPLE .04000 .02000 MAXIMUM RIPPLE .03368 .01686 RIPPLE -29.45335 .14526 A(I,1) A(I,2) B(I,0) B(I,1) B(I,2) .276886 .195648 .253677 -.411407 .253677 -.094299 .780396 .678650 -.485840 .678650 _coeff_hpass co-efficients Cascade section data -9073 -A11 data -6411 -A12 data 8313 data -13481 data 8313 co-efficients Cascade section data 3090 -A21 data -25572 -A22 data 22238 data -15920 data 22238 Band Pass Filter Co-efficients ELLIPTIC BANDPASS FILTER FILTER ORDER Sampling frequency 2.000 KiloHertz BAND BAND BAND LOWER BAND EDGE .00000 .30000 .90000 UPPER BAND EDGE .10000 .70000 1.00000 NOMINAL GAIN .00000 1.00000 .00000 NOMINAL RIPPLE .05000 .05000 .05000 MAXIMUM RIPPLE .03644 .03867 .03641 RIPPLE -28.76779 .32956 -28.77647 A(I,1) A(I,2) B(I,0) B(I,1) B(I,2) -.936676 .550568 .444000 -.865173 .444000 .936707 .550568 .615540 1.199402 .615540
01CB 01CB 01CC 01CD 01CE 01CF 01D0 01D1 01D2 01D3 01D4
DC8F E6F5 2079 CB57 2079 0C12 9C1C 56DE C1D0 56DE
1997 Microchip Technology Inc.
DS00540C-page
AN540
01D5 01D5 01D6 01D7 01D8 01D9 01DA 01DB 01DC 01DD 01DE 3BF2 DCC4 1C6A C8A1 1C6A C40D DCC4 2765 4CC3 2765 00390 00391 00392 00393 00394 00395 00396 00397 00398 00399 00400 00401 00402 00403 00404 00405 00406 00407 00408 00409 00410 00411 00412 00413 00414 00415 00416 00417 00418 00419 00420 00421 00422 00423 00424 00425 00426 00427 00428 00429 00430 00431 00432 00433 00434 00435 00436 00437 00438 00439 00440 00441 00442 00443 00444 00445 00446 _coeff_bpass co-efficients Cascade section data 30693/2 -A11 data -18041/2 -A12 data 14549/2 data -28350/2 data 14549/2 co-efficients Cascade section data -30694/2 -A21 data -18041/2 -A22 data 20170/2 data 39302/2 data 20170/2 Band Stop Filter Co-efficients ELLIPTIC BANDSTOP FILTER FILTER ORDER Sampling frequency 2.000 KiloHertz BAND BAND BAND ;LOWER BAND EDGE .00000 .45000 .70000 ;UPPER BAND EDGE .30000 .55000 1.00000 ;NOMINAL GAIN 1.00000 .00000 1.00000 ;NOMINAL RIPPLE .05000 .05000 .05000 ;MAXIMUM RIPPLE .03516 .03241 .03517 ;RIPPLE .30015 -29.78523 .30027 A(I,1) A(I,2) B(I,0) B(I,1) B(I,2) .749420 .583282 .392685 .087936 .392685 -.749390 .583282 1.210022 -.270935 1.210022 _coeff_bstop co-efficients Cascade section data -24557/2 -A11 data -19113/2 -A12 data 12868/2 data 2881/2 data 12868/2 co-efficients Cascade section data 24556/2 -A21 data -19113/2 -A22 data 39650/2 data -8878/2 data 39650/2
01DF 01DF 01E0 01E1 01E2 01E3 01E4 01E5 01E6 01E7 01E8
D00A DAAC 1922 05A0 1922 2FF6 DAAC 4D71 EEA9 4D71
DS00540C-page
1997 Microchip Technology Inc.
AN540
MEMORY USAGE (`X' Used, 0000 0040 0080 00C0 0100 0140 0180 01C0 XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX Unused) XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXX-XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX -XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX
other memory blocks unused. Program Memory Words Used:
Errors Warnings Messages
reported, reported,
suppressed suppressed
1997 Microchip Technology Inc.
DS00540C-page
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rights reserved. 1997, Microchip Technology Incorporated, USA. 6/97
Information contained this publication regarding device applications like intended suggestion only superseded updates. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights. Microchip logo name registered trademarks Microchip Technology Inc. U.S.A. other countries. rights reserved. other trademarks mentioned herein property their respective companies.
DS00540C-page
1997 Microchip Technology Inc.
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