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Basic Serial EEPROM Operation
AN536
Basic Serial EEPROM Operation
BASIC SERIAL EEPROM OPERATION
Looking optimum non-volatile memory product your system that requires small footprint, byte level flexibility, power, highly cost effective? Serial EEPROM technology non-volatile memory technologies that emerged leading embedded control solution. Unfortunately, most system designers aware serial EEPROM benefits. Also, supporting documentation databooks most often adequate incomplete ambiguous information. result, system designer often selects non-volatile solution that does meet requirements, designer must face more complicated design-in with serial EEPROM. This article addresses issues that exist today designers considering serial EEPROM products: First, provide awareness application benefits. Secondly, provide primer operating principles instructions. These items often buried databook text adequately addressed. Also included common default conditions significantly reduce system designer's learning curve. common applications Serial EEPROMS shown below: Market Consumer Automotive Common Applications tuners, VCRs, players, cameras, radios, remote controls Airbags, anti-lock brakes, odometers, radios, keyless entry
Office Automation Printers, copiers, PCs, portable Telecom Cellular, cordless full feature phones, faxes, modems, pagers, satellite receivers code readers, point-of-sale terminals, smart cards, lock boxes, garage door openers, test measurement equipment
Industrial
typical functions that serial EEPROMs utilized are: Memory storage channel selectors analog controls (volume, tone, etc.) consumer electronics products Power down storage retrieval events such fault detection error diagnostics automotive products Electronic real time event maintenance logs such page counting office automation products. Also, configuration switch storage office automation products Last number redial storage speed dial number storage telecom products User in-circuit reprogrammable look tables such code readers, point-of-sale terminals, environmental controls other industrial products Other application examples include: Data storage from learn function remote control transmitter number storage security remote access electronic keys entry databases Reprogrammable calibration data test equipment analog interface products
CONTENTS
Serial EEPROM Applications Overview Primary Protocol Benefits 3-Wire Operation Primer 2-Wire Operation Primer Microchip 2-Wire Default Conditions Timing Diagram Attachments
SERIAL EEPROM APPLICATIONS
Serial EEPROMS ideal non-volatile cost effective memory solutions applications that require: Small footprint board space cellular phone applications BYTE level ERASE, WRITE, READ data tuner voltage current handheld battery applications keyless entry transmitter Multiple non-volatile functions same application such availability microcontroller lines
1993 Microchip Technology Inc.
DS00536C-page
Basic Serial EEPROM Operation
result density architectural evolution, Serial EEPROMs offer significant benefits some applications that previously could only utilize Parallel EEPROM products. diagram below illustrates footprint board space differences.
I/O'S (ma)
Serial Parallel Benefits
PARALLEL SERIAL
BOARD SPACE
uCont COST
Serial EEPROM requires only board space that Parallel EEPROM requires. Also, Serial EEPROM requires fewer lines from microcontroller which significantly reduces overall system cost board space. very fast READ speed only significant limitation Serial EEPROM decision between serial Parallel EEPROM. very interesting note that Serial EEPROM READ speed restricted more protocol than process technology. 2-wire (Inter-Integrated Circuit) products must large internal delays slow down part meet 100KHz protocol requirements, which will reviewed later. Characterization 3-wire Serial EEPROMs have indicated clock frequencies excess 6MHz.
OVERVIEW PRIMARY PROTOCOL BENEFITS
After designer decides serial EEPROM solution, next step select primary serial EEPROM protocols. Unfortunately, most system designers select type serial EEPROM 3wire) that they most familiar with, regardless benefits associated with each type.
DS00536C-page
1993 Microchip Technology Inc.
Basic Serial EEPROM Operation
benefits each protocol shown below: 3-Wire Serial EEPROMS Single supply 5.5V Very current consumption Reduced overall component cost Four pins (other than GND) required operation data widths Software WRITE Protection Edge triggered clocks signals 2MHz+ operation Ready/Busy data polling Security options available Less complex protocol 2-Wire Serial EEPROMS Single supply 5.5V Very current consumption Reduced overall component cost pins (other than GND) required operation data width Hardware WRITE Protection Level triggered clocks signals input glitch filters high noise immunity standard 100KHz 400KHz protocols with 1MHz option Page WRITE capability bytes Software hardware compatible from densities
wire product utilized applications that require bus, noise immunity, limited microcontroller availability, WRITE buffer multiple bytes stored with instruction. 3-wire product utilized applications that have limited protocol requirements, protocol, higher clock frequency requirements, data width applications. next sections describe basic operation Microchip's default conditions 3-wire 2-wire Serial EEPROMs allow system designer utilize benefits Serial EEPROMs.
Four pins required: (Chip Select) (Clock) (data (data out)
93XXXX parts hardware compatible these four pins. However, there compatibility issues other pins. Even though there hardware compatibility four pins, there differences from software standpoint. Subtle differences between each manufacturer's products, referred default conditions, prevent plug compatibility. These issues addressed later attached 3-Wire Timing Diagram. There industry standardized upgrade path density migration. Please review density upgrades Microchip's products case-by-case basis. Data available organizations. This selection determined either purchasing standard organization. Units will power-up EWDS (ERASE/WRITE Disable State). ERASE WRITE functions disabled until EWEN (ERASE/WRITE Enable) instruction performed. This prevent accidental data corruption. Auto-ERASE (logical "1") cycle performed during each WRITE Cycle. instructions shown attached instruction table. These instructions Microchip's 93LCXX family products. After instruction loaded, pins DON'T CARE state until next START bit.
3-WIRE OPERATION PRIMER
Many serial EEPROM data sheets written conventional memory data sheet format which emphasizes features part more than basic operating principles. operating principles unfortunately either vaguely embedded data sheet text included. Serial EEPROMs conventional memories Serial communication protocols involved. This section PRIMER data sheet familiarize system designer with basic principles 3-wire operation.
Basic Principles
Common device nomenclature 93XXXX. 93XX06 product. 93XX46 product. 93XX56 product. 93XX66 product.
1993 Microchip Technology Inc.
DS00536C-page
Basic Serial EEPROM Operation
following required each instruction (all input bits triggered positive clock edges): Start Opcode Address Data first Data-in high signal clocked after high. Bits identify instruction Refer Instruction table number bits required. Separate data-in data-out pins. However, these pins tied together true 3-wire operation. Please refer attached 3-wire READ timing diagram example.
ERASE (ERAL)
ERASE (ERAL) operation identified "00" opcode. ERAL instruction requires next bits clocked "10" address block instruction set. bits array will logic state command typically less than 10ms.
WRITE (WRAL)
WRITE (WRAL) operation also identified "00" opcode. WRAL requires next bits clocked "01" address block instruction set. data-in block will contain data SINGLE BYTE which repeated throughout entire array. example, 4F5A loaded data-in bits instruction set, 4F5A will written into every word array.
READ, WRITE, ERASE
attached 93LC66 timing diagrams illustrate concepts timing parameters each these operations. Please refer instruction tables parameters databook supplemental information.
EWEN EWDS
stated before, units will power ERASE/ WRITE DISABLE (EWDS) state prevent data corruption. future ERASE/WRITE operations must execute ERASE/WRITE ENABLE (EWEN) opcode until next power down detected until other EWDS opcodes executed. Please refer instruction table.
DS00536C-page
1993 Microchip Technology Inc.
Basic Serial EEPROM Operation
INSTRUCTION 93LC46: organization)
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS Opcode Address Data Data High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. Cycles
INSTRUCTION 93LC46: organization)
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS Opcode Address Data Data High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. Cycles
INSTRUCTION 93LC56: organization)
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS Opcode Address Data Data High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. Cycles
INSTRUCTION 93LC56: organization)
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS Opcode Address Data Data High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. Cycles
INSTRUCTION 93LC66: organization)
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS Opcode Address 11XXXXXX 10XXXXXX 01XXXXXX 00XXXXXX Data Data High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. Cycles
INSTRUCTION 93LC66: organization)
Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS Opcode Address 11XXXXXXX 10XXXXXXX 01XXXXXXX 00XXXXXXX Data Data High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. Cycles
1993 Microchip Technology Inc.
DS00536C-page
Basic Serial EEPROM Operation
2-WIRE OPERATION PRIMER
indicated 3-wire section, many serial EEPROM data sheets written conventional memory data sheet format which emphasizes features part more than basic operating principles. operating principles are, unfortunately, either vaguely embedded data sheet text included. This section PRIMER data sheet familiarize system designer with basic 2-wire serial EEPROM operation principles. Data recognized valid while high. data must observe data set-up hold specifications before after pulsed. There only data each pulse.
Control Byte Requirements
After START bit, each command begins with control byte sent master. This control byte following three primary functions before data and/or word address information loaded commands: Identify serial EEPROM slave addressed bus. Select specific serial EEPROM internal memory block bus. There serial EEPROMs bus) Select READ WRITE function next command transmitted master. diagram control byte (not including START bit) shown below:
Read rite
Basic Principles
common device nomenclature 24XXXX 85XXXX. Only pins essential operation. other pins supplementary: (Serial clock) (Serial Data) (Active High WRITE Protection) (Chip block select) SDA's open-drain requires pull-up resistor VDD. data organized Signals level triggered, edge triggered. Also, there filters inputs that will filter noise glitches <100ns wide. Auto-ERASE logical "1") cycle performed during each WRITE cycle. protocol utilizes master/slave bi-directional communication. device that sends data onto defined transmitter, device that receiving data receiver. Both master slave operate transmitter receiver. must controlled master device (most often microcontroller), which generates serial clock (SCL), controls direction, generates START STOP conditions. serial EEPROM slave. serial EEPROM will transmitter during READ operations when serial EEPROM must acknowledge data transmitted master. START STOP bits control activity. Operations must begin with START with STOP bit. START when transitions while HIGH while observing START set-up hold time specifications. STOP when transitions HIGH while HIGH while observing STOP set-up hold time specifications.
Slave Address
Chip Block Select
Control Bits Slave Address Bits (Must 1010 Memory)
Since there chip select pin, part selected four code control byte identify type product. four code established Philips protocol. 1010 code identifies slave device Serial EEPROM. Serial EEPROM will remain stand-by until 1010 code transmitted bus. Other Serial EEPROM slave devices will respond 1010 code bus.
Control Bits Chip Block Address Select Bits
next three control bits utilized chip selection internal block selection. standard protocol developed allow bits memory selected. This could accomplished accessing combination devices blocks within device, shown table following page:
DS00536C-page
1993 Microchip Technology Inc.
Basic Serial EEPROM Operation
bits Device 24LC01B, 24C01,85C72 24LC02B, 24C02,85C82 24LC04B, 24C04,85C92 24LC08B 24LC16B Density Internal Blocks Access Devices devices devices devices devices Only device
USED. This must tied VDD. recommended FLOAT these pins since there test modes accessed these pins high voltage signal.
These three bits this select must match hardware conditions USED) external pins internal block selects. With this selection scheme, devices from software compatible. example, four devices device could connected with same software. signals same products. product DON'T CARE. pins commonly used today industry with advent density evolution protocol limit bits.
MICROCHIP 2-WIRE DEFAULT CONDITIONS
stated before, data sheets provide adequate information basic operation. This lack information forces each reader databook make interpretations about operating conditions. These readers have included other semiconductor circuit designers, which unfortunately leads subtle compatibility problems. part designed operate default circuit designer's interpretation. This next section details Microchip's default conditions help system engineer minimize "Trial Error" prototyping increase awareness these default conditions. Also, improve corporate-wide compatibility, Microchip standardizing their circuits various product versions. Unless indicated otherwise, references default conditions 24LCXX products, 24CXXXX products.
Control Operation Code
this then operation will READ this then operation will WRITE After control byte acknowledge generated serial EEPROM, master will send appropriate word address data information.
Power
READ, WRITE, ERASE operations valid after ramped specified operating range.
Acknowledge Requirements
serial EEPROM must generate acknowledge after receiving each byte segment command. serial EEPROM will generate acknowledge automatically after master transmitted data segment. acknowledge master, serial EEPROM must pull line during entire HIGH period next clock generated master. During READ operations, master must acknowledge each data byte serial EEPROM will abort READ operation return stand-by mode waiting next START bit. attached 24LC16 timing diagrams illustrate READ WRITE operations.
PAGE WRITE Product Multiple BYTE WRITE Operation
24C01 24C02 have byte buffer. 24C04 byte buffer. 24LC01 24LC02 have byte page. 24LC04, 24LC08, 24LC16 have byte page. buffer will load bytes identically page loads bytes. difference modes that buffer will execute WRITE byte WRITE cycle sequence. page mode will execute bytes loaded WRITE cycle parallel.
1993 Microchip Technology Inc.
DS00536C-page
Basic Serial EEPROM Operation
There pages within blocks. byte page product, most significant bits word address point page address least significant bits point byte address within page. byte page product, most significant bits word address point page address least significant bits point byte address within page. number bytes loaded page from byte page size. example, three bytes loaded into byte page 24LC16. during loading fourth byte STOP received, page will WRITE three bytes. fourth byte will written since loading fourth byte complete. WRITE operation will executed until STOP transmitted. this point, serial EEPROM free from since actual WRITE function self-timed. Therefore, microcontroller interfacing serial EEPROM perform other functions associated communication with serial EEPROM during self-timed WRITE operations. Once part auto-ERASE mode, will complete ERASE/WRITE operation unless power removed. STOP START bits will ignored.
READ
Once Serial EEPROM RANDOM READ operation, placed into sequential READ operation. master issues acknowledge instead STOP bit, Serial EEPROM will READ next sequential bits. Serial will wait next command from master. sequential READ will continue long master issues acknowledge next clock cycle after last READ. READ will continue from block block will wrap around last array addressed. Again, this will continue until master issues STOP instead acknowledge bit. While reading zeroes master cannot pull high generate STOP bit, since serial EEPROM outputting low. recover from fault during READ, repeat clocks with data floating high. Therefore, acknowledge will occur part will reset return stand-by. START during operation will cease current operation begin next operation.
NOTE: versions released March 1993 will default ABORTING entire operation STOP received middle byte while loading page.
more than bytes loaded page byte page product, then 17th byte will override data loaded into original first byte (the page data will wrap around WITHIN page). Therefore, system designer must take precautions WRITE over page boundary during multiple byte WRITE operation. Bytes changed page will result data corruption array. example, bytes loaded 24LC16 page with least significant word address bits 0000 then STOP transmitted. Bytes array will have data changed page contents. Bytes through WILL change.
Author:
Steve Drehobl Memory Products Division
DS00536C-page
1993 Microchip Technology Inc.
WIRE EXAMPLE MICROCHIP 93LC66 READ CYCLE TIMING DIAGRAM
clock rising edge set-up time (Tcss)= 50ns
must Tcsl minimum spec (typically 100ns)
Data SET-UP clock rising edge time (Tdis) =100ns
1993 Microchip Technology Inc.
DONT CARE Data HOLD clock rising edge time (Tdih) =100ns STATE
START
STATE
DOUT
Dummy
Data will valid specification (typically 400ns), which relative each clocks rising edge
NOTE: THIS EXAMPLE OPERATION MICROCHIP'S 93LC66. INSTRUCTION LENGHTS VARY WITH ARRAY SIZE DATA WIDTHS
Basic Serial EEPROM Operation
microcontroller DOUT Serial EEPROM
Data must conform specified set-up hold times (Tdis Tdih) relative RISING clock edge. Each parameter typically 100ns.
Read operation identified op-code following start bit.
Next, address location bits loaded.
Then address contents clocked rising clock pulse edge. Data will become valid DOUT specified time (typically 400ns) relative rising edge clock DOUT pin. Note, first output will "dummy bit" with logical zero state. This event triggered clock rising edge last address duration clock pulse.
data from current address complete clock pulses continue, data from next address will READ automatically long remains high. This SEQUENTIAL READ FUNCTION. READ operations will continue while clock pulses continue until brought low.
possible DOUT together save requirements from microcontroller. Caution must exercised avoid contention high condition, because dummy bit. recommended that resistor between microcontroller port connected DOUT added isolation. This example shown below:
DS00536C-page
WIRE EXAMPLE MICROCHIP'S 93LC66 WRITE CYCLE TIMING DIAGRAM
DS00536C-page
must Tcsl minimum spec (typically 100ns)
clock rising edge set-up time (Tcss)= 50ns
Data SET-UP clock rising edge time (Tdis) =100ns
START Data HOLD clock rising edge time (Tdih) =100ns
READY
DOUT
STATE
STATE
BUSY
Basic Serial EEPROM Operation
NOTE: THIS EXAMPLE OPERATION MICROCHIP'S 93LC66. INSTRUCTION LENGTHS VARY WITH ARRAY SIZE DATA WIDTHS.
Busy typically
8-10
Data must conform specific set-up hold times (Tdis Tdih) relative clock edge. Each parameter typically 100ns.
WRITE operation identified code following start
Next, address location bits loaded pin.
Then, data bits written loaded pin.
must brought after last loaded. When brought Tcsl period, self timed WRITE executed. many bits loaded during ERASE WRITE instructions prior being brought instruction set, then extra bits will ignored. Only first bits loaded will executed.
DOUT pins only function during WRITE indicate status write with READY/BUSY function. While DOUT low, Serial EEPROM indicating that programming complete (the part BUSY). When DOUT high,the Serial EEPROM indicating that programming complete READY another instruction. Note must brought high after completing Tcsl time complete initiate READY/ BUSY function. Microchip's 93LCXX products polled multiple times same cycle.
1993 Microchip Technology Inc.
through clock pulse data instruction being LOADED. When goes low, instruction being EXECUTED. there enough bits loaded during ERASE WRITE instructions prior being brought low, then operation WILL EXECUTED Serial EEPROM will return stand-by.
WIRE EXAMPLE MICROCHIP 93LC66 ERASE CYCLE TIMING DIAGRAM
clock rising edge set-up time (Tcss)= 50ns
1993 Microchip Technology Inc.
must Tcsl minimum spec (typically 100ns)
Data SET-UP clock rising edge time (Tdis) =100ns
Data HOLD clock risingedge time (Tdih) =100ns
READY
START
DOUT
STATE
STATE
NOTE: This example operation MIcrochip's 93LC66. Instruction lengths vary with array size data widths.
BUSY
Basic Serial EEPROM Operation
8-11
Data must conform specified set-up hold times (Tdis Tdih) relative clock edge. Each parameter typically 100ns.
ERASE operation identified code that follows start
Next, address location bits loaded pin.
THERE DATA BITS LOAD. ADDRESS LOCATION LOADED WILL ERASE STATE "1".
must brought after last loaded. When brought Tcsl period, self timed ERASE executed. many bits loaded during ERASE WRITE instructions prior being brought instruction set, then extra bits will ignored. Only first bits loaded will executed.
DOUT pin's only function during ERASE indicate status write with READY/BUSY function. While DOUT islow, Serial EEPROM indicating that programming complete (the part BUSY). When high, Serial EEPROM indicating that programming complete READY another instruction. Note must brought high after completing Tcsl time complete initiate READY/ BUSY function.
DS00536C-page
through clock pulse address instruction being LOADED. When goes low, instruction being EXECUTED.If there enough bits loaded during ERASE WRITE instructions prior being brought low, then operation WILL EXECUTED serial EEPROM will return stand-by.
WIRE EXAMPLE MICROCHIP 24LC16 BYTE WRITE CYCLE TIMING DIAGRAM
DS00536C-page
STOP: BLOCK SELECT WRITE WORD ADDRESS DATA WRITTEN EXECUTE INSTRUCTION PLEASE REFER NOTES BELOW
SLAVE ADDRESS
START
Basic Serial EEPROM Operation
8-12
BYTE WRITE
NOTE POSITION START STOP BITS. TRANSITION DURING HIGH PULSE
SEQUENCE EACH WRITE COMMAND MASTER/SERIAL DIRECTION COMMUNICATION SHOWN BELOW
OTHER BITS TRANSMITTED MUST COMPLY WITH 100KHZ CLOCK PROTOCOL DATA TIME 250NS (TSU: DAT) DATA ESTABLISHED PRIOR RISING CLOCK EDGE HOLD TIME (THD:DAT) FALLING CLOCK EDGE.
BYTE WRITE
START FROM MASTER
STOP CLOCK PULSE WILL INITIATE SELF TIMED WRITE.
START FROM MASTER
CONTROL BYTE FROM MASTER
PAGE WRITE (EXAMPLE WITH BYTES)
CONTROL BYTE FROM MASTER ACKNOWLEDGE FROM START FROM MASTER SERIAL
ACKNOWLEDGE FROM SERIAL CONTROL BYTE FROM MASTER THECONTROL BYTE FROM MASTER WORD ADDRESS FROM MASTER
ACKNOWLEDGE FROM SERIAL WORD ADDRESS FROM MASTER ACKNOWLEDGE FROM THEWORD ADDRESS FROM MASTER SERIAL EXECUTE PAGE WRITE, CONTINUE LOAD BITS DATA CYCLE INSTEAD ISSUING STOP DATA BYTE FROM MASTER ACKNOWLEDGE FROM SERIAL ACKNOWLEDGE FROM SERIAL (FROM MASTER). REMEMBER CLOCK PULSE MUST ALLOCATED AFTER EACH SUBSEQUENT DATA FROM BITS SERIAL EEPROM ISSUE ACKNOWLEDGE SIGNAL (LOW). AFTER DESIRED NUMBER DATA BYTE FROM BYTE MASTER MASTER DATA BYTE FROM MASTER SERIAL ACKNOWLEDGE FROM BYTES HAVE BEEN LOADED, UPTO THEIR PAGE SIZE, MASTER MUST ISSUE STOP EXECUTE ACKNOWLEDGE SERIAL SERIAL ACKNOWLEDGE FROM FROM THEACKNOWLEDGE FROM SERIAL INSTRUCTION. DATA BYTE FROM MASTER STOP FROM MASTER MASTER DATA BYTE FROM MASTER STOP FROM ACKNOWLEDGE FROM SERIAL ACKNOWLEDGE FROM SERIAL
SERIAL EEPROM EXECUTE ADDITIONAL INSTRUCTIONS UNTIL CYCLE COMPLETE.
ACKNOWLEDGE FROM SERIALMASTER WORD ADDRESS FROM ACKNOWLEDGE FROM SERIAL
DATA BYTE FROM MASTER DATA BYTE FROM MASTER ACKNOWLEDGE FROM SERIAL
ACKNOWLEDGE FROM SERIAL
DATA BYTE FROM MASTER ACKNOWLEDGE FROM SERIAL
ACKNOWLEDGE FROM SERIAL STOP FROM MASTER STOP FROM MASTER DATA BYTE FROM MASTER
1993 Microchip Technology Inc.
WIRE EXAMPLE MICROCHIP 24LC16 READ CYCLE TIMING DIAGRAM
1993 Microchip Technology Inc.
STOP BLOCK SELECT WORD ADDRESS WRITE READ START SLAVE ADDRESS BLOCK SELECT DATA FROM SERIAL
SLAVE ADDRESS
START
NOTE FIRST CLOCK PULSES WRITE COMMAND IDENTICAL FIRST CLOCK PULSES READ COMMAND. EVEN CLOCK PULSE WRITE TRANSMIT SERIAL EEPROM DESIRED WORD ADDRESS.
READ (FROM RANDOM ADDRESS)
START FROM MASTER CONTROL BYTE FROM MASTER ACKNOWLEDGE FROM SERIAL WORD ADDRESS FROM MASTER ACKNOWLEDGE FROM SERIAL START FROM MASTER CONTROL BYTE FROM MASTER ACKNOWLEDGE FROM SERIAL DATA FROM SERIAL STOP FROM MASTER
READ (FROM CURRENT ADDRESS)
START FROM MASTER CONTROL BYTE FROM MASTER ACKNOWLEDGE FROM SERIAL DATA FROM SERIAL STOP FROM MASTER
Basic Serial EEPROM Operation
8-13
READ COMMAND START BITS. THIS RANDOM READ COMMAND. SHOWN PREVIOUS PAGES, READ DESIRED FROM CURRENT ADDRESS THEN FIRST CLOCK PULSES REQUIRED. THEREFORE, FIRST START CLOCK PULSE #20. THIS ONLY CURRENT ADDRESS READ COMMAND
ANOTHER USEFUL READ COMMAND SEQUENTIAL READ COMMAND. SEQUENTIAL READ COMMAND SAME RANDOM READ COMMAND; HOWEVER, MASTER MUST ISSUE ACKNOWLEDGE INSTEAD STOP SHOWN CLOCK PULSE #38. THIS SIGNALS SERIAL READ DATA FROM NEXT SEQUENTIAL ADDRESS. MASTER MUST CONTINUE ACKNOWLEDGE EACH BYTE RECEIVED UNTIL MASTER ISSUES STOP BIT.
NOTE POSITION START STOP BITS. TRANSITION DURING HIGH PULSE
READ (Sequential READ bytes)
START FROM MASTER CONTROL BYTE FROM MASTER ACKNOWLEDGE FROM SERIAL WORD ADDRESS FROM MASTER ACKNOWLEDGE FROM SERIAL START FROM MASTER CONTROL BYTE FROM MASTER ACKNOWLEDGE FROM SERIAL DATA FROM SERIAL ACKNOWLEDGE FROM MASTER DATA FROM SERIAL ACKNOWLEDGE FROM MASTER DATA FROM SERIAL STOP FROM MASTER
OTHER BITS TRANSMITTED MUST COMPLY WITH 100KHZ CLOCK PROTOCOL DATA TIME 250NS (TSU: DAT) DATA ESTABLISHED PRIOR RISING CLOCK EDGE HOLD TIME (THD:DAT) FALLING CLOCK EDGE.
DS00536C-page
Basic Serial EEPROM Operation
NOTES:
DS00536C-page
1993 Microchip Technology Inc.
8-14
WORLDWIDE SALES SERVICE
AMERICAS
Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, 85224-6199 Tel: 786-7200 Fax: 786-7277 Technical Support: 786-7627 Web: http://www.mchip.com/microhip Atlanta Microchip Technology Inc. Sugar Mill Road, Suite 200B Atlanta, 30350 Tel: 640-0034 Fax: 640-0307 Boston Microchip Technology Inc. Mount Royal Avenue Marlborough, 01752 Tel: 480-9990 Fax: 480-8575 Chicago Microchip Technology Inc. Pierce Road, Suite Itasca, 60143 Tel: 285-0071 Fax: 285-0075 Dallas Microchip Technology Inc. 14651 Dallas Parkway, Suite Dallas, 75240-8809 Tel: 991-7177 Fax: 991-8588 Dayton Microchip Technology Inc. Rockridge Road Englewood, 45322 Tel: 832-2543 Fax: 832-2841 Angeles Microchip Technology Inc. 18201 Karman, Suite Irvine, 92715 Tel: 263-1888 Fax: 263-1338 York Microchip Technology Inc. Motor Parkway, Suite Hauppauge, 11788 Tel: 273-5305 Fax: 273-5335
AMERICAS (continued)
Jose Microchip Technology Inc. 2107 North First Street, Suite Jose, 95131 Tel: 436-7950 Fax: 436-7955
EUROPE
United Kingdom Arizona Microchip Technology Ltd. Unit Courtyard Meadow Bank, Furlong Road Bourne End, Buckinghamshire Tel: 1628 851077 Fax: 1628 850259 France Arizona Microchip Technology SARL Buisson Fraises 91300 Massy France Tel: Fax: Germany Arizona Microchip Technology GmbH Gustav-Heinemann-Ring D-81739 Muenchen, Germany Tel: Fax: Italy Arizona Microchip Technology Centro Direzionale Colleoni Palazzo Pegaso Ingresso Paracelso 20041 Agrate Brianza (MI) Italy Tel: 9939 Fax: 9883
ASIA/PACIFIC
Hong Kong Microchip Technology Unit 3002-3004, Tower Metroplaza Hing Fong Road Kwai Fong, N.T. Hong Kong Tel: 1200 Fax: 3431 Korea Microchip Technology 168-1, Youngbo Bldg. Floor Samsung-Dong, Kangnam-Ku, Seoul, Korea Tel: 7200 Fax: 5934 Singapore Microchip Technology Middle Road #10-03 Prime Centre Singapore 188980 Tel: 8870 Fax: 8850 Taiwan Microchip Technology 10F-1C Tung North Road Taipei, Taiwan, Tel: 7175 Fax: 0139
JAPAN
Microchip Technology Intl. Inc. Benex 3-18-20, Shin Yokohama Kohoku-Ku, Yokohama Kanagawa Japan Tel: 6166 Fax: 6122 9/22/95
rights reserved. 1995, Microchip Technology Incorporated, USA.
Information contained this publication regarding device applications like intended through suggestion only superseded updates. representation warranty given liability assumed Microchip Technology Incorporated with respect accuracy such information, infringement patents other intellectual property rights arising from such otherwise. Microchip's products critical components life support systems authorized except with express written approval Microchip. licenses conveyed, implicitly otherwise, under intellectual property rights. Microchip logo name registered trademarks Microchip Technology Inc. rights reserved. other trademarks mentioned herein property their respective companies.
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