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EEPROM Emulation with ST10F2xx
External EEPROMs often used automotive applications store adaptative/evolutive data. other hand, Microcontroller used those systems, more more based embedded-Flash. trend continuously reduce number components forcing designers look Flash memory emulate EEPROM. This application note will explain differences between external EEPROMs embeddedFlash will give advises substitute external EEPROM emulated-EEPROM using on-chip Flash ST10F2xx devices. Although concept easy explain implement is", there some embedded aspects that have taken into account. this application note, handling embedded aspects secure content external EEPROM assumed known reader. this document focusing differences between EEPROMs embedded-Flash.
Introduction Embedded-Flash EEPROM Difference write access time Difference writing method Difference erase time Additional information Flash. EEPROM emulation concept Principle Program/erase cycle Read-While-Write Flash organization. Data-set status bits Active Flash bank selection Embedded application aspects Reading Flash while erasing programming
Suspend resume commands Minimum software copied into on-chip
220.127.116.11 18.104.22.168 22.214.171.124
Data programing erasing with ST10F2xx
Flash field reprogramming
Completion programming process Completion erasing process Safety aspects
126.96.36.199 188.8.131.52 184.108.40.206 220.127.116.11
Field Reprogramming with ST10F2xx.
Field events Flash reliability List Events Suggested Handling Methods
Reset Supply variations. Temperature specification. ST10 Unlock
Summary REVISION HISTORY
Substituting external EEPROM with emulated EEPROM from embedded-Flash Microcontroller complex development. This application note assumes that readers already familiar with techniques used secure content evolutive information external EEPROM embedded applications. This application note organized parts: description differences between external EEPROMs embedded-Flash, general description EEPROM emulation concept, introduction embedded application aspects. Although this application note focused applicable ST10F269, ST10F280, ST10F276 (and derivatives: ST10F275, ST10F273, ST10F272, ST10F271), ST10F252 ST10F296, most content dependent microcontroller.
Before describing proposed concept EEPROM emulation, important remember main differences between embedded-Flash memory microcontroller serial external EEPROMs. Those differences generic microcontroller (i.e.: specific ST10F2xx variants). They summarized table below.
Table Differences between Embedded Flash EEPROM
Feature Write time EEPROM some random byte 10ms page: equivalent hundred word 10ms page) Emulated EEPROM from embeddedFlash some 16us word)
seconds 1.5s) once started, dependent: reset will stop write process even supply stays inside specification. parallel hundred very cycles word.
once started, dependent; needs only proper supply.
serial hundred random word 92us page 22.5us /byte
Difference write access time Flash shorter write access time, critical parameters stored faster emulated EEPROM than serial external EEPROM, thereby improving robustness system same safety concept kept. Difference writing method important differences between external EEPROM emulated EEPROM embedded applications writing method. Stand-alone external EEPROM: once started CPU, writing word cannot interrupted reset. Only supply failure will interrupt writing process; properly sizing decoupling capacitors secure complete writing process inside stand-alone EEPROM. Emulated EEPROM from embedded-Flash: once started CPU, writing interrupted power failure reset. This difference should analysed system designers understand possible impact(s) their applications define proper handling method. Difference erase time difference erase time other important difference between stand-alone EEPROMs emulated EEPROM with embedded-Flash. Unlike Flash, EEPROM does require block erase operation free-up space before write. This means that some form software management required store data Flash. Moreover, erase process block Flash takes seconds, power shut-down other spurious events that interrupt
AN2061 erase process (ex: reset) should considered when designing Flash management software. This means that design robust Flash management software necessary have deep understanding Flash erase process. Flash erase process split phases: phase1: write bits starting from initial content. Interrupt during this phase will result more memory cells with logic level; content after interrupt phase1 depends Flash initial content. phase2: write bits starting from configuration. longer time before this phase interrupted, higher number cells will return logic level. content after interrupt this phase does depend Flash initial content; content after phase2 interrupt, shall regarded totally random content. phase3: equalization. This phase necessary recover over-erased cells. Flash management software EEPROM emulation should guarantee that this phase successfully completed before programming this bank. consequence interrupt during phase2 that single approach should avoided flag completion erasing process (see more details Section `Data-set status bits' page consequence interrupt during phase1 and/or phase2 that recommended have fixed data inside emulated EEPROM that checksum tell which Flash bank keeps valid data. most important point ensure that Flash been completely erased (phase3 interrupted) before programming data inside bank. Note: design Flash software management easier programming bank always made just after erasing this bank (when erasing bank necessary). Additional information Flash Incremental programming: Flash controller will accept program word that already programmed word adding more bits. Programming completion: programming completion important guarantee data retention time; programming complete when Flash controller status indicates programming without showing error flag. programming interrupted (ex: supply fail, reset), cells word being programmed will partially programmed. This result unstable "0"s when reading this word.
EEPROM EMULATION CONCEPT
Principle Different concepts described literature. Each them rely partitioning bank Flash into several Data-sets using control bits (per Flash bank Data-set) compute which Flash bank which Data-set valid one. variable-length Datasets, linked data-list structures should considered. method described this document based fixed-length Data-sets Flash banks.
Figure Bank partitioning emulated EEPROM
ST10F2xx Flash bank-x
ST10F2xx Flash bank-y
Area Data-set storage
Data-set-2 Data-set-1 Data-set-0
Status bits Data-set-n
Area status storage (Data-set bits Flash bank bits)
switch between each bank (erase when using other)
Variable update frequency variable update frequency high requirements program erase cycle Flash Flash features (ex: Read-While-Write). Those features analysed details following pages. Program/erase cycle requirements program erase cycles computed dividing needed number erase cycles total number Data-sets Flash banks (example with Figure n+m). When this number still higher than Flash write/erase endurance characteristics, closer analysis needed understand when Data-sets updated: when Data-sets need updated during operation, proposed buffer save data before shutting-down microcontroller. when Data-sets updated only before power-down sequence, proposed increase size Flash bank bank (see additional information Chapter
AN2061 Read-While-Write Most currently available Flash technologies must complete program erase operation before code data read from another memory block. There common misconception that EEPROM emulation only done when Read-While-Write functionality implemented. Read-While-Write, when present, allows access other memory blocks during erasing programming; this means that program does need copied into during programing erasing. Read-While-Write does prevent have buffer access into emulated-EEPROM needed during programming. When Read-While-Write supported, program erase suspend command used temporarily read code. ST10F2xx variants support program erase suspend commands. Flash organization concept described above showing Flash bank split parts: Data-set storage: keep variable information, Status storage: keep status Flash bank Data-sets. Other organizations possible (ex: include Data-set status bits inside each Data-set) which users advantages their application. Data-set status bits status bits proposed each Data-set with combinations shown following table.
Table Status Data-set
Status value Data-set without data (virgin) Data-set with valid data (programmed) Data-set with invalid data (dirty) Reserved (invalid) Meaning
With those combinations, status bits will change from "11", combination after erase, through "01" till "00", configurations reached incremental programming. Reserved configuration should used user's software detect which Flash bank hold valid data. User's software should define rules handling Data-set status bits that possible situation application (ex: reset), software retrieve which bank active which Data-set valid information. when data have been successfully written into Data-set, status bits Data-sets must updated. specific sequence achieve these updates should defined. Active Flash bank selection detection active Flash bank after power-up should rely analysis information inside banks. support this analysis, specific status bits each Flash bank
AN2061 used specify when relevant data other Flash bank. following table showing example status bits that used this purpose.
Table Status Flash banks
Status value 01111111 00111111 00011111 00001111 00000111 00000011 current bank active erase other bank started completion erase other bank data programming other bank started data programming other bank completed other bank active Meaning
improve detection case partially erased bank explained Chapter proposed insert small number fixed data inside Data-sets that running checksum possible detect given Flash bank valid invalid data. Then, EEPROM emulation software should analyse content Flash banks detected contain valid data, order check consistency status bits. This algorithm application dependent possible combinations depend selected implementation different events that application withstand design features (ex: power-fail).
EMBEDDED APPLICATION ASPECTS
This chapter giving advises embedded applications where ST10 embedded-Flash memory only volatile memory available. Reading Flash while erasing programming Depending which ST10F2xx variant used, entire Flash visible when Flash bank erased programmed. When given ST10F2xx does support Read-While-Write, EEPROM emulation software should: disable interrupts: during erasing programming, possible have access ST10 interrupt vector table; copy into routines: before erasing programming, software routines shall copied from Flash into on-chip RAM; this should include least routines generate erasing programming routines waiting erasing programming; temporarily disable code protection: code protection activated, should temporary disabled before executing code copied into on-chip RAM. cope with application constraints, users obliged support communication during programming erasing. This requires that: more software copied into on-chip RAM, software loop polling Flash status register modified handle communication process, minimum communication handler (used during polling) using interrupts, program erase suspend command used. 4.1.1 Suspend resume commands stand-alone Flash memories, ST10F2xx embedded-Flash controller supports suspend resume commands; this allows suspend time erasing programming process resume later Once suspend command completed, ST10F2xx access software routines that needed (ex: communication driver) that were relocated into on-chip RAM. Note: total time which Flash available unchanged this gives possibility suspend process specific routines during Flash erasing programming (ex: communication protocol). 4.1.2 Minimum software copied into on-chip minimum software copied into on-chip functions issuing erasing programming commands ST10 embedded-Flash controller, functions polling Flash status register detecting completion command error detection (see detailed specification), watchdog refresh activated).
AN2061 Data programing erasing with ST10F2xx Flash programing erasing field, requires able deal safely with possible events that occur application. This analysis application dependent carefully conducted user. This section assumes that users have experience with generic aspects field reprogramming; this section will focus only ST10 specific events. 4.2.1 Flash field reprogramming This paragraph giving advises field reprogramming data. Those advice specific ST10; they generic embedded application that reprograms itself Dataset. main points control during Flash programing erasing are: completion programing erasing process itself, events that interrupt reprogramming process. 18.104.22.168 Completion programming process programming process completed when last word programmed been programmed correctly (i.e.: status returned Flash OK). Usually, last word programmed update status word status bits) Data-set. reason, programming process interrupted, next restart, value read either erroneous good with limited retention time. This should influence users coding status bits supply failures detected (early warning) prevented (CPU controlled voltage regulator). here difficult specific choices will depend application requirements constraints. 22.214.171.124 Completion erasing process explained Section 2.3, completion erasing process before programming bank very important. Single information record successful erase process should avoided. Whenever possible: erase necessary because Flash bank full) should done just before Flash programming Flash programming should start only after successful completion erasing process. erase process take seconds, this require software controlled voltage regulators allow erase Flash after main system stopped (ex: ignition removed). 126.96.36.199 Safety aspects Depending safety constraints, usage bank considered: instead using banks alternatively, banks used alternatively; event failure (hardware nonrecoverable software error) inside bank, there still banks available. Such technique already used non-automotive applications EEPROM emulation using stand-alone Flash memories.
AN2061 Field Reprogramming with ST10F2xx Flash programming/reprogramming field, requires able deal safely with possible events that occur application. This analysis application dependent carefully conducted user. This section assumes that users have experience with generic aspects field reprogramming will focus only ST10F2xx specific events. 4.3.1 Field events Flash reliability User's applications must meet ST's recommendations Flash programming erasing. Failure could result lower data retention and/or altered Flash reliability. conditions leading altered data retention altered reliability depend command issued Flash event that occurred during this command (supply range, reset). From FMEA's perspective, customers should consider that when advice implemented, Flash reliability altered. When advice implemented provided field specific events within recommendations (see hereafter), Flash will meet published specification. 4.3.2 List Events Suggested Handling Methods 188.8.131.52 Reset Reset events possible during field reprogramming, whatever possible causes reset (spurious reset, external hardware reset, reset power-shut down). Detection Method: Reset occur time there possibility prevent this. Suggested Handling Method: Restart Flash command that interrupted (i.e.: erasing programming); status bits Flash information recognize this event. 184.108.40.206 Supply variations ST10 supply must kept within limits published Data Sheet during erase programming command. Detection method: specific hardware should added monitor supply reset ST10F2xx device when supply going functional specification. Suggested Handling Method: Restart whole Flash command (i.e.: erasing programming). Note: other parameter, ST10 supply should stay within maximum absolute ratings defined published Data Sheet. 220.127.116.11 Temperature specification Temperature during erasing, programming read fetch operations influencing reliability embedded-Flash. embedded-Flash must programmed erased only while junction temperature
AN2061 within limits published Data Sheet (see relevant product documentation). Failure could result degraded reliability (lower number erase cycles, lower data retention). 18.104.22.168 ST10 Unlock Flash programing erasing timings defined ST10 core, unlock effect Flash erasing programming. Usually, unlock will stop communication because change bit/baud rate. Detection Method: necessary from ST10 point view checked with application specific constraints). Suggested Handling Method: Application dependent.
This application note shown that careful identification events that happen field, definition Flash organization associated control bits, possible define method substitute external EEPROM with embedded-Flash microcontroller. Embedded aspects, handling different events that happen field needed safety level factors that should influence emulation concept described this application note.
Table Revision History
Date November 2004 Revision First Issue Description Changes
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