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AM29818
Top Searches for this datasheetAM29818 - AM29818 CY29FCT818T DIAGNOSTIC SCAN REGISTER WITH 3-STATE OUTPUTS Function, Pinout, Drive Compatible With FCT, Logic, AM29818 Reduced (Typically Version Equivalent Functions Edge-Rate Control Circuitry Significantly Improved Noise Characteristics Ioff Supports Partial-Power-Down Mode Operation Matched Rise Fall Times Fully Compatible With Input Output Logic Levels 8-Bit Pipeline Shadow Register Protection Exceeds JESD 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) CY29FCT818CT 64-mA Output Sink Current 32-mA Output Source Current CY29FCT818ATDMB 20-mA Output Sink Current 3-mA Output Source Current 3-State Outputs PACKAGE (TOP VIEW) DCLK MODE PCLK description CY29FCT818T contains high-speed 8-bit general-purpose data pipeline register high-speed 8-bit shadow register. general-purpose register used 8-bit-wide data path normal system application. shadow register designed applications such diagnostics sequential circuits, where desirable load known data specific location circuit read data that location. shadow register load data from output device, used right-shift register with bit-serial input (SDI) output (SDO), using DCLK. data register input multiplexed enable loading from shadow register from data input pins, using PCLK. Data loaded simultaneously from shadow register pipeline register, from pipeline register shadow register, provided setup-time hold-time requirements satisfied, with respect independent clock inputs. typical application, general-purpose register this device replaces 8-bit data register normal data path system. shadow register placed auxiliary bit-serial loop that used diagnostics. During diagnostic operation, data shifted serially into shadow register, then transferred general-purpose register load known value into data path. read contents that point data path, data transferred from data register into shadow register, then shifted serially auxiliary diagnostic loop make accessible diagnostics controller. This data then compared with expected value diagnose faulty operation sequential circuit. This device fully specified partial-power-down applications using Ioff. Ioff circuitry disables outputs, preventing damaging current backflow through device when powered down. Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. Copyright 2001, Texas Instruments Incorporated products compliant MIL-PRF-38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters. PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303 DALLAS, TEXAS 75265 CY29FCT818T DIAGNOSTIC SCAN REGISTER WITH 3-STATE OUTPUTS ORDERING INFORMATION -40°C 85°C 40°C QSOP SOIC PACKAGE Tube Tape reel Tube Tape reel SPEED (ns) ORDERABLE PART NUMBER CY29FCT818CTPC CY29FCT818CTQCT CY29FCT818CTSOC CY29FCT818CTSOCT TOP-SIDE MARKING CY29FCT818CTPC 29FCT818C 29FCT818C -55°C 125°C CDIP Tube CY29FCT818ATDMB Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. FUNCTION TABLE INPUTS MODE DCLK PCLK OUTPUT SHADOW REGISTER S0SDI SiSi-1 SiYi Hold PIPELINE REGISTER PiDi OPERATION Serial shift; D7-D0 output disabled Load pipeline register from data input Load shadow register from output Hold shadow register; D7-D0 output enabled PiSi Load pipeline register from shadow register High logic level, logic level, Don't care, Low-to-high transition, Transfer direction, applicable POST OFFICE 655303 DALLAS, TEXAS 75265 CY29FCT818T DIAGNOSTIC SCAN REGISTER WITH 3-STATE OUTPUTS logic diagram DCLK 8-Bit Shadow Register D0-D7 S0-S7 MODE PCLK 8-Bit Pipeline Register P0-P7 Y0-Y7 absolute maximum rating over operating free-air temperature range (unless otherwise noted) Supply voltage range ground potential -0.5 input voltage range -0.5 output voltage range -0.5 output current (maximum sink current/pin) Package thermal impedance, (see Note package 67°C/W (see Note package 61°C/W (see Note package 46°C/W Ambient temperature range with power applied, -65°C 135°C Storage temperature range, Tstg -65°C 150_C Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: package thermal impedance calculated accordance with JESD 51-3. package thermal impedance calculated accordance with JESD 51-7. POST OFFICE 655303 DALLAS, TEXAS 75265 CY29FCT818T DIAGNOSTIC SCAN REGISTER WITH 3-STATE OUTPUTS recommended operating conditions (see Note CY29FCT818ATDMB Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature CY29FCT818T 4.75 5.25 UNIT NOTE unused inputs device must held ensure proper device operation. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER 4.75 4.75 4.75 inputs 5.25 5.25 5.25 5.25 5.25 5.25 5.25 VOUT VOUT VOUT VOUT VOUT VOUT VOUT -120 -225 -120 -225 TEST CONDITIONS 0.55 0.55 CY29FCT818ATDMB -0.7 -1.2 -0.7 -1.2 CY29FCT818T UNIT Vhys IOZH IOZL Ioff Outputs open 5.25 Outputs open Typical values 25°C. more than output should shorted time. Duration short should exceed second. high-speed test apparatus and/or sample-and-hold techniques preferable minimize internal chip heating more accurately reflect operational values. Otherwise, prolonged shorting high output raise chip temperature well above normal cause invalid readings other parametric tests. sequence parameter tests, tests should performed last. TTL-driven input (VIN other inputs POST OFFICE 655303 DALLAS, TEXAS 75265 CY29FCT818T DIAGNOSTIC SCAN REGISTER WITH 3-STATE OUTPUTS electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PARAMETER TEST CONDITIONS Outputs open, input switching duty cycle, GND, 5.25 Outputs open, input switching duty cycle, GND, switching duty cycle Eight bits four controls switching duty cycle switching duty cycle Eight bits four controls switching duty cycle 17.8|| 30.8|| 17.8|| 30.8|| CY29FCT818ATDMB 0.25 0.25 CY29FCT818T UNIT open Outputs MHz, 5.25 open Outputs MHz, Typical values 25°C. This parameter derived total power-supply calculations. ICCD (f0/2 Where: Total supply current Power-supply current with CMOS input levels Power-supply current high input (VIN Duty cycle inputs high Number inputs ICCD Dynamic current caused input transition pair (HLH LHL) Clock frequency registered devices, otherwise zero Input signal frequency Number inputs changing currents milliamperes frequencies megahertz. Values these conditions examples formula. POST OFFICE 655303 DALLAS, TEXAS 75265 CY29FCT818T DIAGNOSTIC SCAN REGISTER WITH 3-STATE OUTPUTS timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure PARAMETER Pulse width PCLK high DCLK high before PCLK MODE before PCLK before DCLK Setup time MODE before DCLK before DCLK DCLK before PCLK PCLK before DCLK after PCLK MODE after PCLK Hold time after DCLK MODE after DCLK after DCLK CY29FCT818AT CY29FCT818CT UNIT switching characteristics over operating free-air temperature range (see Figure PARAMETER FROM (INPUT) PCLK MODE DCLK tPZL tPZH tPLZ tPHZ DCLK DCLK DCLK DCLK (OUTPUT) CY29FCT818AT CY29FCT818CT UNIT POST OFFICE 655303 DALLAS, TEXAS 75265 CY29FCT818T DIAGNOSTIC SCAN REGISTER WITH 3-STATE OUTPUTS PARAMETER MEASUREMENT INFORMATION From Output Under Test (see Note Test Point From Output Under Test (see Note Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open LOAD CIRCUIT TOTEM-POLE OUTPUTS LOAD CIRCUIT 3-STATE OUTPUTS Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES tPZL tPLH Output Waveform (see Note Output Waveform (see Note tPZH tPLZ tPHZ VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING Input VOLTAGE WAVEFORMS PULSE DURATION Input tPLH In-Phase Output tPHL Out-of-Phase Output tPHL Output Control VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. outputs measured time with input transition measurement. Figure Load Circuit Voltage Waveforms POST OFFICE 655303 DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 PACKAGING INFORMATION Orderable Device 5962-9682701Q3A 5962-9682701QLA CY29FCT818ATDMB CY29FCT818CTPC CY29FCT818CTPCE4 CY29FCT818CTQC CY29FCT818CTQCT CY29FCT818CTQCTE4 CY29FCT818CTQCTG4 CY29FCT818CTSOC CY29FCT818CTSOCE4 CY29FCT818CTSOCG4 CY29FCT818CTSOCT CY29FCT818CTSOCTE4 CY29FCT818CTSOCTG4 Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE PREVIEW ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type LCCC CDIP CDIP PDIP PDIP SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP SSOP/ QSOP SOIC SOIC SOIC SOIC SOIC SOIC Package Drawing Pins Package Plan Pb-Free (RoHS) Pb-Free (RoHS) Lead/Ball Finish Peak Temp POST-PLATE Type SNPB SNPB NIPDAU NIPDAU Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Type Type Type Type Call Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM 2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device. Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material) MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty Addendum-Page PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2007 accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis. Addendum-Page PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE REEL INFORMATION *All dimensions nominal Device Package Package Pins Type Drawing SSOP/ QSOP SOIC Reel Reel Diameter Width (mm) (mm) 330.0 330.0 16.4 24.4 (mm) (mm) (mm) (mm) 12.0 Pin1 (mm) Quadrant 16.0 24.0 CY29FCT818CTQCT CY29FCT818CTSOCT 2500 2000 10.75 15.7 Pack Materials-Page PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions nominal Device CY29FCT818CTQCT CY29FCT818CTSOCT Package Type SSOP/QSOP SOIC Package Drawing Pins 2500 2000 Length (mm) 346.0 346.0 Width (mm) 346.0 346.0 Height (mm) 33.0 41.0 Pack Materials-Page MECHANICAL DATA MLCC006B OCTOBER 1996 (S-CQCC-N**) TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER TERMINALS 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6) 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0) 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 0.045 (1,14) 0.035 (0,89) 4040140 10/96 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with metal lid. terminals gold plated. Falls within JEDEC MS-004 POST OFFICE 655303 DALLAS, TEXAS 75265 MECHANICAL DATA MPDI004 OCTOBER 1994 (R-PDIP-T**) PINS SHOWN PLASTIC DUAL-IN-LINE PACKAGE PINS 1.260 (32,04) 1.230 (31,24) 0.310 (7,87) 0.290 (7,37) 1.425 (36,20) 1.385 (35,18) 0.315 (8,00) 0.295 (7,49) 0.280 (7,11) 0.250 (6,35) 0.070 (1,78) 0.020 (0,51) 0.200 (5,08) Seating Plane 0.125 (3,18) 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) 0.010 (0,25) 4040050 04/95 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. POST OFFICE 655303 DALLAS, TEXAS 75265 MECHANICAL DATA MCER004A JANUARY 1995 REVISED JANUARY 1997 (R-GDIP-T**) LEADS SHOWN CERAMIC DUAL-IN-LINE PINS 1.280 (32,51) 1.240 (31,50) 0.300 (7,62) 0.245 (6,22) 1.460 (37,08) 1.440 (36,58) 0.291 (7,39) 0.285 (7,24) 0.070 (1,78) 0.030 (0,76) 0.100 (2,54) 0.015 (0,38) 0.320 (8,13) 0.290 (7,37) 0.200 (5,08) Seating Plane 0.130 (3,30) 0.023 (0,58) 0.015 (0,38) 0.100 (2,54) 0.014 (0,36) 0.008 (0,20) 0°-15° 4040110/C 08/96 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with ceramic using glass frit. Index point provided terminal identification. Falls within 1835 GDIP3-T24, GDIP4-T28, JEDEC MO-058 MO-058 POST OFFICE 655303 DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. 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