AL250 251
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AL250/251 Data Sheets
AL250
Features Applications General Description_ Pinout Diagrams Definition Description_ Functional Description
Digital Input/Output Data Formats Default Resolution Video Timing Border/Border Color Interface External Overlay Look-up Table (LUT) Programming Video Decoding
Electrical Characteristics
Recommended Operating Conditions Characteristics_
AL250/251 Register Definition
Register Description
Board Design Layout Considerations
Grounding Power Planes Power Supply Decoupling Digital Signal Clock Interconnect Analog Signal Interconnect_
10.0 Mechanical Drawing 11.0 Power Consumption
July 1999
AL250
AL250/251 Video Scan Doubler
Features
Convert interlaced signal (NTSC/PAL) into non-interlaced format monitors panels Highly integrated design with built-in DAC, SRAM, Built-in on-screen-display with programmable bitmap Interpolated scan doubling with tearing jagged edge artifacts Reduced interlace flicker Auto NTSC/PAL detect Digital video input square pixel, ITU-RBT (CCIR 601), user-defined format Analog/digital non-interlaced (VGA) signal output (Scan Doubled Deinterlaced) programming interface Power-down control Internal video lookup table (LUT) provide gamma correction special effects Overlay support title making complex on-screen display Self-initialization without software (Plug Play) volt support 16-bit digital RGB/YUV output (AL251 only)
Applications
TV-ready Multimedia Computer Monitor Video Scan Converter Progressive Scan Video Game Station Player Monitor
Video Memory
On-screen Display Video Lookup Tables
8-bit
Digital output (AL251)
Digital input
Video Formatter
Video Processor Scan Doubler
8-bit 8-bit
VCLK VCLKX2 VIDHS VIDVS HREF
Timing Control
RSET
Circuit
Mode Control
VREF COMP
OVLCTRL
SQUARE
GHREF
I2CADDR
RESET
INTYPE
AL250-01
July 1999
AL250
General Description
AL250/251 Video Scan Doubler (De-Interlacer) video conversion chip consumer video multimedia applications. converts interlaced NTSC PAL, ITU-RBT (CCIR 601) square pixel, YUV422 RGB565 digital signals into computer monitor signals direct connection computer monitor progressive scan using interface control, AL250/251 also programmed co-ordinate with various input resolutions, adjust screen positioning crop video noise from around original input video boundary. internal video lookup tables (LUT), which controlled interface, provide gamma correction calibrating color accuracy different types CRT's improving contrast level display more vivid pictures. built-in on-screen-display (OSD) provides programmable bitmap custom design icons on-screen control panels. Overlay function supported create titling on-screen-display menus video adjustment. AL251 provides features AL250. Additionally, digital output YUV422 RGB565 format, convert NTSC video panels. AverLogic proprietary digital signal processing technology creates highly stable video image without tearing effects jagged edges. output picture smoother less flicker than original input signal/picture.
July 1999
DO15 DO14 VDIN9 VDIN8 VDIN7 VDIN6 VDIN5
VDIN15
VDIN14
VDIN13
VDIN12
VDIN11
VDIN10
DO13 DO12 VDIN4 VDIN3 VDIN2 VDIN1 VDIN0 OVLCTRL1 OVLCTRL0 COMP AGND AGND VREF AVDD AVDD RSET
VDIN5 VDIN6 VDIN7 VDIN8 VDIN9 VDIN10 VDIN11 VDIN12 VDIN13 VDIN14 VDIN15
VIDHS
Pinout Diagrams
VCLK
VIDVS
VCLKX2
HREF
STD0
STD1
INTYPE
AL250
SQUARE
AL251
TESTIN
I2CADDR
/RESET
VIDHS VCLK VIDVS VCLKX2 HREF STD0 STD1 INTYPE SQUARE TESTIN I2CADDR /RESET
VDIN4 VDIN3 VDIN2 VDIN1 VDIN0 TESTY7 TESTY6 TESTY5 TESTY4 TESTY3 TESTY2 TESTY1 TESTY0 OVLCTRL1 OVLCTRL0
VREF COMP RSET AVDD AGND AVDD AGND GREF
GREF
AL251-01 pinout diagram
D010
D011
July 1999
AL250
AL250
Definition Description
Symbol Video Interface VDIN (CMOS) 64-61, 79-76, Digital video data input. Please refer input 55-52, 70-67, data format table details 51-47 62-58 Video clock input times video clock input Horizontal sync. input signal Vertical sync. input signal Horizontal reference input signal; this signal used indicate data digital bus. positive slope marks beginning active line. Type Description
VCLK VCLKX2 VIDHS VIDVS HREF
(CMOS) (CMOS) (CMOS) (CMOS) (CMOS)
Graphic Interface RSET VREF COMP (100 ohm) (1.235V) (0.1µF) (0.7V) (0.7V) (0.7V) (CMOS) Full Scale Current Adjust; pull-down Voltage Reference Input Compensation pin; 0.1µF pull-up analog output analog green output analog blue output
66-63, Digital YUV422 RGB565 output, selected 56-55, register 52-47 horizontal sync. output signal vertical sync. output signal horizontal reference output signal; used indicate blanking interval.
GHREF
(TTL) (TTL) (CMOS)
Reset Mode Select /RESET (CMOSd) (CMOSd) Reset input; active Video Input Standard select
NTSC input
July 1999
AL250
input Automatic standard detection Reserved testing
INTYPE (CMOSd) Input video data format select (16-bit) (16-bit) Square pixel/YUV (CCIR-601) input select (CCIR-601) Square pixel Test input pin, pulled high normal applications.
SQUARE
(CMOSd)
TESTIN
(CMOSd)
overlay Interface I2CADDR (CMOSsu) in/out (CMOSsu) (CMOSd) I2C-bus serial clock input -bus serial data input/output -bus slave address select write address read address write address read address Overlay control overlay Overlay color Overlay color Overlay color Overlay colors programmed software
OVLCTRL
(CMOSd)
Test pins TESTY (CMOS) 45-44, 41-36 Test output pins, factory test only
Power Ground Pins AVDD AGND power power power power Digital power pins. Connected power Digital ground pins Analog power pins. Connected power Analog ground pins
Notes: CMOSd CMOS with internal pull-down CMOSsu CMOS with Schmitt trigger internal pull-up
July 1999
AL250
Functional Description
Digital Input/Output Data Formats
digital video data formats that AL250/251 accepts YUV422 RGB565. definition mapping follows:
Video Data Signal VDIN15 VDIN14 VDIN13 VDIN12 VDIN11 VDIN10 VDIN9 VDIN8 VDIN7 VDIN6 VDIN5 VDIN4 VDIN3 VDIN2 VDIN1 VDIN0 Pixel clock INTYPE select Number AL250 AL251 VCLK INTYPE VCLK INTYPE 888565
select YUV422 RGB565 input format, program Board Configuration Register #02h, hardware "INTYPE" (AL250 pin#11, AL251 pin#14). AL251 provides digital output RGB565 YUV422 format. definition RGB565 mapping follows:
Video Data Signal
AL251
565888
July 1999
AL250
DO15 DO14 DO13 DO12 DO11 DO10 OutFormat select
select YUV422 RGB565 output format, program Control Register #08h<7>, i.e., OutFormat.
Default Resolution
resolution AL250/251 applications depends input video source, e.g., digital video decoder. typical resolution video decoder that AL250/251 supports without software, VCLK frequency provided decoder AL250/251 follows: Square Pixel NTSC Pixel Total Pixel Active VCLKx2 (MHz) VCLK (MHz) 24.545454 12.272727 29.5 14.75 CCIR NTSC 13.5 13.5
AL250/251 process active pixels line 1024 lines frame.
Video Timing
AL250/251 registers 20h~29h 2Bh~2Eh used control video timing. increments either pixels line lines frame. values (times relative input
July 1999
AL250
video source H-sync V-sync. These registers need programmed input video resolution different from default resolution supported. H-sync Start (registers 23h) define output horizontal sync period relative input H-sync leading edge. Horizontal Blank Start (registers 2Ch) define output H-sync blanking period. Horizontal Capture Start (registers 21h) define active pixels each line relative input video H-sync. These registers also used adjusting position output picture. Horizontal Total High (registers 29h) define total number pixels line. AL250/251 detect H-total automatically when input data typical resolution mentioned Default Resolution section. V-sync Start (registers 28h) define output V-sync period relative input V-sync start. Vertical Blank Start (registers 2Eh) define output V-sync blanking period. Vertical Capture Start (registers 26h) define active lines. total number lines frame (Vertical Total) detected AL250/251 automatically. take advantage auto detection AL250/251, Control register #08h (Softtime) user-defined input format used, then disable hardware default setting this write parameters corresponding registers define format. sample code AL250EVB provides disables hardware settings. following typical parameters well hardware default values) reference:
Mode H(Horizontal) total V(Vertical) total Start H-sync Start H-sync Start Square NTSC Square CCIR NTSC CCIR
July 1999
AL250
V-sync Start V-sync Reg.#20h Start Reg.#21h Reg.#22h H-sync Start Reg.#23h H-sync Reg.#24h HTOTAL10_3 Reg.#29h HTOTAL2_1 Reg.#25h Start Reg.#26h Reg.#27h V-sync Start Reg.#28h V-sync Reg.#2Bh H-blank Start Reg.#2Ch H-blank Reg.#2Dh V-blank Start Reg.#2Eh V-blank
output timing/format follows:
Square NTSC Resolution Pixel rate Interlace Video Sync Video level White level Black level total display F-porch B-porch width 640x480/616x452 24.5454 Analog-color 700mV/1V* 700mV/1V* 616* Square 768x576/736x544 29.5 Analog-color 700mV/1V* 700mV/1V* 736* CCIR NTSC 720x480/680x452 27.00 Analog-color 700mV/1V* 700mV/1V* 680* CCIR 720x576/680x544 27.00 Analog-color 700mV/1V* 700mV/1V* 680*
July 1999
AL250
border total display F-porch B-porch width border output output
452* ON(-)* ON(-)* 31.4685 59.94
544* ON(-)* ON(-)* 31.250
452* ON(-)* ON(-)* 31.4685 59.94
544* ON(-)* ON(-)* 31.250
Remark: Values with programmable (S/W) adjustable (H/W). horizontal video timing diagram follows.
Reference start
VIDHS
Output Total (24h, 29h)
GHSync
HSyncStart (22h) HSyncEnd (23h)
Blank Interval (AL250) HBlankEnd (2Ch) HBlankStart (2Bh) Left Border Right Border
GHREF
HDEStart (20h) HDEEnd (21h) Visible Picture
AL250-06 Horizontal timing diagram
Blank Interval (AL251)
July 1999
AL250
vertical video timing diagram follows.
Reference start
VIDVS
Output Total
GVSync
VSyncStart (27h) VSyncEnd (28h) Blank Interval (AL250) VBlankEnd (2Eh) VBlankStart (2Dh) Border VDEStart (25h) VDEEnd (26h) Blank Interval (AL251) Visible Picture Bottom Border
AL250-26 Vertical timing diagram
Details about registers found Register Definition section.
Border/Border Color
AL250/251 displays active pixels from video source resulting larger viewable area monitor than regular This especially advantageous digital video sources such DVD. However, some other video sources such VCR, unwanted untrimmed border appear. solve this, AL250/251 provides border control cropping video source. addition, cropped border filled with color (24-bit), which defined registers 0Ch~0Eh. Border/border color control applies AL250/251 analog output AL251 digital YUV/RGB output.
July 1999
AL250
Interface
AL250/251 provides ways implement screen display. internal program built-in on-screen display (OSD) bitmap, external control overlay pins showing screen display creating special effects onto each single pixel screen. AL250/251 provides registers implement internal bitmaps, which programmable 16x16 blocks (4x4 pixels each) 48x16 blocks (8x8 pixels each) respectively. program OSD, first LUT/OSD Control register turn bitmap bitmap Then program overlay colors through registers 15h~1Dh. Select index (0~255) through register 11h, then fill data through register 13h. bits each block used define overlay color (transparent) color Mesh color mesh background enabled programming register 2Fh. position bitmaps defined registers 1Eh, 1Fh, 2Fh. data index bitmap starts bitmap address 192, lay-out defined follows:
193<7:0> 194<7:0> 195<7:0>
192<7:0> 196<7:0> 200<7:0> 204<7:0>
252<7:0>
AL250-16 16x16 drawing 253<7:0> 254<7:0> 255<7:0>
Each pixel defined bits value ("00", "01", "10" "11"). Value "00" shows current input video data. Value "01", "10" "11" index overlay color (defined registers 1Dh). data index bitmap starts bitmap address lay-out defined follows:
July 1999
AL250
0<7:0> 4<7:0> 5<7:0>
1<7:0>
188<7:0>
189<7:0>
2<7:0>
190<7:0>
3<7:0>
191<7:0>
AL250-17 16x48 drawing
Similar bitmap each pixel defined bits value ("00", "01", "10" "11") with same definition. horizontal positions bitmaps defined registers respectively. vertical position both defined register 2Fh. external OSD, overlay feature needs used this will explained detail External Overlay section. control applies AL250/251 analog output AL251 digital output, AL251 digital output.
External Overlay
AL250/251 provides overlay pins (OVLCTRL1 OVLCTRL0) overlay control well some special effects. They pulled overlay, different overlay colors effects. colors chosen from colors (defined bits RGB) programming registers 15h~1Dh. effects logic AND, video source with three overlay colors programming register 14h. instance, negative film effect produced original video source with white color. More details found Register Definition section. Using external overlay AL250/251 caption display possible FPGA chip chosen displaying fonts decoded caption overlay pins compatible with AL250. not, then digital analog output still multiplexed with output AL250/251 show captions video display.
July 1999
AL250
External overlay applies AL250/251 analog output AL251 digital output, AL251 digital output.
Look-up Table (LUT)
Because different characteristics TV's monitors, direct color space conversion from show same color that human sees from original video contrast sufficient, accurate, resolve these issues AL250/251 gamma correction internal implemented. AL250/251 provides registers implementing LUT. directly converted colors sent that then sends mapped, corrected colors. program LUT, first choose color from register 10h, select index (0~255) through register 11h, then fill data (0~255) through register 13h. input 8-bit value then converted corrected value. user program based his/her experiments specific types monitors. typical input-output mapping curve usually somewhat like following:
Output Corrected Conversion Direct Conversion
Input
control applies AL251/251 analog output AL251 digital YUV/RGB output.
Programming
AL250/251 programming interface follows Philips standard. interface consists (clock) (data) signals. Data written read from AL250/251. both read write, each byte transferred first, data valid when pulled high.
July 1999
AL250
read/write command format follows: Write: <Write <Register Index> <Data> Read: <Write <Register Index> <Read <Data> <NA> Following details: <S>: Start signal High High High Start signal HIGH transition line when HIGH. <WRITE SA>: Write Slave Address: <READ SA>: Read Slave Address:
Data
Data
<REGISTER INDEX>: Value AL250/251 register index. <A>: Acknowledge stage acknowledge-related clock pulse generated host (master). host releases line (HIGH) AL250/251 (slave) pull down line during acknowledge clock pulse. <NA>: Acknowledge stage acknowledge-related clock pulse generated host (master). host releases line (HIGH) during acknowledge clock pulse, AL250/251 does pull down during this stage.
START
STOP
significant
AL250-15 drawing
<DATA>: Data byte write read from register index. read operation, host must release line (high) before first clock pulse transmitted AL250.
July 1999
AL250
<P>: Stop signal High High High Stop signal HIGH transition line when HIGH.
Suppose data written register using write slave address 58h, timing follows:
Start
Slave addr
Index
Data
Stop
AL250-24 Write timing
Suppose data read from register using read slave address 59h, timing follows:
Start
Slave addr
Index
Stop Read slave addr NAck Start Data read cycle Stop
AL250-25 Read timing
Video Decoding
video decoder (video input processor) needed with AL250/251 S-video composite video processing. Please note that AL250/251 works only with line-locked video decoders. There number video decoders available market; following selection chart. detailed information, please consult with decoder vendors their distributors directly. attached information believed accurate guaranteed.
July 1999
AL250
Decoder 7110 7111 7112 KS0127 VPC3211B
Vendor Philips Philips Philips Samsung
Line locked
NTSC/
RGB565
CCIR
Square Pixel
Closed Caption
Tele text
More information AL250/251 functionality found Register Definition section.
July 1999
AL250
Electrical Characteristics
Recommended Operating Conditions
Parameter TAMB Supply Voltage Ambient Operating Temperature +3.0 +5.5 Unit
Characteristics
Parameter Supply current Power consumption Hi-level input voltage Lo-level input voltage Hi-level output voltage Lo-level output voltage Output current, data Output current, GHREF Output current, GHS, tdCK Input leakage current Input capacitance Duty factor (tCK2H/tCK2) Input data set-up time Input data hold time Input rise time Input fall time VCLK VCLKx2 delay Digital output load cap. Output hold time Propagation delay 15pF 40pF 2.6V 0.6V -0.5V<VO<VDD+0.5 -0.5V<VO<VDD+0.5 -0.5V<VO<VDD+0.5 Test Conditions 0.7VDD -0.5 VDD+0.5 +0.8 Unit
July 1999
AL250
input output timing diagrams follows:
tCK2
VCLKX2
tCK2H tCK2L
VCLK
tdCK
VDIN
AL250-22 Input timing
tCK2
VCLKX2
tCK2H tCK2L
AL250-23 Output timing
July 1999
AL250
AL250/251 Register Definition
AL250/251 powered default state depending hardware mode-setting pins. Hardware configuration pins disabled setting SoftConfig (bit register 03h) one, configurations decided values register which software programmable. following summary AL250/251 control registers
Register COMPANYID REVISION BOARDCONFIG GENERAL FAMILY CONTROL STATUS BORDERRED BORDERGREEN BORDERBLUE LUTOSDCONTROL LUTOSDINDEX LUTOSDDATA OVERLAYCTRL OVL1RED OVL1GREEN OVL1BLUE OVL2RED OVL2GREEN OVL2BLUE OVL3RED OVL3GREEN OVL3BLUE OSD1HSTART OSD2HSTART HDESTART HDEEND Addr. Default Company Revision number Board configuration General control Chip family number Control register Status register Border color, channel Border color, green channel Border color, blue channel LUT/OSD control LUT/OSD index Reserved LUT/OSD data Overlay Effect Control Overlay color channel Overlay color green channel Overlay color blue channel Overlay color channel Overlay color green channel Overlay color blue channel Overlay color channel Overlay color green channel Overlay color blue channel Screen Display bitmap horizontal start Screen Display bitmap horizontal start Horizontal capture start Horizontal capture Function
July 1999
AL250
HSYNCSTART HSYNCEND HTOTAL(1) VDESTART VDEEND VSYNCSTART VSYNCEND HTOTAL(2) TEST HBORDERSTART HBORDEREND VBORDERSTART VBORDEREND OSDVSTART
Horizontal sync. start Horizontal sync. Horizontal total high, bit<10:3> Vertical capture start Vertical capture Vertical sync. start Vertical sync. Horizontal total low, bit<2:1> Test register(Reserved) Horizontal border color start Horizontal border color Vertical border color start Vertical border color Screen Display bitmap vertical start
Register Description
00h: Company [COMPANYID] CompanyId <7:0> Company (46h) Revision [REVISION] Revision <7:0>
01h:
Revision number
02h:
Board Configuration (R/W) [BOARDCONFIG] SoftConfig (Reg.#03h<4>) hardware configuration pins values read. SoftConfig (Reg.#03h<4>) software configuration register values read <1:0> Input video standard NTSC input input Automatic standard detection Reserved analog testing InType Input video format YUV422 RGB565 uvflip flip Square CCIR Square pixel General (R/W) [GENERAL]
03h:
July 1999
AL250
SoftConfig
<3:1> <7:5>
Reserved Reserved Enable configuration defined software configuration register 02h. Please refer Reg.#02h Reserved
04h:
Chip Family [FAMILY] Family <7:0> 25h, AL250/251 series Control (R/W) [CONTROL] Reserved InVsPol Input vsync polarity negative polarity positive polarity InHsPol Input hsync polarity negative polarity positive polarity Softtime Enable adjustment (register 29h) OutHsPol Output hsync polarity negative polarity positive polarity OutVsPol Output vsync polarity negative polarity positive polarity OutFormat Output video format 16-bit CCIR YUV422 Chip Status [STATUS] PalDetected VidVs HRef VidHs GVde OvlCtrl0 OvlCtrl1
08h:
09h:
detected External vsync External href External hsync Internal gvde signal External ovlctrl0 External ovlctrl1
Note: PalDetected always input mode PAL. PalDetected always then input mode NTSC. 0Ch: Border Color (R/W) [BORDERRED] BorderRed <7:0> Border color, component Border Color Green (R/W) [BORDERGREEN] BorderGreen <7:0> Border color, green component Border Color Blue (R/W) [BORDERBLUE]
0Dh:
0Eh:
July 1999
AL250
BorderBlue 10h:
<7:0>
Border color, blue component
LUT/OSD Control (R/W) 0x10 [LUTOSDCONTROL] LutOsdWSel <1:0> LUT/OSD table write select enable LUT-red table write enable LUT-green table write enable LUT-blue table write enable Screen Display) bitmap write RLutEn LUT-red enable bypass enable GLutEn LUT-green enable bypass green enable green BLutEn LUT-blue enable bypass blue enable blue BitMap1En Bitmap enable hide bitmap show bitmap BitMap2En Bitmap enable hide bitmap show bitmap LUT/OSD Index [LUTOSDINDEX] LutOsdIndex <7:0> LUT/OSD index LUT/OSD Data [LUTOSDDATA] LutOsdData <7:0> LUT/OSD data
11h:
13h:
program contents LUT/OSD, first Reg.#10h, bit<1:0>, then repeat writing index value Reg.#11h, data value Reg.#13h. 14h: Overlay Control (R/W) [OVERLAYCTRL] OvlLogic1 <1:0> Overlay logic operation between video overlay color when overlay "01" select overlay color video overlay color video overlay color video overlay color OvlLogic2 <3:2> Overlay logic operation between video overlay color when overlay "10" select overlay color video overlay color video overlay color video overlay color
July 1999
AL250
OvlLogic3
<5:4>
OvlLut
Overlay logic operation between video overlay color when overlay "11" select overlay color video overlay color video overlay color video overlay color video will through LUTs when ovlkey pins "11" OvlLogic3 settings ignored.
15h:
Overlay Color (R/W) [OVL1RED] Overlay1Red <7:0> Overlay color component Overlay Color Green (R/W) [OVL1GREEN] Overlay1Green <7:0> Overlay color green component Overlay Color Blue (R/W) [OVL1BLUE] Overlay1Blue <7:0> Overlay color blue component Default value overlay 255), blue Overlay Color (R/W) [OVL2RED] Overlay2Red <7:0> Overlay color component Overlay Color Green (R/W) [OVL2GREEN] Overlay2Green <7:0> Overlay color green component Overlay Color Blue (R/W) [OVL2BLUE] Overlay2Blue <7:0> Overlay color blue component Default value overlay (255, 255, yellow Overlay Color (R/W) [OVL3RED] Overlay3Red <7:0> Overlay color component Overlay Color Green (R/W) [OVL3GREEN] Overlay3Green <7:0> Overlay color green component Overlay Color Blue (R/W) [OVL3BLUE] Overlay3Blue <7:0> Overlay color blue component Default value overlay (255, On-Screen Display (OSD1) Horizontal Start (R/W) [OSD1HSTART] Osd1HStart <7:3> Screen Display bitmap horizontal start. (unit: pixels) On-Screen Display (OSD2) Horizontal Start (R/W) [OSD2HSTART] Osd2HStart <7:3> Screen Display bitmap horizontal start. (unit: pixels) Screen Display (OSD) Vertical Start (R/W) [OSDVSTART] OsdVstart <7:4> Screen Display bitmap vertical start. (unit: lines)
16h:
17h:
18h:
19h:
1Ah:
1Bh:
1Ch:
1Dh:
1Eh:
1Fh:
2Fh:
July 1999
AL250
Mesh color select gray mesh color mesh MeshEn Mesh background enable mesh Enable mesh background display correctly, make sure horizontal start does locate between horizontal sync start horizontal sync end, vertical start does locate between vertical sync start vertical sync end. Reg.#20h #29h define video capture control timing. 20h: Horizontal Capture Start (R/W) [HDESTART] HDEStart <7:0> Horizontal capture start. (unit: pixels) Horizontal Capture (R/W) [HDEEND] HDEEnd <7:0> Horizontal capture end. (unit: pixels) Horizontal Sync Start (R/W) [HSYNCSTART] HSyncStart <7:0> Horizontal sync start. (unit: pixels) Horizontal Sync (R/W) [HSYNCEND] HSyncEnd <7:0> Horizontal sync end. (unit: pixels) Horizontal Total High (R/W) [HTOTAL1] HTotal10_3 <7:0> horizontal total defined Reg.#29h<1:0> Vertical Capture Start (R/W) [VDESTART] VDEStart <7:0> Vertical capture start. (unit: lines) Vertical Capture (R/W) [VDEEND] VDEEnd <7:0> Vertical capture end. (unit: lines) Vertical Sync Start (R/W) [VSYNCSTART] VSyncStart <7:0> Vertical sync start. (unit: lines) Vertical Sync (R/W) [VSYNCEND] VSyncEnd <7:0> Vertical sync end. (unit: lines)
MeshColor
21h:
22h:
23h:
24h:
25h:
26h:
27h:
28h:
July 1999
AL250
29h:
Horizontal Total (R/W) [HTOTAL2] <7:2> Reserved HTotal2_1 <1:0> horizontal total, htotal Test (R/W) [TEST] testIn testOut testOvl <5:4>
2Ah:
<3:0> 2Bh:
Feed value from 0x15, 0x16, 0x17 registers input Feed value from 0x15, 0x16, 0x17 registers output hardware overlay overlay value overlay value overlay value Reserved
Horizontal Blank Start (R/W) [HBLANKSTART] HBlankStart <7:0> Horizontal blanking start. (unit: pixels) Horizontal Blank (R/W) [HBLANKEND] HBlankEnd <7:0> Horizontal blanking end. (unit: pixels) Vertical Blank Start (R/W) [VBLANKSTART] VBlankStart <7:0> Vertical blanking start. (unit: lines) Vertical Blank (R/W) [VBLANKEND] VBlankStart <7:0> Vertical blanking end. (unit: lines)
2Ch:
2Dh:
2Eh:
July 1999
AL250
Board Design Layout Considerations
AL250/251 contains both precision analog high-speed digital circuitry. Noise coupling from digital circuits analog circuits result poor video quality. layout should optimized lowest noise power ground planes shielding digital circuitry providing good decoupling. recommended place AL250/251 chip close output connector, video decoder close analog video input connectors applicable.
Grounding
Analog digital circuits separated within AL250/251 chip. minimize system noise prevent digital system noise from entering analog portion, common ground plane devices, including AL250/251 recommended. connections ground plane should have very short leads. ground plane should solid, cross-hatched.
Power Planes Power Supply Decoupling
analog portion AL250/251 associated analog circuitry should have their power plane, referred analog power plane (AVDD). analog power plane should connected digital power plane (DVDD) single point through resistance ferrite bead. digital power plane should provide power digital logic board, analog power plane should provide power AL250/251 analog power pins relevant analog circuitry. Power supply connection pins should individually decoupled. best results, 0.1µF ceramic chip capacitors. Lead lengths should minimized. power pins should connected bypass capacitors before being connected power planes. 22µF capacitors should also used between AL250/251 power planes ground planes control low-frequency power ripple.
Digital Signal Clock Interconnect
Digital signals AL250/251 should isolated much possible from analog outputs other analog circuitry. high frequency clock reference crystal should handled carefully. Jitter noise clock will degrade video performance. Keep clock paths decoder short possible reduce noise pickup.
Analog Signal Interconnect
AL250/251 should located closely output connectors minimize noise reflections. Keep critical analog traces short wide (20~30 mil) possible. Digital signals, especially pixel clocks data signals should overlap analog signal circuitry should kept apart possible. AL250/251 decoder should have inputs left floating.
July 1999
AL250
10.0 Mechanical Drawing
AL250: 20mm 14mm 64-pin package
July 1999
AL250
AL251: 20mm 14mm 80-pin package
July 1999
AL250
11.0 Power Consumption
AL250/251 works both 3.3V. following table shows current consumption AL250/251 itself that whole with power supply single 3.3V mixed (3.3V AL250/251 only). AL250/251 chip AL250 (typ.) (typ.) +3.3V AL250 rest (typ.) (typ.)
Please reminded that when lower power supply used, pull-down resistance RSET adjusted compensate accordingly. lower supply voltage lower pulldown resistance ideal resistance value achieved adjusting output 0.7V peak-to-peak higher obtain better output brightness contrast.
more information about AL250/251 other AverLogic products, please contact your local authorized representatives, visit website, contact directly.
July 1999
CONTACT INFORMATION
AverLogic Technologies, Inc. 6840 Suite Jose, 95119
361-0400 361-0404 sales@averlogic.com www.averlogic.com
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