AK4705A AK4702 04

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AK4705A - AK4705A
AK4702 - AK4702

[AK4705A]
AK4705A
24bit with SCART Switch
GENERAL DESCRIPTION AK4705A offers ideal features digital set-top-box systems. Using AKM's multi-bit architecture modulator, AK4705A delivers wide dynamic range while preserving linearity improved THD+N performance. AK4705A integrates combination filters, removing need high cost external filters increasing performance systems with excessive clock jitter. AK4705A also including audio switches, volumes, video switches, video filters, etc. designed primarily digital set-top-box systems. AK4705A offered space saving 48-pin LQFP package. FEATURES Sampling Rates Ranging from 32kHz 50kHz 64dB High Attenuation Digital Filter Order Analog Chip Buffer with Single-Ended Output Digital De-Emphasis 32k, 44.1k 48kHz Sampling Format: 24bit Justified, I2S, 18/16bit Justified Master Clock: 256fs, 384fs High Tolerance Clock Jitter Analog Switches SCART Audio Section THD+N: -86dB (@2Vrms) Dynamic Range: 96dB (@2Vrms) Stereo Analog Volume with Pop-noise Free Circuit (+6dB -60dB Mute) Analog Inputs Stereo Inputs (TV&VCR SCART) Stereo Input (Changeover Internal DAC) Analog Outputs Stereo Outputs (TV, SCART) Mono Output (Modulator) Noise Free Circuit Power On/Off Video Section Integrated LPF: -40dB@27MHz 75ohm Driver Gain Outputs Adjustable Gain Four CVBS/Y Inputs (ENCx2, VCR), Three CVBS/Y Outputs (RF, VCR) Three Inputs (ENCx2, VCR), outputs (TV, VCR) Bi-Directional Control VCR-Red/Chroma Inputs (ENC, VCR), Outputs (TV) Y/Pb/Pr Option 6MHz) Input Monitor Loop-Through Mode Standby Auto-Startup Mode Power Saving SCART Pin#16(Fast Blanking), Pin#8(Slow Blanking) Control AK4702/04 Software Compatible
MS0698-E-00 -12007/12
[AK4705A]
Power Supply 5V+/-5% 12V+/-5% Power Dissipation Power Standby Mode Package Small 48pin LQFP Full Compatible with AK4705
MS0698-E-00
2007/12
[AK4705A]
-6dB/0dB/ +2.44/+4dB MCLK BICK LRCK SDTI Volume TV1/0 VCRINL VCRINR Volume MONO TVOUTL -60dB (2dB/step) MONOOUT
TVOUTR
TVINL
VCROUTL
VCROUTR TVINR Bias (Mute) Register Control VCR1/0 DVCOM PVCOM VMONO
Audio Block(DAPD="0")
-60dB 0dB/+6dB (NC) DACL DACR (NC) Volume TV1/0 VCRINL VCRINR Volume MONO TVOUTR TVOUTL (2dB/step) MONOOUT
TVINL
VCROUTL
VCROUTR TVINR Bias (Mute) Register Control VCR1/0 DVCOM PVCOM VMONO
Audio Block(DAPD="1")
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[AK4705A]
Typical connection
VVD1 VVD2 VVSS
Typical connection
CVBS/Y CVBS/Y CVBS
ENCV ENCY VCRVIN TVVIN TVVOUT
R/C/Pr R/C/Pr
ENCRC ENCC VCRRC TVRC SCART
G/CVBS
ENCG VCRG
B/Pb B/Pb
ENCB VCRB Monitor
REFI VCRVOUT SCART
VCRC
Video Block
Typical connection VCRFB TVFB
Typical connection
SCART
TVSB
VCRSB
SCART
Monitor
Video Blanking Block
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[AK4705A]
Ordering Guide
AK4705AEQ AKD4705A +70°C 48pin LQFP (0.5mm pitch) Evaluation Board AK4705A
Layout
MONOOUT VCROUTR VCROUTL TVOUTR TVOUTL DVCOM VCRINL PVCOM TVINR TVINL VCRINR
MCLK BICK SDTI LRCK VCRVOUT TVFB
View
TVSB VCRSB VCRB VCRG VCRRC VCRFB VCRVIN TVVIN ENCY ENCV ENCC
AK4705AEQ
TVVOUT
MS0698-E-00
ENCG
ENCB
TVRC
VVSS
VVD2
VVD1
REFI
ENCRC
VCRC
2007/12
[AK4705A]
Main difference between AK4702/4704 AK4705/A
Items Audio Audio bits Digital filter attenuation level +4dB gain volume#0 (total: +10dB max) power-down/analog input mode Volume#1 output VCROUTL/R switch matrix MONO mixing VCROUTL/R MONO input Video filter 150ohm video driver modulator mixer modulator video input monitor Slow Blanking monitor output mode. TV/VCR CVBS input detection Power Save Mode Y/Pb/Pr option support Auto Mode MONOIN AK4702 #28) ENCB TVINL speed (max) Mask bits function (09H) FB/SB loop back auto mode. AK4702 18bit 54dB enabled MONOIN Pin# 100kHz AK4704 AK4705/A 24bit 24bit 64dB 64dB disabled disabled FILT REFI 400kHz 400kHz available. Available)
Video
Pinout
Others
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[AK4705A]
PIN/FUNCTION
Name VCRC VVSS TVVOUT VVD2 Function Chrominance Output Video Ground Pin. Composite/Luminance Output Video Power Supply Normally connected VVSS with 0.1F ceramic capacitor parallel with electrolytic cap. Red/Chrominance/Pr Output Green/Y Output Blue/Pb Output Video Power Supply Normally connected VVSS with 0.1F ceramic capacitor parallel with electrolytic cap. Video Current Reference Setup Normally connected VVD1 through 10k±1% resistor externally. Blue/Pb Input Encoder Green/Y Input Encoder Red/Chrominance/Pr Input Encoder Chrominance Input Encoder Composite/Luminance Input1 Encoder Composite/Luminance Input2 Encoder Composite/Luminance Input Composite/Luminance Input Fast Blanking Input Red/Chrominance/Pr Input Green Input Blue/Pb Input Interrupt Video Blanking. Normally connected VD(5V) through resistor externally. Slow Blanking Input/Output Slow Blanking Output Audio Input Audio Input Audio Input Audio Input Audio Output Audio Output Audio Output Audio Output MONO Analog Output Power Supply Pin. 12V. Normally connected with 0.1F ceramic capacitor parallel with electrolytic cap. Common Voltage Normally connected with 0.1F ceramic capacitor parallel with electrolytic cap. Audio Common Voltage Normally connected with 0.1F ceramic capacitor parallel with electrolytic cap. caps affect settling time audio bias level.
TVRC VVD1
REFI ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB VCRSB TVSB VCRINR VCRINL TVINR TVINL VCROUTR VCROUTL TVOUTR TVOUTL MONOOUT
DVCOM
PVCOM
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[AK4705A]
PIN/FUNCTION (Continued)
Ground Pin. Power Supply Pin. Normally connected with 0.1F ceramic capacitor parallel with electrolytic cap. Master Clock Input DAPD= "0". Connect DAPD= "1". This should open. Audio Serial Data Clock DAPD= "0". Analog Audio Input DAPD= "1". Audio Serial Data Input DAPD= "0". Connect DAPD= "1". This should open. Clock DAPD= "0". Analog Audio Input DAPD= "1". Control Data Clock Control Data Power-Down Mode When "L", AK4705A power-down mode held reset. AK4705A should always reset upon power-up. Composite Output modulator Composite/Luminance Output Fast Blanking Output
MCLK (NC) BICK DACR SDTI (NC) LRCK DACL VCRVOUT TVFB
Handling Unused
unused pins should processed appropriately below. Classification Name VCRC, TVVOUT, TVRC, TVG, TVB, ENCB, ENCG, ENCRC, ENCC, ENCV, ENCY, TVVIN, VCRVIN, VCRRC, VCRG, VCRB, VCRINR, VCRINL, TVINR, TVINL, VCROUTR, VCROUTL, TVOUTR, TVOUTL, MONOOUT, DACR, DACL, RFV, VCRVOUT VCRSB (O), TVFB, TVSB VCRFB, VCRSB (I), MCLK, BICK, SDTI, LRCK, SCL, SDA, Setting These pins should open.
Analog
Digital
These pins should open. These pins should connected VSS.
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[AK4705A]
INTARNAL EQUIVALENT CIRCUITS
Name MCLK BICK SDTI LRCK Type Equivalent Circuit (60k)
Description
Digital (DAPD= "0") Analog (DAPD= "1")
attached only BICK LRCK pin.
Digital
voltage must exceed
Digital
Normally connected VD(5V) through resistor externally.
VCROUT TVFB VCRC TVVOUT TVRC
VVD1
VVD2
Video
VVSS
VVSS
VVD1
REFI REFI Normally connected VVD1 through resistor.
VVSS
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[AK4705A]
Name ENCB ENCG ENCRC ENCC ENCV ENCY TVVIN VCRVIN VCRFB VCRRC VCRG VCRB
Type
Equivalent Circuit
VVD1
Description
Video
(60K) VVSS
attached ENCC pin, ENCRC (chroma mode) VCRRC (chroma mode) pin.
VCRSB TVSB
Video
(120k)
120k attached TVSB pin.
VCRINR VCRINL TVINR TVINL
150k
Audio
VCROUTR VCROUTL TVOUTR TVOUTL MONOOU
Audio
DVCOM PVCOM
VCOM
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[AK4705A]
ABSOLUTE MAXIMUM RATINGS
(VSS=VVSS=0V; Note: Parameter Power Supply Symbol VVD1 VVD2 VIND VINV VINA VINA Tstg -0.3 -0.3 -0.3 -0.3-0.3 -0.3 -0.3 -0.3 VD+0.3 VVD1+0.3 VP+0.3 VD+0.3 Units
(Note:
Input Current (any pins except supplies) Input Voltage Video Input Voltage Audio Input Voltage (except DACL/R pins) Audio Input Voltage (DACL/R pins) Ambient Operating Temperature Storage Temperature Note: voltages with respect ground. Note: VVSS must connected same analog ground plane.
WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
RECOMMENDED OPERATING CONDITIONS
(VSS=VVSS=0V; Note: Parameter Power Supply (Note: Symbol VVD1/VVD2 Note: Analog output voltage scales with voltage AOUT (typ@0dB) 2Vrms VD/5. VVD1 VVD2 must same voltage. 4.75 4.75 11.4 5.25 5.25 12.6 Units
*AKEMD assumes responsibility usage beyond conditions this datasheet.
ELECTRICAL CHARACTERISTICS 25°C; VP=12V, VVD1=VVD2 48kHz; BICK 64fs) Power Supplies Parameter Power Supply Current Normal Operation (PDN "H"; Note: VVD1+VVD2 VVD1+VVD2 Power-Down Mode (PDN "L"; Note: VVD1+VVD2
Note: STBY "L", video outputs active. signal, load switches. fs=48kHz "0"data input DAC. Note: digital inputs including clock pins (MCLK, BICK LRCK) held VSS.
Units
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[AK4705A]
DIGITAL CHARACTERISTICS
25°C; 4.75 5.25V) Parameter High-Level Input Voltage Low-Level Input Voltage Low-Level Output Voltage (SDA pin: Iout= 3mA, pin: Iout= 1mA) Input Leakage Current Symbol Units
ANALOG CHARACTERISTICS (AUDIO) 25°C; VP=12V, VVD1=VVD2 48kHz; BICK 64fs; Signal Frequency 1kHz; 24bit Input Data; Measurement frequency 20Hz 20kHz; 4.5k; Volume #0=Volume #1=0dB, 0dB=2Vrms output; unless otherwise specified) Parameter Units Resolution Analog Input: (TVINL/TVINR/VCRINL/VCRINR pins) Analog Input Characteristics Input Voltage Vrms Input Resistance Analog Input: (DACL/DACR pin) Analog Input Characteristics Input Voltage Vrms Input Resistance Stereo/Mono Output: pins; Note: Analog Output Characteristics Volume#0 Gain (DAPD "0") (DVOL1-0 "00") (DVOL1-0 "01") (DVOL1-0 "10") +2.44 (DVOL1-0 "11". Note: Volume#2 Gain (DAPD "1") (DVOL1-0 "00") (DVOL1-0 "01") -0.7 Volume#1 Step Width (+6dB -12dB) (-12dB -40dB) (-40dB -60dB) THD+N 2Vrms output. Note: 3Vrms output. Note: Note: Dynamic Range (-60dB Output, A-weighted. Note: (A-weighted. Note: Interchannel Isolation (Note: Note: Interchannel Gain Mismatch (Note: Note: Gain Drift ppm/°C Load Resistance (AC-Lord) TVOUTL/R, VCROUTL/R, MONOOUT Load Capacitance TVOUTL/R, VCROUTL/R, MONOOUT Output Voltage (Note: 1.85 2.15 Vrms Power Supply Rejection (PSR. Note: Note: Measured Audio Precision System Cascade. Note: Output clips over -2.5dBFS digital input. Note: TVOUT Note: Except VCROUTL/VCROUTL pins. Note: Between TVOUTL TVOUTR with digital inputs 1kHz/0dBFS.
MS0698-E-00 2007/12
[AK4705A]
Note: Full-scale output voltage (0dBFS). Output voltage scales with voltage Stereo output (typ@0dBFS) 2Vrms VD/5 when volume#0=volume#1=0dB. output must exceed 3Vrms. Note: applied with 1kHz, 100mV.
FILTER CHARACTERISTICS 25°C; VP=11.412.6V, 4.755.25V, VVD1=VVD2 4.755.25V; 48kHz; DEM0 "1", DEM1 "0") Parameter Symbol Units Digital filter 21.77 Passband ±0.05dB (Note: 24.0 -6.0dB Stopband (Note: 26.23 Passband Ripple 0.01 Stopband Attenuation Group Delay (Note: 1/fs Digital Filter Frequency Response 20.0kHz
Note: passband stopband frequencies scale with e.g.) (@±0.05dB), Note: calculating delay time which occurred digital filtering. This time from setting 16/18/24bit data both channels input register output analog signal.
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[AK4705A]
ANALOG CHARACTERISTICS (VIDEO) 25°C; VP=12V, VVD1=VVD2 VVOL1/0= "00" unless specified.) Parameter Conditions Sync Clamp Voltage output pin. Chrominance Bias Voltage output pin. Pb/Pr Clamp Voltage output pin. Gain Input=0.3Vp-p, 100kHz Gain Input=0.3Vp-p, VVOL1/0= "00" 100kHz VVOL1/0= "01" VVOL1/0= "10" VVOL1/0= "11" Interchannel Gain Mismatch TVRC, TVG, TVB. Input=0.3Vp-p, 100kHz. -0.5 Frequency Response Input=0.3Vp-p, C1=C2=0pF. 100kHz 6MHz. -1.0 10MHz. 27MHz. Group Delay Distortion 4.43MHz with respect 1MHz. Input Impedance Chrominance input (internally biased) Input Signal f=100kHz, maximum with distortion 1.0%, gain=6dB. Load Resistance (Figure Load Capacitance (Figure (Figure Dynamic Output Signal f=100kHz, maximum with distortion 1.0% Crosstalk f=4.43MHz, 1Vp-p input. Among TVVOUT, TVRC, VCRVOUT VCRC outputs. Reference Level 0.7Vp-p, CCIR weighting. 15kHz 5MHz. Differential Gain 0.7Vpp 5steps modulated staircase. chrominance &burst 280mVpp, 4.43MHz. Differential Phase 0.7Vpp 5steps modulated staircase. chrominance &burst 280mVpp, 4.43MHz.
Video Signal Output max: 15pF max: 400pF
Units Degree
+0.4 +0.8
Figure Load Resistance R1+R2 Load Capacitance C1/C2.
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[AK4705A]
SWITCHING CHARACTERISTICS 25°C; VP=11.4 12.6V, 4.75 5.25V, VVD1=VVD2 4.75 5.25V) Parameter Symbol fCLK 8.192 Master Clock Frequency 256fs: dCLK Duty Cycle fCLK 12.288 384fs: dCLK Duty Cycle LRCK Frequency Duty Duty Cycle Audio Interface Timing tBCK 312.5 BICK Period tBCKL BICK Pulse Width tBCKH Pulse Width High tBLR BICK LRCK Edge (Note: tLRB LRCK Edge BICK (Note: tSDH SDTI Hold Time tSDS SDTI Setup Time Control Interface Timing (I2C Bus): Clock Frequency fSCL Free Time Between Transmissions tBUF Start Condition Hold Time tHD:STA (prior first clock pulse) Clock Time tLOW Clock High Time tHIGH Setup Time Repeated Start Condition tSU:STA Hold Time from Falling (Note: tHD:DAT Setup Time from Rising tSU:DAT Rise Time Both Lines Fall Time Both Lines Setup Time Stop Condition tSU:STO Pulse Width Spike Noise Suppressed Input Filter Capacitive load Reset Timing Pulse Width (Note: Note: BICK rising edge must occur same time LRCK edge. Note: Data must held sufficient time bridge transition time SCL. Note: AK4705A should reset upon power Note: registered trademark Philips Semiconductors.
12.8 19.2
Units
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[AK4705A]
Timing Diagram
1/fCLK tCLKH tCLKL
dCLK=tCLKH fCLK, tCLKL fCLK
MCLK
1/fs
LRCK
tBCK tBCKH tBCKL
BICK
Clock Timing
LRCK tBLR tLRB
BICK tSDS tSDH
SDTI
Serial Interface Timing
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[AK4705A]
Power-down Timing
tBUF tHD:STA Stop Start tHD:DAT tSU:DAT tSU:STA Start
mode Timing
tLOW
tHIGH
tSU:STO Stop
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[AK4705A]
OPERATION OVERVIEW System Reset Power-down options
AK4705A should reset once bringing upon power-up. AK4705A several operation modes. pin, AUTO bit, DAPD bit, MUTE STBY control operation modes shown Table Table Mode AUTO STBY MUTE DAPD Mode Full Power-down Auto Startup mode (power-on default) Standby mute Standby Mute (DAC power down) Mute (DAC operation) Normal operation (DAC power down Analog input) Normal operation (DAC operation) Don't Care)
Table Operation Mode Settings Register Control available video input Video input Available Active Power down Active Power down Needed needed Needed Active Active Hi-Z/ Active Active Active MCLK, BICK, LRCK needed Audio Bias Level Power down Video Output Hi-Z TVFB, TVSB Hi-Z
Mode Full Power-down Auto Startup mode (power-on default)
VCRSB Pull-down
Standby mute Standby Mute (DAC power down) Mute (DAC operation) Normal operation (DAC power down Analog input) Normal operation (DAC operation)
Notes: TVOUTL/R muted VMUTE default state. Internally pulled down 120kohm(typ) resistor. Video input TVVIN VCRVIN. VCRC outputs termination. Table Status each operation modes
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[AK4705A]
Full Power-down Mode
AK4705A should reset once bringing upon power-up. pin: Power down "H": Normal operation "L": Device power down.
Auto Startup Mode
After "H", AK4705A auto startup mode. this mode, blocks except video detection circuit powered down. Once video detection circuit detects video signal from TVVIN VCRVIN pin, AK4705A goes stand-by mode (Both Fast Blanking Slow Blanking also fixed VCR-TV Loop-through) automatically sends pulse pin. exit auto startup mode, AUTO "0". AUTO (00H D3): Auto startup "1": Auto startup enable (default). "0": Auto startup disable (Manual startup).
Power-down Mode
internal block powered-down switched 1Vrms analog input mode. When DAPD ="1", zero-cross detection offset calibration does work. DAPD (00H D2): power-down bit. "1": power-down. Analog-input mode. pin: MCLK (NC) pin: BICK DACR. analog input. pin: SDTI (NC) pin: LRCK DACL. analog input. "0": operation. (default)
Standby Mode
When AUTO MUTE STBY "1", AK4705A forced into TV-VCR loop through mode. this mode, sources TVOUTL/R MONOOUT pins fixed VCRINL/R pins; sources VCROUTL/R fixed TVINL/R pins respectively. gain volume#1 fixed 0dB. register values themselves changed STBY "1". STBY (00H D0): Standby bit. "1": Standby mode. (default) "0": Normal operation.
Mute Mode (Bias-off Mode. 00H:
When MUTE "1", bias voltage audio output goes level. Bringing MUTE changes this bias voltage smoothly from VP/2 2sec(typ.). This removes huge click noise related sudden change bias voltage power-on. change MUTE from also makes smooth transient from VP/2 2sec(typ). This removes huge click noise related sudden change bias voltage power-off. MUTE bit: Bias-off bit. "1": audio bias GND. (default) "0": Normal operation
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[AK4705A]
Normal Operation Mode
change analog switches, AUTO bit, DAPD bit, MUTE STBY "0". power-down mode until MCLK LRCK input. AK4705A power-down mode until MCLK LRCK input. Figure shows example system timing power-down power-up pin.
Typical Operation Sequence auto setup mode)
Figure shows example system timing auto setup mode.
Clock, Data TVVIN VCRVIN TVVOUT, VCRVOUT Audio (DC)
don't care Signal Signal
Power Mode
Power Mode
Power Mode
don't care
Signal
Signal
Signal
don't care
don't care
Signal
Signal
Signal
don't care
Hi-Z
Active (loop-through)
Hi-Z
Active (loop-through)
Hi-Z
(GND)
Active (loop-through)
Active (loop-through)
Figure Typical operating sequence (auto setup mode)
Typical Operation Sequence normal operation mode)
Figure shows example system timing normal operation mode.
AUTO MUTE STBY Clock Data
(internal)
"Stand-by" "Mute" "Stand-by"
(default) (default) (default)
don't care don't care
normal operation Audio data
don't care don't care
TV-Source select
fixed in(Loop-through)
(default)
Figure Typical operating sequence (except auto setup mode) MS0698-E-00 2007/12
[AK4705A]
Notes: analog output corresponding digital input group delay, external clocks (MCLK, BICK LRCK) stopped standby mode. Mute analog outputs externally click noise(3) adversely affects system.
Audio Block
System Clock
external clocks required operate section AK4705A MCLK, LRCK BICK. master clock (MCLK) corresponds 256fs 384fs. MCLK frequency automatically detected, internal master clock becomes 256fs. MCLK should synchronized with LRCK phase critical. Table illustrates corresponding clock frequencies. external clocks (MCLK, BICK LRCK) should always present whenever section AK4705A normal operating mode (STBY DAPD "0"). these clocks provided, AK4705A draw excess current because device utilizes dynamically refreshed logic internally. section AK4705A should reset STBY after threse clocks provided. external clocks present, place AK4705A power-down mode (STBY "1"). After exiting reset power-up etc., AK4705A remains power-down mode until MCLK LRCK input. LRCK 32.0kHz 44.1kHz 48.0kHz MCLK 256fs 384fs 8.1920MHz 12.2880MHz 11.2896MHz 16.9344MHz 12.2880MHz 18.4320MHz Table System clock example BICK 64fs 2.0480MHz 2.8224MHz 3.0720MHz
Audio Serial Interface Format (00H: D5-D4)
Data shifted SDTI using BICK LRCK inputs. DIF0 DIF1 bits select four formats serial mode shown Table modes, serial data MSB-first, compliment format latched rising edge BICK. Mode also used justified formats zeroing unused LSBs. Mode DIF1 DIF0 SDTI Format 16bit Justified 18bit Justified 24bit Justified BICK 32fs 36fs 48fs 48fs 24bit Compatible 32fs Table Audio Data Formats Figure Figure Figure Figure Figure (default)
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[AK4705A]
LRCK BICK SDTI Mode SDTI Mode
Don't care 15:MSB, 0:LSB Don't care 17:MSB, 0:LSB
Don't care
Don't care
Data
Figure Mode Timing
Data
LRCK BICK SDTI
23:MSB, 0:LSB Don't care Don't care
Data
Figure Mode Timing
Data
LRCK BICK SDTI
Don't care
23:MSB, 0:LSB
Don't care
Data
Figure Mode Timing
Data
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[AK4705A]
De-emphasis Filter (00H: D7-D6)
digital de-emphasis filter available 44.1 48kHz sampling rates 50/15µs) controlled DEM0 DEM1 bits. DEM1 DEM0 Mode (default)
44.1kHz 48kHz 32kHz Table De-emphasis Filter Control
Switch Control
AK4705A switch matrixes designed primarily SCART routing. Those controlled control register shown Table Table Table (refer block diagram). (01H: D1-D0) Source TVOUTL/R (default) VCRIN Mute (Reserved) Table TVOUT Switch Configuration (01H: D2-D0) Source MONOOUT (L+R)/2 Bypass (L+R)/2 volume (L+R)/2 (Reserved) Through (L+R)/2 volume VCRIN (L+R)/2 (default) Mute (Reserved) Table MONOOUT Switch Configuration (01H: D5-D4) VCR1 VCR0 Source VCROUTL/R TVIN Mute Output volume Table VCROUT Switch Configuration
(default)
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[AK4705A]
Volume Control (4-Level Volume)
AK4705A 4-level volume control (Volume shown Table Table volume reflects change register value immediately. (03H: D4-D3) DVOL1 DVOL0
Volume Gain -6dB +2.44dB
Output Level (Typ) 2Vrms (with 0dBFS input volume #1=0dB) 1Vrms (with 0dBFS input volume #1=0dB.) 2.65Vrms (with 0dBFS input volume #1=0dB.) 2Vrms (with -10dBFS input volume #1=+6dB. +4dB Clips over -2.5dBFS digital input.) Table Volume DAPD "0". mode)
(default)
(03H: D4-D3) DVOL1 DVOL0
Volume Gain Output Level (Typ) +6dB 2Vrms (with 1Vrms input volume #1=0dB) 1Vrms (with 1Vrms input volume #1=0dB.) (reserved) (reserved) Table Volume DAPD "1". analog input mode.)
(default)
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[AK4705A]
Volume Control (Main Volume)
AK4705A main volume control (Volume shown Table (02H: D5-D0) Note: output must exceed 3Vrms. Table Volume
Gain +6dB +4dB +2dB -60dB Mute
(default)
When "1"(default), there noise changing levels. MDT1-0 bits select transition time (Table 12). When gain value 1EH(-2dB) written gain register while actual (stable) gain 1FH(0dB), gain changes 1EH(-2dB) within transition time selected MDT1-0 bits. AK4705A compares actual gain value gain register after finishing transition time, re-changes actual gain register value within transition time register value different from actual gain. When "0", there transition time gain changes immediately. This change cause click noise.
[Gain=1EH] [Gain=1DH] [Gain=1CH]
Gain Register
compare
compare compare
Actual Gain
1EH)
1DH)
1CH)
Transition Time (256/fs 2048/fs. free.)
Figure Volume Change Operation (MOD "1") MDT1 MDT0 Transition Time 256/fs 512/fs 1024/fs 2048/fs Table Volume Transition Time
(default)
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[AK4705A]
Video Block
Video Switch Control
AK4705A switches modulator. Each switches controlled registers independently. When AUTO STBY "1", these switch setting ignored fixed configuration (loop-through mode). Refer auto setup mode standby mode. (04H: D2-D0) Mode Shutdown Encoder CVBS+RGB Encoder YPbPr Encoder Encoder CVBS (reserved) (reserved) VTV2-0 Source TVVOUT (Hi-Z) ENCV pin. Encoder CVBS ENCV pin. Encoder ENCY pin. Encoder VCRVIN pin. CVBS TVVIN pin. CVBS. Source TVRC (Hi-Z) ENCRC pin. Encoder Red,C ENCRC pin. Encoder ENCC pin. Encoder VCRRC pin. Red,C (Hi-Z) Source (Hi-Z) ENCG pin. Encoder Green (Hi-Z) (Hi-Z) VCRG pin. Green (Hi-Z) Source (Hi-Z) ENCB pin. Encoder Blue (Hi-Z) (Hi-Z) VCRB pin. Blue (Hi-Z) (Note: Note: (default)
Table Video Output (04H: D5-D3) Mode Shutdown Encoder CVBS Encoder CVBS CVBS (reserved) (reserved) (reserved) VVCR2-0 Source VCRVOUT (Hi-Z) ENCV pin. Encoder CVBS ENCY pin. Encoder CVBS TVVIN pin. CVBS. VCRVIN pin. CVBS. Source VCRC (Hi-Z) ENCRC pin. Encoder ENCC pin. Encoder (Hi-Z) VCRRC pin. (Note: (default)
Table Video Output
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[AK4705A]
(04H: D7-D6) Source ENCV pin. Encoder CVBS1 Encoder CVBS. ENCG pin. Encoder CVBS2 Encoder CVBS. (Note: VCRVIN pin. (default) CVBS. Shutdown (Hi-Z) (Note: Table Video Output Mode Note: When input video signal ENCRC VCRRC pin, CLAMP1-0 bits respectively. Note: When VTV2-0 ="001", ="1" VRF1-0 ="01", output same output (Encoder VRF1-0
Video Output Control (05H: D6-D0)
Each video outputs Hi-Z individually control registers. These setting ignored when AUTO "1". When "1", VCRC outputs even VCRC "0". When "0", VCRC follows setting VCRC bit. Please refer "Red/Chroma Bi-directional Control SCART". TVV: TVR: TVG: TVB: VCRV: VCRC: TVFB: TVVOUT output control TVRCOUT output control TVGOUT output control TVBOUT output control VCRVOUT output control VCRC output control TVFB output control
Hi-Z (default) Active.
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Red/Chroma Bi-directional Control SCART (05H:
AK4705A supports bi-directional Red/Chroma signal SCART.
(CIO VCRC bit) VCRC
VCRRC SCART 0.1u
(AK4705A)
Figure Red/Chroma Bi-directional Control
VCRC State VCRC Hi-z Active Connected Connected Table Red/Chroma Bi-directional Control
(default)
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Video Gain Control (06H: D1-D0)
VVOL1-0 bits video gain. VVOL1 VVOL0 Gain Output level (Typ. @Input=0.7Vpp) +6dB 1.4Vpp +7.2dB 1.6Vpp +8.2dB 1.8Vpp +9.1dB 2.0Vpp Table Video Gain Control
(default)
Clamp DC-restore circuit control (06H: D7-D2)
Each CVBS input sync clamp circuit. DC-restore circuit clamp voltages 0.7V(typ) 2.2V(typ) support both YPbPr signal. They correspond 0.35V(typ) 1.1V(typ) SCART connector when matched 75ohm resistors. CLAMP1, CLAMP0 CLAMPB bits select input circuit ENCRC (Encoder Red/Chroma), ENCB (Encoder Blue), VCRRC (VCR Red/Chroma) VCRB (VCR Blue) respectively. VCLP1-0 bits select sync source restore circuit. CLAMPB CLAMP0 VCRRC Input Circuit VCRB Input Circuit restore clamp active restore clamp active (0.7V sync timing/output pin) (0.7V sync timing/output pin) Biased restore clamp active) (2.2V sync timing/output pin) (0.7V sync timing output pin) restore clamp active restore clamp active (2.2V sync timing/output pin) (2.2V sync timing/output pin) (reserved) (reserved) Table DC-restore Control Input note Y/Pb/Pr (default)
CLAMPB
CLAMP1
ENCRC Input Circuit ENCB Input Circuit restore clamp active restore clamp active (0.7V sync timing/output pin) (0.7V sync timing/output pin) Biased restore clamp active (2.2V sync timing/output pin) (0.7V sync timing output pin) restore clamp active restore clamp active (2.2V sync timing/output pin) (2.2V sync timing/output pin) (reserved) (reserved) Table DC-restore Control Encoder Input
note Y/Pb/Pr (default)
CLAMP2
ENCG Input Circuit restore clamp active (0.7V sync timing/output pin) Sync clamp active (0.7V sync timing/output pin)
note Y/Pb/Pr (default)
Note: When VTV2-0 bits "001"(source Encoder CVBS /RGB), (TVG active) VCLP1-0 bits "11"(DC restore source ENCG), sync selected even CLAMP2 "0". Table DC-restore Control Encoder Green/Y Input
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VCLP1-0: restore source control VCLP1 VCLP0 Sync Source Restore ENCV ENCY VCRVIN ENCG
(default)
Note: When AUTO "1", source fixed VCRVIN. Table DC-restore Source Control
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Blanking Control
AK4705A supports Fast Blanking signals Slow Blanking (Function Switching) signals TV/VCR SCART.
Input/Output Control Fast/Slow Blanking
FB1-0: Fast Blanking output control (07H: D1-D0) TVFB Output Level (default) 2V<, 4V(typ) load Same input (4V/0V) (Reserved) (Note: Minimum load 150ohm) Table Fast Blanking Output
SBT1-0: Slow Blanking output control (07H: D3-D2) SBT1 SBT0 TVSB Output Level (default) (Reserved) 10V< (Note: Minimum load 10kohm) Table Slow Blanking Output
SBV1-0: Slow Blanking output control (07H: D5-D4) SBV1 SBV0 VCRSB Output Level (default) (Reserved) 10V< (Note: Minimum load 10kohm) Table Slow Blanking Output
SBIO1-0: TV/VCR Slow Blanking control (07H: D7-D6) SBIO1 SBIO0 VCRSB Direction TVSB Direction Output Output (Controlled SBV1,0) (Controlled SBT1,0) (Reserved) (Reserved) Input Output (Stored SVCR1,0) (Controlled SBT1,0) Input Output (Stored SVCR1,0) (Same output Table TV/VCR Slow Blanking Control
(default)
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Monitor Options function
Monitor Options (08H: D4-D0)
AK4705A several detection functions. SVCR1-0 bits, FVCR bit, VCMON TVMON reflect input level slow blanking, input level fast blanking signals input TVVIN VCRVIN pins. SVCR1-0: Slow blanking status monitor SVCR1-0 reflect voltage VCRSB only when VCRSB input mode. When VCRSB output mode, SVCR1-0 hold previous value. VCRSB input level SVCR1 SVCR0 (Reserved) 9.5< Table Slow Blanking Monitor FVCR: Fast blanking input level monitor This enabled when TVFB "1". VCRFB input level FVCR <0.4V Table Fast Blanking Monitor (Typical threshold 0.7V) VCMON: VCRVIN video input monitor (MCOMN "1"), TVVIN VCRVIN video input monitor (MCOMN "0". AK4704 compatible.) video signal detected. Detects video signal. TVMON: TVVIN video input monitor (active when MCOMN "1") video signal detected. Detects video signal.
AUTO (00H MCOMN (09H TVVIN signal VCRVIN signal TVMON (08H VCMON (08H
Don't care) Note TVVIN/VCRVIN signal: signal applied, signal applied Table TV/VCR Monitor Function
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Function Mask Options (09H: D4-D1)
Changes status monitored pin. open drain output goes 2sec(typ.) when status changed. This should connected (typ. through 10kohm resistor. bit, bit, MCOMN bit, MFVCR MSVCR control reflection status change these monitors onto from report prevent masks each monitor.
AK4705A
R=10k
Figure MVC: VCMON Mask. Refer Table MTV: TVMON Mask. Refer Table MCOMN: Refer Table TVMON (08H (09H Change Hi-Z Change Hi-Z Change Generates Pulse Change Hi-Z Change Hi-Z Change Hi-Z Note: When STBY "0", Monitor Mask function enabled. Note: When AUTO "1", TVMON does change. Table Monitor Mask AUTO (00H VCMON (08H Change Change Change Change (09H Hi-Z Hi-Z Generates Pulse Hi-Z AUTO (00H
Change Hi-Z Change Hi-Z Change Generates Pulse Change Generates Pulse Note: When STBY "0", Monitor Mask function enabled. Table Monitor Mask MFVCR: FVCR Monitor mask. Change FVCR reflected pin. (default) Change FVCR reflected pin. MSVCR: SVCR1-0 Monitor mask Change SVCR1-0 reflected pin. (default) Change SVCR1-0 reflected pin.
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Control Interface
I2C-bus Control Mode
WRITE Operations Figure shows data transfer sequence I2C-bus mode. commands preceded START condition. HIGH transition line while HIGH indicates START condition (Figure 16). After START condition, slave address sent. This address bits long followed eighth which data direction (R/W). most significant seven bits slave address fixed "0010001". When AK4705A receives slave address, AK4705A generates acknowledge operation executed. master must generate acknowledge-related clock pulse release line (HIGH) during acknowledge clock pulse (Figure 17). indicates that read operation executed. indicates that write operation executed. second byte consists address control registers AK4705A. format first, those most significant 3-bits fixed zeros (Figure 12). data after second byte contain control data. format first, 8bits (Figure 13). AK4705A generates acknowledge after each byte received. data transfer always terminated STOP condition generated master. HIGH transition line while HIGH defines STOP condition (Figure 16). AK4705A execute multiple byte write operations sequence. After receipt third byte, AK4705A generates acknowledge, awaits next data again. master transmit more than byte instead terminating write cycle after first data byte transferred. After receipt each data, internal address counter incremented one, next data taken into next address automatically. address exceeds prior generating stop condition, address counter will "roll over" previous data will overwritten. data line must stable during HIGH period clock. HIGH state data line only change when clock signal line (Figure except START STOP condition.
Data(n) Data(n+1) Data(n+x)
R/W=
Slave Address
Address(n)
Figure Data Transfer Sequence I2C-bus Mode
Figure First Byte
Figure Second Byte
Figure Byte Structure After Second Byte
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READ Operations READ operations. After transmission data, master read next address's data generating acknowledge instead terminating write cycle after receiving first data word. After receipt each data, internal address counter incremented one, next data taken into next address automatically. address exceeds prior generating stop condition, address counter will "roll over" previous data will overwritten. AK4705A supports basic read operations: CURRENT ADDRESS READ RANDOM READ. 2-1. CURRENT ADDRESS READ AK4705A contains internal address counter that maintains address last word accessed, incremented one. Therefore, last access (either read write) address "n", next CURRENT READ operation would access data from address "n+1". After receipt slave address with "1", AK4705A generates acknowledge, transmits 1byte data which address internal address counter increments internal address counter master does generate acknowledge data generate stop condition, AK4705A discontinues transmission
R/W= Data(n+1) Data(n+2) Data(n+x)
Slave Address
Data(n)
Figure CURRENT ADDRESS READ 2-2. RANDOM READ Random read operation allows master access memory location random. Prior issuing slave address with "1", master must first perform "dummy" write operation. master issues start condition, slave address(R/W="0") then register address read. After register's address acknowledge, master immediately reissues start condition slave address with "1". Then AK4705A generates acknowledge, 1-byte data increments internal address counter master does generate acknowledge data generate stop condition, AK4705A discontinues transmission.
R/W= Slave Address R/W= Data(n+1) Data(n+x)
Slave Address
Address(n)
Data(n)
Figure RANDOM ADDRESS READ
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start condition stop condition
Figure START STOP Conditions
DATA OUTPUT TRANSMITTER acknowledge DATA OUTPUT RECEIVER acknowledge FROM MASTER START CONDITION clock pulse acknowledgement
Figure Acknowledge I2C-bus
data line stable; data valid
change data allowed
Figure Transfer I2C-bus
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Register
Addr Register Name Control Switch Main volume Zerocross Video switch Video output enable Video volume/clamp Blanking control Blanking monitor Monitor mask
DEM1 VMUTE VRF1 CLAMPB SBIO1 MCOMN
DEM0 VMONO VRF0 TVFB VCLP1 SBIO0
DIF1 VCR1 VVCR2 VCRC VCLP0 SBV1
DIF0 VCR0 DVOL1 VVCR1 VCRV CLAMP2 SBV0 TVMON
AUTO MONO DVOL0 VVCR0 CLAMP1 SBT1 VCMON
DAPD VTV2 CLAMP0 SBT0 FVCR MFVCR
MUTE MDT1 VTV1 VVOL1 SVCR1 MSVCR
STBY MDT0 VTV0 VVOL0 SVCR0
Note: When goes "L", registers initialized their default values. Note: While ="H", registers accessed. Note: write data register over 09H.
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Register Definitions
Addr Register Name Control default DEM1 DEM0 DIF1 DIF0 AUTO DAPD MUTE STBY
STBY: Standby control Normal Operation Standby Mode (default). Gain Volume#1 Source TVOUT Source VCROUT Source MONOOUT Source TVVOUT Source TVRC Source Source Source TVFB Source TVSB Source VCRVOUT Source VCRC
powered down timings reset. fixed fixed VCRIN fixed TVIN fixed VCRIN fixed VCRVIN(or Hi-Z) fixed VCRRC(or Hi-Z) fixed VCRG(or Hi-Z) fixed VCRB(or Hi-Z) fixed VCRFB Hi-Z) fixed VCRSB fixed TVVIN(or Hi-Z) fixed Hi-Z VSS(controlled bit)
MUTE: Audio output control Normal operation Audio outputs (default) DAPD: power down control Normal operation (default). power down. When DAPD "1", soft transition volume does work. AUTO: Auto startup Auto startup disable (Manual startup). Auto startup enable (default). Note: When SBIO1bit "1"(default= "0"), change AUTO cause pulse pin. DIF1-0: Audio data interface format control 16bit Justified 18bit Justified 24bit Justified 24bit Compatible (default) DEM1-0: De-emphasis Response Control 44.1kHz (default) 48kHz 32kHz
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Addr
Register Name Switch default
VMUTE
VCR1
VCR0
MONO
TV1-0: TVOUTL/R pins source switch VCRINL/R pins (default) MUTE (Reserved) VOL: MONOOUT source switch Bypass volume (fixed out) Through volume (default) MONO: Mono select TVOUTL/R pins Stereo. (default) Mono. (L+R)/2 VCR1-0: VCROUTL/R pins source switch TVINL/R pins (default) MUTE Volume output VMUTE: Mute switch volume Normal operation Mute volume (default)
Addr
Register Name Main volume default
L5-0: Volume control Those registers control both Volume 111111 100011: (Reserved) 100010: Volume gain +6dB 100001: Volume gain +4dB 100000: Volume gain +2dB 011111: Volume gain +0dB (default) 011110: Volume gain -2dB 000011: Volume gain -56dB 000010: Volume gain -58dB 000001: Volume gain -60dB 000000: Volume gain Mute
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Addr
Register Name Zerocross default
VMONO
DVOL1
DVOL0
MDT1
MDT0
MDT1-0: time length control volume transition time typ. 256/fs 512/fs 1024/fs 2048/fs (default) MOD: Soft transition enable volume control Disable volume value changes immediately without soft transition. Enable (default) volume value changes with soft transition. This function disabled when STBY DAPD "1". DVOL1-0: Volume #0/Volume control. Refer Table Table VMONO: Mono select VCROUTL/R pins Stereo. (default) Mono. (L+R)/2
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Addr
Register Name Video switch default
VRF1
VRF0
VVCR2
VVCR1
VVCR0
VTV2
VTV1
VTV0
VTV2-0: Selector video output Refer Table VVCR2-0: Selector video output Refer Table VRF1-0: Selector output. Refer Table Addr Register Name
Output enable
TVFB
VCRC
VCRV
default TVV: TVR: TVG: TVB: VCRV: VCRC: TVFB:
TVVOUT output control TVRCOUT output control TVGOUT output control TVBOUT output control VCRVOUT output control VCRC output control (Table TVFB output control Hi-Z (default) Active.
When "1", VCRC connected even VCRC= "0". When "0", VCRC follows setting VCRC bit. CIO: VCRC control Refer Table
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Addr
Register Name Video volume default
CLAMPB
VCLP1
VCLP0
CLAMP2
CLAMP1
CLAMP0
VVOL1
VVOL0
VVOL1-0: video gain control +6dB (default) +7.2dB +8.2dB +9.1dB CLAMPB, CLAMP2-0: Clamp control. Refer Table Table Table VCLP1-0: restore source control ENCV (default) ENCY VCRVIN (Reserved) When AUTO "1", source fixed VCRVIN pin. Addr Register Name Blanking default SBIO1 SBIO0
SBV1
SBV0
SBT1
SBT0
FB1-0: Fast Blanking output control (for TVFB pin) (default) follow input (4V/0V) (Reserved) SBT1-0: Slow Blanking output control (for TVSB pin. Minimum load 10kohm.) (default) (Reserved) 10V< SBV1-0: Slow Blanking output control (for VCRSB pin. Minimum load 10kohm) (default) (Reserved) 10V< SBIO1-0: TV/VCR Slow Blanking control (Table
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Addr
Register Name Monitor default
TVMON READ
VCMON
FVCR
SVCR1
SVCR0
SVCR1-0: Slow blanking status monitor SVCR1-0 reflect voltage VCRSB only when VCRSB input mode. When VCRSB output mode, SVCR1-0 hold previous value.
VCRSB input level SVCR1 SVCR0 (Reserved) 9.5< Table Slow Blanking monitor FVCR: Fast blanking input level monitor This enabled when TVFB "1". VCRFB input level FVCR <0.4V Table Fast Blanking monitor (Typical threshold 0.7V) VCMON: TVMON: Refer Table
Addr
Register Name
Monitor mask
MCOMN
MFVCR
MSVCR
default
MSVCR: SVCR1-0 Monitor mask. reflects change SVCR1-0 bits. (default) does reflect change SVCR1-0 bit. MFVCR: FVCR Monitor mask. reflects change MFVCR bit. (default) does reflect change MFVCR bit. MVC: MTV: Refer Table Table
MCOMN:.
Refer Table
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SYSTEM DESIGN
MONOOUT
CVBS Audio MONO
Phono
TVOUTL TVOUTR TVRC TVFB TVVOUT CVBS/Y Encoder G/CVBS MCLK MPEG Decoder BICK LRCK SDATA Interrupt ENCV ENCY ENCC ENCRC ENCGV ENCB MCLK BICK LRCK SDTI TVVIN TVINL TVINR TVSB VCRFB VCRVIN VCRRC VCRC VCRG VCRB VCRINL Micro Processor VCRINR VCRVOUT VCROUTL VCROUTR VCRSB
Audio Audio Fast Blank Y/CVBS Y/CVBS Audio Audio Slow Blank Fast Blank Y/CVBS SCART
Audio Audio Y/CVBS Audio Audio Slow Blank SCART
Figure Typical Connection Diagram
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Grounding Power Supply Decoupling
VVD1, VVD2, VVSS should supplied from analog supply unit with impedance separated from system digital supply. electrolytic capacitor parallel with 0.1F ceramic capacitor should attached these pins eliminate effects high frequency noise. 0.1F ceramic capacitors should placed near (VP, VVD1, VVD2) possible.
Voltage Reference
DVCOM PVCOM signal common this chip. electrolytic capacitor parallel with 0.1F ceramic capacitor should attached these VCOM pins eliminate effects high frequency noise. load current taken from these VCOM pins. signals, especially clocks, should kept away from these VCOM pins order avoid unwanted coupling into AK4705A.
Analog Audio Outputs
analog outputs also single-ended centered 5.6V(typ.). output signal range typically 2Vrms (typ@VD=5V). internal switched-capacitor filter continuous-time filter attenuate noise generated delta-sigma modulator beyond audio pass band. Therefore, external filters required typical application. output voltage positive full scale 7FFFFFH (@24bit) negative full scale 800000H (@24bit). ideal output 5.6V(typ.) 000000H (@24bit). voltage offset analog outputs eliminated coupling.
REFI
REFI video current reference pin. This should connected VVD1 through 10k±1% resistor externally shown Figure load current drawn from this pin. signals, especially clocks, should kept away from this order avoid unwanted coupling.
AK4705A
VDD1 R=10k±1% IREF
Figure REFI
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External Circuit Example
Analog Audio Input
300ohm TVINL/R VCRINL/R DACL/R
(Cable)
0.47F
Analog Audio Output
MONOOUT TVOUTL/R VCROUTL/R
300ohm
(Cable)
Total 4.5kohm
Analog Video Input
ENCV, ENCY, VCRVIN, TVVIN, ENCRC, ENCC, VCRRC, ENCG, VCRG, ENCB, VCRB
75ohm
(Cable) 75ohm
0.1F
Analog Video Output
TVVOUT, TVRC TVG, TVR, VCRVOUT, VCRC 15pF 75ohm
(Cable) 400pF 75ohm
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Slow Blanking
TVSB VCRSB 400ohm
(max 500ohm)
(Cable) (with 400ohm) min:
Fast Blanking Input
VCRFB 75ohm (Cable) 75ohm
Fast Blanking Output
75ohm TVFB (Cable) 75ohm
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PACKAGE
48pin LQFP(Unit:mm)
1.70Max 0.13 0.13 1.40 0.05
0.22 0.08
0.09~0.20 0.10
0.10
0.3~0.75
Package Lead frame material
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Solder free) plate
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MARKING
4705AEQ XXXXXXX
XXXXXXXX: Date code identifier
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IMPORTANT NOTICE These products their specifications subject change without notice. When consider application these products, please make inquiries sales office Asahi Kasei Corporation (AKEMD) authorized distributors current status products. AKEMD assumes liability infringement patent, intellectual property, other rights application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. AKEMD products neither intended authorized critical componentsNote1) safety, life support, other hazard related device systemNote2), AKEMD assumes responsibility such use, except approved with express written consent Representative Director AKEMD. used here: Note1) critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. Note2) hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. responsibility buyer distributor AKEMD products, distributes, disposes otherwise places product with third party, notify such third party advance above content conditions, buyer distributor agrees assume responsibility liability hold AKEMD harmless from claims arising from said product absence such notification.
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AK4705A AK4702 04

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