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AK4392 - AK4392
[AK4392]
AK4392
High Performance 120dB Premium 32-Bit
GENERAL DESCRIPTION AK4392 32-bit DAC, which corresponds DVD-Audio systems. internal circuit includes newly developed 32bit Digital Filter better sound quality achieving distortion characteristics wide dynamic range. AK4392 full differential outputs, removing need coupling capacitors increasing performance systems with excessive clock jitter. AK4392 accepts 192kHz data 1-bit data, ideal wide range applications including Blu-Ray, DVD-Audio SACD. FEATURES 128x Over sampling Sampling Rate: 30kHz 216kHz 32Bit Digital Filter (Minimum delay option GD=7/fs) Ripple: ±0.005dB, Attenuation: 100dB High Tolerance Clock Jitter Distortion Differential Output data input Digital De-emphasis 44.1, 48kHz sampling Soft Mute Digital Attenuator (255 levels 0.5dB step) Mono Mode External Digital Filter Mode THD+N: -103dB S/N: 120dB Format: 24/32bit justified, 16/20/24/32bit justified, I2S, Master Clock: 30kHz 32kHz: 1152fs 30kHz 54kHz: 512fs 768fs 30kHz 108kHz: 256fs 384fs 108kHz 216kHz: 128fs 192fs Power Supply: 4.75 5.25V Digital Input Level: Package: 44pin LQFP
MS1045-E-02
2009/04
[AK4392]
Block Diagram
DVDD VSS3 AVDD VSS4 VSS2 VDDL Data Interface Interpolator AOUTLP AOUTLN VCML VREFHL VREFLL VREFLR VREFLL VCMR AOUTRP AOUTRN
BICK/DCLK LRCK/DSDR/WCK SDATA/DSDL
Data Interface
DATT Soft Mute
Modulator
Bias Vref
DINL DINR
External Interface
CSN/SMUTE CCLK/DEM0 CDTI/DEM1 Control Register Clock Divider
VDDR
VSS1
CAD0 CAD1/DIF0
DZFL/DIF1 DIF2
MCLK
DZFR
Block Diagram
MS1045-E-02
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[AK4392]
Ordering Guide
AK4392EQ AKD4392 +70°C 44pin LQFP (0.8mm pitch) Evaluation Board AK4392
Layout
AOUTRN VREFHR AOUTLN VREFHL VREFLR VREFLL
VDDR
VSS2
VCML VSS3 AVDD VSS4
View
VSS1
AOUTRP VCMR TST2/DZFR
AK4392
LRCK/DSDR/WCK
DEM0/CCLK
SDATA/DSDL
DEM1/CDTI
BICK/DCLK
TST1/CAD0
MS1045-E-02
SMUTE/CSN
DIF0/CAD1
DIF1/DZFL
DVDD
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[AK4392]
PIN/FUNCTION
Name DVDD BICK DCLK SDATA DSDL LRCK DSDR SMUTE TST1 CAD0 DEM0 CCLK DEM1 CDTI DIF0 CAD1 DIF1 DZFL DIF2 Function Digital Power Supply Pin, 4.75 5.25V Power-Down Mode When "L", AK4392 power-down mode held reset. AK4392 should always reset upon power-up. Audio Serial Data Clock Mode Clock Mode Audio Serial Data Input Mode Data Input Mode Clock Mode Data Input Mode Word Clock input Soft Mute Parallel Control Mode When this changed "H", soft mute cycle initiated. When returning "L", output mute releases. Chip Select Serial Control Mode Test Parallel Control Mode (Internal pull-down pin) Chip Address Serial Control Mode (Internal pull-down pin) De-emphasis Enable Parallel Control Mode Control Data Clock Serial Control Mode De-emphasis Enable Parallel Control Mode Control Data Input Serial Control Mode Digital Input Format Mode Chip Address Serial Control Mode Digital Input Format Mode Zero Input Detect Serial Control Mode Digital Input Format Mode internal bonding. Connect GND.
Note: input pins except internal pull-up/down pins must left floating.
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[AK4392]
TST2 DZFR DINR DINL VCMR AOUTRP AOUTRN VSS1 VDDR VREFHR VREFLR VREFLL VREFHL VDDL VSS2 AOUTLN AOUTLP VCML VSS3 AVDD MCLK VSS4
Parallel Serial Select (Internal pull-up pin) "L": Serial Control Mode, "H": Parallel Control Mode Test Parallel Control Mode. Connect GND. Zero Input Detect Serial Control Mode Audio Serial Data Clock (Internal pull-down pin) internal bonding. Connect GND. Audio Serial Data Input (Internal pull-down pin) Audio Serial Data Input (Internal pull-down pin) internal bonding. Connect GND. Right channel Common Voltage Pin, Normally connected with 10uF electrolytic cap. Positive Analog Output Negative Analog Output Ground Analog Power Supply Pin, 4.75 5.25V High Level Voltage Reference Input Level Voltage Reference Input internal bonding. Connect GND. Level Voltage Reference Input High Level Voltage Reference Input Analog Power Supply Pin, 4.75 5.25V Ground Negative Analog Output Positive Analog Output Left channel Common Voltage Pin, Normally connected with 10uF electrolytic cap. internal bonding. Connect GND. internal bonding. Connect GND. internal bonding. Connect GND. internal bonding. Connect GND. Ground Analog Power Supply Pin, 4.75 5.25V Master Clock Input Ground internal bonding. Connect GND.
Note: input pins except internal pull-up/down pins must left floating.
MS1045-E-02
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[AK4392]
Handling Unused
unused pins should processed appropriately below. Parallel Mode (PCM Mode only) Classification Analog Name AOUTLP, AOUTLN AOUTRP, AOUTRN SMUTE TST1 TST2 Setting These pins must open. These pins must open. This must connected VSS4. This must open. This must connected VSS4.
Digital
Serial Mode Mode Classification Analog Digital Name AOUTLP, AOUTLN AOUTRP, AOUTRN DIF2 DZFL, DZFR Setting These pins must open. These pins must open. These pins must connected VSS4. These pins must open.
Mode Classification Analog Name AOUTLP, AOUTLN AOUTRP, AOUTRN DZFL, DZFR Setting These pins must open. These pins must open. These pins must open.
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[AK4392]
ABSOLUTE MAXIMUM RATINGS
(VSS1-4 =0V; Note Parameter Power Supplies: Analog Analog Digital Symbol AVDD VDDL/R DVDD VIND Tstg -0.3 -0.3 -0.3 -0.3 DVDD+0.3 Units
Input Current, Except Supplies Digital Input Voltage Ambient Temperature (Power applied) Storage Temperature
Note voltages with respect ground. Note VSS1-4 must connected same analog ground plane. WARNING: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes.
RECOMMENDED OPERATING CONDITIONS (VSS1-4 =0V; Note Parameter Symbol 4.75 AVDD Analog Power Supplies 4.75 VDDL/R Analog (Note 4.75 DVDD Digital AVDD-0.5 VREFHL/R voltage reference Voltage VREFLL/R voltage reference Reference VREF VREFH VREFL (Note
Note voltages with respect ground. Note power sequence between AVDD, VDDL/R DVDD critical. Note analog output voltage scales with voltage (VREFH VREFL). AOUT (typ.@0dB) (AOUT+) (AOUT-) ±2.8Vpp (VREFHL/R VREFLL/R)/5. assumes responsibility usage beyond conditions this data sheet.
5.25 5.25 5.25 AVDD AVDD
Units
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[AK4392]
ANALOG CHARACTERISTICS (Ta=25°C; AVDD=VDDL/R=DVDD=5.0V; VSS1-4 =0V; VREFHL/R=AVDD, VREFLL/R= VSS; Input data 24bit; BICK=64fs; Signal Frequency 1kHz; Sampling Frequency 44.1kHz; Measurement bandwidth 20Hz 20kHz; External Circuit: Figure unless otherwise specified.) Parameter Resolution Dynamic Characteristics (Note 0dBFS -103 fs=44.1kHz THD+N BW=20kHz -60dBFS 0dBFS fs=96kHz BW=40kHz -60dBFS 0dBFS fs=192kHz BW=40kHz -60dBFS BW=80kHz -60dBFS Dynamic Range (-60dBFS with A-weighted) (Note (A-weighted) (Note Interchannel Isolation (1kHz) Accuracy Interchannel Gain Mismatch 0.15 Gain Drift (Note Output Voltage (Note ±2.65 ±2.8 ±2.95 Load Capacitance Load Resistance (Note Power Supplies Power Supply Current Normal operation (PDN "H") AVDD VDDL/R DVDD 96kHz) DVDD 192kHz) Power down (PDN "L") (Note AVDD+VDDL/R+DVDD
Units Bits ppm/°C
Note Measured Audio Precision, System Two. Averaging mode. Refer evaluation board manual. Note Figure External Circuit Example 101dB 16-bit data 118dB 20-bit data. Note Figure External Circuit Example does depend input data size. Note voltage (VREFH VREFL) held externally. Note Full-scale voltage(0dB). Output voltage scales with voltage (VREFHL/R VREFLL/R). AOUT (typ.@0dB) (AOUT+) (AOUT-) ±2.8Vpp (VREFHL/R VREFLL/R)/5. Note Regarding Load Resistance, load (min) with capacitor (Figure 20). load 1.5k (min) without capacitor (Figure 19). load resistance value with respect ground. Analog characteristics sensitive capacitive load that connected output pin. Therefore capacitive load must minimized. Note power down mode. DVDD, other digital input pins including clock pins (MCLK, BICK LRCK) held VSS4.
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[AK4392]
SHARP ROLL-OFF FILTER CHARACTERISTICS 44.1kHz) (Ta=25°C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Normal Speed Mode; DEM=OFF; bit="0") Parameter Symbol Units Digital Filter Passband (Note ±0.01dB 20.0 -6.0dB 22.05 Stopband (Note 24.1 Passband Ripple ±0.005 Stopband Attenuation Group Delay (Note 1/fs Digital Filter Frequency Response: 20.0kHz ±0.2
SHARP ROLL-OFF FILTER CHARACTERISTICS 96kHz) (Ta=25°C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Double Speed Mode; DEM=OFF; bit="0") Parameter Symbol Units Digital Filter Passband (Note ±0.01dB 43.5 -6.0dB 48.0 Stopband (Note 52.5 Passband Ripple ±0.005 Stopband Attenuation Group Delay (Note 1/fs Digital Filter Frequency Response: 40.0kHz ±0.3
SHARP ROLL-OFF FILTER CHARACTERISTICS 192kHz) (Ta=25°C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Quad Speed Mode; DEM=OFF; bit="0") Parameter Symbol Units Digital Filter Passband (Note ±0.01dB 87.0 -6.0dB 96.0 Stopband (Note Passband Ripple ±0.005 Stopband Attenuation Group Delay (Note 1/fs Digital Filter Frequency Response: 80.0kHz +0/-1
Note passband stopband frequencies scale with example, (@±0.01dB), Note calculating delay time which occurred digital filtering. This time from setting 16/20/24bit data both channels input register output analog signal.
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[AK4392]
MINIMUM DELAY FILTER CHARACTERISTICS 44.1kHz) (Ta=25°C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Normal Speed Mode; DEM=OFF; bit="1") Parameter Symbol Units Digital Filter Passband (Note ±0.01dB 20.0 -6.0dB 22.05 Stopband (Note 24.1 Passband Ripple ±0.005 Stopband Attenuation Group Delay (Note 1/fs Digital Filter Frequency Response 20.0kHz ±0.2
MINIMUM DELAY FILTER CHARACTERISTICS 96kHz) (Ta=25°C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Double Speed Mode; DEM=OFF; bit="1") Parameter Symbol Units Digital Filter Passband (Note ±0.01dB 43.5 -6.0dB 48.0 Stopband (Note 52.5 Passband Ripple ±0.005 Stopband Attenuation Group Delay (Note 1/fs Digital Filter Frequency Response 40.0kHz ±0.3
MINIMUM DELAY FILTER CHARACTERISTICS 192kHz) (Ta=25°C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V; Quad Speed Mode; DEM=OFF; bit="1") Parameter Symbol Units Digital Filter Passband (Note ±0.01dB 87.0 -6.0dB 96.0 Stopband (Note Passband Ripple ±0.005 Stopband Attenuation Group Delay (Note 1/fs Digital Filter Frequency Response 80.0kHz +0/-1
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[AK4392]
CHARACTERISTICS (Ta=25°C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V) Parameter Symbol High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (Iout=-100A) DVDD-0.5 Low-Level Output Voltage (Iout=100A) Input Leakage Current (Note
Units
Note TST1/CAD0 pins have internal pull-up devices, nominally 100k. Therefore TST1/CAD0 pins included.
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[AK4392]
SWITCHING CHARACTERISTICS (Ta=25°C; AVDD=VDDL/R=4.75 5.25V, DVDD=4.75 5.25V) Parameter Symbol Master Clock Timing Frequency fCLK Duty Cycle dCLK LRCK Frequency (Note 1152fs, 512fs 768fs 256fs 384fs 128fs 192fs Duty Cycle Duty Audio Interface Timing BICK Period 1/128fsn tBCK 1152fs, 512fs 768fs 1/64fsd tBCK 256fs 384fs 1/64fsq tBCK 128fs 192fs tBCKL BICK Pulse Width tBCKH BICK Pulse Width High tBLR BICK LRCK Edge (Note tLRB LRCK Edge BICK (Note tSDH SDATA Hold Time tSDS SDATA Setup Time External Digital Filter Mode BICK Period Pulse Width Pulse Width High Edge Edge tWCK Pulse Width tWCH Pulse Width High DATA Hold Time DATA Setup Time Audio Interface Timing 1/64fs tDCK DCLK Period tDCKL DCLK Pulse Width tDCKH DCLK Pulse Width High tDDD DCLK Edge DSDL/R (Note Control Interface Timing tCCK CCLK Period tCCKL CCLK Pulse Width tCCKH Pulse Width High tCDS CDTI Setup Time tCDH CDTI Hold Time tCSW High Time tCSS CCLK tCSH CCLK Reset Timing Pulse Width (Note
41.472
Units
MS1045-E-02
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[AK4392] Note When 1152fs, 512fs 768fs /256fs 384fs /128fs 192fs switched, AK4392 should reset RSTN bit. Note BICK rising edge must occur same time LRCK edge. Note data transmitting device must meet this time. Note AK4392 reset bringing upon power-up.
Timing Diagram
1/fCLK tCLKH tCLKL
dCLK=tCLKH fCLK, tCLKL fCLK
MCLK
1/fs
tBCK tBCKH tBCKL
LRCK
BICK
1/fs
Clock Timing
MS1045-E-02
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[AK4392]
LRCK tBLR tLRB
BICK tSDS tSDH
SDATA
Audio Interface Timing (PCM Mode)
tDCK tDCKL tDCKH tDDD DSDL DSDR
DCLK
Audio Serial Interface Timing (DSD Normal Mode, DCKB "0")
tDCK tDCKL tDCKH tDDD DSDL DSDR tDDD
DCLK
Audio Serial Interface Timing (DSD Phase Modulation Mode, DCKB "0")
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[AK4392]
tCSS tCCKL tCCKH tCDS tCDH
CCLK
CDTI
WRITE Command Input Timing
tCSW tCSH CCLK
CDTI
WRITE Data Input Timing
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[AK4392]
Power Down Reset Timing
DATA
External Digital Filter mode
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[AK4392]
OPERATION OVERVIEW
Conversion Mode
serial mode, AK4392 perform conversion either data data. controls PCM/DSD mode. When mode, data input from DCLK, DSDL DSDR pins. When mode, data input from BICK, LRCK SDATA pins. When PCM/DSD mode changed bit, AK4392 should reset RSTN bit. takes about 2/fs 3/fs change mode. parallel mode, AK4392 performs only data. Interface Table PCM/DSD Mode Control When bit= "0", internal digital filter external digital filter selected. When using external digital filter mode), data input each MCLK, BCK, WCK, DINL DINR pin. EXDF controls modes. When switching internal external digital filters, AK4392 must reset RSTN bit. Digital filter switching takes 2~3k/fs. Interface Table Digital Filter Control "0")
System Clock
Mode external clocks, which required operate AK4392, MCLK, BICK LRCK. MCLK should synchronized with LRCK phase critical. MCLK used operate digital interpolation filter delta-sigma modulator. Sampling speed MCLK frequency detected automatically then initial master clock appropriate frequency (Table When external clocks changed, AK4392 should reset RSTN bit. AK4392 automatically placed reset state when MCLK LRCK stopped during normal operation (PDN ="H"), analog output becomes Hi-Z. When MCLK LRCK input again, AK4392 exit reset state starts operation. After exiting system reset (PDN ="L""H") power-up other situations, AK4392 power-down mode until MCLK LRCK supplied. MCLK frequency corresponding each sampling speed should provided (Table MCLK 1152fs 512fs 256fs 128fs Mode Normal 768fs Normal 384fs Double 192fs Quad Table Sampling Speed Sampling Rate 30kHz~32kHz 30kHz~54kHz 30kHz~108kHz 108kHz~216kHz
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[AK4392]
LRCK 32.0kHz 44.1kHz 48.0kHz 88.2kHz 96.0kHz 176.4kHz 192.0kHz
MCLK (MHz) 128fs 192fs 256fs 384fs 512fs 768fs 8.1920 12.2880 16.3840 24.5760 11.2896 16.9344 22.5792 33.8688 12.2880 18.4320 24.5760 36.8640 22.5792 33.8688 24.5760 36.8640 22.5792 33.8688 24.5760 36.8640 Table System Clock Example (Parallel Control Mode) (N/A: available)
1152fs 36.8640
MCLK= 256fs/384fs supports sampling rate 30kHz~108kHz (Table But, when sampling rate 30kHz~54kHz, will degrade approximately compared when MCLK= 512fs/768fs. MCLK DR,S/N 256fs/384fs 117dB 512fs/768fs 120dB Table Relationship between MCLK frequency (fs= 44.1kHz)
Mode external clocks, which required operate AK4392, MCLK DCLK. MCLK should synchronized with DCLK phase critical. frequency MCLK DCKS bit. AK4392 automatically placed reset state when MCLK stopped during normal operation (PDN ="H"), analog output becomes Hi-Z. After exiting system reset (PDN ="L""H") power-up other situations, AK4392 power-down mode until MCLK supplied. DCKS MCLK Frequency DCLK Frequency 512fs 64fs 768fs 64fs Table System Clock (DSD Mode)
(default)
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[AK4392]
Audio Interface Format
Mode Data shifted SDATA using BICK LRCK inputs. Eight data formats supported selected DIF2-0 pins (Parallel control mode) DIF2-0 bits (Serial control mode) shown Table formats serial data MSB-first, compliment format latched rising edge BICK. Mode used 20-bit 16-bit justified formats zeroing unused LSBs. Settings should made DIF2-0 pins parallel mode DIF2-0 bits serial mode. Mode DIF2 DIF1 DIF0 Input Format 16bit justified 20bit justified 24bit justified 24bit Compatible 24bit justified 32bit justified 32bit justified 32bit Compatible Table Audio Interface Format BICK 32fs 48fs 48fs 48fs 48fs 64fs 64fs 64fs Figure Figure Figure Figure Figure Figure Figure Figure Figure
(default)
LRCK
BICK (32fs) SDATA Mode
BICK (64fs) SDATA Mode
Don't care 15:MSB, 0:LSB Don't care
Data
Figure Mode Timing
Data
LRCK
BICK (64fs) SDATA Mode SDATA Mode
Don't care 19:MSB, 0:LSB Don't care Don't care Don't care
23:MSB, 0:LSB
Data
Figure Mode Timing MS1045-E-02
Data
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[AK4392]
LRCK
BICK (64fs) SDATA
23:MSB, 0:LSB Don't care Don't care
Data
Figure Mode Timing
Data
LRCK
BICK (64fs) SDATA
23:MSB, 0:LSB Don't care Don't care
Data
Figure Mode Timing
Data
LRCK
BICK(128fs) SDATA
BICK(64fs) SDATA
Data MSB, 0:LSB
Data
Figure Mode Timing
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[AK4392]
LRCK
BICK(128fs) SDATA BICK(64fs) SDATA
Data MSB, 0:LSB
Data
Figure Mode Timing
LRCK
BICK(128fs) SDATA
BICK(64fs) SDATA
Data MSB, 0:LSB
Data
Figure Mode Timing
Mode case mode, DIF2-0 pins DIF2-0 bits ignored. frequency DCLK fixed 64fs. DCKB invert polarity DCLK.
DCLK (64fs) DCKB=1 DCLK (64fs) DCKB=0 DSDL,DSDR Normal DSDL,DSDR
Phase Modulation
Figure Mode Timing
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[AK4392]
External Digital Filter Mode Mode) indicates number cycle. audio data input MCLK, from DINL DINR pins. Three formats available (Table DIF2-0 bits setting. data latched rising edge BCK. MCLK clocks must same frequency must burst. MCLK frequencies each sampling speed shown Table AK4392 automatically placed reset state when MCLK stopped during normal operation (PDN ="H"), analog output becomes Hi-Z. When MCLK input again, AK4392 exit reset state starts operation. After exiting system reset (PDN ="L""H") power-up other situations, AK4392 power-down mode until MCLK supplied. Sampling Speed[kHz] 44.1(30~54) 44.1(30~54) 96(54~108) 96(54~108) 192(108~216) 192(108~216) MCLK&BCK [MHz] 128fs 12.288
24.576
192fs
18.432
256fs 11.2896
24.576
384fs
16.9344
512fs
22.5792
768fs
33.8688
33.8688
36.864
36.864
36.864
36.864
Table System Clock Example mode) (N/A: available)
16fs
Mode DIF2 DIF1 DIF0 Input Format 16bit justified 24bit justified 32bit justified Table Audio Interface Format mode) (N/A: available)
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[AK4392]
1/16fs 1/8fs 1/4fs 1/2fs
DINL DINR
DINL DINR DINL DINR
Don't care Don't care Don't care Don't care Don't care
Don't care
Don't care
Don't care
Figure Mode Timing
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[AK4392]
Conversion Mode Switching Timing
RSTN
4/fs
Mode
Mode
Mode
Data
Data
Data
Figure Mode Switching Timing (PCM DSD)
RSTN Mode
Mode 4/fs
Mode
Data
Data
Data
Figure Mode Switching Timing (DSD PCM) Note. signal range identified duty ratios mode. signal must beyond this duty range SACD format book (Scarlet Book).
De-emphasis Filter
digital de-emphasis filter available 32kHz, 44.1kHz 48kHz sampling rates 50/15µs) enabled disabled with DEM1-0 pins DEM1-0 bits. case 256fs/384fs 128fs/192fs, digital de-emphasis filter always off. When mode, DEM1-0 bits ignored. setting value held even mode mode switched. DEM1 DEM0 Mode 44.1kHz (default) 48kHz 32kHz Table De-emphasis Control
Output Volume
AK4392 includes channel independent digital output volumes (ATT) with levels linear step including MUTE. These volume control front attenuate input data from -127dB mute. When changing output levels, transitions executed soft change; thus switching noise occurs during these transitions.
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[AK4392]
Zero Detection (PCM mode, mode)
AK4392 channel-independent zeros detect function. When input data each channel continuously zeros 8192 LRCK cycles, each channel goes "H". each channel immediately return input data each channel zero after going "H". RSTN "0", pins both channels "H". pins both channels 5/fs after RSTN returns "1". DZFM "1", pins both channels only when input data both channels continuously zeros 8192 LRCK cycles. zero detect function disabled setting DZFE bit. this case, pins both channels always "L". DZFB invert polarity pin.
Mono Output
AK4392 select input/output both output channels setting MONO SELLR bit. This function available audio format.
MONO
SELLR
Table MONO Mode Output Select
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[AK4392]
Soft Mute Operation
soft mute operation performed digital domain. When SMUTE goes SMUTE "1", output signal attenuated during ATT_DATA transition time from current level. When SMUTE returned SMUTE returned "0", mute cancelled output attenuation gradually changes level during ATT_DATA transition time. soft mute cancelled before attenuating after starting operation, attenuation discontinued returned level same cycle. soft mute effective changing signal source without stopping signal transmission.
_Level ttenuation
AOUT 8192/fs
Notes: ATT_DATA transition time. example, this time 1020LRCK cycles (1020/fs) ATT_DATA=255 Normal Speed Mode. analog output corresponding digital input group delay (GD). soft mute cancelled before attenuating after starting operation, attenuation discontinued returned level same cycle. When input data each channel continuously zeros 8192 LRCK cycles, each channel goes "H". immediately returns input data zero. Figure Soft Mute Function
System Reset
AK4392 should reset once bringing upon power-up. initializes register settings device. AK4392 exits this system reset (power-down mode) MCLK LRCK after "H", analog block exits power-down mode. digital block exits power-down mode after internal counter counts MCLK 4/fs.
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[AK4392]
Power ON/OFF timing
AK4392 placed power-down mode bringing registers initialized. analog outputs floating (Hi-Z). some click noise occurs edge signal, analog output should muted externally click noise influences system application. reset setting RSTN "0". this case, registers initialized corresponding analog outputs VCML/R. some click noise occurs edge RSTN signal, analog output should muted externally click noise aversely affect system performance.
Power
Internal State
Normal Operation
Reset
(Digital)
"0"data
"0"data
(Analog) Clock
MCLK,LRCK,BICK
Don't care
Don't care
DZFL/DZFR
External Mute
Mute
Mute
Notes: After AVDD DVDD powered-up, should 150ns. analog output corresponding digital input group delay (GD). Analog outputs floating (Hi-Z) power-down mode. Click noise occurs edge signal. This noise output even data input. MCLK, BICK LRCK clocks stopped power-down mode (PDN pin= "L"). Mute analog output externally click noise adversely affect system performance timing example shown this figure. DZFL/R pins power-down mode (PDN "L"). Figure Power-down/up Sequence Example
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[AK4392]
Reset Function
RESET RSTN When RSTN "0", AK4392's digital block powered down, internal register values initialized. this time, analog outputs VCML/R voltage DZFL/DZFR pins "H". Figure shows example reset RSTN bit.
RSTN
3~4/fs 2~3/fs
Internal RSTN Internal State (Digital) (Analog)
Normal Operation
igital Block
Normal peration
data
fs(4)
Notes: analog output corresponding digital input group delay (GD). Analog outputs settle VCOM voltage. Small noise occurs edges(" internal timing RSTN bit. This noise output even data input. pins change when RSTN becomes "0", return 2/fs after RSTN becomes "1". There delay, 3~4/fs from RSTN internal RSTN "0", 2~3/fs from RSTN internal RSTN "1". Mute analog output externally click noise Hi-Z adversely affect system performance Figure Reset Sequence Example
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[AK4392] RESET MCLK LRCK/WCK Stop AK4392 automatically placed reset state when MCLK LRCK stopped during mode (RSTN ="H"), analog outputs floating (Hi-Z). When MCLK LRCK input again, AK4392 exits reset state starts operation. Zero detect function disable when MCLK LRCK stopped. mode AK4392 reset state when MCLK stopped, reset state when MCLK stopped external digital filter mode.
AVDD DVDD RSTB
Internal State (Digital)
Power-down
Normal peration
Digital Circuit ower-down
Normal Operation
Power-down
MCLK, BICK, LRCK Stop
(Analog)
Clock
MCLK, BICK, LRCK
Hi-Z
External MUTE
Notes: After AVDD DVDD powered-up, should 150ns. analog output corresponding digital input group delay (GD). digital data stopped. Click noise after MCLK, BICK LRCK input again reduced inputting data during this period. Click noise occurs within 4LRCK cycles from riding edge ("") MCLK inputs. This noise occurs even when data input. Clocks (MCLK, BICK, LRCK) stopped reset state (MCLK LRCK stopped). Mute analog output externally click noise influences system applications. timing example shown this figure. Figure Reset Sequence Example
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[AK4392]
Register Control Interface
Pins (parallel control mode) registers (serial control mode) control functions AK4392. parallel control mode, register setting ignored, serial control mode settings ignored. When state changed, AK4392 should reset pin. serial control interface enabled "L". this mode, settings must "L". Internal registers written through3-wire interface pins: CSN, CCLK CDTI. data this interface consists Chip address (2-bits, C1/0), Read/Write (1-bit; fixed "1"), Register address (MSB first, 5-bits) Control data (MSB first, 8-bits). AK4392 latches data rising edge CCLK, data should clocked falling edge. writing data valid when clock speed CCLK 5MHz (max). Function Parallel Control Mode Serial Control Mode Audio Format De-emphasis SMUTE Mode Minimum delay Filter Digital Attenuator Table Function List1 Available, available) Setting resets registers their default values. serial control mode, internal timing circuit reset RSTN bit, registers initialized.
CCLK
CDTI
C1-C0: Chip Address =CAD1 pin, =CAD0 pin) R/W: READ/WRITE (Fixed "1", Write only) A4-A0: Register Address D7-D0: Control Data Figure Control Timing AK4392 does support read command. When AK4392 power down mode (PDN "L") MCLK provided, writing into control registers prohibited. control data written when CCLK rising edge times less times more during "L".
MS1045-E-02
2009/04
[AK4392] Function List Function Attenuation Level Default Address ATT7-0
External Digital Filter Mode Disable EXDF mode clock setting 16fs(fs=44.1kHz) Audio Data Interface Modes 24bit justified DIF2-0 Data Zero Detect Enable Disable DZFE Data Zero Detect Mode Separated DZFM Minimum delay Filter Enable Sharp roll-off filter De-emphasis Response DEM1-0 Soft Mute Enable Normal Operation SMUTE DSD/PCM Mode Select mode Master Clock Frequency Select 512fs DCKS mode MONO mode Stereo mode select Stereo MONO Inverting Enable active DZFB data selection channel channel SELLR channel Table Function List2 Available, available)
MS1045-E-02
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[AK4392]
Register
Addr Register Name Control Control Control DZFE ATT7 ATT7 EXDF DZFM ATT6 ATT6 DCKS ATT5 ATT5 DCKB ATT4 ATT4 DIF2 MONO ATT3 ATT3 DIF1 DEM1 DZFB ATT2 ATT2 DIF0 DEM0 SELLR ATT1 ATT1 RSTN SMUTE ATT0 ATT0
Notes: Data must written into addresses from 1FH. When goes "L", registers initialized their default values. When RSTN "0", only internal timing reset, registers initialized their default values. When state changed, AK4392 should reset pin.
Register Definitions
Addr Register Name Control Default EXDF DIF2 DIF1 DIF0 RSTN
RSTN: Internal Timing Reset Reset. registers initialized. Normal Operation (default) When internal clocks changed, AK4392 should reset RSTN bit. DIF2-0: Audio Data Interface Modes (Table Initial value "010" (Mode 24-bit justified). ECS: mode clock setting (Table Disable: Internal Digital Filter mode (default) Enable: External Digital Filter mode EXDF: External Digital Filter Mode (Serial mode only) Disable: Internal Digital Filter mode (default) Enable: External Digital Filter mode
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[AK4392]
Addr Register Name Control Default DZFE DZFM DEM1 DEM0 SMUTE
SMUTE: Soft Mute Enable Normal Operation (default) outputs soft-muted. DEM1-0: De-emphasis Response (Table Initial value "01" (OFF). Minimum delay Filter Enable Sharp roll-off filter (default) Minimum delay filter Data Zero Detect Mode Channel Separated Mode (default) Channel ANDed Mode DZFM "1", pins both channels only when input data both channels continuously zeros 8192 LRCK cycles. Data Zero Detect Enable Disable (default) Enable Zero detect function disabled DZFE "0". this case, pins both channels always "L".
DZFM:
DZFE:
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[AK4392]
Addr Register Name Control Default DCKS DCKB MONO DZFB SELLR
SELLR: data selection channel channel, when MONO mode channel output channel data, when MONO mode. (default) channel output channel data, when MONO mode. enabled when MONO "1", outputs date both channels when "0",outputs data both channels when "1". DZFB: Inverting Enable goes Zero Detection (default) goes Zero Detection MONO: MONO mode Stereo mode select Stereo mode (default) MONO mode When MONO "1", MONO mode enabled. DCKB: Polarity DCLK (DSD Only) data output from DCLK falling edge. (default) data output from DCLK rising edge. DCKS: Master Clock Frequency Select mode (DSD only) 512fs (default) 768fs DSD/PCM Mode Select Mode (default) Mode When changed, AK4392 should reset RSTN bit.
ATT7 ATT7 ATT6 ATT6 ATT5 ATT5 ATT4 ATT4 ATT3 ATT3 ATT2 ATT2 ATT1 ATT1 ATT0 ATT0
Addr Register Name Default
ATT7-0: Attenuation Level levels, 0.5dB step Data Attenuation -0.5dB -1.0dB -126.5dB -127.0dB MUTE
transition between values soft transition 7425 levels. takes 7424/fs (168ms@fs=44.1kHz) from (0dB) (MUTE). goes "L", ATTs initialized FFH. ATTs when RSTN bit= "0". When RSTN return "1", ATTs fade their current value. This digital attenuator independent soft mute function.
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[AK4392]
SYSTEM DESIGN
Figure shows system connection diagram. Figure Figure Figure show analog output circuit examples. evaluation board (AKD4392) demonstrates optimum layout, power supply arrangements measurement results.
Analog5.0V
Master clock
Digital 5.0V
0.1u
VSS4
VSS3
MCLK
AVDD
VCML
0.1u SDATA LRCK CCLK CDTI
Reset 64fs Audio Data
AOUTLP
Mute
AOUTLN
VSS2 VDDL 0.1u
AK4392EQ
VREFHL VREFLL VREFLR
MicroController
View
EFHR VDDR VSS1 AOUTRP
AOUTRN
DZFL VCMR DZFR DINR DINL DIF2
Mute
Digital
Analog
Electrolytic Capacitor Ceramic Capacitor
Notes: Chip Address "00". BICK 64fs, LRCK Power lines AVDD DVDD should distributed separately from point with impedance regulator etc. VSS1-4 must connected same analog ground plane. When AOUT drives capacitive load, some resistance should connected series between AOUT capacitive load. input pins except pull-down/pull-up pins should allowed float. Figure Typical Connection Diagram (AVDD=VDDL/R=5V, DVDD=5V, Serial control mode)
MS1045-E-02
2009/04
[AK4392]
Digital Ground
Analog Ground
AVDD
AOUTLP AOUTLN
DVDD BICK/DCLK SDATA/DSDL LRCK/DSDR/WCK SMUTE/CSN DFS0/CAD0 DEM0/CCLK DEM1/CDTI ACKS/DZFR
System Controller
MCLK
VCML
VSS4
VSS3
VSS2 VDDL
AK4392EQ
VREFHL VREFLL
VREFLR VREFHR VDDR VSS1 AOUTRP VCMR
DIF0/CAD1 DIF1/DZFL DIF2
AOUTRN
DINL
Figure Ground Layout
Grounding Power Supply Decoupling
minimize coupling digital noise, decoupling capacitors should connected AVDD, VDDL/R DVDD respectively. AVDD VDDL/R supplied from analog supply system DVDD supplied from digital supply system. Power lines AVDD, VDDL/R DVDD should distributed separately from point with impedance regulator etc. power sequence between AVDD, VDDL/R DVDD critical. VSS1-4 must connected same analog ground plane. Decoupling capacitors high frequency should placed near possible supply pin.
Voltage Reference
differential voltage between VREFHL/R VREFLL/R sets analog output range. VREFHL/R normally connected AVDD, VREFLL/R normally connected VSS1/2/3. VREFHL/R VREFLL/R should connected with 0.1µF ceramic capacitor near possible eliminate effects high frequency noise. load current drawn from VCML/R pin. signals, especially clocks, should kept away from VREFHL/R VREFLL/R pins order avoid unwanted noise coupling into AK4392.
Analog Outputs
analog outputs full differential outputs 2.8Vpp (typ, VREFHL/R VREFLL/R centered around AVDD/2. differential outputs summed externally, VAOUT (AOUT+) (AOUT-) between AOUT+ AOUT-. summing gain output range 5.6Vpp (typ, VREFHL/R VREFLL/R 5V). bias voltage external summing circuit supplied externally. input data format complement. output voltage (VAOUT) positive full scale 7FFFFFH (@24bit) negative full scale 800000H (@24bit). ideal VAOUT 000000H(@24bit). internal switched-capacitor filters attenuate noise generated delta-sigma modulator beyond audio passband. Figure shows example external circuit summing differential outputs op-amp. Figure shows example differential outputs circuit example three op-amps.
MS1045-E-02
2009/04
[AK4392]
AK4392
AOUT1.5k 2.2n 1.5k 1.5k 1.5k
+Vop
AOUT+
-Vop
Analog
Figure External Circuit Example 99.2kHz, Q=0.704)
Frequency Response Gain 20kHz -0.011dB 40kHz -0.127dB 80kHz -1.571dB Table Frequency Response External Circuit Example
3.3n
100u
AOUTL-
3.9n
0.1u
NJM5534D
1.0n
0.1u
1.2k
0.1u
3.3n
1.0n NJM5534D
100u
AOUTL+
3.9n
0.1u
0.1u
NJM5534D
1.2k
0.1u
Figure External Circuit Example Stage Stage Total Cut-off Frequency 182kHz 284kHz 0.637 Gain +3.9dB -0.88dB +3.02dB 20kHz -0.025 -0.021 -0.046dB Frequency 40kHz -0.106 -0.085 -0.191dB Response 80kHz -0.517 -0.331 -0.848dB Table Frequency Response External Circuit Example
MS1045-E-02
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[AK4392]
recommended SACD format book (Scarlet Book) that filter response SACD playback analog pass filter with cut-off frequency maximum 50kHz slope minimum 30dB/Oct. AK4392 achieve this filter response combination internal filter (Table external filter (Figure 21). Frequency Gain 20kHz -0.4dB 50kHz -2.8dB 100kHz -15.5dB Table Internal Filter Response Mode
2.0k 1.8k 1.0k 4.3k 270p
AOUT2.8Vpp
2200p 3300p 2.0k 1.8k 1.0k
+Vop
AOUT+
2.8Vpp
4.3k 270p
Analog
6.34Vpp
-Vop
Figure External Order Circuit Example Frequency Gain 20kHz -0.05dB 50kHz -0.51dB 100kHz -16.8dB gain 1.07dB Table Order (Figure Response
MS1045-E-02
2009/04
[AK4392]
PACKAGE
44pin LQFP (Unit:
12.0 1.60max 1.40 ±0.05 10.0 0.10±0.05
10.0
0.80
12.0
0.37 +0.08 -0.07 0.20
1.00
0.145±0.055
0°7°
0.6±0.15 0.10
Material Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy, Halogen (bromine chlorine) free Solder free) plate
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[AK4392]
MARKING
AK4392EQ XXXXXXX
indication Logo Date Code: XXXXXXX(7 digits) Marking Code: AK4392 Audio Logo
REVISION HISTORY
Date (YY/MM/DD) 09/01/09 09/02/25 09/04/27 Revision Reason First Edition Error Correct Description Change Page Contents Figure changed. Table changed. Short Delay Filter Minimum Delay Filter
MS1045-E-02
2009/04
[AK4392]
IMPORTANT NOTICE These products their specifications subject change without notice. When consider application these products, please make inquiries sales office Asahi Kasei Microdevices Corporation (AKM) authorized distributors current status products. assumes liability infringement patent, intellectual property, other rights application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical componentsNote1) safety, life support, other hazard related device systemNote2), assumes responsibility such use, except approved with express written consent Representative Director AKM. used here: Note1) critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. Note2) hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. responsibility buyer distributor products, distributes, disposes otherwise places product with third party, notify such third party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
MS1045-E-02
2009/04
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