ADRF6850
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ADRF6850 - ADRF6850
1000 Integrated Broadband Receiver ADRF6850
quadrature demodulator Integrated fractional-N Gain control range: Input frequency range: 1000 Input P1dB: gain Input IP3: +22.5 gain Noise figure: gain, gain Baseband bandwidth: wideband mode, narrow-band mode SPI/I2C serial interface Power supply: +3.3 V/350
ADRF6850 highly integrated broadband quadrature demodulator, frequency synthesizer, variable gain amplifier (VGA). device covers operating frequency range from 1000 both narrow-band wideband communications applications, performing quadrature demodulation from directly baseband frequencies. ADRF6850 demodulator includes high modulus fractional-N frequency synthesizer with integrated VCO, providing better than frequency resolution, gain control range provided front-end VGA. Control on-chip registers through user-selected interface interface. device operates from single power supply ranging from 3.15 3.45
APPLICATIONS
Broadband communications Cellular communications Satellite communications
FUNCTIONAL BLOCK DIAGRAM
VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 LOMON LOMON
60dB GAIN CONTROL RANGE RFCM SEQUENCED GAIN INTERFACE 0°/90° DRIVER RFDIV CORE VTUNE VOCM RSET REFERENCE REFIN DOUBLER 5-BIT DIVIDER PHASE FREQUENCY DETECTOR CCOMP1 CCOMP2 CCOMP3
VGAIN
CHARGE PUMP
CURRENT SETTING N-COUNTER SDI/SDA CLK/SCL SPI/ INTERFACE THIRD-ORDER FRACTIONAL INTERPOLATOR FRACTIONAL REGISTER MODULUS INTEGER REGISTER RFCP4 RFCP3 RFCP2 RFCP1
LDET TESTLO TESTLO
ADRF6850
MUXOUT
09316-001
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2010 Analog Devices, Inc. rights reserved.
ADRF6850 TABLE CONTENTS
Features Applications General Description Functional Block Diagram Revision History Specifications. Timing Characteristics Absolute Maximum Ratings Caution Configuration Function Descriptions Typical Performance Characteristics Theory Operation Overview. Synthesizer VCO. Quadrature Demodulator. Variable Gain Amplifier (VGA) Interface Interface Program Modes Register Register Summary Register Descriptions Suggested Power-Up Sequence Initial Register Write Sequence Evaluation Board General Description Hardware Description Schematic. Artwork. Bill Materials Outline Dimensions Ordering Guide
REVISION HISTORY
10/10-Revision Initial Version
Rev. Page
ADRF6850 SPECIFICATIONS
ambient temperature (TA) 25°C; differential; loop bandwidth kHz; REFIN 13.5 MHz; MHz; baseband frequency MHz, narrow-band mode, unless otherwise noted. Table
Parameter INPUT Operating Frequency Range Input P1dB Input Input Noise Figure (NF) Test Conditions/Comments RFI, RFI, VGAIN pins gain gain gain gain gain, single-ended input gain, single-ended input gain gain rises gain falls gain single-ended, differential single-ended, differential VGAIN from +22.5 ±100 1000 Unit mV/dB
Maximum Gain Minimum Gain Gain Conformance Error Gain Slope VGAIN Input Impedance Return Loss REFERENCE CHARACTERISTICS Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current CHARGE PUMP Sink/Source High Value Value Absolute Accuracy Gain SYNTHESIZER SPECIFICATIONS Frequency Increment Phase Frequency Detector Spurs
Relative REFIN With divide-by-2 divider enabled With divide-by-2 divider disabled
RSET pins Programmable With RSET With RSET KVCO Loop bandwidth Integer boundary loop bandwidth offset from carrier frequency 1000 offset offset offset offset offset offset offset integration bandwidth
312.5 -110 -136 -149 0.26
MHz/V dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms
Phase Noise
Integrated Phase Noise
Rev. Page
ADRF6850
Parameter Frequency Settling Maximum Frequency Step Autocalibration BASEBAND OUTPUTS Maximum Swing Common-Mode Range Output Impedance Output Offset Bandwidth Wideband Mode Narrow-Band Mode Balance Amplitude Wideband Mode Narrow-Band Mode Phase Wideband Mode Narrow-Band Mode Output Impedance Mismatch Group Delay Variation Wideband Mode Narrow-Band Mode Leakage Test Conditions/Comments step size, maximum frequency error Frequency step with autocalibration routine; Register CR24, IBB, IBB, QBB, QBB, VOCM pins Driving differential Differential terminated Unit
Baseband frequency Baseband frequency 33.2 Baseband frequency Baseband frequency 33.2 Baseband frequency Baseband frequency Baseband frequency Baseband frequency 33.2 Relative output level LOMON LOMON pins SDI/SDA, CLK/SCL, pins SDI/SDA, CLK/SCL SDI/SDA, CLK/SCL SDI/SDA, CLK/SCL SDI/SDA, CLK/SCL SDO, LDET pins; SDO, LDET pins; (SDI/SDA) pins; VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, VCC9 pins
±0.1 ±0.1 ±0.5 ±0.25 ±0.3 0.25 0.35
Degrees Degrees
Leakage MONITOR OUTPUT Nominal Output Power LOGIC INPUTS Input High Voltage, VINH Input Voltage, VINL Input High Voltage, VINH Input Voltage, VINL Input Current, IINH/IINL Input Capacitance, LOGIC OUTPUTS Output High Voltage, Output Voltage, POWER SUPPLIES Voltage Range Supply Current Operating Temperature
3.15
3.45
Difference between channel gain linear channel gain.
Rev. Page
ADRF6850
TIMING CHARACTERISTICS
Interface Timing
Table
Parameter Clock Frequency Pulse Width High Pulse Width Start Condition Hold Time Start Condition Setup Time Data Setup Time Data Hold Time Stop Condition Setup Time Data Valid Time Data Valid Acknowledge Time Free Time
Symbol fSCL tHIGH tLOW tHD;STA tSU;STA tSU;DAT tHD;DAT tSU;STO tVD;DAT tVD;ACK tBUF
Limit 1300 1300
Unit
Figure
tVD;DAT tVD;ACK (ACK SIGNAL ONLY)
tSU;DAT
tBUF
tHD;STA tLOW
tSU;STA
tSU;STO
START CONDITION
tHD;DAT
STOP CONDITION
Figure Port Timing Diagram
Rev. Page
09316-002
1/fSCL
tHIGH
ADRF6850
Interface Timing
Table
Parameter Frequency Pulse Width High Pulse Width Start Condition Hold Time Data Setup Time Data Hold Time Stop Condition Setup Time Access Time High Impedance
Symbol fCLK
Limit
Unit
Figure
09316-003
Figure Port Timing Diagram
Rev. Page
ADRF6850 ABSOLUTE MAXIMUM RATINGS
Table Absolute Maximum Ratings
Parameter Supply Voltage Pins (VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7, VCC8, VCC9) Analog Input/Output Digital Input/Output RFI, RFI, RFCM (Exposed Paddle Soldered Down) Maximum Junction Temperature Storage Temperature Range Rating -0.3 +4.0 -0.3 +4.0 -0.3 +4.0 26°C/W 125°C -65°C +150°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION
Rev. Page
ADRF6850 CONFIGURATION FUNCTION DESCRIPTIONS
RFCM VCC9 VGAIN
VCC1 VOCM RSET VCC2 VCC3
INDICATOR
ADRF6850
VIEW (Not Scale)
VCC8 LDET MUXOUT VTUNE VCC7 CCOMP3 CCOMP2 CCOMP1 VCC6 CLK/SCL SDI/SDA
VCC4 VCC5 REFIN REFIN TESTLO TESTLO LOMON LOMON
NOTES CONNECT EXPOSED GROUND PLANE IMPEDANCE PATH.
Figure Configuration
Table Function Descriptions
Mnemonic VCC1 VCC9 Description Positive Power Supplies. Apply power supply VCCx pins. Decouple each with power supply decoupling capacitor. Analog Ground. Connect impedance ground plane.
IBB, IBB, QBB, VOCM CCOMP1 CCOMP2 CCOMP3 VTUNE RSET
Differential In-Phase Quadrature Baseband Outputs. These impedance outputs drive into differential loads. Baseband Common-Mode Voltage Input. When coupling baseband output pins, ground VOCM. There option apply external voltage, which relevant when coupling baseband output pins. Note that Register CR29, must accordingly. Internal Compensation Node. This must decoupled ground with capacitor. Internal Compensation Node. This must decoupled ground with capacitor. Internal Compensation Node. This must decoupled ground with capacitor. Control Input VCO. This voltage determines output frequency derived from filtering output voltage. Charge Pump Current Set. Connecting resistor between this ground sets maximum charge pump output current. relationship between RSET 23.5 ICPmax RSET where RSET Charge Pump Output. When enabled, this provides ±ICP external loop filter, which turn, drives internal VCO. Chip Select. CMOS input. When high, data stored shift registers loaded into registers. mode, when high, slave address device 0x78, when low, slave address 0x58. Serial Data Input Port, Serial Data Input/Output Port. mode. This input high impedance CMOS data input, data loaded 8-bit word. mode, this bidirectional port. Serial Clock Input SPI/I2C Port. This serial clock used clock serial data registers. This input high impedance CMOS input. Serial Data Output Port. Register states read back data output line 8-bit word. Reference Input. couple this high impedance CMOS input. Reference Input Bar. Ground this pin.
Rev. Page
SDI/SDA CLK/SCL REFIN REFIN
09316-004
ADRF6850
Mnemonic RFI, RFCM Description Inputs. internally biased inputs. single-ended operation, must ac-coupled source, must ac-coupled ground plane. Input Common Mode. Connect when driving input single-ended mode. When driving input differentially using balun, connect this common terminal output coil balun. Decouple RFCM ground plane. Differential Monitor Outputs. These pins provide replica internal local oscillator frequency four different power levels: dBm, dBm, dBm, dBm, approximately. These open-collector outputs must terminated with external resistors VCCx. These outputs disabled through serial port programming should connected VCCx used. Extra Loop Filter Pins Fastlock. these pins reduce lock time. Lock Detect. This provides active high output when frequency locked. lock detect timing controlled Register CR14 (Bit Register CR23 (Bit Muxout. This output test output diagnostic only. Allow this remain open circuit. Differential Test Inputs. internal only. These pins should grounded. Gain Input. Drive this voltage range from This voltage controls gain VGA. input sets gain whereas input sets gain Gain Mode Polarity CR30, gain mode polarity input sets gain whereas input sets gain Exposed Paddle. Connect exposed ground plane impedance path.
LOMON, LOMON LF3/LF2 LDET MUXOUT TESTLO, TESTLO VGAIN
Rev. Page
ADRF6850 TYPICAL PERFORMANCE CHARACTERISTICS
nominal condition defined 25°C, 3.30 worst-case frequency. worst-case condition defined having worst-case temperature, supply voltage, frequency.
100MHz 300MHz 550MHz 800MHz 1000MHz
NOMINAL WORST-CASE
OCCURRENCE
09316-011
10.2 10.6 11.0 11.4 11.8 12.2 12.6 13.0 13.4
09316-008
IP1dB (dBm)
CHANNE GAIN (dB)
INPUT P1dB CHANNEL GAIN (dBm)
Figure Input Compression Point (IP1dB) Channel Gain, Input Frequency, Nominal Conditions, Narrow-Band Mode
3.30V, 25°C 3.15V, -40°C 3.45V, -40°C 3.15V, 85°C 3.45V, 85°C
Figure Input Compression Point (IP1dB) Distribution with Channel Gain Nominal Worst-Case Conditions
NOMINAL WORST-CASE
OCCURRENCE
09316-012
IP1dB (dBm)
CHANNE GAIN (dB)
09316-009
-47.6
-50.0
-49.6
-49.2
-48.8
-48.4
-50.4
INPUT P1dB CHANNEL GAIN 60dB (dBm)
Figure Input Compression Point (IP1dB) Channel Gain, Supply, Temperature, Input Frequency MHz, Narrow-Band Mode
3.30V, 3.15V, 3.45V, 3.15V, 3.45V, +25°C -40°C -40°C +85°C +85°C
Figure Input Compression Point (IP1dB) Distribution with Channel Gain Nominal Worst-Case Conditions
100MHz 300MHz 550MHz 800MHz 1000MHz
IP1dB (dBm)
IP1dB (dB)
-48.0
-47.2
-46.8
09316-033
09316-034
CHANNEL GAIN (dB)
CHANNEL GAIN (dB)
Figure Input Compression Point (IP1dB) Channel Gain, Supply, Temperature, Input Frequency 1000 MHz, Narrow-Band Mode
Figure Input Compression Point (IP1dB) Channel Gain, Input Frequency, VOCM Nominal Conditions, Narrow-Band Mode
Rev. Page
ADRF6850
100MHz 300MHz 550MHz 800MHz 1000MHz
100MHz 300MHz 550MHz 800MHz 1000MHz
IP1dB (dBm)
INPUT (dBm)
09316-016
09316-057
CHANNE GAIN (dB)
CHANNEL GAIN (dB)
Figure Input Compression Point (IP1dB) Channel Gain, Input Frequency, VOCM Nominal Conditions, Narrow-Band Mode
20MHz 50MHz 100MHz 200MHz 250MHz
Figure Input Channel Gain, Input Frequency, Worst-Case Conditions
NOMINAL WORST-CASE
09316-010
OCCURRENCE
IP1dB (dBm)
19.6 20.0 20.4 20.8 21.2 21.6 22.0 22.4 22.8 23.2 23.6 24.0 IIP3 CHANNEL GAIN (dBm)
CHANNE GAIN (dB)
Figure Input Compression Point (IP1dB) Channel Gain, Output Frequency, 1000 MHz, Nominal Conditions, Wideband Mode
100MHz 300MHz 550MHz 800MHz 1000MHz
Figure Input Distribution with Channel Gain Nominal Worst-Case Conditions
NOMINAL WORST-CASE
INPUT (dBm)
09316-015
OCCURRENCE
-40.4 -40.0 -39.6 -39.2 -38.8 -38.4 -38.0 -37.6 -37.2 -36.8 -36.4 -36.0 IIP3 CHANNEL GAIN 60dB (dBm)
CHANNE GAIN (dB)
Figure Input Channel Gain, Input Frequency, Nominal Conditions
Figure Input Distribution with Channel Gain Nominal Worst-Case Conditions
Rev. Page
09316-036
09316-035
ADRF6850
INPUT (dBm)
INPUT (dBm)
FREQUENCIES 16MHz 19MHz FREQUENCIES 46MHz 49MHz FREQUENCIES 96MHz 99MHz FREQUENCIES 196MHz 199MHz FREQUENCIES 246MHz 249MHz
09316-037
09316-014
DIRECT IIP2 DOWN-CONVERTED IIP2
CHANNEL GAIN (dB)
CHANNE GAIN (dB)
Figure Input Channel Gain, Output Frequency, Wideband Mode, Nominal Conditions
Figure Input Channel Gain, Wideband Mode, Worst-Case Conditions
100MHz 300MHz 550MHz 800MHz 1000MHz
NOISE FIGURE (dB)
FREQUENCIES 16MHz 19MHz FREQUENCIES 46MHz 49MHz FREQUENCIES 96MHz 99MHz FREQUENCIES 196MHz 199MHz FREQUENCIES 246MHz 249MHz
09316-038
INPUT (dBm)
09316-023
CHANNEL GAIN (dB)
CHANNEL GAIN (dB)
Figure Input Channel Gain, Output Frequency, Wideband Mode, Worst-Case Conditions
Figure Noise Figure Channel Gain, Input Frequency, Narrow-Band Mode, Nominal Conditions
100MHz 300MHz 550MHz 800MHz 1000MHz
NOISE FIGURE (dB)
INPUT (dBm)
09316-013
DIRECT IIP2 DOWN-CONVERTED IIP2
CHANNEL GAIN (dB)
CHANNE GAIN (dB)
Figure Input Channel Gain, Wideband Mode, Nominal Conditions
Figure Noise Figure Channel Gain, Input Frequency, Narrow-Band Mode, Worst-Case Conditions
Rev. Page
09316-024
ADRF6850
100MHz 300MHz 550MHz 800MHz 1000MHz
CHANNEL GAIN (dB)
NOISE FIGURE (dB)
09316-007
CHANNEL GAIN (dB)
09316-045
VGAIN
Figure Noise Figure Distribution Channel Gain, Narrow-Band Mode, Nominal Conditions
Figure Channel Gain VGAIN Input Frequency, Nominal Conditions
NOMINAL WORST-CASE
NOISE FIGURE (dB)
OCCURRENCE
09316-006
59.6
61.8
62.0
60.0
60.2
60.4
60.6
60.8
61.0
61.2
61.4
CHANNEL GAIN (dB)
59.8
CHANNEL GAIN RANGE (dB)
Figure Noise Figure Distribution Channel Gain, Narrow-Band Mode, Worst-Case Conditions
100MHz 300MHz 550MHz 800MHz 1000MHz
Figure Channel Gain Range Distribution Nominal Worst-Case Conditions
3.30V, 25°C 3.15V, -40°C 3.45V, -40°C 3.15V, 85°C 3.45V, 85°C
NOISE FIGURE (dB)
CHANNEL GAIN (dB)
-0.5
-1.0
09316-025
-1.5
09316-021
CHANNEL GAIN (dB)
-2.0
61.6
1000
INPUT FREQUENCY (MHz)
Figure Noise Figure Channel Gain, Input Frequency, Wideband Mode, Nominal Conditions
Figure Minimum Channel Gain Input Frequency, Supply, Temperature
Rev. Page
62.2
09316-046
ADRF6850
CHANNEL GAIN CONFORMANCE ERROR (dB)
NOMINAL WORST-CASE
100MHz 300MHz 550MHz 800MHz 1000MHz
OCCURRENCE
09316-019
09316-005
VGAIN
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.8
-0.6
-0.4
MINIMUM CHANNEL GAIN (dB)
Figure Minimum Channel Gain Distribution Nominal Worst-Case Conditions
63.0 3.30V, 25°C 3.15V, -40°C 3.45V, -40°C 3.15V, 85°C 3.45V, 85°C
-0.2
Figure Channel Gain Conformance Error VGAIN Input Frequency, Nominal Conditions
VGAIN VGAIN 0.5V VGAIN 1.0V VGAIN 1.5V
MAXIMUM CHANNEL GAIN (dB)
62.5
62.0
RETURN LOSS (dB)
09316-018
61.5
61.0
60.5
1000
1000
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure Maximum Channel Gain Input Frequency, Supply, Temperature
NOMINAL WORST-CASE
Figure Input Return Loss Input Frequency Channel Gain, Nominal Conditions
INTEGER BOUNDARY SPUR 9.6kHz OFFSET INTEGER BOUNDARY SPUR 19.2kHz OFFSET INTEGER BOUNDARY SPUR 38.4kHz OFFSET
INTEGER BOUNDARY SPURS (dBc)
1000
09316-044
OCCURRENCE
09316-017
59.6
59.8
60.0
60.2
60.4
60.6
60.8
61.0
61.2
61.4
61.6
61.8
62.0
62.2
-100
FREQUENCY (MHz)
MAXIMUM CHANNEL GAIN (dB)
Figure Maximum Channel Gain Distribution Nominal Worst-Case Conditions
Figure Integer Boundary Spurs Frequency, Channel Gain, Supply, Temperature
Rev. Page
09316-039
60.0
ADRF6850
TABLE DISTRIBUTION DATA: OFFSET FREQUENCY (Hz): 100k TYPICAL RANGE (dBc/Hz): -75/-85 -78/-89 -84/-95 -97/-100 -110/-113 -136/-138 -149/-153 WORST-CASE RANGE (dBc/Hz): -72/-82 -74/-89 -89/-96 -97/-100 -110/-112 -136/-138 -149/-152
REFERENCE SPUR (dBc)
PHASE NOISE (dBc/Hz)
1000
09316-049
VGAIN 1.5V
-100 -110 -120 -130 -140
VGAIN 1.0V
-100
-120
-150
100k
09316-051
09316-040
FREQUENCY (MHz)
-160
OFFSET FREQUENCY (Hz)
Figure Reference Spurs 13.5 from Carrier Frequency, Channel Gain, Supply, Temperature
Figure Phase Noise Performance Including Distribution Table Frequency 1000 Nominal Worst-Case Conditions
3.30V; +25°C 3.15V; +85°C 3.45V; +85°C 3.15V; -40°C 3.45V; -40°C
SPUR (dBc)
JITTER (Degrees)
09316-048
VGAIN 1.5V
VGAIN 1.0V
-100
1000
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Spurs from Carrier Frequency, Channel Gain, Supply, Temperature
TABLE DISTRIBUTION DATA: OFFSET FREQUENCY (Hz): 100k TYPICAL RANGE (dBc/Hz): -91/-100 -99/-111 -107/-115 -118/-121 -129/-132 -150/-154 -151/-153 WORST-CASE RANGE (dBc/Hz): -90/-105 -95/-108 -105/-116 -118/-121 -128/-131 -151/-154 -151/-153
Figure Integrated Phase Noise Frequency, Supply, Temperature
NOMINAL WORST-CASE
OCCURRENCE
PHASE NOISE (dBc/Hz)
-100 -110 -120 -130 -140 -150 -160
100k
09316-052
0.19 0.21 0.23 0.25 0.27 0.29 0.31 0.33 JITTER (Degrees)
-170
OFFSET FREQUENCY (Hz)
Figure Phase Noise Performance Including Distribution Table Frequency Nominal Worst-Case Conditions
Figure Integrated Phase Noise Distribution with Frequency 1000 Nominal Worst-Case Conditions
Rev. Page
09316-041
-120
ADRF6850
100M BEST CASE TYPICAL WORST CASE
ACQUISITION 1kHz
ERROR FREQUENCY (Hz)
100k START ACQUISITION WRITE
LDET
OCCURRENCE
CR23[3] CR23[3]
09316-031
LDET
0.005
0.010 0.015
0.020 0.025
0.030 0.035
0.040
0.045
0.050
0.055 0.060
0.065
0.070 0.075
0.080 0.085
TIME (µs)
ABSOLUTE AMPLITUDE BALANCE (dB)
Figure Frequency Settling Time with Typical, Best-Case, WorstCase Frequency with Lock Detect Shown, Nominal Conditions
OUTPUT OUTPUT
Figure Absolute Amplitude Balance, Narrow-Band Mode, Nominal Conditions
OCCURRENCE
OCCURRENCE
09316-050
-0.45 -0.35 -0.25 -0.15 -0.05 0.05 0.15 0.25 0.35 0.45
09316-042
09316-026
PHASE BALANCE (Degrees)
OUTPUT OFFSET (mV)
Figure Output Offset Distribution Outputs, Nominal Conditions
MODE MODE= 50MHz MODE 43MHz MODE 37MHz MODE= 30MHz 1000
09316-047
Figure Phase Balance, Narrow-Band Mode, Nominal Conditions
FEEDTHROUGH (dBm)
-100 VGAIN 0.5V, VGAIN 1.5V
OUTPUT POWER (dB)
OUTPUT FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Normalized Output Bandwidth, Narrow-Band, Wideband Modes, Nominal Conditions
Figure Feedthrough Frequency, VGAIN, Supply, Temperature (Narrow-Band Mode)
Rev. Page
0.090 0.095 0.100
1000
09316-055
0.01
ADRF6850
FEEDTHROUGH (dBm)
FEEDTHROUGH (dBm)
VGAIN 1.5V
VGAIN 1.3V
VGAIN 0.5V, -100
09316-022
-100
09316-029
-120
1000
-120
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Feedthrough Frequency, VGAIN, Supply, Temperature (Narrow-Band Mode)
Figure Feedthrough Frequency, VGAIN, Supply, Temperature, Fourth-Order Filter Applied, Wideband Mode
FEEDTHROUGH (dBm)
LEAKAGE (dBc)
VGAIN 1.5V
-100
09316-030
-100 VGAIN 0.5V, -120 1000
09316-028
-120
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Feedthrough Frequency, VGAIN, Supply, Temperature (Narrow-Band Mode)
NOMINAL WORST-CASE
Figure Feedthrough Input Frequency, VGAIN, Supply, Temperature, Narrow-Band Mode
LEAKAGE (dBc)
VGAIN 1.0V VGAIN 1.5V VGAIN 1.3V -100 -120 VGAIN 0.5V,
09316-027
OCCURRENCE
09316-020
-46.5 -46.0 -45.5 -45.0 -44.5 -44.0 -43.5 -43.0 -42.5 -42.0 -41.5 -41.0 -40.5 -40.0 -39.5 -39.0 -38.5 -38.0 -37.5 -37.0 -36.5 -36.0
-140
FREQUENCY (MHz)
FEEDTHOUGH (dBm)
Figure Feedthrough Distribution Nominal Worst-Case Conditions with Frequency MHz, Narrow-Band Mode
Figure Feedthrough Input Frequency, VGAIN, Supply, Temperature, Fourth-Order Filter Applied, Wideband Mode
Rev. Page
ADRF6850 THEORY OPERATION
ADRF6850 device separated into following basic building blocks: synthesizer Quadrature demodulator Variable gain amplifier (VGA) I2C/SPI interface
FROM REFIN DOUBLER 5-BIT R-DIVIDER
09316-061
OVERVIEW
Figure Reference Input Path
frequency equation fPFD fREFIN D)/(R T))] where: fREFIN reference input frequency. doubler bit. programmed divide ratio binary 5-bit programmable reference divider 32).
Each these building blocks described detail sections that follow.
SYNTHESIZER
Overview
phase-locked loop (PLL) consists fractional-N frequency synthesizer with 25-bit fixed modulus, allowing frequency resolution less than over entire frequency range. also integrated voltage controlled oscillator (VCO) with fundamental output frequency ranging from 2000 4000 MHz. divider, controlled Register CR28, Bits[2:0], extends lower limit frequency range less than MHz. This 4000 frequency output then applied divide-by-4 quadrature circuit provide local oscillator (LO) ranging from 1000 quadrature demodulator.
Fractional-N Divider
fractional-N divider allows division ratio feedback path that range from 4095. relationship between fractional-N divider frequency described following section.
FRAC Relationship
integer (INT) fractional (FRAC) values make possible generate output frequencies that spaced fractions phase frequency detector (PFD) frequency. Programming Correct Frequency section more information. frequency equation fPFD (INT (FRAC/225))/2 2RFDIV where: local oscillator frequency. fPFD frequency. integer component required division factor controlled registers. FRAC fractional component required division factor controlled registers. RFDIV setting Register CR28, Bits[2:0], controls setting divider output PLL.
N-DIVIDER FROM OUTPUT DIVIDERS N-COUNTER THIRD-ORDER FRACTIONAL INTERPOLATOR FRAC/225
Reference Input Section
reference input stage shown Figure normally closed switches. normally open. When power-down initiated, closed, open. This ensures that there loading REFIN power-down.
POWER-DOWN CONTROL
REFIN
100k BUFFER
09316-060
R-DIVIDER
Figure Reference Input Stage
Reference Input Path
on-chip reference frequency doubler allows input frequency reference signal doubled. This useful increasing comparison frequency. Making frequency higher improves noise performance system. Doubling frequency usually improves in-band phase noise performance dBc/Hz. 5-bit R-divider allows input reference frequency (REFIN) divided down produce reference clock PFD. Division ratios from allowed. additional divide-by-2 (÷2) function reference input path allows greater division range.
Figure Fractional-N Divider
Phase Frequency Detector (PFD) Charge Pump
takes inputs from R-divider N-counter produces output proportional phase frequency difference between them (see Figure simplified schematic). includes fixed delay element that sets width antibacklash pulse, ensuring that there dead zone transfer function.
Rev. Page
09316-062
FRAC VALUE
ADRF6850
CLR1
correct band chosen automatically band select circuitry when Register updated. This referred autocalibration. autocalibration time Register CR25.
CHARGE PUMP
DELAY
Autocalibration Time (BSCDIV 24)/PFD where: BSCDIV Register CR25, Bits[7:0]. frequency.
09316-063
CLR2 DOWN
frequency MHz, BSCDIV autocalibration time Note that BSCDIV must recalculated frequency changed. recommended autocalibration setting During this time, VTUNE disconnected from output loop filter connected internal reference voltage. typical frequency acquisition shown Figure
100M 100k ACQUISITION 1kHz
09316-054
09316-053
Figure Simplified Schematic
Lock Detect (LDET)
LDET (Pin signals when achieved lock error frequency less than kHz. write Register CR0, acquisition cycle starts, LDET signal goes low. When lock been achieved, this signal returns high.
Voltage Controlled Oscillator (VCO)
core ADRF6850 consists three separate VCOs, each with overlapping bands. This configuration bands allows frequency range extend from 2000 4000 MHz. three VCOs divided externally programmable divider (RFDIV controlled Register CR28, Bits[2:0]). This divider provides divisions ensure that frequency range extended from (2000 MHz/8) 4000 (4000 MHz/1). lower limit only required. divide-by-4 quadrature circuit provides full frequency range from 1000 MHz. Figure shows sweep VTUNE frequency demonstrating three VCOs overlapping multiple overlapping bands within each frequency range 1000 MHz. Note that this plot includes RFDIV divider being incorporated provide further divisions fundamental frequency; thus, each used four different occasions throughout full frequency range. choice three 16-band VCOs RFDIV divider allows wide frequency range covered without large sensitivity (KVCO) resultant poor phase noise spurious performance.
FREQUENCY ERROR (Hz)
AUTOCAL TIME (µs)
TIME (µs)
Figure Acquisition
After autocalibration, normal action resumes, correct frequency acquired within frequency error typically. maximum cumulative step kHz, autocalibration turned Register CR24, This enables cumulative acquisitions less occur without autocalibration procedure, which improves acquisition times significantly (see Figure 59).
100M 100k
ACQUISITION 1kHz
FREQUENCY ERROR (Hz)
VTUNE
09316-056
1000
TIME (µs)
FREQUENCY (MHz)
Figure Acquisition Without Autocalibration Step
Figure VTUNE Frequency
Rev. Page
ADRF6850
displays variation KVCO VTUNE varies within band from band band. Figure shows KVCO varies across fundamental frequency range from 1000 MHz. Note that KVCO shown frequency rather than frequency. Figure useful when calculating loop filter bandwidth individual loop filter components using ADISimPLLTM. ADISimPLL Analog Devices, Inc., simulator that aids design, particularly with respect loop filter. reports parameters such phase noise, integrated phase noise, acquisition time, forth particular input conditions. ADISimPLL downloaded from www.analog.com.
Example Program Correct Frequency
Assume that frequency required frequency MHz. Step From Table 2RFDIV Step 330E+6)/(27E+6) 48.88888889. N-divider value composed integer (INT) fractional (FRAC) components according following equation: FRAC/225 FRAC 29,826,162. appropriate registers must then programmed according register map, ensuring that Register last register programmed because this write starts acquisition cycle.
SENSITIVITY (MHz/V)
QUADRATURE DEMODULATOR
quadrature demodulator powered Register CR29, output filter with narrow-band wideband modes, which selected Register CR29, Wideband mode filter cutoff MHz. Narrow-band mode selectable cutoff filters through programming Register CR29, Bits[5:4]. bias voltage (VOCM) internally setting Register CR29, select external bias voltage, Register CR29, drive VOCM, with requisite external bias voltage.
1000
FREQUENCY (MHz)
Figure KVCO Frequency
09316-059
Programming Correct Frequency
There steps programming correct frequency. user calculate N-divider ratio that required RFDIV value based required frequency frequency. Calculate value RFDIV, which used program Register CR28, Bits[2:0], from following lookup table (Table also Table
RFDIV Register CR28[2:0] divide-by-1 divide-by-2 divide-by-4 divide-by-8
VARIABLE GAIN AMPLIFIER (VGA)
variable gain amplifier (VGA) input demodulator driven either single-ended differentially. drive single-ended, connect RFCM, RFI, decouple both pins ground with capacitor. Drive input signal through RFI. drive differentially, balun with pins driven balanced outputs balun, connect RFCM common balun output terminal. Decouple RFCM ground. gain range approximately achieved varying VGAIN voltage from Typical Performance Characteristics section more information gain performance. input VGAIN sets gain whereas input sets gain Gain Mode Polarity CR30, gain mode polarity input voltage VGAIN sets gain whereas input sets gain powered down setting Register CR30, powered setting this same
Table RFDIV Lookup Table
Frequency (MHz) 1000
Using following equation, calculate value N-divider: (2RFDIV LO)/(fPFD) where: N-divider value. RFDIV setting Register CR28, Bits[2:0]. local oscillator frequency. fPFD frequency.
INTERFACE
ADRF6850 supports 2-wire, I2C-compatible serial that drives multiple peripherals. part powers mode locked this mode. remain mode,
Rev. Page
This equation different representation Equation
ADRF6850
recommended that user line either GND, thus disabling mode. serial data (SDA) serial clock (SCL) inputs carry information between devices that connected bus. Each slave device recognized unique address. ADRF6850 possible 7-bit slave addresses both read write operations, 0x78 0x58. 7-bit slave address slave address (Pin 27). Bits[4:0] slave address 11000. slave address consists seven MSBs 8-bit word. word sets either read write operation (see Figure 61). Logic corresponds read operation, whereas Logic corresponds write operation. control device bus, following protocol must followed: master initiates data transfer establishing start condition, defined high-to-low transition while remains high. This indicates that address/ data stream follows. peripherals respond start condition shift next eight bits (the 7-bit address bit). bits transferred from LSB. peripheral that recognizes transmitted address responds pulling data line during ninth clock pulse. This known acknowledge bit. other devices then withdraw from maintain idle condition. During idle condition, device monitors lines waiting start condition correct transmitted address. determines direction data. Logic first byte indicates that master writes information peripheral. Logic first byte indicates that master reads information from peripheral.
ADRF6850 acts standard slave device bus. data eight bits long, supporting 7-bit addresses plus bit. ADRF6850 subaddresses enable user-accessible internal registers; therefore, interprets first byte device address second byte starting subaddress. Auto-increment mode supported, which allows data read from written starting subaddress, each subsequent address, without manually addressing subsequent subaddress. data transfer always terminated stop condition. user also access unique subaddress register one-by-one basis without updating registers. Stop start conditions detected stage data transfer. these conditions asserted sequence with normal read write operations, they cause immediate jump idle condition. invalid subaddress issued user, ADRF6850 does issue acknowledge returns idle condition. acknowledge condition, line pulled ninth pulse. Figure Figure sample write read data transfers, Figure timing protocol, Figure more detailed timing diagram.
CTRL
09316-064
SLAVE ADDRESS[6:0]
Figure Slave Address Configuration
SLAVE ADDR, (WR) A(S) SUBADDR A(S) DATA A(S) DATA A(S)
09316-067
START A(S) ACKNOWLEDGE SLAVE
STOP
Figure Write Data Transfer
SLAVE ADDR, (WR) A(S) SUBADDR A(S) SLAVE ADDR, (RD) A(S) DATA A(M) DATA A(M)
09316-065
START A(S) ACKNOWLEDGE SLAVE
STOP A(M) ACKNOWLEDGE MASTER A(M) ACKNOWLEDGE MASTER
Figure Read Data Transfer
START SLAVE ADDRESS SUBADDRESS DATA STOP
SLAVE ADDR[4:0] SUBADDR[6:1] DATA[6:1]
09316-066
Figure Data Transfer Timing
Rev. Page
ADRF6850
INTERFACE
ADRF6850 supports protocol; however, part powers mode. select lock mode, three pulses must sent pin, shown Figure When protocol locked cannot unlocked while device remains powered reset serial interface, part must powered down powered again. part. line used write registers. dedicated output read mode. part operates slave mode requires externally applied serial clock pin. serial interface designed allow part interfaced systems that provide serial clock that synchronized serial data. Figure shows example write operation ADRF6850. Data clocked into registers rising edge using 24-bit write command. first eight bits represent write command (0xD4), next eight bits register address, final eight bits data written specific register. Figure shows example read operation. this example, shortened 16-bit write command first used select appropriate register read operation, first eight bits representing write command (0xD4) final eight bits representing specific register. Then line pulsed second time retrieve data from selected register using 16-bit read command, first eight bits representing read command (0xD5) final eight bits representing contents register being read. Figure shows timing both read write operations.
Serial Interface Selection
controls selection interface. Figure shows selection process that required lock mode. communicate with part using protocol, three pulses must sent pin. third rising edge, part selects locks protocol. Consistent with most standards, must held during communication part held high other times.
Serial Interface Functionality
serial interface ADRF6850 consists (SDI/SDA), (CLK/SCL), pins. used select device when more than device connected serial clock data lines. used clock data
(STARTING HIGH)
LOCKED THIRD RISING EDGE
FRAMING EDGE
(STARTING LOW)
09316-077
LOCKED THIRD RISING EDGE
FRAMING EDGE
Figure Selecting Protocol
Rev. Page
ADRF6850
START
WRITE COMMAND [0xD4]
REGISTER ADDRESS
(CONTINUED)
(CONTINUED)
DATA BYTE
STOP
Figure Byte Write Example
START
WRITE COMMAND [0xD4]
REGISTER ADDRESS
09316-069
START
READ COMMAND [0xD5]
DATA BYTE
STOP
Figure Byte Read Example
Rev. Page
09316-068
(CONTINUED)
ADRF6850
PROGRAM MODES
ADRF6850 8-bit registers allow program control number functions. Only these registers writeable. Either interface used program register set. details about interfaces timing, Figure Figure registers documented Table Table Several settings ADRF6850 double buffered. These settings include FRAC value, value, RFDIV value, 5-bit R-divider value, reference doubler, divider, charge pump current setting. This means that events must occur before part uses value double buffered settings. First, value latched into device writing appropriate register. Next, write must performed Register CR0. When Register written, acquisition occurs. example, updating fractional value involves write Register CR3, Register CR2, Register CR1, Register CR0. Register should written first, followed Register Register and, finally, Register CR0. acquisition begins after write Register CR0. Double buffering ensures that bits written take effect until after write Register CR0. 5-bit divider enabled programming Register CR5, division ratio programmed through Register CR10, Bits[4:0]. divider programmed through Register CR10, Note that these registers double buffered.
Charge Pump Current
Register CR9, Bits[7:4], charge pump current setting. With RSET value maximum charge pump current following equation applies: 23.5/RSET charge pump current settings from
Power-Down/Power-Up Control Bits
four programmable power-up power-down control bits follows: Register CR12, Master power control PLL, including VCO. This normally default value power PLL. Register CR27, Controls monitor outputs, LOMON LOMON. default when monitor outputs powered down. Setting this powers monitor outputs dBm, dBm, dBm, dBm, controlled Register CR27, Bits[1:0]. Register CR29, Controls quadrature demodulator power. default which powers down demodulator. Write this power demodulator. Register CR30, This controls power must power VGA.
12-Bit Integer Value
Register Register program integer value (INT) feedback division factor (N); Equation details. value 12-bit number whose MSBs programmed through Register CR7, Bits[3:0]. LSBs programmed through Register CR6, Bits[7:0]. frequency setting described Equation alternative this equation provided Equation which details N-divider value. Note that these registers double buffered.
Lock Detect (LDET)
Lock detect enabled setting Register CR23, Register CR23, conjunction with Register CR14, sets number up/down pulses generated before lock detect declared LDET returning high. options 2048 pulses, 3072 pulses, 4096 pulses. default setting 3072 pulses, which selected programming Register CR23, Register CR14, more aggressive setting 2048 selected when Register CR23, Register CR14, This improves lock detect time (for frequency MHz). Note, however, that does affect acquisition time error frequency kHz. setting 4096 pulses selected when Register CR14, best operation, Register CR23, This sets up/down pulses coarse precision setting.
25-Bit Fractional Value
Register Register program fractional value (FRAC) feedback division factor (N); Equation details. FRAC value 25-bit number whose programmed through Register CR3, programmed through Register CR0, frequency setting described Equation Again, alternative this equation described Equation which details N-divider value. Note that these registers double buffered.
RFDIV Value
RFDIV value dependent value frequency. RFDIV value selected from list Table Apply selected RFDIV value Equation together with frequency frequency values, calculate correct Ndivider value.
Baseband VOCM Reference
Register CR29, selects whether common-mode reference baseband outputs internal external. When baseband outputs ac-coupled, then internal reference must selected setting Register CR29, grounding VOCM. When baseband outputs dc-coupled, likely that external bias needed unless internal bias provided
Reference Input Path
reference input path consists reference doubler, 5-bit frequency divider, divide-by-2 function (see Figure 54). doubler programmed through Register CR10,
Rev. Page
ADRF6850
within suitable range match specification followon device. This accomplished setting Register CR29, driving VOCM, with requisite external bias voltage. Table Baseband Filter Settings
CR29[5:4] Filter Cutoff Frequency (MHz)
Narrow-Band Wideband Filter Mode
default, second-order low-pass filter output buffers baseband output signal paths selected, baseband outputs narrow-band mode. setting Register CR29, Bits[5:4], this filter cutoff frequency MHz, MHz, MHz, MHz. setting Register CR29, this filter bypassed wideband mode selected.
Gain Mode Polarity
polarity gain programming Register CR30. setting Register CR30, positive gain slope selected where VGAIN sets gain VGAIN sets gain setting Register CR30, negative gain slope selected.
Rev. Page
ADRF6850 REGISTER
REGISTER SUMMARY
Table Register Summary
Register Address (Hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 Register Name CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR19 CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR30 CR31 CR32 CR33 Type Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Read only Read only Description Fractional Word Fractional Word Fractional Word Fractional Word Reserved Reference 5-bit, R-divider enable Integer Word Integer Word Reserved Charge pump current setting Reference frequency control Reserved power-up Reserved Lock Detector Control Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Lock Detector Control Autocalibration Autocalibration timer Reserved monitor output selection Demodulator power filter selection Reserved Reserved Revision code
Rev. Page
ADRF6850
REGISTER DESCRIPTIONS
Table Register (Address 0x00), Fractional Word
Table Register (Address 0x05), Reference 5-Bit, R-Divider Enable
Description Reserved Reserved Reserved 5-bit R-divider enable1 disable 5-bit R-divider (default) enable 5-bit R-divider Reserved Reserved Reserved Reserved
Description Fractional Word Fractional Word Fractional Word Fractional Word Fractional Word Fractional Word Fractional Word Fractional Word (LSB)1
Double buffered. Load write Register CR0.
Table Register (Address 0x01), Fractional Word
Double buffered. Load write Register CR0.
Description Fractional Word F151 Fractional Word F141 Fractional Word F131 Fractional Word F121 Fractional Word F111 Fractional Word F101 Fractional Word Fractional Word
Table Register (Address 0x06), Integer Word
Double buffered. Load write Register CR0.
Description Integer Word Integer Word Integer Word Integer Word Integer Word Integer Word Integer Word Integer Word
Table Register (Address 0x02), Fractional Word
Double buffered. Load write Register CR0.
Description Fractional Word F231 Fractional Word F221 Fractional Word F211 Fractional Word F201 Fractional Word F191 Fractional Word F181 Fractional Word F171 Fractional Word F161
Table Register (Address 0x07), Integer Word
[7:4] Description MUXOUT control 0000 tristate 0001 logic high 0010 logic 1101 RCLK/2 1110 NCLK/2 Integer Word N111 Integer Word N101 Integer Word Integer Word
Double buffered. Load write Register CR0.
Table Register (Address 0x03), Fractional Word
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Fractional Word (MSB)1
Double buffered. Load write Register CR0.
Double buffered. Load write Register CR0.
Rev. Page
ADRF6850
Table Register (Address 0x09), Charge Pump Current Setting
[7:4] Description Charge pump current1 0000 0.31 (default) 0001 0.63 0010 0.94 0011 1.25 0100 1.57 0101 1.88 0110 2.19 0111 2.50 1000 2.81 1001 3.13 1010 3.44 1011 3.75 1100 4.06 1101 4.38 1110 4.69 1111 5.00 Reserved Reserved Reserved Reserved
Table Register CR12 (Address 0x0C), Power-Up
Description Reserved Reserved Reserved Reserved Reserved power-down power (default) power down Reserved Reserved
Table Register CR14 (Address 0x0E), Lock Detector Control
Description Lock Detector Up/Down Count 2048/3072 up/down pulses 4096 up/down pulses Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Double buffered. Load write Register CR0.
Table Register CR10 (Address 0x0A), Reference Frequency Control
Description Reserved1 divide-by-2 divider enable1 bypass divide-by-2 divider enable divide-by-2 divider R-doubler enable1 disable doubler (default) enable doubler 5-bit R-divider setting1 00000 divide (default) 00001 divide 00010 divide 11110 divide 11111 divide
Table Register CR23 (Address 0x17), Lock Detector Control
Description Reserved Reserved Reserved Lock detector enable lock detector disabled (default) lock detector enabled Lock detector up/down count With Register CR14[7] 3072 up/down pulses 2048 up/down pulses Lock detector precision low, coarse high, fine Reserved Reserved
[4:0]
Double buffered. Load write Register CR0.
Rev. Page
ADRF6850
Table Register CR24 (Address 0x18), Autocalibration
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Disable autocalibration enable autocalibration (default) disable autocalibration
Table Register CR29 (Address 0x1D), Demodulator Power Filter Selection
Description Reserved Internal baseband (VOCM) select select external baseband (VOCM) reference select internal baseband (VOCM) reference Narrow-band filter Baseband wideband/narrow-band modes narrow-band mode wideband mode Reserved; Reserved; Power-up demodulator power down (default) power
[5:4]
Table Register CR25 (Address 0x19), Autocalibration Timer
[7:0] Description Autocalibration timer
Table Register CR27 (Address 0x1B), Monitor Output
Description Reserved Reserved Reserved Reserved Reserved Power-up monitor output power down (default) power Monitor output power into (default)
Table Register CR30 (Address 0x1E),
Description Reserved Reserved Reserved Reserved Reserved gain mode polarity positive gain slope negative gain slope Reserved Power-up power down power
[1:0]
Table Register CR28 (Address 0x1C), Selection
[2:0] Description Reserved Reserved Reserved Reserved Reserved; RFDIV divide 1000 divide divide divide
Table Register CR33 (Address 0x21), Revision Code1
Description Revision code Revision code Revision code Revision code Revision code Revision code Revision code Revision code
Read-only register.
Rev. Page
ADRF6850 SUGGESTED POWER-UP SEQUENCE
INITIAL REGISTER WRITE SEQUENCE
After applying power device, adhere following write sequence, particularly with respect reserved register settings. Note that Register CR33, Register CR32, Register CR31 read-only registers. Also note that writeable registers should written power-up. Refer Register section more details registers. Write following Register CR30 0x00. power gain slope positive. Write following Register CR29: 0x41. demodulator powered baseband narrow-band mode selected cutoff frequency MHz. internal baseband VOCM reference selected. Write following Register CR28: 0x0X RFDIV depends value frequency used according Table Note that Register CR28, Write following Register CR27: 0x00. Power monitor power-down state. Write following Register CR26: 0x00. Reserved register. Write following Register CR25: 0x70. autocalibration time with frequency setting MHz. frequency different, CR25 according Equation Write following Register CR24: 0x38. Enable autocalibration. Write following Register CR23: 0x70. Enable lock detector lock detector counter 3072 up/down pulses. Write following Register CR22: 0x00. Reserved register. Write following Register CR21: 0x00. Reserved register. Write following Register CR20: 0x00. Reserved register. Write following Register CR19: 0x00. Reserved register. Write following Register CR18: 0x60. Reserved register. Write following Register CR17: 0x00. Reserved register. Write following Register CR16: 0x00. Reserved register. Write following Register CR15: 0x00. Reserved register. Write Register CR14: 0x00. Lock Detector Control Write Register CR13: 0x08. Reserved register. Write following Register CR12: 0x18. powered Write following Register CR11: 0x00. Reserved register. Write following Register CR10: 0x21. reference path doubler enabled 5-bit divider divideby-2 divider bypassed. Write following Register CR9: 0x70. With recommended loop filter component values RSET charge pump current loop bandwidth kHz. Write following Register CR8: 0x00. Reserved register. Write following Register CR7: 0x0X. according Equation Equation Theory Operation section. Write following Register CR6: 0xXX. according Equation Equation Theory Operation section. Write Register CR5: 0x00. Disable 5-bit reference divider. Write following Register CR4: 0x01. Reserved register. Write following Register CR3: 0x0X. according Equation Equation Theory Operation section. Write following Register CR2: 0xXX. according Equation Equation Theory Operation section. Write following Register CR1: 0xXX. according Equation Equation Theory Operation section. Write following Register CR0: 0xXX. according Equation Equation Theory Operation section. Register must last register written double buffered writes take effect. Monitor LDET output wait ensure that locked. Write following Register CR30: 0x01. power
Rev. Page
ADRF6850 EVALUATION BOARD
evaluation board designed allow user evaluate performance ADRF6850. contains following: ADRF6850 DUT. This demodulator with integrated fractional-N VCO. interface connectors. Baseband output connectors. Fourth-order low-pass loop filter circuitry. 13.5 reference clock, ability drive reference input external board. Circuitry support differential signaling TESTLO inputs, including biasing circuitry. Circuitry monitor LOMON outputs. connectors power supplies, VGAIN input single-ended input. capacitors that placed close possible good local decoupling. impedance these capacitors should constant across broad frequency range. Surface-mount multilayered ceramic chip (MLCC) Class capacitors provide very ESR, which assist decoupling supply noise effectively. They also provide good temperature stability good aging characteristics. Capacitance changes bias voltage that applied. Larger case sizes have less capacitance change applied bias voltage, also lower higher ESL. combination 0402 size cases capacitors 0603 size cases capacitors give good compromise allowing capacitors placed close possible supply pins side with capacitors placed bottom side quite close supply pins. capacitors examples these types capacitors recommended decoupling.
evaluation board comes with associated software allow easy programming ADRF6850.
Interface
interface connector nine-way, D-type connector that connected printer port Figure shows cable diagram that must used with provided software. There also option interface using receptacle connector. This standard connector. supply voltage +3.3 provided master. Pull-up resistors required signal lines. used slave address ADRF6850. high sets slave address 0x78, sets slave address 0x58.
HARDWARE DESCRIPTION
more information, refer circuit diagram Figure
Power Supplies
external +3.3 supply (DUT powers each nine VCCx supplies ADRF6850 well 13.5 clock reference.
Recommended Decoupling Supplies
Initially, external +3.3 supply decoupled capacitor then further parallel combination
DATA
9-WAY FEMALE D-TYPE
25-WAY MALE D-TYPE PRINTER PORT
Figure Cable Diagram
Rev. Page
09316-070
ADRF6850
Baseband Outputs VOCM
pair baseband outputs connected board connectors. They ac-coupled output connectors. VOCM, which sets common-mode output voltage, grounded internal baseband (VOCM) reference selected Register CR29, external baseband (VOCM) reference selected setting this then voltage needs applied through needs removed.
LOMON Outputs
These pins differential monitor outputs that provide replica internal frequency single-ended power load programmed dBm, dBm, dBm, dBm. These open-collector outputs must terminated Because both outputs must terminated options provided terminate using onboard resistors series inductors ferrite bead), which case termination provided measuring instrument.
Loop Filter
fourth-order loop filter provided output charge pump required adequately filter noise from modulator used N-divider. With charge pump current midscale value using on-chip VCO, loop bandwidth approximately kHz, phase margin 55°. capacitors recommended loop filter because they have dielectric absorption, which required fast accurate settling time. capacitors result long tail being introduced into settling time transient.
CCOMPx Pins
CCOMPx pins internal compensation nodes that must decoupled ground with capacitor.
MUXOUT
MUXOUT test output that allows different internal nodes monitored. CMOS output stage that requires termination.
Lock Detect (LDET)
Lock detect CMOS output that indicates state PLL. high level indicates locked condition, level indicates loss lock condition.
Reference Input
reference input supplied 13.5 Jauch clock generator external clock through Connector frequency range reference input from with frequency limited maximum MHz. Double 13.5 clock using onchip reference frequency doubler optimize phase noise performance.
Inputs (RFI, RFCM, RFI)
internally biased inputs. singleended operation demonstrated evaluation board, must ac-coupled source must ac-coupled ground plane. RFCM input common-mode pin. should connected when driving input singleended mode. When driving input differentially using balun, connect this common terminal output coil balun.
TESTLO Inputs
These pins differential test inputs that allow variety debug options. this board, capability provided drive these pins with external signal that then applied Anaren balun provide differential input signal. When driving TESTLO pins, bypassed, demodulator driven directly this external signal. frequency signal needs times operating frequency. These inputs also require bias. bias default option used board.
VGAIN
VGAIN sets gain VGA. VGAIN voltage range from This allows gain vary from
Rev. Page
ADRF6850
SCHEMATIC
09316-058
Figure Applications Circuit
Rev. Page
ADRF6850
ARTWORK
Component Placement
Figure Evaluation Board, Side Component
09316-071
Figure Evaluation Board, Bottom Side Component Placement
09316-073
Figure Evaluation Board, Side-Layer
Figure Evaluation Board Power-Layer
09316-075
Figure Evaluation Board, Ground-Layer
Figure Evaluation Board, Bottom Side-Layer
Rev. Page
09316-074
09316-076
09316-072
ADRF6850
BILL MATERIALS
Table Bill Materials
Qty. Reference Designator C10, C12, C14, C16, C40, C48, C53, C11, C13, C15, C17, C22, C27, C47, C52, C21, C38, C44, C43, J12, J20, R20, R14, R17, R35, R44, R60, R46, LDET, MUXOUT, VTUNE, SCLK, SDA, BAL1 Description ADRF6850 LFCSP, 56-lead VCO, 13.5 Connector, 9-pin, D-sub plug, D-SUB9MR Connector, I2C, SEMCONN receptacle Capacitor, tantalum, TAJ-C Capacitor, ceramic, C0G, 0402 Capacitor, X7R, ceramic, 0603 Capacitor, C0G, ceramic, 0603 Capacitor, NPO, ceramic, 1206 Capacitor, C0G, ceramic, 0603 Capacitor, C0G, ceramic, 0402 Capacitor, X7R, ceramic, 0402 Capacitor, C0G, ceramic, 0402 Capacitor, X5R, ceramic, 0603 launch connector Jumper, 3-pin plus shunt Inductor, 0402, series Inductor, 0805, series Resistor, 1/16 0402 Resistor, 1/10 0603 Resistor, 1/10 0603 Resistor, 1/16 0603 Resistor, 1/16 0402 Resistor, 0603, spacing install) Resistor, 1/16 0402 Resistor, 1/10 0805 Resistor, 1/10 0805 Resistor, 1/16 0402 Test point, 1-pin, 0.035 inch diameter Balun, 0805, balanced (1.3 GHz) Manufacturer Analog Devices Jauch McMurdo Digikey Murata Kemet Murata Murata Murata Murata Phycomp Johnson/Emerson Harwin Murata Murata Vishay Draloric Multicomp Phycomp Multicomp Vishay Dale Multicomp Vishay Draloric Bourns Phycomp inserted Anaren Part Number ADRF6850BCPZ 13.50-VX7-G-3.3-1T1-LF 1071806 5-1761185-1-ND 197518 1658861 317287 1402814 1535582 8819920 8819572 1414575 8819564 1458902 142-0701-851 148533 150411 LQW15AN20N LQM21FN1N100M 1158241 1576293 9233393 9330801 1514682 1358008 1739223 Digi RR12P100DTR-ND 9239359
BD1631J50100A00
Rev. Page
ADRF6850 OUTLINE DIMENSIONS
8.10 8.00 7.90 0.60 0.60
0.30 0.23 0.18
INDICATOR
INDICATOR
7.85 7.75 7.65
0.50
EXPOSED
5.25 5.10 4.95
VIEW 1.00 0.85 0.80 SEATING PLANE 0.80 0.65
0.50 0.40 0.30 0.05 0.02 COPLANARITY 0.20 0.08
BOTTOM VIEW 6.50
0.25
PROPER CONNECTION EXPOSED PAD, REFER CONFIGURATION FUNCTION DESCRIPTIONS SECTION THIS DATA SHEET.
081809-B
COMPLIANT JEDEC STANDARDS MO-220-VLLD-2
Figure 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Body, Very Thin Quad (CP-56-5) Dimensions shown millimeters
ORDERING GUIDE
Model ADRF6850BCPZ ADRF6850BCPZ-R7 EVAL-ADRF6850EB1Z
Temperature Range -40°C +85°C -40°C +85°C
Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Tray 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ], Tape Reel Evaluation Board
Package Option CP-56-5 CP-56-5
RoHS Compliant Part.
refers communications protocol originally developed Philips Semiconductors (now Semiconductors).
©2010 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D09316-0-10/10(0)
Rev. Page
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