ADC10D1000 1500RB
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September 2009
ADC10D1000/1500RB
Reference Board Users' Guide
Copyright 2009 National Semiconductor Corporation
Table Contents Overview
Features Packing List References
Quick Start
Installing WaveVision Software Installing ADC10D1000/1500RB Hardware Launching WaveVision Software WaveVision User Interface Overview System Device Configuration Data Capturing
Secondary Panel Description Reference Board Functional Description
System Block Diagram System Description
Electrical Specification
Copyright 2009 National Semiconductor Corporation
Overview
ADC10D1000/1500RB demonstrates high-performance signal acquisition sub-system that achieves 10-bit resolution corresponding dynamic range channels signal frequencies excess sampling rates least 1.0/1.5 GS/s channel sampling rate 2.0/3.0 GHz. board showcases following National Semiconductor devices: ADC10D1000/1500 analog-to-digital converter LMX2531 clock synthesizer LP3878 LP38853 linear regulators LM20242, LM25576 LM26400 switching regulators LM3880 power sequencing controller LM95233 temperature sensor
addition, board also employs Xilinx XC4VLX25-11FFG668 Virtex-4 FPGA critical function capturing high-speed digital data sourced ADC.
Copyright 2009 National Semiconductor Corporation
Features
Demonstrates ADC10D1000/1500's typical dynamic performance datasheet full details. Sample rates 1.0/1.5 GS/s (limited specifications FPGA capture limitations) Input signal frequencies 2.8/3.1 On-board LMX2531 based clock circuit with connector selectable external clock complete high-performance low-noise power management section ADC, clock circuit, FPGA controller Single +7.5V power adapter input Simplicity performance connection Functions with National's latest WaveVision signal-path control analysis software.
Packing List
ADC10D1500RB consists following components: ADC10D1000/1500RB Board Documentation Including ADC10D1000/1500 datasheet Anaren balun datasheet ADC10D1000/1500RB Users Guide (this document) WaveVision Users Guide ADC10D1000/1500RB schematic ADC10D1000/1500RB bill materials ADC10D1000/1500RB test results from National user license agreement Letter user Hardware Including 110V-240V +7.5V Power Adapter cable blocks terminators Anaren balun board (useful bandwidth GHz) MiniCircuits balun board (useful bandwidth GHz) cables
References
*ADC10D1000/1500 datasheet *LMX2531 datasheet
*Note: Please refer www.national.com latest edition datasheets.
Copyright 2009 National Semiconductor Corporation
Board Orientation
Ext. Trigger LMX2531 Clock Clock DCLK_RST Q-ch. Sig. I-ch. Sig. LEDs
ADC10D1500
Power section
Control FPGA (Xilinx
Controller
Power +7.5
Power Switch
Auxiliary Data Port (Mictor
Figure ADC10D1000/1500RB Board Layout
Copyright 2009 National Semiconductor Corporation
Figure Jumpers LEDs
Copyright 2009 National Semiconductor Corporation
Quick Start
This section will bringing board first time well brief tutorial WaveVision (WV5) software. Further description Reference Board subsequent sections this document. software further described WaveVision Users' Guide HELP function within software. ADC10D1000/1500 LMX2531 datasheets should consulted detailed understanding device functionality. user advised construct setup close shown Figure possible. This setup, along with board software configuration described below, what used test reference board National's lab. This conditions produces stated reference performance which normally included with each board shipped customers. objective assure that user achieve same performance that recorded National's prior board shipment.
overdrive signal clock inputs damaged. Refer Electrical Specification section voltage tolerance these inputs. very cautious signal generator power levels above dBm. Input maximum about maximum.
Figure Recommended setup. filter necessary clock generator very clean (beyond -80dBm SFDR).
Copyright 2009 National Semiconductor Corporation
Installing WaveVision Software
(Note: WaveVision software requires Windows operating system)
Insert included WaveVision CD-ROM into computer drive. Locate WaveVision Setup.exe program CD-ROM. Follow on-screen instructions complete installation.
Installing ADC10D1000/1500RB Hardware
Place ADC10D1000/1500RB Reference Board clean, static-free surface. Make sure board's jumpers configured follows shown Figure ADC, "ECE (Extended Control Enable, active low)" jumper should installed position. This enables control ADC. must connected Ground ac-coupled operation. board ships with this jumper place configured ac-coupled operation only. (The jumper removed dc-coupled operation. that case applied signal must dc-coupled, have common mode voltage required ADC10D1500 voltage.) jumpers must place shown enable both channels ADC. Connect enclosed +7.5V power adapter power jack. Connect other side power supply outlet (100-240 VAC, 50-60 Hz). Connect input signal generator, band-pass filter, balun blocks ADC10D1000/1500RB Reference Board's I-channel input connectors. signal generator frequencies signal levels stated reference performance report. Always high-quality cables optimum performance.
overdrive signal clock inputs damaged. Refer Electrical Specification section voltage tolerance these inputs. very cautious signal generator power levels above about (2mW). This approximately V-P-P which also full scale range ADC. Depending other hardware that casaded with generator path (baluns, filters, etc), caution should taken with signals above +3dBm
National lab, following equivalent performance) equipment used test board. essential that customer signal generators, filters, blocks balun equivalent better performance. Rohde Schwarz SME-03 SMA-100 signal generator Filters Trilithic tunable bandpass filter other fixed frequency bandpass filter equivalent performance Balun Anaren Balun Board blocks Mini Circuits BLK-89 terminators Mini Circuits ANNE Note: board comes equipped with DC-blocks applied I-channel signal input connectors blocks terminators applied unused Q-channel input connectors. These must used times that channel being used must connected through dc-blocks configured ac-coupled operation shipped). unused channel must also blocked then terminated ground. This graphically illustrated Figure Turn rocker power switch. Verify that (labeled LD1, near power jack) lit.
Copyright 2009 National Semiconductor Corporation
Connect supplied cable from port ADC10D1000/1500RB jack.
Launch WaveVision Software.
Start WaveVision software your computer selecting desktop icon "WaveVision clicking Start button, selecting Programs WaveVision WaveVision software will automatically detect board load appropriate software profile will proceed download controller firmware FPGA code onto reference board. alternative, icon desktop used launch WaveVision WaveVision user interface will appear computer screen. STANDBY should green meaning that hardware ready capture data from upon user's command. software board ready acquire data this point. status LED's should take following states when system ready acquisition:
(Where yellow black yellow with spokes indicates blinking)
health2 overrange_Q trigger standby acquire overrange_I health1 needcal overtemp
FPGA operational
trigger seen Ready acquire Acquiring
DCLKs good (either/both I&Q) implemented
Copyright 2009 National Semiconductor Corporation
WaveVision User Interface Overview
Figure WaveVision Example Window Figure above shows user interface panel (GUI). This level interface panel. arranged such that plot always middle. There tabs arranged each side window give user additional information control features. tabs available left side access panels that pertinent current plot window such channel selection, grid selection, Readouts, controls. right side panels allow user take control hardware. These include Signal Source, Signal Control Registers panels (the most relevant this board). addition, small parameter summary displayed pressing CTL-R. more details general operation WaveVision please refer WaveVision Users Guide.
Copyright 2009 National Semiconductor Corporation
System Device Configuration
Prior capturing data, confirm that board "ECE (Extended Control Enable)" mode, jumper located control jumper area shown Figure board should sent with this jumper place. This means that will controlled through interface with jumpers driving control pins. This allows user control ADC's behavior through WaveVision Registers panel.
Figure WaveVision overview control buttons
Figure WaveVision main window command buttons
Copyright 2009 National Semiconductor Corporation
2.5.1 Main Panel
main menu WaveVision software several control buttons shown Figures which used perform most tasks with button click. Load Plot plot window created Plot Load dialog displayed. selected plot file loaded into window. Import Data Clicking this button creates time-domain plot opens Import Data dialog. Data imported from WaveVision data files well from ASCII data files created other programs. Create Time Domain Plot Clicking this button creates time-domain plot. plot will contain data, available data destination. Create Hardware Histogram Plot Clicking this button creates hardware histogram plot. Hardware histograms available only conjunction with evaluation boards which gather histogram data internally. This button enabled only when evaluation board which supports hardware histograms attached. Acquire Data Click this button acquire data active plot. have created more than plot, Active plot highlighted title bar. Continuous Acquisition This button toggle when pressed, data acquired continuously, buffer after another fast hardware when pressed again data acquisition stops. When continuous acquisition mode, acquisition started stopped using Acquire button without leaving continuous acquisition mode. Averaging This button also toggle when pressed, FFT's averaged. number buffers averaged specified hardware section Signal Sources tab. Please refer WaveVision Users Guide more information.
Copyright 2009 National Semiconductor Corporation
2.5.2 Plot Window Controls
Figure WaveVision plot window controls Load Plot Plot Load dialog displayed, selected plot file loaded into window. Save Plot Displays Plot Save dialog (this button only active when plot contains more channels with data). Reset Zoom Reset axis zoom 100%. Clear Clear data from channels. Print Print plot. Time Domain Display plot time domain data. Display plot Histogram Display histogram data. Close Close this plot.
Copyright 2009 National Semiconductor Corporation
2.5.3 Right Panels Signal Source
Figure WaveVision main window command buttons Open Signal Source panel right side window confirm that ADC10D1500RB available confirm that selected. There three possible modes operation selectable here: I-Channel channel mode capturing viewing I-channel data Q-Channel channel mode capturing viewing Q-channel data DES-mode -Dual Edge Sampling (interleaved) Mode Double Edge Sampling (DES) Double edge sampling works much same single edge
sampling except that signals sampled both rising falling edge sample clock. This effectively doubles sample rate. this mode, both converters inside ADC10D1000/1500 work common input signal. mode selected from Signal Source right side. Then, Q-channel must also selected input. this, Register panel select Config DESQ then perform Write Config Register. Q-channel operation will give best mode performance. Also, selecting DESIQ Config register recommended since parallels channel inputs resulting lower than normal input impedance.
Copyright 2009 National Semiconductor Corporation
Figure WaveVision main window command buttons
Sampling Rate When signal source panel selected, clock frequency displayed. This initially internal clock. this example, 986/1500 generated LMX2531 evaluation board. sampling rate determined FPGA when board powered calculation accurate better than external source use, confirm that this number corresponds clock reference that applied. correct, subsequent data captures display will correct. Resolution This will always ADC10D1000/1500 resolution which bits. Acquisition Size This setting displays selects number samples captured each acquisition. samples default, with settings samples. larger sample size increases equivalent bandwidth resolution, expense more memory slower acquisition time. Data Format default data format offset binary ADC10D1000/1500. buffers average last option averaging function. Using this feature, subsequent samples averaged obtain improved signal noise. However, this expense time. example, averages will improve about 10dB requires more time.
Copyright 2009 National Semiconductor Corporation
2.5.4 Right Panels Registers
Next, configure hardware (including ADC) using Registers control panel right side. This most important panels controlling ADC10D1000/1500RB. This panel seven sub-tabs that control settings board registers inside ADC10D1000/1500. seven sub-tabs shown below include; Settings, Config, Ichannel, Q-channel, Adjust, Filter Adjust, AutoSync, Temperature.
Figure level Register panel showing available tabs following short description each under Register panel.
Settings: This gives choice either External Clock Internal Clock, buttons
initiate FPGA Reset, Reset Registers Calibrate ADC. Calibration should performed changes occur such device temperature, mode changes (single channel dual channel, single edge sampling (Non-DES) double edge sampling (DES). more information, refer Calibration section ADC10D1000/1500 datasheet. Trigger function also enabled using check this tab. Note: Internal Clock selected, then External Clock signal generator should disconnected switched prevent performance degradation.
Copyright 2009 National Semiconductor Corporation
Config: This configures various features modes ADC10D1000/1500
shown below. accesses changes following functions, which controlled through Configuration Register
Figure Config Panel
Phase Select Determines Data-to-DCLK phase relationship. When unchecked, Mode selected. When checked Mode selected. This effect when Non-Demux Mode selected. Output Voltage Select Selects LVDS differential output voltage. When this unchecked, reduced output amplitude selected. When checked, standard (higher) output amplitude used. Test Pattern Mode When checked device will continually output fixed pattern Data outputs. When cleared, normal Data information output. Power down Channel when checked. Power down channel when checked. Double Edge Sample mode selected when checked. DESQ Double Edge Sample mode uses input (rather than input) when checked. DESIQ Double Edge Sample mode with input shorts both inputs together. Two's Complement output mode selected when checked. Default offset binary.
Note: changes will take effect until Write Config button clicked.
Copyright 2009 National Semiconductor Corporation
I-channel: This changes sign magnitude offset full scale range
settings.
Figure I-Channel Panel I-channel Offset Sign This pull-down selects positive negative offset. I-ch Offset This slider selects magnitude I-ch Offset applied. Adjustment done using computer mouse/pointer, using left/right arrow keys once slider been selected. Although offset entered 4095) relative form, also displayed approximate I-Channel Full Scale approximate I-Channel input full scale range peak-topeak) selected, ranging from minimum 600mV maximum 980mV. default setting 790mV.
Note: changes will take effect until Write I-ch button clicked. Also, must re-calibrated full-scale changed.
Q-channel: Similar I-channel
Copyright 2009 National Semiconductor Corporation
Adjust: This controls Aperture Delay function.
Figure Filter Adjust Panel Duty Cycle Correction When checked (default), automatic Duty Cycle Correction circuit enabled. Select Adjust When checked, enables Aperture Delay Time adjust feature. Coarse Phase Adjust Sets approximate amount coarse Aperture Delay applied. Fine Phase Adjust Sets approximate amount fine Aperture Delay applied. Select Adjust with Filter Enabled When checked, enables Aperture Delay Time adjust feature, with Filter enabled well. (Overrides function)
Note: changes will take effect until Write Adjust button clicked.
Copyright 2009 National Semiconductor Corporation
Filter Adjust: This enables controls center frequency clock filter.
Figure Filter Adjust Panel Select Adjust with Filter Enabled When checked, enables Aperture Delay Time adjust feature, with Filter enabled well. (Overrides function) Filter Adjust Selects approximate Filter center frequency.
Note: changes will take effect until Write Adjust button clicked.
Copyright 2009 National Semiconductor Corporation
AutoSync: This enables controls settings AutoSync feature.
Figure AutoSync Panel Disable DCLK Reset When checked (default) disables DCLK Reset feature Disable Output reference Clocks When checked (default) disables AutoSync reference output clocks. When un-checked CLK/4 signal sent RCOut1 RCOut2 outputs. Enable Slave mode When checked configures this AutoSync slave device. Select Phase Selects Phase incoming reference clock used AutoSync feature. Reference Clock Delay This selects additional delay added input reference clock. Settings (0s) 639d (1000ps). Settings higher than 639d will give 1000ps delay.
Note: changes will take effect until Write AutoSync button clicked.
Copyright 2009 National Semiconductor Corporation
Temperature: This panel provides read-out three different temperatures
ADC10D1000/1500RB.
Figure Temperature Panel Ambient Temperature Provides local/board temperature LM95233 Temperature Provides approximate temperature ADC10D1000/1500. FPGA Temperature Provides approximate temperature Xilinx Virtex-4 FPGA.
Note: changes will appear until Update Temperatures button clicked.
Copyright 2009 National Semiconductor Corporation
Data Capturing
board ready data capture. Before proceeding, perform manual calibration ADC. Even though performs self-calibration time power-up, recommended that user perform another calibration after sufficient time passed system (primarily temperature) stabilize. Manual calibration performed clicking Calibrate feature Register control panel, Settings sub-tab.
2.6.1 Configure Display Settings
Open Control left panel. Confirm that dBFS unit selected. Also confirm that correct clock frequency being measured software checking Signal Source right panel. default frequency on-board clock source shown board performance data shipped with your board.
2.6.2 Check Input Amplitude
Confirm that Over-range LEDs illuminated. increase signal amplitude 'till input just barely lit. increase signal power much beyond this point ADC's inputs damaged Operating Maximums exceeded (see Electrical Specification section). Then reduce signal amplitude until Over-range longer illuminated. should have input signal that very close ADC's full-scale range (e.g., within dB). IMPORTANT: Since signal clock inputs provided with additional protection circuitry this board, burden user overdrive inputs extent damaging them. "Over-range" provided each channel indicate that signal amplitude beyond full-scale range. Increasing signal amplitude much above this point will soon violate Absolute Maximum ratings chip irreparable damage device done. Thus, safe method setting signal amplitude full-scale level utilize described previous paragraph roughly obtain full-scale amplitude then inspect captured data software's time-domain plot fine tune amplitude desired level.
2.6.3 Acquire Display Data
Perform data acquisition clicking Acquire Data button (Item Figure acquired data will appear (default) time domain plot window. Switch frequency-domain window (FFT) using WaveVision controls. Type Ctrl-r obtain summary acquisition. Place software continuous mode (Item Figure then acquire again. This confirm that Over-range method used earlier indeed gave signal that within -0.5 -1.0 full-scale range. not, adjust input signal generator's signal power approximately -0.5dB full scale. this point, dynamic performance metrics similar those shown reference data shipped with board obtained. basic variables that experiment with this point change input signal strength frequency. Please note that achieve reference performance, band-pass filters similar items referenced Section should used. absence these filters input signal external clock will usually result sub-standard performance. displayed units should dBFS selected earlier. switch units back dBFS desired.
Copyright 2009 National Semiconductor Corporation
2.6.4 External Clock Source
also possible apply high-quality external signal source clock input rather than using on-board LMX2531 clock synthesizer. This will help quantify LMX2531's performance ultra-high-speed signal-path such this one. When connecting external clock source, generator amplitude should 0dBm. Experiment with clock signal strength determine what effect this channel performance. Care should taken exceed clock input, avoid damage ADC. external clock source enabled through register control panel software after applying signal generator Clock input SMA. external clock source should disconnected turned when on-board clock source selected. Failure will result poor performance mixing on-board clock small amount external clock signal leaking through clock selection relay. important keep mind that ADC's operating conditions changed significant way, especially temperature, should calibrated again before proceeding. Please refer WaveVision Users' Guide integral Help feature more information concerning software.
Copyright 2009 National Semiconductor Corporation
Secondary Panel Description
Please refer WaveVision Users Guide detailed descriptions remaining Left Right panels, additional Main Panel features.
Copyright 2009 National Semiconductor Corporation
Reference Board Functional Description
System Block Diagram
7.5V Power Management Analog_3.3/5.0V (for -board use) Analog_3.3V
Analog Front-End Boards Plug-in Here (LMH6518, Balun, Power Sequencing Control
Analog_1.9V
Digital_3.3V Digital_2.5V Digital_1.8V Digital_1.2V
Temp Sensor (LM95233)
EEPROM
VinI+/ VinQ+/ ADC10D1000/ ADC10D1500
Vcmo
Vreg ORI/Q 12x2 12x2
ADR/DATA
+3.3V
DCLKI/Q SPI(1.8V) SPI(3.3V)
Xilinx Virtex-4 FPGA
Ctrlr.
FIFO
DCLK_RST
SE2DIFF
SE2DIFF
Clock (LMX2531) Trigger
+3.3V/5V, USI-1 Conx.x2 external devices uWire
Local Clock MHz)
SE2DIFF
Figure ADC10D1000/1500RB System Block Diagram
Copyright 2009 National Semiconductor Corporation
System Description
4.2.1 ADC10D1000/1500
ADC10D1000/1500 forms heart this reference board. This low-power, high-performance CMOS analog-to-digital converter digitizes signals 10-bit resolution guaranteed minimum sampling rates 1.0/1.5 Gs/s dual channel configuration 2.0/3.0 Gs/s single channel configuration. ADC10D1000/1500 targeted achieving very good accuracy dynamic performance while consuming less than Watts power when both channels powered-up. product packaged thermally enhanced package that does require heat sink over rated ambient temperature range degrees degrees Refer latest version ADC10D1000/1500 datasheet more detailed information. This reference board gives complete control over ADC10D1000/1500 gives user direct performance results chip without need elaborate setup. Each device's control pins high low. Control provided different manners direct control with jumpers through serial interface (the device's extended control mode) using register control panel. order extended control mode jumper must LOW. This recommended method gives user most flexibility ease use. Analog Front-End: analog signal connection kept simple this board order achieve highest possible bandwidth. board designed coupled front-end circuitry coupled manner. AC-coupling requires dc-blocks connectors. default, board shipped National with dc-blocks. addition, board also jumper-configured DC-coupled operation (pin removed operation). IMPORTANT: Since signal clock inputs provided with additional protection circuitry this board, burden user overdrive inputs extent damaging them. "Over-range" provided each channel indicate that signal amplitude beyond full-scale range. Increasing signal amplitude much above this point will soon violate Absolute Maximum ratings chip irreparable damage device done. same caution applies clock input when external signal generator used. However, this case, there Over-range assist user. National's setups, clock signal generator power level 0dBm used. Going beyond +4dBm pins could damage device. Multi-channel synchronization: DCLK_RST signal input provided synchronize ADCs multiple boards systems. addition, ADC10D1000/1500 supports method synchronization, called AutoSync. Please refer ADC10D1000/1500 datasheet more details.
4.2.2 LMX2531 Clock Synthesis chip
LMX2531xxxx family provides single-chip, very low-jitter clock solution frequencies almost GHz. this application, LMX2531LQ1500E used which programmed operate over range 1499-1510 MHz. ADC10D1500RB board, device configured frequency this range through serial interface which controlled through WaveVision register control panel. particular frequency chosen that generates least phase noise. necessarily round number depends loop feedback PLL's clock synthesis chip.
Copyright 2009 National Semiconductor Corporation
clock source selected between on-board LMX2531 external clock source connected through connector. selection performed through register panel. recommended that external clock source should connected enabled before selected. optimum performance, external clock signal generator LMX2531 should enabled same time. This because relay used select between them does provide adequate isolation keep from affecting other. Having both clocks simultaneously will result excessive spurious signals. default setting this board on-board LMX2531 clock source.
4.2.3 FPGA
design employs Xilinx Virtex-4 FPGA capturing digital data. While board powered configured, FPGA continually receiving data from ADC. response user command through WV-5 software, captures desired amount data on-chip buffer maximum samples per-channel). user then command FPGA upload captured data through interface further processing. This board support ability program FPGA specific requirements. standard JTAG connector provided downloading FPGA object code from Xilinx development environment. Please note that National Semiconductor does provide support user-designed FPGA functionality beyond standard functionality that shipped with board. Hardware Trigger: board design supports external hardware trigger that connected FPGA. When hardware trigger enabled, acquisition selected from software, actual beginning data capture will postponed until external trigger pulse applied connector. Auxiliary Port: Mictor 38-pin connectors form auxiliary data port. With user program FPGA output high-speed continuous streaming data from signal-path rest system. This feature currently supported.
4.2.4 LM95233 Temperature Sensor
Using National LM95233 temp sensor chip; ambient, ADC10D1000/1500 Xilinx FPGA temperatures monitored. temperature readings available through WV-5 software.
Copyright 2009 National Semiconductor Corporation
Electrical Specification
Power Supply: Nominal 7.5V Minimum 7.0V, Maximum 8.0V (Voltage above this level will cause damage!!)
Power Consumption: Nominal Watts Maximum Watts Input Signals: Maximum Operating Voltage +2.0V Recommended/initial (full scale) generator setting Maximum generator setting (Voltage above this level will cause damage!!) Maximum Operating Voltage +2.0V Recommended generator setting Maximum generator setting (Voltage above this level will cause damage!!) compliant
Clock Input Signal:
Port:
Copyright 2009 National Semiconductor Corporation
USING THIS PRODUCT, AGREEING BOUND TERMS CONDITIONS NATIONAL SEMICONDUCTOR'S USER LICENSE AGREEMENT. THIS PRODUCT UNTIL HAVE READ AGREED TERMS CONDITIONS THAT AGREEMENT. AGREE WITH THEM, CONTACT VENDOR WITHIN (10) DAYS RECEIPT INSTRUCTIONS RETURN UNUSED PRODUCT REFUND PURCHASE PRICE PAID, ANY.
ADC10D1500RB Reference Board intended product evaluation purposes only intended resale consumers, authorized such designed compliance with European Directive 89/336/EEC, compliance with other electromagnetic compatibility requirements. National Semiconductor Corporation does assume responsibility circuitry and/or software supplied described. circuit patent licenses implied. LIFE SUPPORT POLICY NATIONAL'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL PRESIDENT NATIONAL SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
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www.national.com National does assume responsibility circuitry described, circuit patent licenses implied National reserves right time without notice change said circuitry specifications.
Copyright 2009 National Semiconductor Corporation
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