AD9271
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Octal LNA/VGA/AAF/ADC Crosspoint Switch AD9271
channels LNA, VGA, AAF, noise preamplifier (LNA) Input-referred noise nV/Hz typical, gain SPI-programmable gain dB/15.6 dB/18 Single-ended input; maximum p-p/ p-p/250 Dual-mode active input impedance matching Bandwidth (BW) Full-scale (FS) output differential Variable gain amplifier (VGA) Gain range Linear-in-dB gain control Antialiasing filter (AAF) 3rd-order Butterworth cutoff Programmable from Analog-to-digital converter (ADC) bits MSPS MSPS SFDR Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link) Data frame clock outputs Includes crosspoint switch support continuous wave (CW) Doppler power, channel bits/40 MSPS (TGC) channel Doppler Single supply (3.3 supply Doppler output bias) Flexible power-down modes Overload recovery Fast recovery from power standby mode, 100-lead TQFP
DRVDD PDWN STBY AVDD
LOSW-A LO-A LI-A LG-A LOSW-B LO-B LI-B LG-B LOSW-C LO-C LI-C LG-C LOSW-D LO-D LI-D LG-D LOSW-E LO-E LI-E LG-E LOSW-F LO-F LI-F LG-F LOSW-G LO-G LI-G LG-G LOSW-H LO-H LI-H LG-H
AD9271
12-BIT
SERIAL LVDS
DOUTA+ DOUTA-
12-BIT
SERIAL LVDS
DOUTB+ DOUTB-
12-BIT
SERIAL LVDS
DOUTC+ DOUTC-
12-BIT
SERIAL LVDS
DOUTD+ DOUTD-
12-BIT
SERIAL LVDS
DOUTE+ DOUTE-
12-BIT
SERIAL LVDS
DOUTF+ DOUTF-
12-BIT
SERIAL LVDS
DOUTG+ DOUTG-
12-BIT
SERIAL LVDS
DOUTH+ DOUTH-
SERIAL PORT INTERFACE
DATA RATE MULTIPLIER
FCO+ FCO- DCO+ DCO-
APPLICATIONS
Medical imaging/ultrasound Automotive radar
REFERENCE SWITCH ARRAY
GAIN-
SENSE VREF REFB REFT RBIAS
GAIN+
SCLK
SDIO
CWVDD
AD9271 designed cost, power, small size, ease use. contains eight channels variable gain amplifier (VGA) with noise preamplifier (LNA); antialiasing filter (AAF); 12-bit, MSPS MSPS analog-to-digital converter (ADC). Each channel features variable gain range fully differential signal path, active input preamplifier termination, maximum gain with conversion rate MSPS. channel optimized dynamic performance power applications where small package size critical.
Figure
single-ended-to-differential gain that selectable through SPI. input noise typically nV/Hz, combined input-referred noise entire channel nV/Hz maximum gain. Assuming noise bandwidth (NBW) 15.6 gain, input roughly Doppler mode, output drives transconductance that switched through differential crosspoint switch. switch programmable through SPI.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007-2009 Analog Devices, Inc. rights reserved.
06304-001
GENERAL DESCRIPTION
CWD[5:0]+/-
CLK+ CLK-
AD9271 TABLE CONTENTS
Features Applications General Description Functional Block Diagram Revision History Product Highlights Specifications. Specifications. Digital Specifications Switching Specifications Timing Diagrams Absolute Maximum Ratings. Thermal Impedance Caution Configuration Function Descriptions Equivalent Circuits Typical Performance Characteristics Theory Operation Ultrasound. Channel Overview. Input Overdrive Doppler Operation Operation Clock Input Considerations Serial Port Interface (SPI) Hardware Interface. Memory Reading Memory Table Reserved Locations Default Values Logic Levels Applications Information Design Guidelines Evaluation Board Power Supplies Input Signals. Output Signals Default Operation Jumper Selection Settings Quick Start Procedure Schematics Artwork Outline Dimensions Ordering Guide
REVISION HISTORY
5/09-Rev. Rev. Changes Figure Changes Figure Figure Changes Ordering Guide 12/07-Rev. Rev. Change Specifications Text Added Input Noise Current Added Noise Figure Changes Signal-to-Noise Ratio Units Changes Harmonic Distortion Units Added Endnote Changes Table Inserted Figure Figure Changes Figure Changes Theory Operation Section Changes Figure Figure Change Active Impedance Matching Section Changes Noise Section Changes Figure Change Input Overload Protection Section Changes Operation Section Changes Gain Control Section Changes Figure Change Table Changes Serial Interface Port (SPI) Section Changes Hardware Interface Section Changes Reading Memory Table Section Added Applications Information Design Guidelines Sections Change Input Signals Section. Changes Figure Changes Table 6/07-Revision Initial Version
Rev. Page
AD9271
AD9271 requires LVPECL-/CMOS-/LVDS-compatible sample rate clock full performance operation. external reference driver components required many applications. automatically multiplies sample rate clock appropriate LVDS serial data rate. data clock (DCO±) capturing data output frame clock (FCO±) trigger signaling output byte provided. Powering down individual channels supported increase battery life portable applications. There also standby mode option that allows quick power-up power cycling. Doppler operation, VGA, AAF, powered down. power path scales with selectable speed grades. contains several features designed maximize flexibility minimize system cost, such programmable clock, data alignment, programmable digital test pattern generation. digital test patterns include built-in fixed patterns, built-in pseudorandom patterns, custom user-defined test patterns entered serial port interface. Fabricated advanced CMOS process, AD9271 available RoHS compliant, 100-lead TQFP. specified over industrial temperature range -40°C +85°C.
PRODUCT HIGHLIGHTS
Small Footprint. Eight channels contained small, space-saving package. Full path, ADC, crosspoint switch contained within 100-lead, TQFP. Power Channel MSPS. Integrated Crosspoint Switch. This switch allows numerous multichannel configuration options enable Doppler mode. Ease Use. data clock output (DCO±) operates supports double data rate (DDR) operation. User Flexibility. Serial port interface (SPI) control offers wide range flexible features meet specific system requirements. Integrated Third-Order Antialiasing Filter. This filter placed between path programmable from MHz.
Rev. Page
AD9271 SPECIFICATIONS
SPECIFICATIONS
AVDD DRVDD CWVDD internal reference, MHz, gain 15.6 (6), cutoff cutoff kHz, full temperature, unless otherwise noted. Table
Parameter CHARACTERISTICS Gain 5/6/8 Conditions Single-ended input differential output Single-ended input single-ended output output limited differential output AD9271-25 14/15.6/18 8/9.6/12 AD9271-40 14/15.6/18 8/9.6/12 AD9271-50 14/15.6/18 8/9.6/12 Unit
Input Voltage Range, Gain 5/6/8 Input Common Mode Input Resistance
400/333/250
400/333/250
400/333/250
pA/Hz nV/Hz
LI-x 1.4/1.4/1.3 770/650/495
1.3/1.2/1.1 770/650/495
1.3/1.2/1.1 770/650/495
Input Capacitance Bandwidth Input Noise Current, Gain 5/6/8 Input Noise Voltage, Gain 5/6/8 Input Compression Point, Gain 5/6/8 Noise Figure Active Termination Match Unterminated FULL-CHANNEL (TGC) CHARACTERISTICS High-Pass Cutoff Low-Pass Cutoff Bandwidth Tolerance Group Delay Variation Input-Referred Noise Voltage Correlated Noise Ratio Output Offset Signal-to-Noise Ratio (SNR) dBFS dBFS
VGAIN
programmable
MHz, gain gain 5/6/8, signal, correlated/ uncorrelated high pass
DC/350/700 fSAMPLE 1.7/1.6/1.5
DC/350/700 fSAMPLE 1.6/1.4/1.3
DC/350/700 fSAMPLE 1.6/1.4/1.2
nV/Hz
VGAIN VGAIN
65.8
64.4 59.7
63.7
dBFS dBFS
Rev. Page
AD9271
Parameter Harmonic Distortion Second Harmonic dBFS Second Harmonic dBFS Third Harmonic dBFS Third Harmonic dBFS Two-Tone IMD3 Distortion fIN1 dBFS, fIN2 dBFS Channel-to-Channel Crosstalk Channel-to-Channel Crosstalk (Overrange Condition) Overload Recovery Conditions VGAIN AD9271-25 AD9271-40 AD9271-50 Unit dBFS
VGAIN
dBFS
VGAIN
dBFS
VGAIN
dBFS
VGAIN
-54.6
-63.4
-68.5
GAIN ACCURACY Gain Conformance Error
Full path, MHz, gain 25°C VGAIN VGAIN VGAIN VGAIN normalized ideal loss VGAIN -1.2
Degrees
+0.8 +1.2 -1.2 -1.3 +1.3 -1.3 -1.2
+0.8 +1.2 -1.2 +1.3 -1.3 -1.2
+0.8 +1.2 -1.2 +1.3
Linear Gain Error
Channel-to-Channel Matching GAIN CONTROL INTERFACE Normal Operating Range Gain Range Scale Factor Response Time DOPPLER MODE Transconductance Common Mode Input-Referred Noise Voltage Output Bias Maximum Output Swing
normalized ideal loss change gain 5/6/8 Doppler output pins gain 5/6/8, channel channel 31.6 10/12/16 /1.7/1.5
31.6 10/12/16
31.6 10/12/16
dB/V mA/V nV/Hz
/1.5/1.4
/1.5/1.3
Rev. Page
AD9271
Parameter POWER SUPPLY AVDD DRVDD CWVDD IAVDD Conditions Full-channel mode Doppler mode with four channels enabled Full-channel mode, signal AD9271-25 AD9271-40 AD9271-50 Unit
IDRVDD Total Power Dissipation (Including Output Drivers)
46.7
1063
48.7 1190
1280
1425
1494
Doppler mode with four channels enabled Power-Down Dissipation Standby Power Dissipation Power Supply Rejection Ratio (PSRR) RESOLUTION REFERENCE Output Voltage Error (VREF Load Regulation (VREF Input Resistance
101.7
112.5
120.6
mV/V
Bits
AN-835 Application Note, Understanding High Speed Testing Evaluation, complete definitions these tests were completed. single ended. overrange condition specified being more than full-scale input range.
Rev. Page
AD9271
DIGITAL SPECIFICATIONS
AVDD DRVDD CWVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
Parameter CLOCK INPUTS (CLK+, CLK-) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, STBY, SCLK) Logic Voltage Logic Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic Voltage Logic Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO) Logic Voltage Logic Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO) Logic Voltage (IOH Logic Voltage (IOL DIGITAL OUTPUTS (D+, D-), (ANSI-644)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D+, D-), (LOW POWER, REDUCED SIGNAL OPTION)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default)
Temperature
Unit
CMOS/LVDS/LVPECL Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full 1.79 0.05 LVDS Full Full 1.125 Offset binary 1.375 DRVDD
LVDS Full Full 1.10 Offset binary 1.30
AN-835 Application Note, Understanding High Speed Testing Evaluation, complete definitions these tests were completed. Specified LVDS LVPECL only. Specified SDIO pins sharing same connection.
Rev. Page
AD9271
SWITCHING SPECIFICATIONS
AVDD DRVDD CWVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
Parameter CLOCK Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width (tEL) OUTPUT PARAMETERS2, Propagation Delay (tPD) Rise Time (tR) (20% 80%) Fall Time (tF) (20% 80%) Propagation Delay (tFCO) Propagation Delay (tCPD) Data Delay (tDATA)4 Delay (tFRAME)4 Data-to-Data Skew (tDATA-MAX tDATA-MIN) Wake-Up Time (Standby), VGAIN Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Uncertainty (Jitter)
Temp Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C Full
Unit MSPS MSPS Clock cycles
10.0 10.0 tFCO (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24)
(tSAMPLE/24) (tSAMPLE/24)
(tSAMPLE/24) (tSAMPLE/24) ±200
25°C
AN-835 Application Note, Understanding High Speed Testing Evaluation, complete definitions these tests were completed. adjusted interface. Measurements were made using part soldered FR-4 material. tSAMPLE/24 based number bits divided because delays based half duty cycles.
Rev. Page
AD9271
TIMING DIAGRAMS
CLK-
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
DOUTx- DOUTx+
tDATA
06304-002 06304-004
Figure 12-Bit Data Serial Stream (Default)
CLK-
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
DOUTx- DOUTx+
tDATA
Figure 12-Bit Data Serial Stream, First
Rev. Page
AD9271 ABSOLUTE MAXIMUM RATINGS
Table
Parameter ELECTRICAL AVDD DRVDD CWVDD AVDD Digital Outputs (DOUTx+, DOUTx-, DCO+, DCO-, FCO+, FCO-) CLK+, CLK- LI-x LO-x LOSW-x CWDx-, CWDx+ SDIO, GAIN+, GAIN- PDWN, STBY, SCLK, REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Storage Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, sec) With Respect DRVDD Rating -0.3 +2.0 -0.3 +2.0 -0.3 +3.9 -0.3 +0.3 -2.0 +2.0 -0.3 +2.0
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
THERMAL IMPEDANCE
Table
Flow Velocity (m/s)
LG-x LG-x LG-x
-0.3 +3.9 -0.3 +2.0 -0.3 +2.0 -0.3 +2.0 -0.3 +3.9 -0.3 +2.0 -0.3 +3.9 -0.3 +2.0 -0.3 +2.0 -40°C +85°C -65°C +150°C 150°C 300°C
20.3 14.4 12.9
Unit °C/W °C/W °C/W
4-layer with solid ground plane (simulated). Exposed soldered PCB.
CAUTION
Rev. Page
AD9271 CONFIGURATION FUNCTION DESCRIPTIONS
LOSW-E LOSW-D CWVDD CWD1+ CWD5+ CWD4+ CWD3+ CWD2+ CWD0+ CWD1- CWD5- CWD4- CWD3- CWD2- CWD0- SENSE RBIAS GAIN+ GAIN- AVDD REFB VREF REFT LO-D LO-E
LI-E LG-E AVDD AVDD LO-F LOSW-F LI-F LG-F AVDD AVDD LO-G LOSW-G LI-G LG-G AVDD AVDD LO-H LOSW-H LI-H LG-H AVDD AVDD CLK- CLK+ AVDD
DRVDD
INDICATOR
LI-D LG-D AVDD AVDD LO-C LOSW-C LI-C LG-C AVDD AVDD LO-B LOSW-B LI-B LG-B AVDD AVDD LO-A LOSW-A LI-A LG-A AVDD AVDD SDIO SCLK
EXPOSED PADDLE, (BOTTOM PACKAGE)
AD9271
VIEW (Not Scale)
DOUTH-
DOUTH+
DOUTG-
DOUTG+
DOUTF-
DOUTF+
DOUTE-
DOUTE+
DCO-
DCO+
FCO-
FCO+
DOUTD-
DOUTD+
DOUTC-
DOUTC+
DOUTB-
DOUTB+
DOUTA-
DOUTA+
DRVDD
STBY
PDWN
AVDD
Figure 100-Lead TQFP Configuration
Table Function Descriptions
Name AVDD Description Ground (exposed paddle should tied quiet analog ground) Analog Supply
DRVDD CWVDD LI-E LG-E LO-F LOSW-F LI-F LG-F LO-G LOSW-G LI-G LG-G LO-H
Digital Output Driver Supply Analog Supply Analog Input Channel Ground Channel Analog Output Channel Analog Output Complement Channel Analog Input Channel Ground Channel Analog Output Channel Analog Output Complement Channel Analog Input Channel Ground Channel Analog Output Channel
Rev. Page
06304-005
AD9271
Name LOSW-H LI-H LG-H CLK- CLK+ DOUTH- DOUTH+ DOUTG- DOUTG+ DOUTF- DOUTF+ DOUTE- DOUTE+ DCO- DCO+ FCO- FCO+ DOUTD- DOUTD+ DOUTC- DOUTC+ DOUTB- DOUTB+ DOUTA- DOUTA+ STBY PDWN SCLK SDIO LG-A LI-A LOSW-A LO-A LG-B LI-B LOSW-B LO-B LG-C LI-C LOSW-C LO-C LG-D LI-D LOSW-D LO-D CWD0- CWD0+ CWD1- CWD1+ CWD2- CWD2+ GAIN- Description Analog Output Complement Channel Analog Input Channel Ground Channel Clock Input Complement Clock Input True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Data Clock Digital Output Complement Data Clock Digital Output True Frame Clock Digital Output Complement Frame Clock Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Standby Power-Down Full Power-Down Serial Clock Serial Data Input/Output Chip Select Ground Channel Analog Input Channel Analog Output Complement Channel Analog Output Channel Ground Channel Analog Input Channel Analog Output Complement Channel Analog Output Channel Ground Channel Analog Input Channel Analog Output Complement Channel Analog Output Channel Ground Channel Analog Input Channel Analog Output Complement Channel Analog Output Channel Doppler Output Complement Channel Doppler Output True Channel Doppler Output Complement Channel Doppler Output True Channel Doppler Output Complement Channel Doppler Output True Channel Gain Control Voltage Input Complement
Rev. Page
AD9271
Name GAIN+ RBIAS SENSE VREF REFB REFT CWD3- CWD3+ CWD4- CWD4+ CWD5- CWD5+ LO-E LOSW-E Description Gain Control Voltage Input True External Resistor Internal Core Bias Current Reference Mode Selection Voltage Reference Input/Output Differential Reference (Negative) Differential Reference (Positive) Doppler Output Complement Channel Doppler Output True Channel Doppler Output Complement Channel Doppler Output True Channel Doppler Output Complement Channel Doppler Output True Channel Analog Output Channel Analog Output Complement Channel
Rev. Page
AD9271 EQUIVALENT CIRCUITS
AVDD
AVDD
LI-x, LG-x
06304-073
SDIO
Figure Equivalent Input Circuit
Figure Equivalent SDIO Input Circuit
DRVDD
AVDD
DOUTx-
LO-x, LOSW-x
DOUTx+
06304-075
DRGND
Figure Equivalent Output Circuit
Figure Equivalent Digital Output Circuit
CLK+
1.25V CLK-
SCLK PDWN STBY
06304-007
06304-009
06304-008
Figure Equivalent Clock Input Circuit
Figure Equivalent SCLK Input Circuit
Rev. Page
06304-010
AD9271
AVDD
RBIAS
AVDD
VREF
06304-011
Figure Equivalent RBIAS Circuit
Figure Equivalent VREF Circuit
AVDD
GAIN+
06304-014
06304-012
Figure Equivalent Input Circuit
Figure Equivalent GAIN+ Input Circuit
SENSE
GAIN-
+0.5V
06304-013
Figure Equivalent SENSE Circuit
Figure Equivalent GAIN- Input Circuit
CWDx+, CWDx-
Figure Equivalent CWDx± Output Circuit
Rev. Page
06304-076
06304-112
06304-074
AD9271 TYPICAL PERFORMANCE CHARACTERISTICS
fSAMPLE MSPS, MHz, fSAMPLE, kHz, gain
SAMPLE SIZE CHANNELS
ABSOLUTE ERROR (dB) PERCENT UNITS
06304-019
+85°C -0.5 -1.0 -1.5 -2.0 +25°C -40°C
06304-121
VGAIN
-1.0 -0.8 -0.6 -0.4 -0.2 GAIN ERROR (dB)
Figure Gain Error VGAIN Three Temperatures
Figure Gain Error Histogram with VGAIN
SAMPLE SIZE CHANNELS
PERCENT UNITS
PERCENT UNITS
06304-120
06304-118
-1.25 -1.00 -0.75 -0.50 -0.25 0.25 0.50 0.75 1.00 1.25
-1.0 -0.8
-0.6 -0.4 -0.2
GAIN ERROR (dB)
CHANNEL-TO-CHANNEL GAIN MATCHING (dB)
Figure Gain Error Histogram with VGAIN
Figure Gain Match Histogram VGAIN
SAMPLE SIZE CHANNELS PERCENT UNITS
PERCENT UNITS
06304-116
-1.25 -1.00 -0.75 -0.50 -0.25 0.25 0.50 0.75 1.00 1.25
-1.0
-0.9
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
GAIN ERROR (dB)
CHANNEL-TO-CHANNEL GAIN MATCHING (dB)
Figure Gain Error Histogram with VGAIN
Figure Gain Match Histogram VGAIN
Rev. Page
06304-117
AD9271
2000000 OUTPUT-REFERRED NOISE (dBFS/ 1800000 1600000
-131 -132 GAIN -133 -134 -135 GAIN -136 -137 -138 -139 -140 GAIN
06304-021
NUMBER HITS
1400000 1200000 1000000 800000 600000 400000 200000 CODES
06304-022
VGAIN
Figure Output-Referred Noise Histogram with VGAIN
Figure Short-Circuit, Output-Referred Noise VGAIN
1200000
64.0 63.5 (dBFS)
1000000
63.0
NUMBER HITS
800000 SNR/SINAD
62.5 62.0 61.5 61.0 60.5
SINAD (dBFS)
600000
400000
200000
06304-023
60.0 59.5
CODES
VGAIN
Figure Output-Referred Noise Histogram with VGAIN
Figure SNR/SINAD VGAIN, -6.5 dBFS
INPUT-REFERRED NOISE (nV/
1.70
INPUT-REFERRED NOISE (nV/
1.65
GAIN
06304-025
1.60
1.55
GAIN GAIN
1.50
1.45
06304-024
1.40
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure Short-Circuit, Input-Referred Noise Frequency
Figure Short-Circuit, Input-Referred Noise Temperature
Rev. Page
06304-020
AD9271
THIRD HARMONIC (dBFS)
FUNDAMENTAL (dBFS)
-3dB LINE
(1/3) 50MSPS
VGAIN VGAIN 0.5V VGAIN 0.2V
(1/3) 40MSPS (1/3) 25MSPS
06304-030
10.0
12.5
15.0
17.5
20.0
22.5
25.0
FREQUENCY (MHz)
(MHz)
Figure Antialiasing Filter (AAF) Pass-Band Response, Applied
Figure Third-Order Harmonic Distortion Frequency, -0.5 dBFS
VGAIN 0.5V
SECOND HARMONIC (dBFS)
VGAIN 1.0V
GROUP DELAY (ns)
GAIN VGAIN
VGAIN
06304-033
VGAIN 0.5V -110
ANALOG INPUT FREQUENCY (MHz)
OUTPUT LEVEL (dBFS)
Figure Antialiasing Filter (AAF) Group Delay Response
Figure Second-Order Harmonic Distortion Output Level
THIRD HARMONIC (dBFS) GAIN VGAIN
SECOND HARMONIC (dBFS)
VGAIN 0.2V VGAIN
VGAIN 0.5V
06304-028
VGAIN 0.5V -110
(MHz)
OUTPUT LEVEL (dBFS)
Figure Second-Order Harmonic Distortion Frequency, -0.5 dBFS
Figure Third-Order Harmonic Distortion Output Level
Rev. Page
06304-115
-100
06304-114
-100
06304-029
AD9271
AMPLITUDE (dBFS) AIN1 AIN2 -7dBFS
AIN1 AIN2 -7dBFS 5MHz 6MHz IMD2 -70.59dBc IMD3 -64.45dBc VGAIN
IMD3 (dBFS)
-100 -110 5MHz 6MHz VGAIN 2.3MHz 3.5MHz
06304-106
8MHz 10.3MHz
-100
06304-108
-120
FREQUENCY (MHz)
Figure IMD3 VGAIN
Figure Typical IMD3 IMD2 Performance
5MHz 6MHz
IMD3 (dBFS)
-100 -110 VGAIN VGAIN 0.5V VGAIN
06304-107
INPUT AMPLITUDE (dBFS)
Figure IMD3 Amplitude
Rev. Page
AD9271 THEORY OPERATION
ULTRASOUND
primary application AD9271 medical ultrasound. Figure shows simplified block diagram ultrasound system. critical function ultrasound system time gain control (TGC) compensation physiological signal attenuation. Because attenuation ultrasound signals exponential with respect distance (time), linear-in-dB optimal solution. requirements ultrasound signal chain very noise, active input termination, fast overload recovery, power, differential drive ADC. Because ultrasound machines beam-forming techniques requiring large binaryweighted numbers (for example, 512) channels, lowest power lowest possible noise importance. Most modern machines digital beam forming. this technique, signal converted digital format immediately following amplifier, then beam forming accomplished digitally. resolution bits with MSPS sampling satisfies requirements both general-purpose highend systems. Power consumption cost primary importance low-end portable ultrasound machines, AD9271 designed these criteria. additional information regarding ultrasound systems, refer "How Ultrasound System Considerations Influence Front-End Component Choice," Analog Dialogue, Volume Number May-July 2002, "The AD9271-A Revolutionary Solution Portable Ultrasound," Analog Dialogue, Volume Number July 2007.
AMPs
BEAM FORMER
BEAM FORMER CENTRAL CONTROL
MULTICHANNELS
MUX/ DEMUX
SWITCHES
BEAM FORMER MODES)
AD9271
TRANSDUCER ARRAY 128, 256, ETC., ELEMENTS BIDIRECTIONAL CABLE
(ANALOG) BEAM FORMER
SPECTRAL DOPPLER PROCESSING MODE
IMAGE MOTION PROCESSING MODE)
COLOR DOPPLER (PW) PROCESSING MODE)
Figure Simplified Ultrasound System Block Diagram
Rev. Page
06304-077
AUDIO OUTPUT
DISPLAY
AD9271
RFB1 RFB2 SWITCH LO-x
LOSW-x
SWITCH ARRAY
CDWx+ CDWx-
LI-x LG-x ATTENUATOR -30dB +24dB
TRANSDUCER
12-BIT PIPELINE
SERIAL LVDS
DOUTx- DOUTx+
GAIN INTERPOLATOR
AD9271
GAIN+
GAIN-
Figure Simplified Block Diagram Single Channel
CHANNEL OVERVIEW
Each channel contains both signal path Doppler signal path. Common both signal paths, provides useradjustable input impedance termination. Doppler path includes transconductance amplifier crosspoint switch. path includes differential X-AMP® VGA, antialiasing filter, ADC. Figure shows simplified block diagram with external components. signal path fully differential throughout maximize signal swing reduce even-order distortion; however, designed driven from single-ended signal source.
supports differential output voltages high with positive negative excursions ±0.5 from commonmode voltage differential gain sets maximum input signal before saturation. three gains through SPI. corresponding input full scale gain settings p-p, p-p, p-p, respectively. Overload protection ensures quick recovery time from large input voltages. Because inputs capacitively coupled bias voltage near midsupply, very large inputs handled without interacting with protection. value feedback resistors current-driving capability output stage allow achieve input-referred noise voltage nV/Hz. This achieved with current consumption only channel mW). On-chip resistor matching results precise single-ended gains, which critical accurate impedance control. fully differential topology negative feedback minimizes distortion. particularly important second-harmonic ultrasound imaging applications. Differential signaling enables smaller swings each output, further reducing third-order distortion.
Noise Amplifier (LNA)
Good noise performance relies proprietary ultralow noise beginning signal chain, which minimizes noise contribution following VGA. Active impedance control optimizes noise performance applications that benefit from input impedance matching. simplified schematic shown Figure LI-x capacitively coupled source. on-chip bias generator establishes input bias voltages around centers output common-mode levels (VDD/2). capacitor, CLG, same value input coupling capacitor, connected from LG-x ground.
AVDD2 SWITCH
TRANSDUCER
Active Impedance Matching
consists single-ended voltage gain amplifier with differential outputs negative output externally available. example, with fixed gain (15.6 dB), active input termination synthesized connecting feedback resistor between negative output pin, LO-x, positive input pin, LI-x. This technique well known results input resistance shown Equation
RFB1 RFB2 LOSW-x LO-x
LI-x
LG-x
06304-101
06304-071
where single-ended gain gain from LI-x inputs LO-x outputs.
Figure Simplified Schematic
Rev. Page
AD9271
Because amplifier gain from input differential output, important note that gain gain from LI-x LO-x, less than gain amplifier, input resistance reduced internal bias resistor parallel with source resistance connected LI-x, with LG-x grounded. Equation used calculate needed desired RIN, even higher values RIN.
Table Active Termination External Component Values
Gain 1000 Minimum (pF) (MHz)
example, value simplified equation (Equation used calculate RIN, value resulting gain error less than Some factors, such presence dynamic source resistance, might influence absolute gain accuracy more significantly. higher frequencies, input capacitance needs considered. user must determine level matching accuracy adjust accordingly. bandwidth (BW) about MHz. Ultimately limits accuracy synthesized RIN. about best match between MHz, where lower frequency limit determined size ac-coupling capacitors, upper limit determined Furthermore, input capacitance limit higher frequencies. Figure shows frequency various values RFB.
500,
Noise
short-circuit noise voltage (input-referred noise) important limit system performance. short-circuit noise voltage nV/Hz nV/Hz 15.6 gain), including noise. These measurements, which were taken without feedback resistor, provide basis calculating input noise noise figure (NF) performance configurations shown Figure Figure Figure simulations noise figure results using these configurations input-referred noise voltage nV/Hz VGA. Unterminated (RFB operation exhibits lowest equivalent input noise noise figure. Figure shows noise figure source resistance rising RS-where voltage noise large compared with source noise-and high noise contribution from RFB. lowest achieved when matches RIN.
UNTERMINATED VOUT
INPUT IMPEDANCE
200, 100, 400, 20pF 200, 70pF
RESISTIVE TERMINATION
06304-105
VOUT
100k
FREQUENCY (Hz)
Figure Frequency Various Values (Effects Also Shown)
ACTIVE IMPEDANCE MATCH
06304-104
Note that lowest value, Figure peaks frequencies greater than MHz. This roll-off LNA, mentioned previously. However, seen larger values, parasitic capacitance starts rolling signal before produce peaking. further degrades match; therefore, should used values that greater than Table lists recommended values terms RIN. needed series with because levels LO-x LI-x unequal.
Rev. Page
VOUT
Figure Input Configurations
AD9271
UNTERMINATED NOISE FIGURE (dB) RESISTIVE TERMINATION
06304-103
INPUT OVERDRIVE
Excellent overload behavior primary importance ultrasound. Both have built-in overdrive protection quickly recover after overload event.
ACTIVE TERMINATION
Input Overload Protection
with amplifier, voltage clamping prior inputs highly recommended application subject high transient voltages. block diagram simplified ultrasound transducer interface shown Figure common transducer element serves dual functions transmitting receiving ultrasound energy. During transmitting phase, high voltage pulses applied ceramic elements. typical transmit/receive (T/R) switch consist four high voltage diodes bridge configuration. Although diodes ideally block transmit pulses from sensitive receiver input, diode characteristics ideal, resulting leakage transients imposed LI-x inputs problematic. Because ultrasound pulse system time-of-flight used determine depth, quick recovery from input overloads essential. Overload occur preamp VGA. Immediately following transmit pulse, typical gains low, subject overload from switch leakage. With increasing gain, become overloaded strong echoes that occur near field echoes acoustically dense materials, such bone. Figure illustrates external overload protection scheme. pair back-to-back Schottky diodes installed prior installing ac-coupling capacitors. Although BAS40 diodes shown, diode prone exhibiting some amount shot noise. Many types diodes available achieving desired noise performance. configuration shown Figure tends nV/Hz input-referred noise. Decreasing resistor increasing resistor improve noise contribution, depending application. With diodes shown Figure clamping levels ±0.5 less significantly enhance overload performance system.
DRIVER BAS40-04 10nF TRANSDUCER 10nF
06304-100
1000
Figure Noise Figure Resistive Termination, Active Termination Matched, Unterminated Inputs, VGain 15.6 Gain
NOISE FIGURE (dB)
UNTERMINATED
1000
Figure Noise Figure Various Fixed Values RIN, Active Termination Matched Inputs, VGain 15.6 Gain
primary purpose input impedance matching improve transient response system. With resistive termination, input noise increases thermal noise matching resistor increased contribution LNA's input voltage noise generator. With active impedance matching, however, contributions both smaller factor 1/(1 Gain)) than they would resistive termination. Figure shows relative noise figure performance. this graph, input impedance swept with preserve match each point. noise figures source impedance resistive termination, active termination, unterminated configurations, respectively. noise figures respectively. Figure shows noise figure relates various values RIN, which helpful design purposes.
06304-102
AD9271
Figure Input Overload Protection
Rev. Page
AD9271
DOPPLER OPERATION
Modern ultrasound machines used medical applications employ binary array receivers beam forming, with typical array sizes receiver channels phase-shifted summed together extract coherent information. When used multiples, desired signals from each channel summed yield larger signal (increased factor where number channels), noise increased square root number channels. This technique enhances signal-to-noise performance machine. critical elements beam-former design means align incoming signals time domain means individual signals into composite whole. Beam forming, applied medical ultrasound, defined phase alignment summation signals that generated from common source received different times multielement ultrasound transducer. Beam forming functions: imparts directivity transducer, enhancing gain, defines focal point within body from which location returning echo derived. AD9271 includes front-end components needed implement analog beam forming Doppler operation. These components allow channels with similar phases coherently combined before phase alignment down mixing, thus reducing number delay lines adjustable phase shifters/ down mixers (AD8333 AD8339) required. Next, delay lines used, phase alignment performed then channels coherently summed down converted dynamic range demodulator. Alternatively, phase shifters/down mixers, such AD8333 AD8339, used, phase alignment downconversion done before coherently summing channels into signals. either case, resultant signals filtered sampled high resolution ADCs, sampled signals processed extract relevant Doppler information.
AD9271
SWITCH ARRAY
CHANNEL
AD8333
600nH 2.5V 600nH
600nH 2.5V 600nH
AD9271
2.5V
AD8333
600nH 600nH
SWITCH ARRAY
600nH 2.5V 600nH 16-BIT
06304-096
CHANNEL
16-BIT
Figure Typical Doppler System Using AD9271 AD8333 AD8339
Rev. Page
AD9271
Crosspoint Switch
Each followed transconductance conversion. Currents routed pairs differential outputs single-ended outputs summing. Each output sinks current, signal full-scale current each channel selected crosspoint switch. example, four channels were summed output, output would sink have full-scale current output maximum number channels combined must considered when setting load impedance conversion ensure that full-scale swing common-mode voltage within operating limits AD9271. When interfacing AD8339, commonmode voltage full-scale swing desired. This accomplished connecting inductor between each output supply, then connecting either single-ended differential load resistance CWD± outputs. value resistance should calculated based maximum number channels that combined. CWD± outputs required under full-scale swing greater than less than CWVDD (3.3 supply). system gain distributed listed Table
Table Channel Gain Distribution
Section Attenuator Filter Total Nominal Gain (dB) 14/15.6/18 38.4/10 40/12.4 42.4
linear-in-dB gain (law conformance) range path extending from slope gain control interface 31.6 dB/V, gain control range specified Equation Equation expression channel gain.
VGAIN (GAIN (GAIN
Gain (dB) 31.6
VGAIN ICPT
where ICPT intercept point gain. default condition, gain 15.6 gain voltage GAIN± pins This gives rise total gain ICPT) through path input unmatched, matched (RFB voltage GAIN± pins however, gain This gives rise total gain through path input unmatched, input matched. Each output dc-coupled input. consists attenuator with range followed amplifier with gain gain range X-AMP gain-interpolation technique results gain error uniform bandwidth, differential signal paths minimize distortion. gains, should limit system noise performance (SNR); high gains, noise defined source LNA. maximum voltage swing bound full-scale peak-to-peak input voltage p-p). Both have limitations within each section path, depending voltage applied GAIN+ GAIN- pins. three limitations, full-scale settings, depending gain selection applied through interface. When voltage less applied GAIN± pins, operates near full-scale input range maximize dynamic range without clipping signal. When more than applied GAIN± pins, input signal must lowered keep within full-scale range (see Figure 49).
OPERATION
signal path fully differential throughout maximize signal swing reduce even-order distortion; however, LNAs designed driven from single-ended signal source. Gain values referenced from single-ended input differential input. simple exercise understanding maximum minimum gain requirements shown Figure
MINIMUM GAIN (0.333V 87dB >8dB MARGIN NOISE FLOOR (224µV rms) MAXIMUM GAIN
06304-097
p-p) ~5dB MARGIN 70dB
INPUT-REFERRED NOISE FLOOR (5.4µV rms) 15MHz NOISE 1.4nV/
GAIN RANGE 30dB CHANNEL GAIN 40dB
Figure Gain Requirements 12-Bit, MSPS
summary, maximum gain required determined (ADC Noise Floor/VGA Input Noise Floor) Margin log(224/5.4) 40.3 minimum gain required determined (ADC Input FS/VGA Input Margin log(2/0.333) 10.6 Therefore, 12-bit, MSPS with bandwidth should suffice achieving dynamic range required most today's ultrasound systems.
Rev. Page
AD9271
0.450 GAIN 0.400
INPUT FULL-SCALE p-p)
slope monotonic with respect control voltage stable with variations process, temperature, supply. X-AMP inputs part gain feedback amplifier that completes VGA. bandwidth about MHz. input stage designed reduce feedthrough output ensure excellent frequency response uniformity across gain setting.
0.350 0.300 0.250 0.200 0.150 0.100 0.050
06304-110
GAIN
GAIN
Gain Control
gain control interface, GAIN±, differential input. gain, VGAIN, shown Equation VGAIN varies gain VGAs through interpolator selecting appropriate input stages connected input attenuator. nominal VGAIN range dB/V with best gain linearity from about where error typically less than ±0.5 VGAIN voltages greater than less than error increases. value VGAIN exceed supply voltage without gain foldover. Gain control response time less than settle within final value change from minimum maximum gain. There ways which GAIN+ GAIN- pins interfaced. Using single-ended method, Kelvin type connection ground used shown Figure driving multiple devices, preferable differential method, shown Figure either method, GAIN+ GAIN- pins should dc-coupled driven accommodate full-scale input.
AD9271
GAIN+ 0.01µF
06304-078
VGAIN
Figure LNA/VGA Full-Scale Limitations
Variable Gain Amplifier
differential X-AMP provides precise input attenuation interpolation. input-referred noise nV/Hz excellent gain linearity. simplified block diagram shown Figure
GAIN GAIN INTERPOLATOR POSTAMP
KELVIN CONNECTION
06304-109
POSTAMP
GAIN- 0.01µF
Figure Simplified Schematic
Figure Single-Ended GAIN± Pins Configuration
AVDD 0.5V
06304-098
input 12-stage differential resistor ladder with 3.01 tap. resulting total gain range which allows range loss endpoints. effective input resistance side nominally total differential resistance ladder driven fully differential input signal from LNA. outputs dc-coupled avoid external decoupling capacitors. common-mode voltage attenuator controlled amplifier that uses same midsupply voltage derived LNA, permitting coupling without introducing large offsets commonmode differences. However, offset from will amplified gain increased, producing exponentially increasing output offset. input stages X-AMP distributed along ladder, biasing interpolator, controlled gain interface, determines input point. With overlapping bias currents, signals from successive taps merge provide smooth attenuation range from This circuit technique results linear-in-dB gain conformance distortion levels-only deviating ±0.5 less from ideal. gain
AD9271
GAIN+
0.01µF
±0.25DC 0.5V
±0.5V
AD8138
±0.25DC 0.5V
GAIN-
0.01µF
Figure Differential GAIN± Pins Configuration
Noise
typical application, compresses wide dynamic range input signal within input span ADC. input-referred noise limits minimum resolvable input signal, whereas output-referred noise, which depends primarily VGA, limits maximum instantaneous dynamic range that processed particular gain control voltage. This latter limit accordance with total noise floor ADC. Output-referred noise function VGAIN shown Figure Figure short-circuit input conditions. input
Rev. Page
AD9271
noise voltage simply equal output noise divided measured gain each point control range. output-referred noise flat nV/Hz over most gain range, because dominated fixed output-referred noise VGA. high gain control range, noise source prevail. input-referred noise reaches minimum value near maximum gain control voltage, where input-referred contribution miniscule. lower gains, input-referred noise and, therefore, noise figure increases gain decreases. instantaneous dynamic range system lost, however, because input capacity increases input-referred noise increases. contribution noise floor same dependence. important relationship magnitude output noise floor relative that ADC. Gain control noise concern very noise applications. Thermal noise gain control interface modulate channel gain. resultant noise proportional output signal level usually evident only when large signal present. gain interface includes on-chip noise filter, which significantly reduces this effect frequencies above MHz. Care should taken minimize noise impinging GAIN± input. external filter used remove VGAIN source noise. filter bandwidth should sufficient accommodate desired control bandwidth. filter configured coupling have single pole high-pass filtering either (programmed through SPI). high-pass pole, however, tuned vary ±30%. third-order Butterworth low-pass filter used reduce noise bandwidth provide antialiasing ADC. filter uses on-chip tuning trim capacitors turn desired cutoff frequency reduce variations. default cutoff sample clock rate. cutoff scaled 0.7, 0.8, 0.9, 1.1, 1.2, times this frequency through SPI. cutoff from MHz. Tuning normally avoid changing capacitor settings during critical times. tuning circuit enabled disabled through SPI. Initializing tuning filter must done after initial power-up after reprogramming filter cutoff scaling sample rate. Occasional retuning during idle time recommended compensate temperature drift.
AD9271 architecture consists pipelined divided into three sections: 4-bit first stage followed eight 1.5-bit stages 3-bit flash. Each stage provides sufficient overlap correct flash errors preceding stages. quantized outputs from each stage combined into 12-bit result digital correction logic. pipelined architecture permits first stage operate input sample remaining stages operate preceding samples. Sampling occurs rising edge clock. Each stage pipeline except last consists resolution flash connected switched-capacitor interstage residue amplifier (for example, multiplying digital-to-analog converter (MDAC)). residue amplifier magnifies difference between reconstructed output flash input next stage pipeline. redundancy used each stage facilitate digital correction flash errors. last stage consists flash ADC. output staging block aligns data, carries error correction, passes data output buffers. data then serialized aligned frame output clock.
Antialiasing Filter
filter that signal reaches prior used reject signals band limit signal antialiasing. Figure shows architecture filter.
56pF/112pF
7.5C* 56pF/112pF
6.5C*
0.5pF 3.1pF
Figure Simplified Filter Schematic
Rev. Page
06304-099
AD9271
CLOCK INPUT CONSIDERATIONS
optimum performance, AD9271 sample clock inputs (CLK+ CLK-) should clocked with differential signal. This signal typically ac-coupled into CLK+ CLK- pins transformer capacitors. These pins biased internally require additional bias. Figure shows preferred method clocking AD9271. jitter clock source, such Valpey Fisher oscillator VFAC3-BHL-50MHz, converted from single-ended differential using transformer. back-to-back Schottky diodes across secondary transformer limit clock excursions into AD9271 approximately differential. This helps prevent large voltage swings clock from feeding through other portions AD9271, preserves fast rise fall times signal, which critical jitter performance.
3.3V MINI-CIRCUITS ADT1-1WT, 1:1Z 0.1µF XFMR 0.1µF 0.1µF SCHOTTKY DIODES: HSM2812
3.3V
some applications, acceptable drive sample clock inputs with single-ended CMOS signal. such applications, CLK+ should driven directly from CMOS gate, CLK- should bypassed ground with capacitor parallel with resistor (see Figure 57). Although CLK+ input circuit supply AVDD (1.8 this input designed withstand input voltages making selection drive logic voltage very flexible.
3.3V VFAC3
0.1µF
AD951x FAMILY
OPTIONAL 0.1µF
CMOS DRIVER
0.1µF
CLK+
AD9271
CLK-
06304-053
0.1µF
RESISTOR OPTIONAL.
Figure Single-Ended CMOS Sample Clock
AD951x FAMILY
OPTIONAL 0.1µF
0.1µF VFAC3
CLK+
0.1µF
06304-050
AD9271
CLK-
CMOS DRIVER
CLK+
VFAC3 0.1µF
0.1µF
AD9271
06304-054
Figure Transformer-Coupled Differential Clock
CLK-
RESISTOR OPTIONAL.
jitter clock available, another option ac-couple differential PECL signal sample clock input pins shown Figure AD951x family clock drivers offers excellent jitter performance.
3.3V VFAC3
Figure Single-Ended CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs both clock edges generate variety internal timing signals. result, these ADCs sensitive clock duty cycle. Commonly, tolerance required clock duty cycle maintain dynamic performance characteristics. AD9271 contains duty cycle stabilizer (DCS) that retimes nonsampling edge, providing internal clock signal with nominal duty cycle. This allows wide range clock input duty cycles without affecting performance AD9271. When noise distortion performance nearly flat wide range duty cycles. However, some applications require function off. keep mind that dynamic range performance affected when operated this mode. Memory section more details using this feature. duty cycle stabilizer uses delay-locked loop (DLL) create nonsampling edge. result, changes sampling frequency require approximately eight clock cycles allow acquire lock rate.
AD951x FAMILY
0.1µF PECL DRIVER
06304-051
0.1µF CLK+ 0.1µF
0.1µF
AD9271
CLK-
RESISTOR OPTIONAL.
Figure Differential PECL Sample Clock
3.3V VFAC3 0.1µF LVDS DRIVER 0.1µF
AD951x FAMILY
0.1µF CLK+
0.1µF
AD9271
CLK-
06304-052
RESISTOR OPTIONAL.
Figure Differential LVDS Sample Clock
Clock Jitter Considerations
High speed, high resolution ADCs sensitive quality clock input. degradation given input frequency (fA) only aperture jitter (tJ) calculated Degradation 10[1/2
Rev. Page
AD9271
this equation, aperture jitter represents root mean square jitter sources, including clock input, analog input signal, aperture jitter. undersampling applications particularly sensitive jitter (see Figure 59). clock input should treated analog signal cases where aperture jitter affect dynamic range AD9271. Power supplies clock drivers should separated from output driver supplies avoid modulating clock signal with digital noise. jitter, crystal-controlled oscillators make best clock sources, such Valpey Fisher VFAC3 series. clock generated from another type source gating, dividing, other methods), should retimed original clock during last step. Refer AN-501 Application Note AN-756 Application Note more in-depth information about jitter performance relates ADCs (visit www.analog.com).
CLOCK JITTER REQUIREMENT BITS BITS BITS BITS ANALOG INPUT FREQUENCY (MHz) 1000 BITS 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps
06304-038
POWER/CHANNEL (mW)
50MSPS SPEED GRADE 40MSPS SPEED GRADE 25MSPS SPEED GRADE SAMPLING FREQUENCY (MSPS)
06304-031
Figure Power Channel fSAMPLE
asserting PDWN high, AD9271 placed into power-down mode. this state, device typically dissipates During power-down, LVDS output drivers placed into high impedance state. AD9271 returns normal operating mode when PDWN pulled low. This both tolerant. asserting STBY high, AD9271 placed into standby mode. this state, device typically dissipates During standby, entire part powered down except internal references. LVDS output drivers placed into high impedance state. This mode well suited applications that require power savings because allows device powered down when then quickly powered time power device back also greatly reduced. AD9271 returns normal operating mode when STBY pulled low. This both tolerant. power-down mode, power dissipation achieved shutting down reference, reference buffer, PLL, biasing networks. decoupling capacitors REFT REFB discharged when entering power-down mode must recharged when returning normal operation. result, wake-up time related time spent power-down mode: shorter cycles result proportionally shorter wake-up times. restore device full operation, approximately required when using recommended decoupling capacitors REFT REFB pins 0.01 decoupling capacitors GAIN± pins. Most this time dependent gain decoupling; higher value decoupling capacitors GAIN± pins result longer wake-up times. There number other power-down options available when using port interface. user individually power down each channel entire device into standby mode. This allows user keep internal powered when fast wake-up times required. wake-up time slightly dependent gain. achieve wake-up time when device standby mode, must applied GAIN± pins. Memory section more details using these features.
Rev. Page
(dB)
Figure Ideal Input Frequency Jitter
Power Dissipation Power-Down Mode
shown Figure power dissipated AD9271 proportional sample rate. digital power dissipation does vary much because determined primarily DRVDD supply bias current LVDS output drivers (Figure 60).
CURRENT (mA)
IAVDD 50MSPS SPEED GRADE IAVDD 40MSPS SPEED GRADE
IAVDD 25MSPS SPEED GRADE
06304-032
IDRVDD
SAMPLING FREQUENCY (MSPS)
Figure Supply Current fSAMPLE
AD9271
Digital Outputs Timing
AD9271 differential outputs conform ANSI-644 LVDS standard default power-up. This changed power, reduced signal option similar IEEE 1596.3 standard using SDIO SPI. This LVDS standard further reduce overall power dissipation device approximately SDIO section Table more information. LVDS driver current derived chip sets output current each output equal nominal differential termination resistor placed LVDS receiver inputs results nominal swing receiver. AD9271 LVDS outputs facilitate interfacing with LVDS receivers custom ASICs FPGAs that have LVDS capability superior switching performance noisy environments. Single point-to-point topologies recommended with termination resistor placed close receiver possible. far-end receiver termination poor differential trace routing result timing errors. recommended that trace length longer than inches that differential output traces kept close together equal lengths. example FCO, DCO, data stream with proper trace length position found Figure Additional options allow user further increase internal termination (and therefore increase current) eight outputs order drive longer trace lengths (see Figure 65). Even though this produces sharper rise fall times data edges, less prone errors, improves frequency distribution (see Figure 65), power dissipation DRVDD supply increases when this option used. cases that require increased driver strength DCO± FCO± outputs because load mismatch, Register 0x15 allows user double drive strength. this, first appropriate Register 0x05. Note that this feature cannot used with Register 0x15 because these bits take precedence over this feature. Memory section more details.
DIAGRAM VOLTAGE
EYE: BITS
ULS: 2398/2398
-100 -200 -400 -600
-1.5ns
-1.0ns
-0.5ns
0.5ns
1.0ns
1.5ns
JITTER HISTOGRAM (Hits)
06304-034
500mV/DIV 500mV/DIV 500mV/DIV
5.0ns/DIV
Figure LVDS Output Timing Example ANSI-644 Mode (Default)
06304-035
example LVDS output using ANSI-644 standard (default) data time interval error (TIE) jitter histogram with trace lengths less than inches regular FR-4 material shown Figure Figure shows example trace lengths exceeding inches regular FR-4 material. Notice that jitter histogram reflects decrease data opening edge deviates from ideal position; therefore, user must determine waveforms meet timing budget design when trace lengths exceed inches.
-200ps
-100ps
100ps
200ps
Figure Data LVDS Outputs ANSI-644 Mode with Trace Lengths Less Than Inches Standard FR-4
Rev. Page
AD9271
DIAGRAM VOLTAGE
EYE: BITS
ULS: 2399/2399
DIAGRAM VOLTAGE
EYE: BITS
ULS: 2396/2396
-100 -200 -300 -400
-200
-400
-1.5ns
-1.0ns
-0.5ns
0.5ns
1.0ns
1.5ns
-600
-1.5ns
-1.0ns
-0.5ns
0.5ns
1.0ns
1.5ns
JITTER HISTOGRAM (Hits)
JITTER HISTOGRAM (Hits)
06304-036
06304-037
-200ps
-100ps
100ps
200ps
-200ps
-100ps
100ps
200ps
Figure Data LVDS Outputs ANSI-644 Mode with Trace Lengths Greater Than Inches Standard FR-4
Figure Data LVDS Outputs ANSI-644 Mode with Termination Trace Lengths Greater Than Inches Standard FR-4
Rev. Page
AD9271
format output data offset binary default. example output coding format found Table change output data format twos complement, Memory section.
Table Digital Output Coding
Code 4095 2048 2047 (VIN+) (VIN-), Input Span +1.00 0.00 -0.000488 -1.00 Digital Output Offset Binary (D11 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000
times sample clock rate, with maximum Mbps bits MSPS Mbps). lowest typical conversion rate MSPS, encode rates MSPS lower sample rates required specific application. Memory section details enabling this feature. output clocks provided assist capturing data from AD9271. DCO± used clock output data equal times sampling clock rate. Data clocked AD9271 must captured rising falling edges DCO± that supports double data rate (DDR) capturing. frame clock output (FCO±) used signal start output byte equal sampling clock rate. timing diagram shown Figure more information.
Data from each serialized provided separate channel. data rate each serial stream equal bits
Table Flexible Output Test Modes
Output Test Mode Sequence 0000 0001 Pattern Name (default) Midscale short
0010
+Full-scale short
0011
-Full-scale short
0100
Checkerboard
0101 0110 0111
sequence long sequence short1 One-/zero-word toggle
1000 1001
User input 1-/0-bit toggle
1010
sync
1011
high
1100
Mixed frequency
Digital Output Word 1000 0000 bits) 0000 0000 bits) 1000 0000 0000 bits) 0000 0000 0000 bits) 1111 1111 bits) 1111 1111 bits) 1111 1111 1111 bits) 1111 1111 1111 bits) 0000 0000 bits) 0000 0000 bits) 0000 0000 0000 bits) 0000 0000 0000 bits) 1010 1010 bits) 1010 1010 bits) 1010 1010 1010 bits) 1010 1010 1010 bits) 1111 1111 bits) 1111 1111 bits) 1111 1111 1111 bits) 1111 1111 1111 bits) Register 0x19 Register 0x1A 1010 1010 bits) 1010 1010 bits) 1010 1010 1010 bits) 1010 1010 1010 bits) 0000 1111 bits) 0001 1111 bits) 0000 0011 1111 bits) 0000 0111 1111 bits) 1000 0000 bits) 0000 0000 bits) 1000 0000 0000 bits) 0000 0000 0000 bits) 1010 0011 bits) 0110 0011 bits) 1010 0011 0011 bits) 1000 0110 0111 bits)
Digital Output Word Same
Subject Data Format Select
Same
Same
0101 0101 bits) 0101 0101 bits) 0101 0101 0101 bits) 0101 0101 0101 bits) 0000 0000 bits) 0000 0000 bits) 0000 0000 0000 bits) 0000 0000 0000 bits) Register 0x1B Register 0x1C
test mode options except sequence short sequence long support 14-bit word lengths order verify data capture receiver.
Rev. Page
AD9271
When using serial port interface (SPI), DCO± phase adjusted increments relative data edge. This enables user refine system timing margins required. default DCO± timing, shown Figure relative output data edge. 10-, 14-bit serial stream also initiated from SPI. This allows user implement different serial streams test device's compatibility with lower higher resolution systems. When changing resolution 10-bit serial stream, data stream shortened. When using 14-bit option, data stream stuffs normal 14-bit serial data. When using SPI, data outputs also inverted from their nominal state. This confused with inverting serial stream LSB-first mode. default mode, shown Figure represented first data output serial stream. However, this inverted that represented first data output serial stream (see Figure There digital output test pattern options available that initiated through SPI. This feature useful when validating receiver capture timing. Refer Table output sequencing options available. Some test patterns have serial sequential words alternated various ways, depending test pattern chosen. should noted that some patterns adhere data format select option. addition, customer user patterns assigned 0x19, 0x1A, 0x1B, 0x1C register addresses. test mode options except sequence short sequence long support 14-bit word lengths order verify data capture receiver. sequence short pattern produces pseudorandom sequence that repeats itself every bits, bits. description sequence generated found Section ITU-T 0.150 (05/96) standard. only difference that starting value specific value instead (see Table initial values). sequence long pattern produces pseudorandom sequence that repeats itself every bits, 8,388,607 bits. description sequence generated found Section ITU-T 0.150 (05/96) standard. only differences that starting value specific value instead AD9271 inverts stream with relation standard (see Table initial values).
Table Sequence
Sequence Sequence Short Sequence Long Initial Value 0x0df 0x29b80a First Three Output Samples (MSB First) 0xdf9, 0x353, 0x301 0x591, 0xfd7, 0xa3
SDIO
This required operate SPI. internal pull-down resistor that pulls this only tolerant. applications require that this driven from logic level, insert resistor series with this limit current.
SCLK
This required operate port interface. internal pull-down resistor that pulls this both tolerant.
This required operate port interface. internal pull-down resistor that pulls this both tolerant.
RBIAS
internal core bias current ADC, place resistor that nominally equal 10.0 between RBIAS ground. Using resistor another value degrades performance device. Therefore, imperative that least tolerance this resistor used achieve consistent performance.
Voltage Reference
stable accurate voltage reference built into AD9271. This gained internally factor setting VREF which results full-scale differential input span ADC. VREF internally default, VREF driven externally with reference achieve more accuracy. However, full-scale ranges below supported this device. When applying decoupling capacitors VREF, REFT, REFB pins, ceramic capacitors. These capacitors should close reference pins same layer AD9271. recommended capacitor values configurations AD9271 reference found Figure
Table Reference Settings
Selected Mode External Reference Internal, SENSE Voltage AVDD AGND Resulting VREF Resulting Differential Span p-p) external reference
Consult Memory section information change these additional digital output timing features through SPI.
Rev. Page
AD9271
Internal Reference Operation
comparator within AD9271 detects potential SENSE configures reference. SENSE grounded, reference amplifier switch connected internal resistor divider (see Figure 66), setting VREF REFT REFB pins establish their input span core from reference configuration. analog input fullscale range equals twice voltage reference either internal external reference configuration.
VIN+ VIN- REFT CORE 0.1µF 0.1µF REFB VREF 0.1µF SELECT LOGIC SENSE 0.5V 0.1µF
VREF ERROR
External Reference Operation
external reference necessary enhance gain accuracy improve thermal drift characteristics. Figure shows typical drift characteristics internal reference mode. When SENSE tied AVDD, internal reference disabled, allowing external reference. external reference loaded with equivalent load. internal reference buffer generates positive negative full-scale references, REFT REFB, core. Therefore, external reference must limited nominal voltage
4.7µF
06304-064 06304-017
Figure Internal Reference Configuration
0.02
REFT CORE EXTERNAL REFERENCE VREF 1µF* 0.1µF* AVDD SENSE SELECT LOGIC 0.5V 0.1µF 0.1µF REFB 0.1µF
CURRENT LOAD (mA)
Figure VREF Accuracy Load, AD9271-50
VIN+ VIN-
-0.02 -0.04
4.7µF
VREF ERROR
-0.06 -0.08 -0.10 -0.12 -0.14 -0.16 -0.18 -0.20
06304-015
TEMPERATURE (°C)
06304-065
Figure Typical VREF Drift, AD9271-50
*OPTIONAL.
Figure External Reference Operation
Rev. Page
AD9271 SERIAL PORT INTERFACE (SPI)
AD9271 serial port interface allows user configure signal chain specific functions operations through structured register space provided inside chip. This offers user added flexibility customization depending application. Addresses accessed serial port written read from port. Memory organized into bytes that further divided into fields, documented Memory section. Detailed operational information found Analog Devices, Inc., AN-877 Application Note, Interfacing High Speed ADCs SPI. Three pins define serial port interface, SPI: SCLK, SDIO, pins. SCLK (serial clock) used synchronize read write data presented device. SDIO (serial data input/output) dual-purpose that allows data sent read from device's internal memory registers. (chip select bar) active control that enables disables read write cycles (see Table 13).
Table Serial Port Pins
SCLK SDIO Function Serial Clock. serial shift clock input. SCLK used synchronize serial interface reads writes. Serial Data Input/Output. dual-purpose pin. typical role this input output, depending instruction sent relative position timing frame. Chip Select (Active Low). This control gates read write cycles.
addition operation modes, port configured operate different manners. example, tied enable 2-wire mode. When tied low, SCLK SDIO only pins required communication. Although device synchronized during power-up, caution must exercised when using this mode ensure that serial port remains synchronized with line. When operating 2-wire mode, recommended that 3-byte transfer used exclusively. Without active line, streaming mode entered exited. addition word length, instruction phase determines serial frame read write operation, allowing serial port used both program chip read contents on-chip memory. instruction readback operation, performing readback causes serial data input/output (SDIO) change direction from input output appropriate point serial frame. Data sent MSB- LSB-first mode. MSB-first mode default power-up changed adjusting configuration register. more information about this other features, AN-877 Application Note, Interfacing High Speed ADCs SPI.
HARDWARE INTERFACE
pins described Table constitute physical interface between user's programming device serial port AD9271. SCLK pins function inputs when using interface. SDIO bidirectional, functioning input during write phases output during readback. cases where multiple SDIO pins share common connection, care should taken ensure that proper levels met. Figure shows number SDIO pins that connected together, assuming same load AD9271 resulting level.
1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 NUMBER SDIO PINS CONNECTED TOGETHER
falling edge conjunction with rising edge SCLK determines start framing sequence. During instruction phase, 16-bit instruction transmitted, followed more data bytes, which determined Field Field example serial timing definitions found Figure Table normal operation, used signal device that commands received processed. When brought low, device processes SCLK SDIO process instructions. Normally, remains until communication cycle complete. However, connected slow device, brought high between bytes, allowing older microcontrollers enough time transfer data into shift registers. stalled when transferring one, two, three bytes data. When device enters streaming mode continues process data, either reading writing, until taken high communication cycle. This allows complete memory transfers without having provide additional instructtions. Regardless mode, taken high middle byte transfer, state machine reset device waits instruction.
Figure SDIO Loading
Rev. Page
06304-113
AD9271
This interface flexible enough controlled either serial PROMs mirocontrollers. This provides user alternative method, other than full controller, program device (see AN-812 Application Note).
tCLK
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
DON'T CARE
Figure Serial Timing Details
Table Serial Timing Definitions
Parameter tCLK tEN_SDIO tDIS_SDIO Minimum Timing (ns) Description Setup time between data rising edge SCLK Hold time between data rising edge SCLK Period clock Setup time between SCLK Hold time between SCLK Minimum period that SCLK should logic high state Minimum period that SCLK should logic state Minimum time SDIO switch from input output relative SCLK falling edge (not shown Figure Minimum time SDIO switch from output input relative SCLK rising edge (not shown Figure
Rev. Page
06304-068
AD9271 MEMORY
READING MEMORY TABLE
Each memory table eight address locations. memory roughly divided into three sections: chip configuration register (Address 0x00 Address 0x02), device index transfer register (Address 0x04, Address 0x05, Address 0xFF), functions register (Address 0x08 Address 0x2D). leftmost column memory indicates register address number; default value shown second rightmost column. (MSB) column start default hexadecimal value given. example, Address 0x09, clock register, default value 0x01, meaning that 0000 0001 binary. This setting default duty cycle stabilizer condition. writing this address followed writing 0x01 Register 0xFF (transfer bit), duty cycle stabilizer turns off. important follow each writing sequence with transfer update registers. registers, except Register 0x00, Register 0x02, Register 0x04, Register 0x05, Register 0xFF, buffered with master-slave latch require writing transfer bit. more information this other functions, consult AN877 Application Note, Interfacing High Speed ADCs SPI.
RESERVED LOCATIONS
Undefined memory locations should written except when writing default values suggested this data sheet. Addresses that have values marked should considered reserved have written into their registers during power-up.
DEFAULT VALUES
After reset, critical registers automatically loaded with default values. These values indicated Table where refers undefined feature.
LOGIC LEVELS
explanation various registers follows: "Bit set" synonymous with "bit Logic "writing Logic bit." Similarly, "clear bit" synonymous with "bit Logic "writing Logic bit."
Rev. Page
AD9271
Table Memory Register
Addr. (Hex) Register Name (MSB) Chip Configuration Registers chip_port_config first (default) Soft reset (default) Soft reset (default) first (default) (LSB) Default Value 0x18 Notes/ Comments nibbles should mirrored that LSB- MSB-first mode correctly regardless shift mode. Default unique chip different each device. This readonly register. Child used differentiate graded devices.
chip_id
Chip Bits [7:0] (AD9271 0x13), (default)
Read only
chip_grade
Child [5:4] (identify device variants Chip MSPS (default) MSPS MSPS
0x00
Device Index Transfer Registers device_index_2
device_index_1
device_update
Clock Channel DCO± (default)
Clock Channel FCO± (default)
Data Channel (default) Data Channel (default)
Data Channel (default) Data Channel (default)
Data Channel (default) Data Channel (default)
Data Channel (default) Data Channel (default) transfer (default)
0x0F
Bits determine which on-chip device receives next write command. Bits determine which on-chip device receives next write command. Synchronously transfers data from master shift register slave. Determines various generic modes chip operation.
0x0F
0x00
Functions Registers modes
bypass (default)
clock
Internal power-down mode chip (default) full power-down standby reset mode (TGC PDWN) Duty cycle stabilizer (default)
0x00
0x01
Turns internal duty cycle stabilizer off.
Rev. Page
AD9271
Addr. (Hex) Register Name test_io (MSB) User test mode (default) single alternate single once alternate once Reset long (default) Reset short (default) (LSB) Output test mode-see Table 0000 (default) 0001 midscale short 0010 short 0011 short 0100 checkerboard output 0101 sequence long 0110 sequence short 0111 one-/zero-word toggle 1000 user input 1001 1-/0-bit toggle 1010 sync 1011 high 1100 mixed frequency (format determined output_mode) Default Value 0x00 Notes/ Comments When this register set, test data placed output pins place normal data. (Local, expect sequence.)
flex_channel_input
flex_offset
flex_gain
Filter cutoff frequency control 0000 fSAMPLE 0001 fSAMPLE 0010 fSAMPLE 0011 fSAMPLE 0100 fSAMPLE 0101 fSAMPLE 0110 fSAMPLE 6-bit offset adjustment 011001 MSPS speed grade 011010 MSPS speed grade 011111 MSPS speed grade
0x30
Antialiasing filter cutoff (global).
0x20
output_mode
output_adjust
LVDS ANSI-644 (default) LVDS power, (IEEE 1596.3 similar)
Output invert (default)
gain offset binary (default) twos complement
0x01
force offset correction (local). gain adjustment (global). Configures outputs format data.
0x00
Output driver termination none (default)
DCO± FCO± drive strength (default)
0x00
output_phase
0011 output clock phase adjust (0000 through 1010) (Default: 180° relative data edge) 0000 relative data edge 0001 relative data edge 0010 120° relative data edge 0011 180° relative data edge 0100 240° relative data edge 0101 300° relative data edge 0110 360° relative data edge 0111 420° relative data edge 1000 480° relative data edge 1001 540° relative data edge 1010 600° relative data edge 1011 1111 660° relative data edge
0x03
Determines LVDS other output prop erties. Primarily functions LVDS span commonmode levels place external resistor. devices that utilize global clock divide, determines which phase divider output used supply output clock. Internal latching unaffected.
Rev. Page
AD9271
Addr. (Hex) Register Name user_patt1_lsb (MSB) (LSB) Default Value 0x00 Notes/ Comments User-defined pattern, (global). User-defined pattern, (global). User-defined pattern, (global). User-defined pattern, (global). Serial stream control. Default causes first native stream (global).
user_patt1_msb
0x00
user_patt2_lsb
0x00
user_patt2_msb
0x00
serial_control
first (default)
serial_ch_stat
MSPS, encode rate mode (default)
bits (default, normal stream) bits bits bits bits
0x00
flex_filter
Enable automatic low-pass tuning (default)
Channel Channel poweroutput down reset (default) (default) High-pass filter cutoff (default)
0x00
Used power down individ sections converter (local). Filter cutoff (global).
0x00
analog_input
LOSW-x (default)
0x00
cross_point_switch
Crosspoint switch enable 0000 CWD0± (differential) 0001 CWD1± (differential) 0010 CWD2± (differential) 0011 CWD3± (differential) 0100 CWD4± (differential) 0101 CWD5± (differential) 0111 power down channel 0000 CWD0+ (single ended) 0001 CWD1+ (single ended) 0010 CWD2+ (single ended) 0011 CWD3+ (single ended) 0100 CWD4+ (single ended) 0101 CWD5+ (single ended) 0111 power down channel 1000 CWD0- (single ended) 1001 CWD1- (single ended) 1010 CWD2- (single ended) 1011 CWD3- (single ended) 1100 CWD4- (single ended) 1101 CWD5- (single ended) 1111 power down channel
0x07
active termination/ input impedance (global). Crosspoint switch enable (local).
undefined feature
Rev. Page
AD9271 APPLICATIONS INFORMATION
DESIGN GUIDELINES
Before starting design layout AD9271 system, recommended that designer become familiar with these guidelines, which discuss special circuit connections layout requirements needed certain pins.
Exposed Paddle Thermal Heat Slug Recommendations
required that exposed paddle underside device connected analog ground (AGND) achieve best electrical thermal performance AD9271. exposed continuous copper plane should mate AD9271 exposed paddle, copper plane should have several vias achieve lowest possible resistive thermal path heat dissipation flow through bottom PCB. These vias should filled plugged with nonconductive epoxy. maximize coverage adhesion between device PCB, partition continuous copper overlaying silkscreen solder mask divide into several uniform sections. This ensures several points between during reflow process. Using continuous plane with partitions guarantees only point between AD9271 PCB. Figure layout example. more detailed information packaging more layout examples, AN-772 Application Note.
SILKSCREEN PARTITION INDICATOR
Power Ground Recommendations
When connecting power AD9271, recommended that separate supplies used: analog (AVDD) digital (DRVDD). AD9271 also requires supply (CWVDD) crosspoint section. only supply available, should routed AVDD first then tapped isolated with ferrite bead filter choke preceded decoupling capacitors DRVDD. user should employ several decoupling capacitors supplies cover both high frequencies. These capacitors should located close point entry board level close parts with minimal trace lengths. single board ground plane should sufficient when using AD9271. With proper decoupling smart partitioning board's analog, digital, clock sections, optimum performance easily achieved.
Figure Typical Layout
Rev. Page
06304-069
AD9271 EVALUATION BOARD
AD9271 evaluation board provides support circuitry required operate AD9271 various modes configurations. driven differentially through transformer. Figure shows typical bench characterization setup used evaluate performance AD9271. critical that signal sources used analog input clock have very phase noise jitter) realize optimum performance signal chain. Proper filtering analog input signal remove harmonics lower integrated broadband noise input also necessary achieve specified noise performance. Quick Start Procedure section started Figure Figure complete schematics layout diagrams that demonstrate routing grounding techniques that should applied system level. alternate clock options, separate analog supply needed addition other supplies. supply, AVDD_3.3 should have current capability. bias crosspoint switch circuitry section, separate supplies required P511. These should each have current capability. This section cannot biased from wall supply. Separate supplies required P511.
INPUT SIGNALS
When connecting clock analog source, clean signal generators with phase noise, such Rohde Schwarz HP8644B signal generators equivalent. shielded, RG-58, coaxial cable making connections evaluation board. Enter desired frequency amplitude from specifications tables. evaluation board clocked from crystal oscillator, OSC401. different external clock source desired, follow instructions CLOCK outlined Default Operation Jumper Selection Settings section. Typically, most Analog Devices evaluation boards accept ~2.8 sine wave input clock. When connecting analog input source, recommended multipole, narrow-band, band-pass filter with terminations. Analog Devices uses Microwave, Inc., band-pass filters. filter should connected directly evaluation board.
POWER SUPPLIES
This evaluation board comes with wall-mountable switching power supply that provides maximum output. Connect supply rated wall outlet other inner diameter jack that connects P701. Once board, supply fused conditioned before connecting three dropout linear regulators that supply proper bias each various sections board. When operating evaluation board nondefault condition, L702 L704 removed disconnect switching power supply. This enables user bias each section board individually. P501 connect different supply each section. least supply needed with current capability AVDD_DUT DRVDD_DUT; however, recommended that separate supplies used both analog digital domains. operate evaluation board using
WALL OUTLET 100V 240V 47Hz 63Hz SWITCHING POWER SUPPLY
OUTPUT SIGNALS
default setup uses FIFO5 high speed, dual-channel FIFO data capture board (HSC-ADC-EVALCZ). eight channels then evaluated same time. more information channel settings these boards their optional settings, visit www.analog.com/FIFO.
1.8V
1.8V
3.3V
RUNNING ANALYZER VISUAL ANALOG USER SOFTWARE
FPGA
ANALOG INPUT ROHDE SCHWARZ, SMA, SIGNAL SYNTHESIZER ROHDE SCHWARZ, FS5A20 SPECTRUM ANALYZER
DRVDD_DUT
AVDD_3.3V
AVDD_DUT
BAND-PASS FILTER
AD9271
VFAC3 OSCILLATOR
12-BIT SERIAL LVDS
HSC-ADC-EVALCZ FIFO DATA CAPTURE BOARD
OUTPUT EVALUATION BOARD
Figure Evaluation Board Connection
Rev. Page
06304-070
CONNECTOR (DATA/SPI)
VREG
AD9271
DEFAULT OPERATION JUMPER SELECTION SETTINGS
following list default optional settings modes allowed AD9271 Rev. evaluation board.
PDWN: enable power-down feature, short P303 position (AVDD) PDWN pin. STBY: enable standby feature, short P302 position (AVDD) STBY pin. GAIN+, GAIN-: change attenuation, drive GAIN+ from J301. This changes gain from This feature also driven from R335 R336 on-board resistive divider installing resistor R337. Non-SPI Mode: users wish operate without using SPI, remove jumpers J501. This disconnects CSB, SCLK, SDIO pins from control bus, allowing operate simplest mode. Each these pins internal termination will float respective level. Note that device will only work default condition. CWD+, CWD-: view CWD2+/CWD2- CWD3+/ CWD3- outputs, jumper together appropriate outputs P403. outputs summed together buses, impedance ratio transformer, buffered that user view output spectrum analyzer. This configured viewed singleended mode (default) differential mode. voltage appropriate number channels summed, change value R447 R448 primary transformer (T402). Upon shipment, CWD0+/CWD0-, CWD1+/CWD1-, CWD4+/CWD4-, CWD5+/CWD5- outputs properly biased ready with AD8339 quad demodulator phase shifter. AD9271 evaluation board simply snaps into place AD8339 evaluation board (AD8339-EVALZ). Remove jumpers connected AD8339 evaluation board, snap standoffs labeled MH502, MH504, MH505 that provided with AD9271 into AD8339 evaluation board standoff holes center board. standoffs automatically lock into place create direct connection between AD9271 CWDx± outputs AD8339 inputs.
Power: Connect switching power supply that supplied evaluation between rated wall outlet P701. AIN: evaluation board transformercoupled analog input with optimum impedance match bandwidth. different bandwidth response, antialiasing filter settings. VREF: VREF tying SENSE ground, R317. This causes operate full-scale range. separate external reference option using ADR510 ADR520 also included evaluation board. Populate R311 R315 with resistors remove C307. Proper VREF options noted Voltage Reference section. Note that full-scale ranges less than supported this device. RBIAS: RBIAS default setting (R301) ground used core bias current. However, note that using other than resistor RBIAS degrade performance device, depending resistor chosen. Clock: default clock input circuitry derived from simple transformer-coupled circuit using high bandwidth impedance ratio transformer (T401) that adds very amount jitter clock path. clock input terminated ac-coupled handle single-ended sine wave types inputs. transformer converts single-ended input differential signal that clipped before entering clock inputs. evaluation board already clocked from crystal oscillator, OSC401. This oscillator phase noise oscillator from Valpey Fisher (VFAC3-BHL-50MHz). different clock source desired, remove R403, Jumper J401 disable oscillator from running, connect external clock source connector, P401. differential LVPECL clock driver also used clock input using AD9515 (U401). Populate R406 R407 with resistors remove R415 R416 disconnect default clock path inputs. addition, populate C405 C406 with capacitor remove C409 C410 disconnect default clock path outputs. AD9515 many pin-strappable options that default mode operation. Consult AD9515 data sheet more information about these other options.
DOUTx+, DOUTx-: alternative data capture method setup described Figure used, optional receiver terminations, R601 R610, installed next high speed backplane connector.
Rev. Page
AD9271
QUICK START PROCEDURE
following list default optional settings when using AD9271 either evaluation board system level design. evaluation board being used, follow only controller steps. When using AD9271 evaluation board, Open Analyzer click Configuration, select appropriate product configuration file. correct product configuration file available, choose similar product configuration file click Cancel create one. Analyzer User Manual located www.analog.com/FIFO. From Config menu, choose Channel Select. evaluate Channel evaluation board, ensure that only Channel checkbox Analyzer selected. Channel through Channel correspond Channel Analyzer. Channel through Channel correspond Channel Analyzer. Click Analyzer open controller software. prompted configuration file, select appropriate one. not, look title window which configuration loaded. necessary, choose Open from File menu select appropriate one. Note that CHIP ID(1) field filled regardless whether correct controller configuration file loaded.
AMPLITUDE (dBFS)
Controller, select Controller Dialog from Config menu. PROGRAM CONTROL box, ensure that Enable Auto Channel Update selected click Global Controller, find DEVICE INDEX(4/5) box. column, click that adjustment next step applies channels. Controller, find OFFSET(10) drop-down menu labeled Offset select correct offset correction: decimal MSPS speed grade, decimal MSPS speed grade, decimal MSPS speed grade. Click
-100 -110 -120 -130 FREQUENCY (MHz)
06304-119
Visual Analog.
3.5MHz -1dBFS
VGAIN FILTER TUNED 700kHz
Figure Typical FFT, AD9271-50
When using AD9271 evaluation board system level design, Click Controller software.
Global Controller, find CHIP GRADE(2) drop-down menu select correct speed grade. ADCGlobal Controller, find HIGHPASS(2B) select Manual Tune calibrate antialiasing filter.
Adjust amplitude input signal that fundamental desired level. (Examine Fund: reading left panel Analyzer window.) GAIN± pins voltage (near possible reach full scale without distortion. higher gain setting lower input level avoid distortion. Right-click plot select Comments. this record information such serial number board, channel, input clock frequencies, GAIN± pins voltage, date. Press PRINT SCREEN save screenshot desired.
Rev. Page
1K-DN LOSW ADT1-1WT ADT1-1WT 0.1U 0.1U 49.9-DN 49.9 49.9 0.1U
1K-DN LOSW 0.1U
SCHEMATICS ARTWORK
49.9-DN
0-DN 0-DN
22PF 10K-DN 0-DN 0-DN 0.1UF-DN 0.1U
0.1U 22PF 0.1UF-DN
10K-DN
0-DN
0-DN
0.1UF-DN
10K-DN 0.1UF-DN
10K-DN
1K-DN LOSW 0.1U 0.1U 49.9 0.1U 22PF 0.1UF-DN 49.9-DN
1K-DN
06304-086
Figure Evaluation Board Schematic, Analog Input Circuits
Rev. Page
ADT1-1WT
LOSW 0.1U
ADT1-1WT
49.9 0.1U
49.9-DN
0-DN
0-DN
0.1U 22PF 10K-DN 0.1UF-DN
10K-DN 0-DN 0-DN
0-DN
0-DN
0.1UF-DN
10K-DN
0.1UF-DN
10K-DN
AD9271
AD9271
1K-DN LOSW
1K-DN LOSW
49.9 0-DN ADT1-1WT 0.1UF 22PF 10K-DN 0-DN 0-DN 0.1UF-DN 0.1U 0-DN 49.9 49.9-DN 0.1UF
0.1U
0.1U
0.1U
49.9-DN
ADT1-1WT
22PF
0.1UF-DN
10K-DN
0-DN
0-DN
0.1UF-DN
10K-DN 0.1UF-DN
10K-DN
1K-DN LOSW
1K-DN
06304-087
Figure Evaluation Board Schematic, Analog Input Circuits (Continued)
Rev. Page
0-DN 0.1U 22PF 0.1UF-DN 49.9 0.1U
LOSW
0.1UF
49.9-DN CTH5
0.1U
0.1U
.9-DN
0-DN
49.9
ADT1-1WT
ADT1-1WT 0.1U 22PF 10K-DN 0.1UF-DN
10K-DN 0-DN 0-DN
0-DN
0-DN
0.1UF-DN
10K-DN
0.1UF-DN
10K-DN
GAIN DRIVE INPUT Reference Circuitry
470K
0.1UF
4.7UF
0.1UF
0.1U 0-DN
8.06
TRIM/N
0.1U
0.1UF
ADR510ART
LOSW
CWD5 CWD5-
CWD4 CWD4-
CWD3 CWD3AVD
VREF_DUT
VSENSE_DUT
AVDD_3.3V CWD2 CWD2-
CWD1 CWD1-
CWD0 CWD0LOD
LOSW
U302
REFT
REFB
SENS
RBIAS
CWD5-
CWD4-
CWD3-
CWD2-
CWD1-
LOSW
RAVDD
CWD0-
CWD5
CWD4
CWD3
CWVD
CWD2
CWD1
LO-C LOSW LOSW LO-B LO-B LOSW LOSW LO-A LOSW
DOUTH DOUTH DOUTG DOUTG DOUTF DOUTF DOUTE DOUTE DCODCO+ FCOFCO+ DOUTD DOUTD DOUTC DOUTC DOUTB DOUTB DOUTA DOUTA DRVDD DRVDD STDBY
CWD0
LOSW
LO-C LO-A LOSW CSB_DU SDIO_DU SCLK_DU
GAIN
GAIN
0.1U
LO-F
LO-F
LOSW
LOSW
0-DN
0.1U
LO-G
LO-G
LOSW
LOSW
VREF_DU
AD9271BSVZ-50
06304-088
Figure Evaluation Board Schematic, DUT, VREF, Gain Circuitry
Rev. Page
DRVDD_DUT
LO-H
LO-H
0-DN
0-DN
LOSW
LOSW
Vref Selec
using external Vref
Remove C307 when
Vref=1V
Vref External
Vref=0.5V(1+R313/R312)
VSENSE_DU
P302
P303
DRVDD_DUT
AD9271
AD9271
AOUT
AVDD_2.5V
J402 J403
AVDD_2.5V
AOUT
L401 L402 560UH
R459 0-DNP CWD1 CWD2 L403 R460 0.1UF
R455 49.9 R458 49.9 R461 0-DNP 560UH L404 560UH
DOPPLER CIRCUITR
R462 0.1UF C420 R468 U402 R453 OUT1 -IN1 CWD4+ CWD4750 CWD5R469
C419 CWD0+ CWD0CWD1+ CWD12 0.1UF C422 CWD5+ P405 OUT2 -IN2 R454
R464 560UH
R463
R467
E402
P403 R447 R452 R448 0.1UF R470
T402 AD822ARTZ +IN2
R451
OPTION CONNECTIO AD8339 EVAL BOARD
CWD3+ R446
CWD31 ADTT4-1T+ 560UH L405
CWD2-
AVDD_3.3V
AVDD_3.3V
P406 560UH L406 560UH CWD1 L407 AVDD_2.5V CWD2 560UH L408 R424 AVDD_3.3V AVDD_3.3V C405 R414 4.12K AVDD_3.3V R422 0.1UF-DNP C406 AVDD_3.3V 0-DNP AVDD_2.5V AVDD_3.3V 0-DNP R428 R426 0-DNP R465 0-DNP C421 R450 R449 0-DNP R466
CWD2+
R425 R427 AVDD_3.3V
OPTION CLOCK DRIVE CIRCUI
AD9515Pin-strapsetting
0.1UF
C401
R401
R436 R429 AVDD_3.3V 0-DNP R438
R437 0-DNP
DISABLE R408 OPT_CLK R406 U401 R409 R410 J401
R439
AVDD_3.3V
LVPECLOUTPU
R430 AVDD_3.3V 0.1UF-DNP R432 R421 AVDD_3.3V 0-DNP C407 R434 AVDD_3.3V 0-DNP R435 AVDD_3.3V R433 AVDD_3.3V R431 AVDD_3.3V 0-DNP
R440 0-DNP R442 0-DNP R444 0-DNP R445 R443 R441
RSET
VREF
E401
C402
P401
0.1UF
C410
C409
C403
P402 ADT1-1W+ 0.1UF OPT_CLK C411
0.1UF
R416
0.1UF
06304-089
Figure Evaluation Board Schematic, Clock Doppler Circuitry
ENABLE
R415
T401
0.1UF
Rev. Page
0-DNP R411 49.9-DNP CLKB OUT0B R420 R402 OPT_CLK 0-DNP SYNCB R412 R413 OUT1 SIGNAL=DNC;27,28 OUT1B R407 OUT0 GND_PAD
OSC401
STAT
AD9515BCPZ
VFAC3H-L-50MHZ
OPT_CLK
R403
0.1UF-DNP R423 C408
LVDSOUTPU
R418
0.1UF-DNP
R404 49.9
CR401 HSMS-2812
R417
CLIPSINEOUT (DEFAULT
AVDD_3.3V
0.1UF C412
0.1UF C413
0.1UF C414
0.1UF C415
0.1UF C416
0.1UF C417
0.1UF C418
R405
SDO_CHA
J501
R710 10UF
7.5V POWER 2.5MM JACK
R714 0.1UF
CSB1_CHA
SDI_CHA
Power Supply Inpu
L701 BNX016-0 PWR_IN D702 BIAS
SCLK_CH
CIRCUITRY FROM FIFO
D703
D704 D705 S2A-TP C704 D701 R716 CR702 GREEN S2A-TP S2A-TP S2A-TP
PWR_OUT
AVDD_3.3
NANOSMDC110
DISCONNECT OPTIO
SDIO_DUT NC7WZ07P6X_N AVDD R713 R712
R711
R715
BOARD MOUNTING HOLE PopulateMH501-504for standardboardevaluatio PopulateMH503-505for dockingwith AD8339Eval Board
OPTIONALPOWERINPU
P511
L501 L703 3.3V_AVD
P501
C501 10UF 0.1UF C502 C709 DUT_AVDD 10UF
DUT_DRVD 10UH
10UH
AVDD_3.3 C710 0.1UF
POWER INPUT
Z5.531.3325.
+3.3
MH50
U702 C702 0.1UF
MH50
NC7WZ16P6X_N L502
L702
Z5.531.3625. C503 10UF 0.1UF C504
AVDD 10UH C707 10UF C708 0.1UF
SCLK_DUT AVDD CSB_DUT U703 C703
10UH
+1.8v
MH50
MH50
L704
MH50
DRVDD_DUT 10UH C711 C712 10UF 0.1UF
+1.8
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
PWR_OUT L705
U707
ADP3339AKCZ-1.8-R
DUT_AVDD C722 C723
10UH C715
INPUT
OUTPUT OUTPUT
AVDD
C714
C744 0.1UF
C745 0.1UF
C746 0.1UF
C747 0.1UF
C748 0.1UF
06304-090
Figure Evaluation Board Schematic, Power Supply Interface Circuitry
C721
PWR_OUT U705 INPUT C719 L706
U704 DUT_DRVD
PWR_IN
ADP3339AKCZ-1.8-R
ADP3339AKCZ-3.3-R L707
AVDD_3.3 OUTPUT OUTPUT
DRVDD_DUT 3.3V_AVD 10UH C720 C740 0.1UF C751 0.1UF C742 0.1UF C743 0.1UF
10UH C717
INPUT
OUTPUT OUTPUT
C716
E705 E706 E707 E708
Rev. Page
U706 ADP3335ACPZ-2. 100P
AVDD
Test Points
E701 E702 E703 E704
C730 C731 C732 C733 C734 C735
AVDD_3.3
AVDD_2.5
ADP333
AD9271
AD9271
Digital Outputs
FIFO5: DATA CONNECTOR
6469169-1
GNDCD1 GNDAB1 GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD GNDCD
FIFO5: SERIAL/SPI/AUX CONNECTOR
6469169-1
GNDCD1
R601-R610 Optional Output Terminations
GNDCD
GNDAB1
GNDAB
R601 R602
GNDAB
100-DNP
CSB1_ CSB2_ CSB3_ CSB4_
GNDAB
100-DNP
GNDAB
GNDAB
R603 R604
GNDAB
100-DNP
GNDAB
100-DNP
GNDAB
GNDAB
R605 R606
GNDAB
100-DNP
GNDAB
SCLK_CH SDI_CHA SDO_CH
100-DNP
GNDAB
GNDAB
R607 R608
GNDAB
100-DNP
GNDAB
100-DNP
GNDAB
GNDAB
R609 R610
100-DNP
GNDAB
100-DNP
Figure Evaluation Board Schematic, Digital Output Interface
Rev. Page
06304-111
AD9271
Figure Evaluation Board Layout, Side
Figure Evaluation Board Layout, Ground Plane (Layer
Rev. Page
06304-083
06304-084
AD9271
Figure Evaluation Board Layout, Power Plane (Layer
Figure Evaluation Board Layout, Power Plane (Layer
Rev. Page
06304-082
06304-081
AD9271
Figure Evaluation Board Layout, Ground Plane (Layer
06304-080
Figure Evaluation Board Layout, Bottom Side
Rev. Page
06304-085
AD9271
Table Evaluation Board Bill Materials (BOM)
Item Qty. Reference Designator C101, C103, C105, C107, C109, C111, C113, C115, C121, C122, C123, C124, C201, C203, C205, C207, C209, C211, C213, C215, C221, C222, C223, C224, C301, C303, C304, C305, C306, C308, C309, C401, C402, C403, C409, C410, C411, C412, C413, C414, C415, C416, C417, C418, C419, C420, C421, C422, C502, C504, C702, C703, C708, C710, C712, C730, C731, C732, C733, C734, C735, C740, C742, C743, C744, C745, C746, C747, C748, C751 C302 C307, C714, C715, C716, C717, C719, C720, C722, C723 C102, C106, C110, C114, C202, C206, C210, C214 C721 Device Capacitor Package Description ceramic, X5R, Manufacturer Panasonic Murata RoHS Part Number ECJ-0EB1A104K 0402YD104KAT2A2 GRM155R71C104KA88D2
Capacitor Capacitor
Capacitor
Capacitor
C704 C501, C503, C707, C709, C711 CR401
Capacitor Capacitor
1812
Diode
SOT23
X5R, ceramic, X5R, ceramic, NPO, tol, ceramic, COG, X5S, ceramic, X5R, dual Schottky
Murata Panasonic Murata Kemet Murata Murata
06036D475KAT2A GRM188R60J475KE19D ECJ-1VB0J105K2 GRM188R61C105KA93D2 C0402C220J5GACTU2 04025A220JAT2A2 GRM1555C1H220JZ01D2 GRM1555C1H101JZ01D2
Taiyo Yuden Panasonic Murata Avago Technologies Limited (Agilent) Panasonic Micro Commercial Tyco/Raychem
UMK432C106MM-T2 ECJ-1VB0J106M2 GRM188R60J106M2 HSMS-2812-TR1G
CR702 D701, D702, D703, D704, D705 F701
Diode
DO-214AB
Green, candela
LNJ314G8TRA2 S2A-TP2
Fuse
1210
L401, L402, L403, L404, L405, L406, L407, L408 L501, L502, L702, L703, L704, L705, L706, L707
Inductor
1210
Ferrite bead
1210
L701
Choke coil
5-pin
trip current resettable fuse test freq kHz, tol, test freq MHz, tol, GHz, insertion loss
NANOSMDC110F-22
Murata
LQH32MN561J23L2
Murata
BLM31PG500SH1L2
Murata
BNX016-01
Rev. Page
AD9271
Item Qty. Reference Designator J501, P403 Device Connector Package 8-pin Description header, male, double straight header jumper, header, female, double straight header strip, male, single straight header jumper, Side mount 0.063 board thickness 1469169-1, right angle 2-pair, header assembly RAPC722, power supply connector 1/16 Manufacturer Samtec RoHS Part Number TSW-104-08-T-D2
P302, P303 P405, P406
Connector Connector
2-pin 8-pin
Samtec Samtec
TSW-102-07-G-S2 SSW-104-06-G-D2
P511
Connector
3-pin
Wieland
Z5.531.3325.02
J401 J101, J102, J103, J104, J201, J202, J203, J204, J301, J402, J403, P401, P402 P601, P602
Connector Connector
3-pin
Samtec Samtec
TSW-103-07-G-S2 SMA-J-P-H-ST-EM12
Connector
HEADER
Tyco/AMP
1469169-1 6469169-1
P701
Connector
0.08", PCMT
Switchcraft
RAPC722X2
R102, R103, R105, R106, R111, R112, R114, R115, R120, R121, R123, R124, R129, R130, R131, R132, R133, R137, R138, R139, R140, R149, R151, R152, R153, R162, R163, R164, R202, R203, R205, R206, R211, R213, R214, R215, R220, R221, R223, R224, R229, R230, R232, R233, R237, R238, R239, R240, R249, R250, R251, R252, R253, R262, R263, R264, R304, R317, R331, R403, R405, R415, R416, R417, R418, R425, R427, R429, R431, R433, R435, R436, R439, R441, R443, R445, R446, R450, R451, R452, R460, R462, R463, R464, R466 R108, R117, R126, R135, R208, R217, R226, R235 R158, R159, R160, R161, R258, R259, R260, R261, R302, R404, R455, R458 R301, R338, R401, R402, R410, R413, R711, R714, R715
Resistor
Panasonic Yageo Components
ERJ-2GE0R00X2 RK73Z1ETTP2 RC0402JR-070RL2 NRC04Z0TRF2
Resistor Resistor
1/16 49.9 1/16 0.5% 1/16
Components Susumu
NRC04J201TRF2 RR0510R-49R9-D2
Resistor
Panasonic Yageo Components
ERJ-2GEJ103X2 RK73B1ETTP103J2 RC0402JR-0710KL2 NRC04J103TRF2
Rev. Page
AD9271
Item Qty. Reference Designator R303, R422, R423 Device Resistor Package Description 1/16 Manufacturer Panasonic Yageo Panasonic Yageo Components Panasonic Yageo Components Murata RoHS Part Number ERJ-2RKF1000X2 RK73H1ETTP1000F2 RC0402FR-07100RL2 NRC04F1000TRF2 ERJ-2RKF1001X2 RK73H1ETTP1001F2 RC0402FR-071KL2 NRC04F1001TRF2 ERJ-2GEJ474X2 RK73B1ETTP474J2 RC0402JR-07470KL2 NRC04J474TRF2 PVA2A103A01R002
R309, R319, R325, R326, R710, R712, R713
Resistor
1/16
R308
Resistor
1/16
R310, R336
Potentiometer
3-lead
R414
Resistor
cermet trimmer potentiometer, 18-turn adjust, 10%, 4.12 1/16 1/16 8.06 1/16 1/16 1/16 clock 50.000 impedance ratio transformer, impedance ratio transformer, Octal LNA/VGA/ AAF/ADC crosspoint switch precision noise shunt voltage reference Clock dist.
R420, R421, R716
Resistor
R335 R447, R448 R453, R454, R467, R468, R469, R470 OSC401
Resistor Resistor Resistor Oscillator
Surface mount
Panasonic Components Yageo Components Components Components Components Valpey Fisher Mini-Circuits®
ERJ-2RKF4121X2 NRC04F4121TRF2 RC0402JR-07240RL2 NRC04J241TRF2 NRC04F8061TRF2 NRC04F1270TRF2 NRC04J751TRF2 VFAC3-BHL-50MHz CB3LV-3C-50M0000-T ADT1-1WT+
T101, T102, T103, T104, T201, T202, T203, T204, T401
Transformer
CD542
T402
Transformer
CD637
Mini-Circuits
ADTT4-1+
U301
SV-100-3
Analog Devices
AD9271BSVZ-50
U302
SOT23
Analog Devices
ADR510ARTZ
U401
LFCSP32-5X5
Analog Devices
AD9515BCPZ
Rev. Page
AD9271
Item Qty. Reference Designator U402 Device Package Description Dual current feedback amp, noise, dropout Regulator Regulator NC7WZ07, dual buffer, SC88 NC7WZ16P6X, dual buffer, SC88 Manufacturer Analog Devices Analog Devices Analog Devices Analog Devices Fairchild Fairchild RoHS Part Number AD812ARZ
U706
CP-8
ADP3335ACPZ-2.5
U704, U707 U705 U702 U703
SOT223-2 SOT223-2 SC88 SC88
ADP3339AKCZ-1.8 ADP3339AKCZ-3.3 NC7WZ07P6X_NL2 NC7WZ16P6X_NL2
This RoHS compliant. suitable alternative.
Rev. Page
AD9271 OUTLINE DIMENSIONS
0.75 0.60 0.45 1.20
16.00 14.00
VIEW
(PINS DOWN)
EXPOSED
9.50
1.05 1.00 0.95
0.15 0.05
SEATING PLANE
0.20 0.09 3.5° 0.08 COPLANARITY
BOTTOM VIEW (PINS
VIEW
0.50 LEAD PITCH
0.27 0.22 0.17
VIEW
ROTATED
COMPLIANT JEDEC STANDARDS MS-026-AED-HD NOTES: PACKAGE CONDUCTIVE HEAT SLUG HELP DISSIPATE HEAT ENSURE RELIABLE OPERATION DEVICE OVER FULL INDUSTRIAL TEMPERATURE RANGE. SLUG EXPOSED BOTTOM PACKAGE ELECTRICALLY CONNECTED CHIP GROUND. RECOMMENDED THAT SIGNAL TRACES VIAS LOCATED UNDER PACKAGE THAT COULD COME CONTACT WITH CONDUCTIVE SLUG. ATTACHING SLUG GROUND PLANE WILL REDUCE JUNCTION TEMPERATURE DEVICE WHICH BENEFICIAL HIGH TEMPERATURE ENVIRONMENTS.
Figure 100-Lead Thin Quad Flat Package, Exposed [TQFP_EP] (SV-100-3) Dimensions shown millimeters
ORDERING GUIDE
Model AD9271BSVZ-50 AD9271BSVZRL-501 AD9271BSVZ-401 AD9271BSVZRL-401 AD9271BSVZ-251 AD9271BSVZRL-251
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
080706-A
Package Description 100-Lead Thin Quad Flat Package, Exposed [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed [TQFP_EP] Tape Reel 100-Lead Thin Quad Flat Package, Exposed [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed [TQFP_EP] Tape Reel 100-Lead Thin Quad Flat Package, Exposed [TQFP_EP] 100-Lead Thin Quad Flat Package, Exposed [TQFP_EP] Tape Reel
Package Option SV-100-3 SV-100-3 SV-100-3 SV-100-3 SV-100-3 SV-100-3
RoHS Compliant Part.
Rev. Page
AD9271 NOTES
Rev. Page
AD9271 NOTES
©2007-2009 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D06304-0-5/09(B)
Rev. Page
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