AD824

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FEATURES Single-Supply Operation: Volts Very Input Bias Current: Wide Input Voltage Range Rail-to-Rail Output Swing Supply Current: µA/Amp Wide Bandwidth: Slew Rate: V/µs Phase Reversal APPLICATIONS Photo Diode Preamplifier Battery Powered Instrumentation Power Supply Control Protection Medical Instrumentation Remote Sensors Voltage Strain Gage Amplifiers Output Amplifier GENERAL DESCRIPTION
Single Supply, Rail-to-Rail Power, FET-Input AD824
CONFIGURATIONS 14-Lead Epoxy Suffix) 14-Lead Epoxy Suffix)
VIEW
+INB -INB OUTB
AD824
AD824
VIEW (Not Scale)
AD824 quad, input single-supply amplifier featuring rail-to-rail outputs. combination inputs rail-to-rail outputs makes AD824 useful wide variety voltage applications where input current primary consideration. AD824 guaranteed operate from single supply volt dual supplies. Fabricated ADI's complementary bipolar process, AD824 unique input stage that allows input voltage safely extend beyond negative supply positive supply without phase inversion latchup. output voltage swings within millivolts supplies. Capacitive loads handled without oscillation. input combined with laser trimming provides input that extremely bias currents with guaranteed offsets below This enables high accuracy designs even with high
source impedances. Precision combined with noise making AD824 ideal battery powered medical equipment. Applications AD824 include portable medical equipment, photo diode preamplifiers, high impedance transducer amplifiers. ability output swing rail-to-rail enables designers build multistage filters single supply systems maintain high signal-to-noise ratios. AD824 specified over extended industrial (-40°C +85°C) temperature range available 14-pin DIPs narrow 14-pin packages.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Analog Devices, Inc., 1994 Technology Way, P.O. 9106, Norwood. 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD824-SPECIFICATIONS
ELECTRICAL SPECIFICATIONS +5.0
VOUT +25°C unless otherwise noted)
4000 1013 Units V/mV V/mV V/mV V/mV µV/°C
V/µs Degrees nV/Hz fA/Hz
Parameter INPUT CHARACTERISTICS Offset Voltage AD824A Offset Voltage AD824B
Symbol
Conditions
TMIN TMAX TMIN TMAX Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio TMIN TMAX TMIN TMAX CMRR TMIN TMAX TMIN TMAX, -0.2
Input Impedance Large Signal Voltage Gain
Offset Voltage Drift
OUTPUT CHARACTERISTICS Output Voltage High
VOS/T
1000
4.988 4.985 4.85 4.82 -123 0.005
Output Voltage
Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion
ZOUT PSRR
ISOURCE TMIN TMAX ISOURCE TMIN TMAX ISINK TMIN TMAX ISINK TMIN TMAX Sink/Source TMIN TMAX MHz, TMIN TMAX TMIN TMAX Distortion, VOUT 0.01% Load kHz, kHz,
4.975 4.97 4.80 4.75
REV.
AD824 ELECTRICAL SPECIFICATIONS ±15.0
+25°C unless otherwise noted)
1013 2000 1000 14.988 14.985 14.85 14.82 -14.985 -14.98 -14.88 -14.86 4000 Units V/mV V/mV V/mV V/mV µV/°C V/µs Degrees nV/Hz fA/Hz
Parameter INPUT CHARACTERISTICS Offset Voltage AD824A Offset Voltage AD824B
Symbol
Conditions
TMIN TMAX CMRR TMIN TMAX TMIN TMAX TMIN TMAX Input Voltage Range Common-Mode Rejection Ratio Input Impedance Large Signal Voltage Gain TMIN TMAX TMIN TMAX, Input Bias Current Input Bias Current Input Offset Current
Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High
VOS/T
Output Voltage
Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion
ZOUT PSRR
ISOURCE TMIN TMAX ISOURCE TMIN TMAX ISINK TMIN TMAX ISINK TMIN TMAX Sink/Source, TMIN TMAX MHz, TMIN TMAX TMIN TMAX Distortion, VOUT 0.01% kHz, kHz, rms,
14.975 14.970 14.80 14.75
-14.975 -14.97 -14.85 -14.8
-123 0.005
REV.
AD824-SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
Parameter INPUT CHARACTERISTICS Offset Voltage AD824A Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Input Impedance Large Signal Voltage Gain TMIN TMAX TMIN TMAX TMIN TMAX CMRR TMIN TMAX TMIN TMAX, 1013 2.988 2.985 2.85 2.82
+3.0 VOUT +25°C unless otherwise noted)
Conditions 4000 Units V/mV V/mV V/mV V/mV µV/°C V/µs degrees nV/Hz fA/Hz
Symbol
Offset Voltage Drift OUTPUT CHARACTERISTICS Output Voltage High
VOS/T
Output Voltage
Short Circuit Limit Short Circuit Limit Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Full-Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion
ZOUT PSRR
ISOURCE TMIN TMAX ISOURCE TMIN TMAX ISINK TMIN TMAX ISINK TMIN TMAX Sink/Source Sink/Source, TMIN TMAX MHz, TMIN TMAX TMIN TMAX Distortion, VOUT 0.01% kHz, kHz,
2.975 2.97 2.75
-123 0.01
REV.
AD824 WAFER TEST LIMITS +5.0
+25°C unless otherwise noted)
Conditions Limit -0.2 4.975 Units µV/V V/mV
Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage High Output Voltage Supply Current/Amplifier
Symbol CMRR PSRR
ISOURCE ISINK
NOTE Electrical tests wafer probe limits shown. variations assembly methods normal yield loss, yield after packaging guaranteed standard product dice. Consult factory negotiate specifications based dice qualifications through sample assembly testing.
DICE CHARACTERISTICS
Supply Voltage Input Voltage Differential Input Voltage Output Short Circuit Duration Indefinite Storage Temperature Range Package -65°C +150°C Operating Temperature Range AD824A, -40°C +85°C Junction Temperature Range Package -65°C +150°C Lead Temperature Range (Soldering, Sec) +300°C Package Type 14-Pin Plastic 14-Pin SOIC Units °C/W °C/W
ABSOLUTE MAXIMUM RATINGS
AD824 Size 0.70 0.130 inch, 9,100 mils. Substrate (Die Backside) Connected Transistor Count, 143.
NOTES Absolute maximum ratings apply both DICE packaged parts, unless otherwise noted. specified worst case conditions, i.e., specified device socket P-DIP packages; specified device soldered circuit board SOIC package.
VOUT
ORDERING GUIDE
Model AD824AN AD824BN AD824AR-14 AD824AR-14-REEL AD824AR-14-3V AD824AR-14-3V-REEL AD824AR-16 AD824AR-16-REEL AD824ACHIPS Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C +25°C Package Option 14-Pin Plastic 14-Pin Plastic 14-Pin SOIC 14-Pin SOIC 14-Pin SOIC 14-Pin SOIC 16-Pin SOIC 16-Pin SOIC DICE
Figure Simplified Schematic AD824 CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily WARNING! accumulate human body test equipment discharge without detection. Although AD824 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper SENSITIVE DEVICE precautions recommended avoid performance degradation loss functionality.
REV.
AD824-Typical Characteristics
±15V LOAD
LOAD
GAIN
GAIN
100k
PHASE Degrees PHASE Degrees
100k
PHASE Degrees
50mV
50mV
Figure Open-Loop Gain/Phase Small Signal Response, Load
Figure Open-Loop Gain/Phase Small Signal Response, Load
±15V 100pF
220pF
GAIN
GAIN
100k
PHASE Degrees
100k
50mV
50mV
Figure Open-Loop Gain/Phase Small Signal Response,
Figure Open-Loop Gain/Phase Small Signal Response,
REV.
AD824
LOAD
9.950
GAIN
PHASE Degrees
10.810
100k
Figure Slew Rate,
50mV
Figure Open-Loop Gain/Phase Small Signal Response, Load
VOUT
220pF
GAIN
100µs
PHASE Degrees
Figure Phase Reversal with Inputs Exceeding Supply Volt
OUTPUT RAIL Volts
100k
SOURCE SINK
50mV
100µ 500µ LOAD CURRENT
Figure Open-Loop Gain/Phase Small Signal Response,
Figure Output Voltage Supply Rail Sink Source Load Currents
REV.
AD824-Typical Characteristics
COUNT
NOISE DENSITY nV/Hz
±15V
NUMBER UNITS
FREQUENCY
-2.5
-2.0
-1.5
-1.0 -0.5 OFFSET VOLTAGE DRIFT
Figure Voltage Noise Density
Figure Distribution, -55°C +125°C,
INPUT OFFSET CURRENT
0.010
THD+N
0.001
0.0001
FREQUENCY
TEMPERATURE
Figure Total Harmonic Distortion
Figure Input Offset Current Temperature
COUNT
100k
INPUT BIAS CURRENT
NUMBER UNITS
-0.5
-0.4
-0.3
-0.2 -0.1 OFFSET VOLTAGE
TEMPERATURE
Figure Input Offset Distribution,
Figure Input Bias Current Temperature
REV.
AD824
COMMON-MODE REJECTION
INPUT VOLTAGE NOISE nV/Hz
100k FREQUENCY
FREQUENCY
100k
Figure Common-Mode Rejection Frequency
Figure Input Voltage Noise Spectral Density Frequency
POWER SUPPLY REJECTION
-100
-120
FREQUENCY
100k
100k FREQUENCY
Figure Frequency,
Figure Power Supply Rejection Frequency
OPEN-LOOP GAIN
PHASE MARGIN Degrees
OUTPUT VOLTAGE Volts
±15V
100k FREQUENCY
100k INPUT FREQUENCY
300k
Figure Open-Loop Gain Phase Frequency
Figure Large Signal Frequency Response
REV.
AD824
CROSSTALK
-100
-110 -120 -130
-140
FREQUENCY
100k
Figure Crosstalk Frequency
Figure Large Signal Response
2750 2500 ±15V
OUTPUT IMPEDANCE
SUPPLY CURRENT
2250
2000 1750 1500
1250 1000
100k FREQUENCY
TEMPERATURE
Figure Output Impedance Frequency, Gain
Figure Supply Current Temperature
1000
OUTPUT SATURATION VOLTAGE
20mV
500ns
±15V
0.01
0.10 LOAD CURRENT
10.0
Figure Small Signal Response, Unity Gain Follower, Load
Figure Output Saturation Voltage
-10-
REV.
AD824
APPLICATION NOTES
INPUT CHARACTERISTICS
AD824, n-channel JFETs used provide offset, noise, high impedance input stage. Minimum input common-mode voltage extends from below less than +VS. Driving input voltage closer positive rail will cause loss amplifier bandwidth. AD824 does exhibit phase reversal input voltages including +VS. Figure shows response AD824 voltage follower (+VS) square wave input. input output superimposed. output tracks input without phase reversal. reduced bandwidth above input causes rounding output wave form. input voltages greater than +VS, resistor series with AD824's noninverting input will prevent phase reversal, expense greater input voltage noise. This illustrated Figure 29b.
current limiting resistor should used series with input AD824 there possibility input voltage exceeding positive supply more than input voltage will applied AD824 when amplifier will damaged left that condition more than seconds. resistor allows amplifier withstand volts continuous overvoltage, increases input voltage noise negligible amount. Input voltages less than completely different story. amplifier safely withstand input voltages volts below minus supply voltage long total voltage from positive supply input terminal less than volts. addition, input stage typically maintains picoamp level input currents across that input voltage range.
OUTPUT CHARACTERISTICS
AD824's unique bipolar rail-to-rail output stage swings within positive negative supply voltages. AD824's approximate output saturation resistance both sourcing sinking. This used estimate output saturation voltage when driving heavier current loads. instance, saturation voltage will volts from either supply with current load. load resistances over AD824's input error voltage virtually unchanged until output voltage driven either supply.
AD824's output overdriven saturate either output devices, amplifier will recover within input returning amplifier's linear operating region.
10µs
Direct capacitive loads will interact with amplifier's effective output impedance form additional pole amplifier's feedback loop, which cause excessive peaking pulse response loss stability. Worst case when amplifier used unity gain follower. Figures show AD824's pulse response unity gain follower driving Configurations with less loop gain, result less loop bandwidth, will much less sensitive capacitance load effects. Noise gain inverse feedback attenuation factor provided feedback network use. Figure shows method extending capacitance load drive capability unity gain follower. With these component values, circuit will drive 5,000 with overshoot.
VOUT
0.01µF 0.01µF VOUT 20pF
AD824
Figure Response with from VOUT 49.9
Since input stage uses n-channel JFETs, input current during normal operation positive; current flows from input terminals. input voltage driven more positive than input current will reverse direction internal device junctions become forward biased. This illustrated Figure
Figure Extending Unity Gain Follower Capacitive Load Capability Beyond
REV.
-11-
AD824
APPLICATIONS Single Supply Voltage-to-Frequency Converter Table AD824 Performance
circuit shown Figure uses AD824 drive power timer, which produces stable pulse width positive going output pulse integrated R1-C1 used input AD824, which connected differential integrator. other input (nonloading) unknown voltage, VIN. AD824 output drives timer trigger input, closing overall feedback loop.
+10V 0.1µF REF02 VREF RSCALE CMOS 74HCO4 CMOS 116k OUT2 0.1µF
Parameters CMRR Common-Mode Voltage Range tSETTLING Step Noise kHz,
-0.2 -5.2 nV/Hz µV/Hz nV/Hz µV/Hz
OUT1
0.01µF, 499k,
499k, 2.5V FULL SCALE 0.01µF,
AD824B
390pF (NPO)
0.01µF
NOTES: fOUT /(VREF*t1 1.1*R3*C6 25kHz SHOWN.
Figure 32a. Pulse Response Input Signal; Gain
METAL FILM, <50ppm/°C 10%, FILM, <100ppm/°C
33µs 20kHz 2.0V
VREF
OHMTEK PART 1043
Figure Single Supply Voltage-to-Frequency Converter
=100
=100
Typical AD824 bias currents allow megaohm-range source impedances with negligible errors. Linearity errors order 0.01% full scale achieved with this circuit. This performance obtained with volt single supply which delivers less than entire circuit.
Single-Supply Programmable Gain Instrumentation Amplifier
0.1µF VIN2 =10) (VIN1 +VREF (VIN1 +VREF
VIN1
AD824
AD824
VOUT
AD824 configured single supply instrumentation amplifier that able operate from single supplies down dual supplies AD824 inputs' bias currents minimize offset errors caused high unbalanced source impedances. array precision thin-film resistors sets gain either 100. These resistors laser-trimmed ratio match 0.01%, have rnaximum differential ppm/°C.
=100)
Figure 32b. Single-Supply Programmable Instrumentation Amplifier
-12-
REV.
AD824
Volt, Single Supply Stereo Headphone Driver
AD824 exhibits good current drive THD+N performance, even single supplies. kHz, total harmonic distortion plus noise (THD+N) equals (0.079%) output signal. This comparable other single supply amps which consume more power cannot power supplies. Figure each channel's input signal coupled Mylar capacitor. Resistor dividers voltage noninverting inputs that output voltage midway between power supplies (+1.5 gain 1.5. Each half AD824 then used drive headphone channel. high-pass filter realized capacitors headphones, which modeled load resistors ground. This ensures that signals audio frequency range Hz-20 kHz) delivered headphones.
0.1µF 0.1µF
+4.5 used drive converter front end. other half AD824 configured unity-gain inverter, generates other bridge input -4.5 Resistors provide constant current bridge excitation. AD620 power instrumentation amplifier used condition differential output voltage bridge. gain AD620 programmed using external resistor determined
49.4
Volt/5 Volt Precision Sample-and-Hold Amplifier
CHANNEL MYLAR
95.3k
47.5k
AD824 500µF
95.3k
4.99k HEADPHONES IMPEDANCE
battery-powered applications, supply voltage operational amplifiers required power consumption. Also, supply voltage applications limit signal range precision analog circuitry. Circuits like sample-and-hold circuit, shown Figure illustrate techniques designing precision analog circuitry supply voltage applications. maintain high signal-to-noise ratios (SNRs) supply voltage application requires rail-to-rail, input/output operational amplifiers. This design highlights ability AD824 operate rail-to-rail from single V/+5 supply, with advantages high input impedance. AD824, quad JFETinput amp, well suited circuits input bias currents typical) high input impedances 1013 typical). AD824 also exhibits very supply currents such that total supply current this circuit less than
3.3/5V 3.3/5V 0.1µF 3.3/5V VOUT 500pF ADG513
4.99k 47.5k AD824
CHANNEL MYLAR
AD824A
500µF
FALSE GROUND (FG)
Figure Volt Single Supply Stereo Headphone Driver
Dropout Bipolar Bridge Driver
AD824 used driving Wheatstone bridge. Figure shows half AD824 being used buffer AD589-a 1.235 power reference. output
49.9k +1.235V AD589 AD824 26.4k, AD824 -4.5V 0.1µF 0.1µF AD620 VREF CONVERTER REFERENCE INPUT
AD824B
AD824C
500pF
AD824D
SAMPLE/ HOLD
Figure V/5.5 Precision Sample Hold
Figure Dropout Bipolar Bridge Driver
many single supply applications, false ground generator required. this circuit, divide supply voltage symmetrically, creating false ground voltage one-half supply. Amplifier then buffers this voltage creating impedance output drive. circuit configured inverting topology centered around this false ground level. -13-
REV.
AD824
design consideration sample-and-hold circuits voltage droop output caused bias switch leakage currents. choosing JFET leakage CMOS switch, this design minimizes droop rate error better than µV/µs this circuit. Higher values will yield lower droop rate. best performance should polystyrene, polypropylene, Teflon capacitors. These types capacitors exhibit leakage dielectric absorption. Additionally, metal film resistors were used throughout design. sample mode, closed, output VOUT -VIN. purpose SW4, which operates parallel with SW1, reduce pedestal, hold step, error injecting same amount charge into noninverting input that injects into inverting input This creates common-mode voltage across inputs then rejected Otherwise, charge injection from would create differential voltage step error that would appear VOUT. pedestal error this circuit less than over entire signal range. Another method reducing pedestal error reduce pulse amplitude applied control pins. order control ADG513, only required "ON" state "OFF" state. possible, input control signal whose amplitude ranges from instead full range minimum pedestal error. Other circuit features include acquisition time less than reducing will speed acquisition time further, increased pedestal error will result. Settling time less than sample-mode signal kHz. ADG513 chosen ability work with supplies, having normally-open normally-closed precision CMOS switches dielectrically isolated process. required this circuit; however, used parallel with provide lower analog switch.
-14-
REV.
AD824
AD824 SPICE Macro-model 9/94, Rev. ARG/ADI Copyright 1994 Analog Devices, Inc. Refer "README.DOC" file License Statement. this model indicates your acceptance with terms provisions License Statement. Node assignments noninverting input inverting input positive supply negative supply output .SUBCKT AD824 INPUT STAGE POLE 1.193E3 1.193E3 4E-12 19.229E-12 108E-6 1E-12 POLY(1) (12,98) 100E-6 GAIN STAGE DOMINANT POLE EREF (30,0) 2.205E6 54E-12 (6,5) 0.838E-3 COMMON-MODE GAIN NETWORK WITH ZERO 159E-12 POLY(2) (2,98) (1,98) POLE 15.9E-15 (9,98) 1E-6 OUTPUT STAGE (18,98) 2.404E-3 2.404E-3 2E-12 2E-12 (99,0) (50,0) FSY1 FSY2 MODELS USED .MODEL NJF(BETA=3.2526E-3 VTO=-2.000 IS=2E-12) .MODEL NPN(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=550 IS=1E-16) .MODEL PNP(BF=120 VAF=150 VAR=15 RB=2E3 RE=4 RC=750 IS=1E-16) .MODEL D(IS=1E-15) .MODEL .MODEL D(IS=1E-16) .ENDS AD824
REV.
-15-
AD824
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
Mini-DIP Package
0.795 (20.19) 0.725 (18.42) 0.210 (5.33) 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) 0.070 (1.77) 0.045 (1.15) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.280 (7.11) 0.240 (6.10)
0.130 (3.30) SEATING PLANE
0.015 (0.381) 0.008 (0.204)
SOIC Package
0.1574 (4.00) 0.1497 (3.80)
0.2440 (6.20) 0.2284 (5.80)
0.3444 (8.75) 0.3367 (8.55) 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.0500 (1.27)
0.0196 (0.50) 0.0099 (0.25)
0.0192 (0.49) 0.0138 (0.35)
0.0098 (0.25) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
-16-
REV.
PRINTED U.S.A.
C1988-18-12/94

AD824

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