AD7714-3 AD7714-5
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FEATURES Charge Balancing Bits Missing Codes 0.0015% Nonlinearity Five-Channel Programmable Gain Front Gains from Configured Three Fully Differential Inputs Five Pseudo-Differential Inputs Three-Wire Serial Interface (AD7714-3) (AD7714-5) Operation Noise (<150 rms) Current (350 typ) with Power-Down typ) Low-Pass Filter with Programmable Filter Cutoffs Ability Read/Write Calibration Coefficients APPLICATIONS Portable Industrial Instruments Portable Weigh Scales Loop-Powered Systems Pressure Transducers GENERAL DESCRIPTION
AVDD AIN1 AIN2 AIN3 AIN4 AIN5 AIN6
SWITCHING MATRIX
CMOS, Signal Conditioning AD7714*
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD IN(-) IN(+)
AD7714
CHARGING BALANCING CONVERTER STANDBY
BUFFER
1-128
MODULATOR
DIGITAL FILTER
SYNC
AGND BUFFER MCLK MCLK CLOCK GENERATION SERIAL INTERFACE REGISTER BANK SCLK DOUT
AGND
DGND
DRDY
RESET
AD7714 complete analog front low-frequency measurement applications. device accepts level signals directly from transducer outputs serial digital word. employs sigma-delta conversion technique realize bits missing codes performance. input signal applied proprietary programmable gain front based around analog modulator. modulator output processed on-chip digital filter. first notch this digital filter programmed on-chip control register allowing adjustment filter cutoff settling time. part features three differential analog inputs (which also configured five pseudo-differential analog inputs) well differential reference input. operates from single supply AD7714 thus performs signal conditioning conversion system consisting five channels. AD7714 ideal smart, microcontroller- DSPbased systems. features serial interface that configured three-wire operation. Gain settings, signal polarity channel selection configured software using serial port. AD7714 provides self-calibration, system calibration background calibration options also allows user read write on-chip calibration registers.
*Protected U.S. Patent 5,134,401. page data sheet index.
CMOS construction ensures very power dissipation, power-down mode reduces standby power consumption typ. part available 24-pin, inch-wide, plastic hermetic dual-in-line package (DIP); lead small outline (SOIC) package 28-lead shrink small outline package (SSOP).
PRODUCT HIGHLIGHTS
AD7714 consumes less than (fCLK MHz) (fCLK MHz) total supply current, making ideal loop-powered systems. programmable gain channels allow AD7714 accept input signals directly from strain gage transducer removing considerable amount signal conditioning. AD7714 ideal microcontroller processor applications with three-wire serial interface reducing number interconnect lines reducing number opto-couplers required isolated systems. part contains on-chip registers that allow control over filter cutoff, input gain, channel selection, signal polarity calibration modes. part features excellent static performance specifications with 24-bit missing codes, ±0.0015% accuracy noise (140 nV). End-point errors effects temperature drift eliminated on-chip self-calibration, which removes zero-scale full-scale errors.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood. 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD7714-5-SPECIFICATIONS 2.4576 unless otherwise stated. specifications
DVDD +3.3 IN(+) +2.5 IN(-) AGND; TMAX unless otherwise noted.)
Conditions/Comments Guaranteed Design. Bipolar Mode. Filter Notches Filter Notch Filter Notch Filter Notch Filter Notch Depends Filter Cutoffs Selected Gain Filter Notches Gains Gains Gains Gains Gains Gains Typically 0.0004% Gains Gains Specifications Unless Noted Table Filter Notches 0.02 fNOTCH Filter Notches 0.02 fNOTCH Filter Notches 0.02 fNOTCH Filter Notches 0.02 fNOTCH BUFFER BUFFER BUFFER Version BUFFER Version Version Version Unipolar Input Range (B/U Filter High Register Bipolar Input Range (B/U Filter High Register Gains Gains Specified Performance. Functional with Lower VREF
Parameter STATIC PERFORMANCE Missing Codes
Versions1 Tables 0.0015 Note Note Note Note 0.0015 AGND AVDD AGND AVDD AGND AGND AVDD +VREF/GAIN11 VREF/GAIN GAIN fCLK IN/64 fCLK IN/8 +2.5 fCLK IN/64 DVDD
Units Bits Bits Bits Bits Bits µV/°C µV/°C µV/°C µV/°C µV/°C µV/°C FSR/°C µV/°C µV/°C
Output Noise Integral Nonlinearity Unipolar Offset Error Unipolar Offset Drift3 Bipolar Zero Error Bipolar Zero Drift3 Positive Full-Scale Error4 Full-Scale Drift3, Gain Error6 Gain Drift3, Bipolar Negative Full-Scale Error Bipolar Negative Full-Scale Drift3 ANALOG INPUTS/REFERENCE INPUTS Common-Mode Rejection (CMR) Normal-Mode Rejection8 Normal-Mode Rejection8 Common-Mode Rejection8 Common-Mode Rejection8 Common-Mode Voltage Range9 Absolute AIN/REF Voltage9 Absolute/Common-Mode Voltage9 Input Current8 Sampling Capacitance8 Differential Voltage Range10 Input Sampling Rate, IN(+) IN(-) Voltage Input Sampling Rate, LOGIC INPUTS Input Current Inputs Except MCLK VINL, Input Voltage VINL, Input Voltage VINH, Input High Voltage MCLK Only VINL, Input Voltage VINL, Input Voltage VINH, Input High Voltage VINH, Input High Voltage LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Voltage VOL, Output Voltage VOH, Output High Voltage VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance13
DVDD DVDD +3.3
DVDD DVDD +3.3 DVDD DVDD +3.3 ISINK Except MCLK OUT.12 DVDD ISINK Except MCLK OUT.12 DVDD +3.3 ISOURCE Except MCLK OUT.12 DVDD ISOURCE Except MCLK OUT.12 DVDD +3.3
NOTES Temperature ranges follows: Version: -40°C +85°C; Version: -55°C +125°C. calibration effectively conversion these errors will order conversion noise shown Tables This applies after calibration temperature interest. Recalibration temperature will remove these drift errors. Positive Full-Scale Error includes Zero-Scale Errors (Unipolar Offset Error Bipolar Zero Error) applies both unipolar bipolar input ranges. Full-Scale Drift includes Zero-Scale Drift (Unipolar Offset Drift Bipolar Zero Drift) applies both unipolar bipolar input ranges. Gain Error does include Zero-Scale Errors. calculated Full-Scale Error-Unipolar Offset Error unipolar ranges Full-Scale Error-Bipolar Zero Error bipolar ranges.
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AD7714
AD7714-3-SPECIFICATIONS 2.4576 unless otherwise stated. specifications
+3.3 DVDD +3.3 IN(+) +1.25 IN(-) =AGND; TMAX unless otherwise noted.)
Parameter STATIC PERFORMANCE Missing Codes
Versions Tables 0.0015 Note Note Note Note 0.003 AGND AVDD AGND AVDD AGND AVDD +VREF/GAIN11 VREF/GAIN GAIN fCLK IN/64 fCLK IN/8 +1.25 fCLK IN/64 DVDD
Units Bits Bits Bits Bits Bits µV/°C µV/°C µV/°C µV/°C µV/°C µV/°C FSR/°C µV/°C µV/°C
Conditions/Comments Guaranteed Design. Bipolar Mode. Filter Notches Filter Notch Filter Notch Filter Notch Filter Notch Depends Filter Cutoffs Selected Gain Filter Notches Gains Gains Gains Gains Gains Gains Typically 0.0004% Gains Gains Specifications Unless Noted Table Filter Notches 0.02 fNOTCH Filter Notches 0.02 fNOTCH Filter Notches 0.02 fNOTCH Filter Notches 0.02 fNOTCH BUFFER BUFFER BUFFER
Output Noise Integral Nonlinearity Unipolar Offset Error Unipolar Offset Drift3 Bipolar Zero Error Bipolar Zero Drift3 Positive Full-Scale Error Full-Scale Drift3,
Gain Error Gain Drift3, Bipolar Negative Full-Scale Error Bipolar Negative Full-Scale Drift3 ANALOG INPUTS/REFERENCE INPUTS Common-Mode Rejection (CMR) Normal-Mode Rejection8 Normal-Mode Rejection8 Common-Mode Rejection8 Common-Mode Rejection8 Common-Mode Voltage Range9 Absolute AIN/REF Voltage9 Absolute/Common-Mode Voltage9 Input Current Sampling Capacitance8 Differential Voltage Range10 Input Sampling Rate, IN(+) IN(-) Voltage Input Sampling Rate, LOGIC INPUTS Input Current Inputs Except MCLK VINL, Input Voltage VINH, Input High Voltage MCLK Only VINL, Input Voltage VINH, Input High Voltage LOGIC OUTPUTS (Including MCLK OUT) VOL, Output Voltage VOH, Output High Voltage Floating State Leakage Current Floating State Output Capacitance13
Unipolar Input Range (B/U Filter High Register Bipolar Input Range (B/U Filter High Register Gains Gains Specified Performance. Part Functions with Lower VREF
ISINK Except MCLK OUT12 ISOURCE Except MCLK OUT12
NOTES Gain Error Drift does include Unipolar Offset Drift/Bipolar Zero Drift. effectively drift part zero-scale calibrations only were performed case with background calibration. These numbers guaranteed design and/or characterization. common-mode voltage range input pairs applies provided absolute input voltage specification obeyed. input voltage range analog inputs given here with respect voltage respective negative input differential pseudo-differential pair. Table which inputs form differential pairs. VREF IN(+) IN(-). These logic output levels apply MCLK output only when loaded with single CMOS load. Sample tested +25°C ensure compliance. Burn-Out Current section.
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+3.3 +1.25 (AD7714-3) AD7714-SPECIFICATIONS 3.3otherwiseV,stated.=All specificationsREF IN(+) unless Votherwise noted.)+2.5 (AD7714-5); IN(-) AGND; MCLK 2.4576 unless
Parameter TRANSDUCER BURNOUT14 Current Initial Tolerance Drift SYSTEM CALIBRATION Positive Full-Scale Calibration Limit15 Negative Full-Scale Calibration Limit15 Offset Calibration Limit16 Input Span16
Versions
Units %/°C
Conditions/Comments
(1.05 VREF)/GAIN -(1.05 VREF)/GAIN -(1.05 VREF)/GAIN VREF/GAIN (2.1 VREF)/GAIN
GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128) GAIN Selected Gain (Between 128)
POWER REQUIREMENTS Power Supply Voltages AVDD Voltage (AD7714-3) AVDD Voltage (AD7714-5) DVDD Voltage Power Supply Currents AVDD Current
+3.6 +4.75 +5.25 +5.25
Specified Performance Specified Performance Specified Performance AVDD Filter High Register Typically BUFFER fCLK 2.4576 Typically BUFFER DVDD. fCLK 2.4576 AVDD Filter High Register Typically BUFFER fCLK 2.4576 Typically BUFFER DVDD. fCLK 2.4576 Digital I/Ps DVDD. External MCLK Typically 0.15 DVDD fCLK Typically DVDD fCLK Typically DVDD fCLK 2.4576 Typically DVDD fCLK 2.4576 AVDD DVDD +3.3 Digital I/Ps DVDD. External MCLK Typically 1.25 BUFFER fCLK MHz. Typically BUFFER +3.3 fCLK MHz. Typically BUFFER fCLK 2.4576 MHz. Typically BUFFER +3.3 fCLK 2.4576 MHz. AVDD DVDD Digital I/Ps DVDD. External MCLK Typically BUFFER fCLK MHz. Typically BUFFER fCLK MHz. Typically BUFFER fCLK 2.4576 MHz. Typically BUFFER fCLK 2.4576 MHz. External MCLK DVDD. Typically External MCLK DVDD. Typically +3.3
0.27 DVDD Current18 0.23 Note 1.65 2.75 2.55 3.65 Normal-Mode Power Dissipation 3.35 5.35
Power Supply Rejection19 Normal-Mode Power Dissipation18
Standby (Power-Down) Current21 Standby (Power-Down) Current21
NOTES After calibration, input voltage exceeds positive full scale, converter will output input less than negative full scale, then device outputs These calibration span limits apply provided absolute voltage analog inputs does exceed more negative than AGND offset calibration limit applies both unipolar zero point bipolar zero point. higher gains fCLK 2.4576 MHz, Filter High Register must other conditions, When using crystal ceramic resonator across MCLK pins clock source device, current power dissipation will vary depending crystal resonator type (see Clocking Oscillator Circuit section). Measured applies selected passband. PSRR will exceed with filter notches PSRR will exceed with filter notches PSRR depends gain. Gain typ: Gain typ; Gain typ; Gains typ. external master clock continues standby mode, standby current increases typical with supplies typical with supplies. When using crystal ceramic resonator across MCLK pins clock source device, internal oscillator continues standby mode power dissipation depends crystal resonator type (see Standby Mode section). Specifications subject change without notice.
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AD7714 TIMING
Parameter fCLKIN
CLKIN CHARACTERISTICS1, Logic Logic DVDD unless otherwise noted.)
+5.25 AGND DGND
MHz; Input
Limit TMIN, TMAX Versions) tCLK tCLK tCLK
Units
Conditions/Comments Master Clock Frequency: Crystal/Resonator Externally Supplied Specified Performance Master Clock Input Time. tCLK 1/fCLK Master Clock Input High Time DRDY High Time SYNC Pulse Width RESET Pulse Width DRDY Setup Time Falling Edge SCLK Active Edge Setup Time5 SCLK Active Edge Data Valid Delay5 DVDD DVDD SCLK High Pulse Width SCLK Pulse Width Rising Edge SCLK Active Edge Hold Time5 Relinquish Time after SCLK Active Edge5 DVDD DVDD SCLK Active Edge DRDY High5, Falling Edge SCLK Active Edge Setup Time5 Data Valid SCLK Edge Setup Time Data Valid SCLK Edge Hold Time SCLK High Pulse Width SCLK Pulse Width Rising Edge SCLK Edge Hold Time
tCLK tCLK tDRDY Read Operation Write Operation
NOTES Sample tested +25°C ensure compliance. input signals specified with (10% timed from voltage level Figures CLKIN Duty Cycle range 55%. CLKIN must supplied whenever AD7714 standby mode. clock present this case, device draw higher current than specified possibly become uncalibrated. AD7714 production tested with CLKIN 2.4576 some tests). guaranteed characterization operate kHz. SCLK active edge falling edge SCLK with SCLK active edge rising edge SCLK with These numbers measured with load circuit Figure defined time required output cross limits. These numbers derived from measured time taken data output change when loaded with circuit Figure measured number then extrapolated back remove effects charging discharging capacitor. This means that times quoted timing characteristics true relinquish times part such independent external loading capacitances. DRDY returns high after first read from device after output update. same data read again, required, while DRDY high although care should taken that subsequent reads occur close next output update.
ORDERING GUIDE
Model
ISINK (800µA DVDD 100µA DVDD +3.3V) OUTPUT +1.6V 50pF ISOURCE (200µA DVDD 100µA DVDD +3.3V)
AVDD Supply
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -55°C +125°C -40°C +85°C -40°C +85°C Evaluation Board Evaluation Board
Package Option* N-24 R-24 RS-28 N-24 R-24 RS-28 Q-24
Figure Load Circuit Access Time Relinquish Time
AD7714AN-5 AD7714AR-5 AD7714ARS-5 AD7714AN-3 AD7714AR-3 AD7714ARS-3 AD7714SQ-5 AD7714AChips-5 AD7714AChips-3 EVAL-AD7714-5EB EVAL-AD7714-3EB
Plastic DIP; SOIC; SSOP; Cerdip.
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AD7714
ABSOLUTE MAXIMUM RATINGS*
+25°C unless otherwise noted)
AVDD AGND -0.3 AVDD DGND -0.3 DVDD AGND -0.3 DVDD DGND -0.3 Analog Input Voltage AGND -0.3 AVDD Reference Input Voltage AGND -0.3 AVDD Digital Input Voltage DGND -0.3 DVDD Digital Output Voltage DGND -0.3 DVDD Operating Temperature Range Commercial Version) -40°C +85°C Extended Version) -55°C +125°C Storage Temperature Range -65°C +150°C Junction Temperature +150°C Plastic Package, Power Dissipation Thermal Impedance 105°C/W
Lead Temperature (Soldering, sec) +260°C Cerdip Package, Power Dissipation Thermal Impedance 70°C/W Lead Temperature (Soldering, sec) +300°C SOIC Package, Power Dissipation Thermal Impedance 75°C/W Lead Temperature, Soldering Vapor Phase sec) +215°C Infrared sec) +220°C Power Dissipation (Any Package) +75°C
*Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device these other conditions above those listed operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although these devices feature proprietary protection circuitry, permanent damage still occur these devices they subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
CONFIGURATIONS SOIC
SCLK MCLK MCLK SYNC RESET AIN1 AIN2 AIN3 DGND DVDD DOUT DRDY VIEW (Not Scale) AGND AIN6 AIN5 IN(+) IN(-) BUFFER SCLK MCLK MCLK SYNC RESET AIN1
SSOP
DGND DVDD DOUT DRDY VIEW (Not Scale) AGND AIN6 AIN5 IN(+) IN(-) BUFFER
AD7714
AD7714
AIN4 STANDBY AVDD
AIN2 AIN3 AIN4 STANDBY AVDD
CONNECT
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AD7714
FUNCTION DESCRIPTION DIP/SOIC NUMBERS
Mnemonic SCLK
Function
Serial Clock. Logic Input. external serial clock applied this input access serial data from AD7714. This serial clock continuous clock with data transmitted continuous train pulses. Alternatively, noncontinuous clock with information being transmitted AD7714 smaller batches data. MCLK Master Clock signal device. This provided form crystal/resonator external clock. crystal/resonator tied across MCLK MCLK pins. Alternatively, MCLK driven with CMOS-compatible clock MCLK left unconnected. part specified with clock input frequencies both 2.4576 MHz. MCLK When master clock device crystal/resonator, crystal/resonator connected between MCLK MCLK OUT. external clock applied MCLK MCLK provides inverted clock signal. This clock used provide clock source external circuits. Clock Polarity. Logic Input. With this input low, first transition serial clock data transfer operation from high. microcontroller applications, this means that serial clock should idle between data transfers. With this input high, first transition serial clock data transfer operation from high low. microcontroller applications, this means that serial clock should idle high between data transfers. SYNC Logic Input which allows synchronization digital filters analog modulators when using number AD7714s. While SYNC low, nodes digital filter, filter control logic calibration control logic reset analog modulator also held reset state. SYNC does affect digital interface does reset DRDY low. RESET Logic Input. Active input which resets control logic, interface logic, digital filter analog modulator part power-on status. AIN1 Analog Input Channel Programmable-gain analog input which used pseudo-differential input when used with AIN6 positive input differential analog input pair when used with AIN2 (see Communications Register section). AIN2 Analog Input Channel Programmable-gain analog input which used pseudo-differential input when used with AIN6 negative input differential analog input pair when used with AIN1 (see Communications Register section). AIN3 Analog Input Channel Programmable-gain analog input which used pseudo-differential input when used with AIN6 positive input differential analog input pair when used with AIN4 (see Communications Register section). AIN4 Analog Input Channel Programmable-gain analog input which used pseudo-differential input when used with AIN6 negative input differential analog input pair when used with AIN3 (see Communications Register section). STANDBY Logic Input. Taking this shuts down analog digital circuitry, reducing current consumption typically AVDD Analog Positive Supply Voltage, +3.3 nominal (AD7714-3) nominal (AD7714-5). BUFFER Buffer Option Select. Logic Input. With this input low, on-chip buffer analog input (after multiplexer before analog modulator) shorted out. With buffer shorted current flowing AVDD line reduced With this input high, on-chip buffer series with analog input allowing inputs handle higher source impedances. IN(-) Reference Input. Negative input differential reference input AD7714. IN(-) anywhere between AVDD AGND provided IN(+) greater than IN(-). IN(+) Reference Input. Positive input differential reference input AD7714. reference input differential with provision that IN(+) must greater than IN(-). IN(+) anywhere between AVDD AGND. AIN5 Analog Input Channel Programmable-gain analog input which positive input differential analog input pair when used with AIN6 (see Communications Register section). AIN6 Analog Input Channel Reference point AIN1 through AIN4 pseudo-differential mode negative input differential input pair when used with AIN5 (see Communications Register section). AGND Ground reference point analog circuitry.
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AD7714
FUNCTION DESCRIPTION (Continued)
Mnemonic
Function Chip Select. Active Logic Input used select AD7714. With this input hard-wired low, AD7714 operate three-wire interface mode with SCLK, DOUT used interface device. used select device systems with more than device serial frame synchronization signal communicating with AD7714. Logic output. logic this output indicates that output word available from AD7714 data register. DRDY will return high upon completion read operation full output word. data read taken place, after output update, DRDY line will return high tCLK cycles prior next output update. This gives indication when read operation should attempted avoid reading from data register being updated. DRDY also used indicate when AD7714 completed on-chip calibration sequence. Serial Data Output with serial data being read from output shift register part. This output shift register contain information from calibration registers, mode register, communications register, filter selection registers data register depending register selection bits Communications Register. Serial Data Input with serial data being written input shift register part. Data from this input shift register transferred calibration registers, mode register, communications register filter selection registers depending register selection bits Communications Register. Digital Supply Voltage, +3.3 nominal. Ground reference point digital circuitry. AIN(+) voltage (AIN(-) VREF/GAIN LSB) when operating bipolar mode.
POSITIVE FULL-SCALE OVERRANGE
DRDY
DOUT
DVDD DGND
TERMINOLOGY*
INTEGRAL NONLINEARITY
This maximum deviation code from straight line passing through endpoints transfer function. endpoints transfer function zero scale (not confused with bipolar zero), point below first code transition (000 001) full scale, point above last code transition (111 111). error expressed percentage full scale.
POSITIVE FULL-SCALE ERROR
Positive Full-Scale Overrange amount overhead available handle input voltages AIN(+) input greater than AIN(-) VREF/GAIN (for example, noise peaks excess voltages system gain errors system calibration routines) without introducing errors overloading analog modulator overflowing digital filter.
NEGATIVE FULL-SCALE OVERRANGE
Positive Full-Scale Error deviation last code transition (111 111) from ideal AIN(+) voltage (AIN(-) VREF/GAIN LSBs). applies both unipolar bipolar analog input ranges.
UNIPOLAR OFFSET ERROR
This amount overhead available handle voltages AIN(+) below AIN(-) VREF/GAIN without overloading analog modulator overflowing digital filter. Note that analog input will accept negative voltage peaks even unipolar mode provided that AIN(+) greater than AIN(-) greater than AGND
OFFSET CALIBRATION RANGE
Unipolar Offset Error deviation first code transition from ideal AIN(+) voltage (AIN(-) LSB) when operating unipolar mode.
BIPOLAR ZERO ERROR
This deviation midscale transition (0111 1000 000) from ideal AIN(+) voltage (AIN(-) LSB) when operating bipolar mode.
GAIN ERROR
system calibration modes, AD7714 calibrates offset with respect analog input. Offset Calibration Range specification defines range voltages that AD7714 accept still calibrate offset accurately.
FULL-SCALE CALIBRATION RANGE
This range voltages that AD7714 accept system calibration mode still calibrate full scale correctly.
INPUT SPAN
This measure span error ADC. includes fullscale errors zero-scale errors. unipolar input ranges defined (full-scale error unipolar offset error) while bipolar input ranges defined (full-scale error bipolar zero error).
BIPOLAR NEGATIVE FULL-SCALE ERROR
system calibration schemes, voltages applied sequence AD7714's analog input define analog input range. input span specification defines minimum maximum input voltages from zero full scale that AD7714 accept still calibrate gain accurately.
*AIN(-) refers negative input differential input pairs AIN6 when referring pseudo-differential input configurations.
This deviation first code transition from ideal
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AD7714
AD7714-5 OUTPUT NOISE
Table shows output noise effective resolution some typical notch frequencies AD7714-5 with fCLK 2.4576 while Table gives information fCLK MHz. numbers given bipolar input ranges with VREF +2.5 with BUFFER These numbers typical generated analog input voltage numbers brackets each table effective resolution part (rounded nearest LSB). effective resolution device defined ratio output noise input full scale (i.e., VREF/GAIN). should noted that calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers times numbers while effective resolution numbers based peak-to-peak noise bits below effective resolution based noise quoted tables. output noise from part comes from sources. first electrical noise semiconductor devices used implementation modulator (device noise). Secondly, when analog input signal converted into digital domain, quantization noise added. device noise level largely independent frequency. quantization noise starts even lower level rises rapidly with increasing frequency become dominant noise source. Consequently, lower filter notch settings (below approximately fCLK 2.4576 below approximately fCLK MHz) tend device noise dominated while higher notch settings dominated quantization noise. Changing filter notch cutoff frequency quantization-noise dominated region results more dramatic improvement noise performance than does device-noise dominated region shown Table Furthermore, quantization noise added after PGA, effective resolution largely independent gain higher filter notch frequencies. Meanwhile, device noise added and, therefore, effective resolution reduces high gains lower notch frequencies. Additionally, device-noise dominated region, output noise largely independent reference voltage while quantization-noise dominated region, noise proportional value reference. possible post-filtering device improve output data rate given frequency also further reduce output noise. lower filter notch settings (below fCLK 2.4576 below fCLK MHz), missing codes performance device 24-bit level. higher settings, more codes will missed until notch setting fCLK 2.4576 (400 fCLK MHz), missing codes performance only guaranteed 12-bit level.
Table AD7714-5 Output Noise/Resolution Gain First Notch 2.4576 MHz, BUFFER Filter First Notch Data Rate Typical Output Noise (Effective Resolution Bits) Gain Gain Gain Gain Gain Gain 0.48 0.78 1.31 2.06 2.36 1,258 (22.5) (21.5) (21) (21) (20) (20) (18.5) (15.5) (13) (11) 0.24 0.48 0.63 0.84 1.33 2.86 (22.5) (21.5) (21) (20.5) (20) (20) (19) (15.5) (13) (11) 0.33 0.57 0.64 0.87 1.91 15.9 (21.5) (21) (20) (20) (20) (19.5) (18.5) (15.5) (13) (11) 0.18 0.25 0.44 0.46 0.54 0.63 1.06 (20.5) (20.5) (19.5) (19.5) (19) (19) (18) (15.5) (13) (11) 0.17 0.25 0.41 0.43 0.46 0.62 0.83 3.72 (20) (19.5) (18.5) (18.5) (18.5) (18) (17.5) (15.5) (13) (10.5) 0.17 0.25 0.38 0.46 0.82 1.96
Frequency 1.31 2.62 6.55 7.86 13.1 15.72 26.2 65.5
Gain 0.87 4.33 5.28 12.1 2,850 (22.5) (22.5) (21.5) (21) (20) (20) (18.5) (15.5) (13) (11)
Gain (18) (17.5) (16.5) (16.5) (16.5) (16) (15.5) (14.5) (13) (10.5)
(19) 0.17 (18.5) 0.25 (17.5) 0.38 (17.5) (17.5) 0.46 (17) 0.56 (16.5) 0.76 (15.5) (13) (10.5)
Table AD7714-5 Output Noise/Resolution Gain First Notch MHz, BUFFER Filter First Notch Data Rate Typical Output Noise (Effective Resolution Bits) Gain Gain Gain Gain Gain Gain 0.56 0.88 1.01 2.06 3.28 9.11 1,430 (22) (21.5) (21.5) (20) (19.5) (18) (17.5) (15.5) (13) (11) 0.31 0.45 0.77 1.42 (22) (21.5) (20.5) (20) (19.5) (18) (17.5) (15.5) (13) (11) 0.19 0.28 0.41 0.86 1.07 2.45 13.5 (21.5) (21) (20.5) (19.5) (19) (18) (17.5) (15.5) (13) (11) 0.17 0.21 0.37 0.63 0.78 1.56 1.93 (21) (20.5) (19.5) (19) (18.5) (17.5) (17.5) (15.5) (13) (10.5) 0.14 0.21 0.35 0.61 0.64 (20) (19.5) (19) (18) (18) (17) (17) (15.5) (13) (10.5) 0.14 0.21 0.35 0.59 0.61 0.82
Frequency 0.52 1.05 2.62 6.55 7.86 13.1 15.72 26.2 52.4 104.8
Gain 0.75 1.04 1.66 19.4 2,830 (22.5) (22) (21.5) (20) (19.5) (18) (17.5) (15.5) (13) (11)
Gain (18) (17.5) (17) (16) (16) (15.5) (15.5) (15) (12.5) (10.5)
(19) 0.14 (18.5) 0.21 (18) 0.35 (17) 0.59 (17) 0.61 (16.5) (16) 0.98 (15) (13) (10.5)
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AD7714
AD7714-3 OUTPUT NOISE
Table shows output noise effective resolution some typical notch frequencies AD7714-3 with fCLK 2.4576 while Table gives information fCLK MHz. numbers given bipolar input ranges with VREF +1.25 BUFFER These numbers typical generated analog input voltage numbers brackets each table effective resolution part (rounded nearest LSB). effective resolution device defined ratio output noise input full scale (i.e., VREF/GAIN). should noted that calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers times numbers while effective resolution numbers based peak-to-peak noise bits below effective resolution based noise quoted tables. output noise from part comes from sources. first electrical noise semiconductor devices used implementation modulator (device noise). Secondly, when analog input signal converted into digital domain, quantization noise added. device noise level largely independent frequency. quantization noise starts even lower level rises rapidly with increasing frequency become dominant noise source. Consequently, lower filter notch settings (below approximately fCLK 2.4576 below approximately fCLK MHz) tend device noise dominated while higher notch settings dominated quantization noise. Changing filter notch cutoff frequency quantization noise dominated region results more dramatic improvement noise performance than does device-noise dominated region shown Table Furthermore, quantization noise added after PGA, effective resolution largely independent gain higher filter notch frequencies. Meanwhile, device noise added and, therefore, effective resolution suffers little high gains lower notch frequencies. Additionally, device-noise dominated region, output noise largely independent reference voltage while quantization-noise dominated region, noise proportional value reference. possible post-filtering device improve output data rate given frequency also further reduce output noise. lower filter notch settings (below fCLK 2.4576 below fCLK MHz), missing codes performance device 24-bit level. higher settings, more codes will missed until notch setting fCLK 2.4576 (400 fCLK MHz), missing codes performance only guaranteed 12-bit level.
Table IIa. AD7714-3 Output Noise/Resolution Gain First Notch 2.4576 MHz, BUFFER Filter First Notch Data Rate Typical Output Noise (Effective Resolution Bits) Gain Gain Gain Gain Gain Gain 0.68 (21) (20) (19.5) (19) (19) (18.5) (18) (15.5) (13) (11) 0.29 0.56 0.89 (21) (20) (19.5) (19) (18.5) (18) (18) (15.5) (13) (11) 0.24 0.35 0.55 0.61 0.84 0.98 (20) (19.5) (19) (18.5) (18.5) (18) (18) (15.5) (13) (11) 0.22 0.33 0.49 0.58 (19.5) (19) (18.5) (18) (18) (17.5) (17) (15.5) (13) (10.5) 0.22 0.33 0.46 0.57 0.68 0.95 (18.5) (18) (17.5) (17) (17) (17) (16.5) (15) (13) (10.5) 0.22 0.33 0.46 0.55 0.67 0.69 0.88
Frequency 1.31 2.62 6.55 7.86 13.1 15.72 26.2 65.5
Gain 1.07 1.69 3.03 3.55 4.72 5.12 9.68 1410 (21) (20.5) (19.5) (19.5) (19) (19) (18) (16) (13) (11)
Gain (16.5) (16) (15.5) (15) (15) (15) (14.5) (13.5) (12.5) (10.5)
(17.5) 0.22 (17) 0.33 (16.5) 0.45 (16) 0.55 (16) 0.66 (16) 0.68 (15.5) (14.5) (12.5) (10.5)
Table IIb. AD7714-3 Output Noise/Resolution Gain First Notch MHz, BUFFER Filter First Notch Data Rate Typical Output Noise (Effective Resolution Bits) Gain Gain Gain Gain Gain Gain 0.58 0.74 1.33 (21) (20.5) (20) (19.5) (19) (18) (17.5) (15.5) (13) (11) 0.32 0.44 0.73 (21) (20.5) (20) (19) (19) (18) (17.5) (15.5) (13) (11) 0.21 0.35 0.88 0.93 (20.5) (20) (19) (18.5) (18.5) (18) (17) (15.5) (13) (11) 0.49 0.66 0.82 (19.5) (19) (18.5) (18) (17.5) (17) (16.5) (15.5) (13) (10.5) 0.49 0.57 0.69 0.73 0.95 (18.5) (18) (17.5) (17) (17) (16.5) (16.5) (15) (13) (10.5) 0.48 0.55 0.68 0.71 0.88
Frequency 0.52 1.05 2.62 6.55 7.86 13.1 15.72 26.2 52.4 104.8
Gain 0.86 1.26 1.68 3.82 4.88 14.7 1435 (21.5) (21) (20.5) (19.5) (19) (18) (17.5) (15.5) (13) (11)
Gain (16.5) (16) (15.5) (15) (15) (15) (14.5) (13.5) (12.5) (10.5)
(17.5) (17) (16.5) 0.47 (16) 0.55 (16) 0.66 (15.5) (15) (14.5) (12.5) (10.5)
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AD7714
BUFFERED MODE NOISE
Table shows typical output noise effective resolution some typical notch frequencies AD77145 with fCLK 2.4576 BUFFER Table gives information AD7714-3 again with fCLK 2.4576 BUFFER numbers given bipolar input ranges generated with differential analog input voltage AD7714-5, VREF voltage +2.5 while AD7714 VREF voltage +1.25 numbers brackets each table effective resolution part (rounded nearest LSB). effective resolution device defined ratio output noise input full scale (i.e., VREF/GAIN). should noted that calculated using peak-to-peak output noise numbers. Peak-to-peak noise numbers times numbers while effective resolution numbers based peak-to-peak noise bits below effective resolution based noise quoted tables.
Table III. AD7714-5 Buffered Mode Output Noise/Resolution 2.4576 Filter First Notch Data Rate Typical Output Noise (Effective Resolution Bits) Gain Gain Gain Gain Gain Gain 0.68 0.95 1700 (22) (21.5) (20.5) (20.5) (20) (19.5) (18.5) (15.5) (13.5) (10.5) 0.46 0.63 0.88 (21.5) (21) (20.5) (20) (19.5) (19.5) (18.5) (15.5) (13.5) (10.5) 0.26 0.41 0.75 0.87 (21) (20.5) (19.5) (19.5) (19) (19) (18) (15.5) (13) (10.5) 0.26 0.39 0.57 0.75 0.94 (20) (19.5) (19) (18.5) (18.5) (18.5) (18) (15.5) (13) (10.5) 0.26 0.36 0.57 0.72 0.94 0.97 (19) (18.5) (18) (17.5) (17.5) (17.5) (17) (15.5) (13) (10.5) 0.26 0.36 0.57 0.72 0.94 0.95 (18) (17.5) (17) (16.5) (16.5) (16.5) (16) (15) (13) (10.5)
Frequency 1.31 2.62 6.55 7.86 13.1 15.72 26.2 65.5
Gain 0.99 13.8 2860 (22.5) (21.5) (21) (20.5) (20) (19.5) (18.5) (16) (13.5) (11)
Gain 0.26 0.36 0.56 0.71 0.87 0.94 (17) (16.5) (16) (15.5) (15.5) (15.5) (15) (14) (13) (10.5)
Table AD7714-3 Buffered Mode Output Noise/Resolution 2.4576 Filter First Notch Data Rate Typical Output Noise (Effective Resolution Bits) Gain Gain Gain Gain Gain Gain 0.76 (20.5) (20.5) (19.5) (19) (18.5) (18.5) (18) (15.5) (13) (10.5) 0.34 (20) (20) (19) (19) (18.5) (18.5) (17.5) (15.5) (13) (10.5) 0.29 0.46 0.74 0.76 (20) (19.5) (18.5) (18.5) (18) (18) (17.5) (15.5) (13) (10.5) 0.29 0.45 0.63 0.68 0.92 (19) (18.5) (18) (18) (17.5) (17) (17) (15) (13) (10.5) 0.28 0.66 0.96 (18) (17.5) (17) (17) (16.5) (16.5) (16) (15) (13) (10.5) 0.26 0.66 0.89 0.96 (17) (16.5) (16) (16) (15.5) (15.5) (15) (14) (13) (10.5)
Frequency 1.31 2.62 6.55 7.86 13.1 15.72 26.2 65.5
Gain 1.16 1722 (21) (20.5) (19.5) (19.5) (19) (19) (18) (15.5) (13.5) (10.5)
Gain 0.26 0.66 0.89 0.96 (15.5) (15) (15) (14.5) (14.5) (14) (13.5) (12.5) (10.5)
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AD7714
ON-CHIP REGISTERS
AD7714 contains eight on-chip registers which accessed serial port part. first these Communications Register which controls channel selection, decides whether next operation read write operation also decides which register next read write operation accesses. communications part must start with write operation Communications Register. After power-on RESET, device expects write Communications Register. data written this register determines whether next operation part read write operation also determines which register this read write operation occurs. Therefore, write access other registers part starts with write operation Communications Register followed write selected register. read operation from other register part (including output data register) starts with write operation Communications Register followed read operation from selected register. communications register also controls channel selection DRDY status also available reading from Communications Register. second register Mode Register which determines calibration mode gain setting. third register labelled Filter High Register this determines word length, bipolar/unipolar operation contains upper bits filter selection word. fourth register labelled Filter Register contains lower bits filter selection word. fifth register Test Register which accessed when testing device. sixth register Data Register from which output data from part accessed. final registers allow access part's calibration registers. Zero Scale Calibration Register allows access zero scale calibration coefficients selected input channel while Full Scale Calibration Register allows access full scale calibration coefficients selected input channel. registers discussed more detail following sections.
Communications Register (RS2-RS0
Communications Register 8-bit register from which data either read which data written. communications part must start with write operation Communications Register. data written Communications Register determines whether next operation read write operation which register this operation takes place. Once subsequent read write operation selected register complete, interface returns where expects write operation Communications Register. This default state interface, power-up after RESET, AD7714 this default state waiting write operation Communications Register. situations where interface sequence lost, write operation sufficient duration (containing least serial clock cycles) takes place with high, AD7714 returns this default state. Table outlines designations Communications Register.
Table Communications Register
0/DRDY
0/DRDY
write operation, must written this that write operation Communications Register actually takes place. written this bit, part will clock subsequent bits register. will stay this location until written this bit. Once written this bit, next bits will loaded Communications Register. read operation, this provides status DRDY flag from part. status this same DRDY output pin. Register Selection Bits. three selection bits. three bits select which eight on-chip registers next read write operation takes place shown Table along with register size.
Table Register Selection
RS2-RS0
Register Communications Register Mode Register Filter High Register Filter Register Test Register Data Register Zero-Scale Calibration Register Full-Scale Calibration Register
Register Size Bits Bits Bits Bits Bits Bits Bits Bits Bits
Read/Write Select. This selects whether next operation read write operation selected register. indicates write cycle next operation appropriate register, while indicates read operation from appropriate register.
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AD7714
CH2-CH0 Channel Select. These three bits select channel either conversion access calibration coefficients outlined Table VII. There three pairs calibration registers part. fully differential mode, part three input channels each channel pair calibration registers. pseudo-differential mode, AD7714 five input channels with some input channel combinations sharing calibration registers. With CH2, logic part looks AIN6 input internally shorted itself. This used test method evaluate noise performance part with external noise sources. this mode, AIN6 input should connected external voltage within allowable common-mode range part. Power-On RESET status these bits 1,0,0 selecting differential pair AIN1 AIN2.
Table VII. Channel Selection
AIN(+) AIN1 AIN2 AIN3 AIN4 AIN1 AIN3 AIN5 AIN6
AIN(-) AIN6 AIN6 AIN6 AIN6 AIN2 AIN4 AIN6 AIN6
Type Pseudo Differential Pseudo Differential Pseudo Differential Pseudo Differential Fully Differential Fully Differential Fully Differential Test Mode
Calibration Register Pair Register Pair Register Pair Register Pair Register Pair Register Pair Register Pair Register Pair Register Pair
Mode Register (RS2-RS0 Power On/Reset Status:
Mode Register eight register from which data either read which data written. Table VIII outlines designations Mode Register.
Table VIII. Mode Register
FSYNC
Operating Mode Normal Mode; this normal mode operation device whereby device performing normal conversions. This default condition these bits after Power-On RESET. Self-Calibration; this activates self-calibration channel selected CH2, Communications Register. This step calibration sequence when complete part returns Normal Mode with MD2, returning DRDY output goes high when calibration initiated returns when this self-calibration complete valid word available data register. zero-scale calibration performed selected gain internally shorted (zeroed) inputs full-scale calibration performed selected gain internallygenerated VREF/Selected Gain. Zero-Scale System Calibration; this activates zero scale system calibration channel selected CH2, Communications Register. Calibration performed selected gain input voltage provided analog input during this calibration sequence. This input voltage should remain stable duration calibration. DRDY output goes high when calibration initiated returns when this zero-scale calibration complete valid word available data register. calibration, part returns Normal Mode with MD2, returning Full-Scale System Calibration; this activates full-scale system calibration selected input channel. Calibration performed selected gain input voltage provided analog input during this calibration sequence. This input voltage should remain stable duration calibration. Once again, DRDY output goes high when calibration initiated returns when this full-scale calibration complete valid word available data register. calibration, part returns Normal Mode with MD2, returning
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AD7714
Operating Mode (continued) System-Offset Calibration; this activates system-offset calibration channel selected CH2, Communications Register. This step calibration sequence when complete part returns Normal Mode with MD2, returning DRDY output goes high when calibration initiated returns when this system offset calibration complete valid word available data register. this calibration type, zero-scale calibration performed selected gain input voltage provided analog input during this calibration sequence. This input voltage should remain stable duration calibration. full-scale calibration performed selected gain internally generated VREF/Selected Gain. Background Calibration; this activates background calibration channel selected CH2, Communications Register. background calibration mode then AD7714 provides continuous self-calibration shorted (zeroed) inputs. This calibration takes place part conversion sequence, extending conversion time reducing word rate factor six. major advantage that user does have worry about recalibrating offset device when there change ambient temperature supplies. this mode, zero-scale calibration performed selected gain internally shorted (zeroed) inputs. calibrations interleaved with normal conversions calibration registers device automatically updated. Because background calibration does perform full-scale calibrations, self-calibration should performed before placing part background calibration mode. Zero-Scale Self-Calibration; this activates zero-scale self-calibration channel selected CH2, Communications Register. This zero-scale self-calibration performed selected gain internally shorted (zeroed) inputs. This step calibration sequence when complete part returns Normal Mode with MD2, returning DRDY output goes high when calibration initiated returns when this zero-scale self-calibration complete valid word available data register. Full-Scale Self-Calibration; this activates full-scale self-calibration channel selected CH2, Communications Register. This full-scale self-calibration performed selected gain internally-generated VREF/Selected Gain. This step calibration sequence when complete part returns Normal Mode with MD2, returning DRDY output goes high when calibration initiated returns when this full-scale selfcalibration complete valid word available data register. Gain Setting
Burn-Out Current. this turns on-chip burn-out currents. This default (PowerOn RESET) status this bit. this activates burn-out currents. When active, burnout currents connect selected analog input pair, AIN(+) input AIN(-) input. Filter Synchronization. When this high, nodes digital filter, filter control logic calibration control logic held reset state analog modulator also held reset state. When this goes low, modulator filter start process data valid word available 1/(output update rate), i.e., settling time filter. This FSYNC does affect digital interface does reset DRDY output low.
FSYNC
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AD7714
Filter Registers. Power On/Reset Status: Filter High Register: Hex. Filter Register: Hex.
There 8-bit Filter Registers AD7714 from which data either read which data written. Tables outline designations Filter Registers.
Table Filter High Register (RS2-RS0
ZERO
FS11
FS10
Table Filter Register (RS2-RS0
Bipolar/Unipolar Operation. this selects Bipolar Operation. This default (Power-On RESET) status this bit. this selects unipolar operation. Word Length. this selects 16-bit word length when reading from data register (i.e., DRDY returns high after serial clock cycles read operation). This default (Power-On RESET) status this bit. this selects 24-bit word length. Current Boost. this reduces current taken analog front end. When part operated with fCLK gains with fCLK 2.4576 MHz, this should reduce current drawn from AVDD, although device will operate just well with this When AD7714 operated gains with fCLK 2.4576 MHz, this must ensure correct operation device. Power-On RESET status this ensure correct operation part, must written this bit. Filter Selection. on-chip digital filter provides Sinc3 (Sinx/x)3 filter response. bits data programmed into these bits determine filter cut-off frequency, position first notch filter data rate part. association with gain selection, also determines output noise (and hence effective resolution) device. first notch filter occurs frequency determined relationship: filter first notch frequency (fCLK IN/128)/code where code decimal equivalent code bits FS11 range 4,000. With nominal fCLK 2.4576 MHz, this results first notch frequency range from 1.01 kHz. ensure correct operation AD7714, value code loaded these bits must within this range. Failure this will result unspecified operation device. Changing filter notch frequency, well selected gain, impacts resolution. Tables through show effect filter notch frequency gain effective resolution AD7714. output data rate effective conversion time) device equal frequency selected first notch filter. example, first notch filter selected then word available rate every first notch kHz, word available every settling time filter full-scale step input change worst case 1/(output data rate). example, with first filter notch settling time filter full-scale step input change max. This settling time reduced 1/(output data rate) synchronizing step input change reset digital filter. other words, step input takes place with SYNC input FSYNC high, settling time will 1/(output data rate) from when SYNC returns high FSYNC returns low. change channel takes place, settling time 1/(output data rate) regardless SYNC FSYNC status part issues internal SYNC command when requested change channels. frequency determined programmed first notch frequency according relationship: filter -3dB frequency 0.262 filter first notch frequency.
ZERO FS11
Test Register (RS2-RS0
part contains Test Register which used testing device. user advised change status bits this register from default (Power-On RESET) status part will placed test modes will operate correctly. part enters test modes, exercising RESET will exit part from mode. alternative scheme getting part test modes, reset interface writing successive part then write Test Register. REV. -15-
AD7714
Data Register (RS2-RS0
Data Register part read-only register which contains most up-to-date conversion result from AD7714. register programmed either 16-bits 24-bits wide, determined status Mode Register. Communications Register data sets part write operation this register, write operation must actually take place order return part where expecting write operation Communications Register (the default state interface). However, bits data written part will ignored AD7714.
Zero-Scale Calibration Register (RS2-RS0 Power On/Reset Status: 1F4000
AD7714 contains three zero-scale calibration registers, labelled Zero-Scale Calibration Register Zero Scale Calibration Register three registers totally independent each other such that fully differential mode there zero-scale register each input channels. Each these registers 24-bit read/write register and, when writing registers, bits must written; otherwise data will transferred register. register used conjunction with associated full-scale calibration register form register pair. These register pairs associated with input channel pairs outlined Table VII. While part allow access these registers over digital interface, part itself longer access register coefficients correctly scale output data. result, there possibility that after accessing calibration registers (either read write operation) first output data read from part contain incorrect data. addition, read write operation calibration register should attempted while calibration progress. These eventualities avoided taking either SYNC input FSYNC Mode Register high before calibration register operation taking them either high respectively after operation complete.
Full-Scale Calibration Register (RS2-RS0 Power On/Reset Status: 5761AB
AD7714 contains three full-scale calibration registers, labelled Full-Scale Calibration Register Full-Scale Calibration Register three registers totally independent each other such that fully differential mode there full-scale register each input channels. Each these registers 24-bit read/write register and, when writing registers, bits must written, otherwise data will transferred register. register used conjunction with associated zero-scale calibration register form register pair. These register pairs associated with input channel pairs outlined Table VII. While part allow access these registers over digital interface, part itself longer access coefficients correctly scale output data. result, there possibility that after accessing calibration registers (either read write operation) first output data read from part contain incorrect data. addition, read write operation calibration register should attempted while calibration progress.These eventualities avoided taking either SYNC input FSYNC Mode Register high before calibration register operation taking them either high respectively after operation complete.
CALIBRATION OPERATION
AD7714 contains number calibration options outlined previously. Table summarizes calibration types, operations involved duration operations. There methods determining calibration. first monitor when DRDY returns sequence. DRDY only indicates when sequence complete also that part valid sample data register. This valid sample result normal conversion which follows calibration sequence. second method determining when calibration complete monitor MD2, bits Mode Register. When these bits return following calibration command, indicates that calibration sequence complete. This method does give indication there being valid result data register. However, gives earlier indication that calibration complete than DRDY. time when Mode Bits (MD2, MD0) return represents duration calibration. sequence when DRDY goes also includes normal conversion pipeline delay, (2000 tCLK IN), correctly scale results this first conversion. time both methods given table.
Table Calibration Operations
Calibration Type Self Calibration System Calibration System Calibration System-Offset Calibration Background Calibration Self Calibration Self Calibration MD2, MD1, Calibration Sequence Internal Selected Gain Internal Selected Gain Selected Gain Selected Gain Selected Gain Internal Selected Gain Internal Selected Gain Normal Conversion Internal Selected Gain Internal Selected Gain Duration Mode Bits 1/Output Rate 1/Output Rate 1/Output Rate 1/Output Rate Bits Reset 1/Output Rate 1/Output Rate Duration DRDY 1/Output Rate 1/Output Rate 1/Output Rate 1/Output Rate 1/Output Rate 1/Output Rate 1/Output Rate
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AD7714
CIRCUIT DESCRIPTION
AD7714 sigma-delta converter with on-chip digital filtering, intended measurement wide dynamic range, frequency signals such those weigh-scale, pressure transducer, industrial control process control applications. contains sigma-delta charge-balancing) ADC, calibration microcontroller with on-chip static RAM, clock oscillator, digital filter bidirectional serial communications port. part consumes only power supply current features standby mode which requires only making ideal battery-powered loop-powered instruments. part comes versions, AD7714-5 which specified operation from nominal analog supply (AVDD) AD7714-3 which specified operation from nominal +3.3 analog supply. Both versions operated with digital supply (DVDD) voltage either +3.3 part contains three programmable-gain fully differential analog input channels which reconfigured five pseudodifferential inputs. gain range channels from allowing part accept unipolar signals between +2.5 bipolar mode, part handles genuine bipolar signals quasi-bipolar signals when reference input voltage equals +2.5 With reference voltage +1.25 input ranges from +1.25 unipolar mode while bipolar mode, part handles genuine bipolar signals quasi-bipolar signals 1.25 part employs sigma-delta conversion technique realize bits missing codes performance. sigmadelta modulator converts sampled input signal into digital pulse train whose duty cycle contains digital information.
programmable gain function analog input also incorporated this sigma-delta modulator with input sampling frequency modulator being modified give higher gains. sinc3 digital low-pass filter processes output sigma-delta modulator updates output register rate determined first notch frequency this filter. output data read from serial port randomly periodically rate output register update rate. first notch this digital filter, frequency output rate programmed filter high filter registers. With master clock frequency 2.4576 MHz, programmable range this first notch frequency output rate from 1.01 giving programmable range frequency 1.26 basic connection diagram part shown Figure This shows both AVDD DVDD pins AD7714 being driven from analog supply. Some applications will have AVDD DVDD driven from separate supplies. connection diagram shown, AD7714's analog inputs configured three fully differential inputs. part unbuffered mode these analog inputs. AD780, precision +2.5 reference, provides reference source part. digital side, part configured three-wire operation with tied DGND. quartz crystal ceramic resonator provides master clock source part. necessary connect capacitors crystal resonator ensure that does oscillate overtones fundamental operating frequency. values capacitors will vary depending manufacturer's specifications.
ANALOG SUPPLY
10µF
0.1µF
0.1µF
AVDD DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT AIN1 AIN2 AIN3 AIN4 AIN5 AIN6
DVDD DRDY DOUT SCLK RECEIVE (READ) SERIAL DATA SERIAL CLOCK DATA READY
AD7714
ANALOG SUPPLY VOUT ANALOG GROUND DIGITAL GROUND AGND DGND RESET SYNC STANDBY IN(+) 10µF 0.1µF MCLK IN(-) MCLK BUFFER
AD780
CRYSTAL CERAMIC RESONATOR
Figure Basic Connection Diagram
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AD7714
ANALOG INPUT Analog Input Ranges
AD7714 contains analog input pins (labelled AIN1 AIN6) which configured either three fully differential input channels five pseudo-differential input channels. Bits CH0, Communications Register configure analog input arrangement channel selection outlined previously Table VII. input pairs (either differential pseudo-differential) provide programmable-gain, input channels which handle either unipolar bipolar input signals. should noted that bipolar input signals referenced respective AIN(-) input input pair. unbuffered mode, common mode range these inputs from AGND AVDD provided that absolute value analog input voltage lies between AGND AVDD This means that unbuffered mode part handle both unipolar bipolar input ranges gains. buffered mode, analog inputs handle much larger source impedances, absolute input voltage range restricted between AGND AVDD which also places restrictions common-mode range. This means that buffered mode there some restrictions allowable gains bipolar input ranges. Care must taken setting common-mode voltage input voltage range that above limits exceeded, otherwise there will degradation linearity performance. unbuffered mode, analog inputs look directly into input sampling capacitor, CSAMP. input leakage current this unbuffered mode maximum Version) maximum Version). result, analog inputs dynamic load which switched input sample rate (see Figure This sample rate depends master clock frequency selected gain. CSAMP charged AIN(+) discharged AIN(-) every input sample cycle. effective on-resistance switch, RSW, typically
CSAMP must charged through through external source impedances every input sample cycle. Therefore, unbuffered mode, source impedances mean longer charge time CSAMP this result gain errors part. Table shows allowable external resistance/capacitance values, unbuffered mode, such that gain error 16-bit level introduced part. Table XIII shows allowable external resistance/capacitance values, once again unbuffered mode, such that gain error 20-bit level introduced.
Table XII. External Combination 16-Bit Gain Error (Unbuffered Mode Only) Gain 8-128 177.2 82.8 35.2 External Capacitance (pF) 90.6 44.2 21.2 54.2 26.4 12.6 14.6 1.58 1000 1.94 5000 1.12
Table XIII. External Combination 20-Bit Gain Error (Unbuffered Mode Only) Gain 8-128 63.6 26.8 External Capacitance (pF) 33.8 40.8 10.4 1000 1.34 5000
AIN(+) TYP) HIGH IMPEDANCE
buffered mode, analog inputs look into high impedance inputs stage on-chip buffer amplifier. CSAMP charged this buffer amplifier such that source impedances affect charging CSAMP. This buffer amplifier offset leakage current this buffered mode, large source impedances result offset voltage developed across source impedance gain error.
Input Sample Rate
AIN(-)
CSAMP (7pF VBIAS SWITCHING FREQUENCY DEPENDS fCLKIN SELECTED GAIN
Figure Unbuffered Analog Input Structure
modulator sample frequency AD7714 remains fCLK IN/128 (19.2 fCLK 2.4576 MHz) regardless selected gain. However, gains greater than achieved combination multiple input samples modulator cycle scaling ratio reference capacitor input capacitor. result multiple sampling, input sample rate device varies with selected gain (see Table XIV). buffered mode, input buffered before input sampling capacitor. unbuffered mode, where analog input looks directly into sampling capacitor, effective input impedance 1/CSAMP.fs where CSAMP input sampling capacitance input sample rate.
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AD7714
Table XIV. Input Sampling Frequency Gain
Gain
Input Sampling Freq (fs) fCLK IN/64 (38.4 fCLK 2.4576 MHz) fCLK IN/64 (76.8 fCLK 2.4576 MHz) fCLK IN/64 (153.6 fCLK 2.4576 MHz) fCLK IN/64 (307.2 fCLK 2.4576 MHz) fCLK IN/64 (307.2 fCLK 2.4576 MHz) fCLK IN/64 (307.2 fCLK 2.4576 MHz) fCLK IN/64 (307.2 fCLK 2.4576 MHz) fCLK IN/64 (307.2 fCLK 2.4576 MHz)
IN(-)), specified operation +2.5 AD7714-5 +1.25 AD7714-3. part functional with VREF voltages down with degraded performance output noise will, terms size, larger. IN(+) must always greater than IN(-) correct operation AD7714. Both reference inputs provide high impedance, dynamic load similar analog inputs unbuffered mode. maximum input leakage current over temperature source resistance result gain errors part. this case, sampling switch resistance reference capacitor (CREF) varies with gain. sample rate reference inputs fCLK IN/64 does vary with gain. gains CREF gain gain 4.25 gain 3.625 gain 128, 3.3125 output noise performance outlined Tables through analog input unaffected noise reference. obtain same noise performance shown noise tables over full input range requires noise reference source AD7714. reference noise bandwidth interest excessive, will degrade performance AD7714. applications where excitation voltage bridge transducer analog input also derives reference voltage part, effect noise excitation voltage will removed application ratiometric. Recommended reference voltage sources AD7714-5 include AD780, REF43 REF192 while recommended reference sources AD7714-3 include AD589 AD1580. generally recommended decouple output these references further reduce noise level.
DIGITAL FILTERING
AD7714 contains currents, source current from AVDD AIN(+) sink from AIN(-) AGND. currents either both depending Mode Register. These currents used checking that transducer burnt-out gone open circuit before attempting take measurements that channel. currents turned allowed flow transducer, measurement input voltage analog input taken voltage measured full scale then indicates that transducer gone open-circuit; voltage measured zero, indicates that transducer gone short-circuit. normal operation, these burn-out currents turned writing bit. source current work correctly, applied voltage AIN(+) should within AVDD. sink current work correctly, applied voltage AIN(-) input should within AGND.
Bipolar/Unipolar Inputs
Burn-Out Current
analog inputs AD7714 accept either unipolar bipolar input voltage ranges. Bipolar input ranges imply that part handle negative voltages analog inputs, since analog input cannot more negative than ensure correct operation part. input channels either fully differential pseudo-differential (all other channels referenced AIN6). either case, input channels arranged pairs with AIN(+) AIN(-). result, voltage which unipolar bipolar signals AIN(+) input referenced voltage respective AIN(-) input. example, AIN(-) +2.5 AD7714 configured unipolar operation with gain VREF +2.5 input voltage range AIN(+) input +2.5 +3.75 AIN(-) +2.5 AD7714 configured bipolar mode with gain VREF +2.5 analog input range AIN(+) input +1.25 +3.75 (i.e., 1.25 AIN(-) AGND, part cannot configured bipolar ranges excess Bipolar unipolar options chosen programming Filter High Register. This programs selected channel either unipolar bipolar operation. Programming channel either unipolar bipolar operation does change input signal conditioning; simply changes data output coding points transfer function where calibrations occur.
REFERENCE INPUT
AD7714 contains on-chip low-pass digital filter which processes output part's sigma-delta modulator. Therefore, part only provides analog-to-digital conversion function also provides level filtering. There number system differences when filtering function provided digital domain rather than analog domain user should aware these. First, since digital filtering occurs after A-to-D conversion process, remove noise injected during conversion process. Analog filtering cannot this. Also, digital filter made programmable more readily than analog filter. Depending digital filter design, this gives user capability programming cutoff frequency output update rate. other hand, analog filtering remove noise superimposed analog signal before reaches ADC. Digital filtering cannot this noise peaks riding signals near full scale have potential saturate analog modulator digital filter, even though average value signal within limits. alleviate this problem, AD7714 overrange headroom built into sigma-delta modulator digital filter which allows overrange excursions above analog input range. noise signals larger than this, consideration should given analog input filtering, reducing input channel voltage that full scale half that analog input channel full scale. This will provide overrange capability greater than 100% expense reducing dynamic range (50%).
AD7714's reference inputs, IN(+) IN(-), provide differential reference input capability. commonmode range these differential inputs from AGND AVDD. nominal reference voltage, VREF (REF IN(+) REV.
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AD7714
addition, digital filter does provide rejection integer multiples digital filter's sample frequency. However, input sampling part provides attenuation multiples digital filter's sampling frequency that unattenuated bands actually occur around multiples input sampling frequency defined Table XIV). Thus, unattenuated bands occur (where these frequencies, there frequency bands, wide cutoff frequency digital filter) either side where noise passes unattenuated output.
Filter Characteristics
FS11 does alter profile filter response; changes frequency notches outlined Filter Registers section. output update first notch correspond determined relationship: Output Rate fCLK IN/(N.128) where decimal equivalent word loaded FS11 bits Filter Registers while frequency determined relationship: frequency 0.262 filter first notch frequency filter provides linear phase response with group delay determined Group Delay -3.(N.f/fMOD where decimal equivalent word loaded FS11 bits Filter Registers fMOD fCLK IN/128. Since AD7714 contains this on-chip, low-pass filtering, there settling time associated with step function inputs data output will invalid after step change until settling time elapsed. settling time depends upon output rate chosen filter. settling time filter full-scale step input times output data period. synchronized step input (using SYNC FSYNC functions) settling time times output data period. When changing channels part, change from channel other synchronized output settling time also times output data period. Thus, switching between channels, output data register updated until settling time filter elapsed.
Post-Filtering
AD7714's digital filter low-pass filter with (sinx/x)3 response (also called sinc3). transfer function this filter described z-domain
H(z) frequency domain
Figure shows filter frequency response cutoff frequency 2.62 which corresponds first filter notch frequency plot shown from This response repeated either side input sampling frequency either side multiples input sampling frequency.
GAIN
-100 -120 -140 -160 -180 -200 -220 -240 FREQUENCY
on-chip modulator provides samples 19.2 output rate with fCLK 2.4576 MHz. on-chip digital filter decimates these samples provide data output rate which corresponds programmed output rate filter. Since output data rate higher than Nyquist criterion, output rate given bandwidth will satisfy most application requirements. However, there some applications which require higher data rate given bandwidth noise performance. Applications which need this higher data rate will require some post-filtering following part's digital filter. example, required bandwidth 7.86 required update rate data taken from AD7714 rate giving bandwidth 26.2 Post-filtering applied this reduce bandwidth output noise, 7.86 bandwidth level, while maintaining output rate Post-filtering also used reduce output noise from device bandwidths below 1.26 gain bandwidth 1.26 output noise This essentially device noise white noise since input chopped, noise primarily flat frequency response. reducing bandwidth below 1.26 noise resultant passband reduced. reduction bandwidth factor results reduction approximately 1.25 output noise. This additional filtering will result longer settling time.
Figure Frequency Response AD7714 Filter
response filter similar that averaging filter with sharper roll-off. output rate digital filter corresponds with positioning first notch filter's frequency response. Thus, plot Figure where output rate first notch filter notches this (sinx/x)3 filter repeated multiples first notch. filter provides attenuation better than these notches. example given, first notch there will notches (and hence >100 rejection) both cutoff frequency digital filter determined value loaded bits FS11 Filter High Filter Registers. Programming different cutoff frequency
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AD7714
ANALOG FILTERING
digital filter does provide rejection integer multiples input sampling frequency, outlined earlier. However, AD7714's high oversampling ratio, these bands occupy only small fraction spectrum most broadband noise filtered. This means that analog filtering requirements front AD7714 considerably reduced versus conventional converter with on-chip filtering. addition, because part's common-mode rejection performance extends several kHz, common mode noise this frequency range will substantially reduced. Depending application, however, necessary provide attenuation prior AD7714 order eliminate unwanted frequencies from these bands which digital filter will pass. also necessary some applications provide analog filtering front AD7714 ensure that differential noise signals outside band interest saturate analog modulator. passive components placed front AD7714, unbuffered mode, care must taken ensure that source impedance enough introduce gain errors system. This significantly limits amount passive antialiasing filtering which provided front AD7714 when used unbuffered mode. However, when part used buffered mode, large source impedances will simply result small offset error source resistance will cause offset error less than µV). Therefore, system requires significant source impedances provide passive analog filtering front AD7714, recommended that part operated buffered mode.
CALIBRATION
value which, when normalized, subtracted from conversion results. full-scale calibration register contains value which, when normalized, multiplied conversion results. offset calibration coefficient subtracted from result prior multiplication full-scale coefficient. This means that full-scale coefficient effectively span gain coefficient. AD7714 offers self-calibration, system calibration background calibration facilities. full calibration occur selected channel, on-chip microcontroller must record modulator output different input conditions. These "zero-scale" "full-scale" points. These points derived performing conversion different input voltages provided input modulator during calibration. result, accuracy calibration only good noise level which part provides normal mode. result "zero-scale" calibration conversion stored Zero Scale Calibration Register appropriate channel. result "full-scale" calibration conversion stored Full-Scale Calibration Register appropriate channel. With these readings, microcontroller calculate offset gain slope input output transfer function converter. Internally, part works with bits resolution determine conversion result either bits bits.
Self-Calibration
AD7714 provides number calibration options which programmed MD2, bits Mode Register. different calibration options outlined Mode Register Calibration Sequences sections. calibration cycle initiated time writing these bits Mode Register. Calibration AD7714 removes offset gain errors from device. calibration routine should initiated device whenever there change ambient operating temperature supply voltage. should also initiated there change selected gain, filter notch bipolar/unipolar input range. AD7714 gives user access on-chip calibration registers allowing microprocessor read device's calibration coefficients also write calibration coefficients part from prestored values E2PROM. This gives microprocessor much greater control over AD7714's calibration procedure. also means that user verify that device performed calibration correctly comparing coefficients after calibration with prestored values E2PROM. values these calibration registers 24-bit wide. addition, span offset part adjusted user. There significant variation value these coefficients across different output update rates, gains unipolar/ bipolar operation. Internally AD7714, these coefficients normalized before being used scale words coming digital filter. offset calibration register contains
self-calibration initiated AD7714 writing appropriate values MD2, bits Mode Register. self-calibration mode with unipolar input range, zero-scale point used determining calibration coefficients with inputs differential pair internally shorted part (i.e., AIN(+) AIN(-) Internal Bias Voltage). selected gain bits Mode Register) this zero-scale calibration conversion. full-scale calibration conversion performed selected gain internally-generated voltage VREF/ Selected Gain. duration time calibration 1/Output Rate. This made 1/Output Rate zero-scale calibration 1/Output Rate full-scale calibration. this time MD2, bits Mode Register return This gives earliest indication that calibration sequence complete. DRDY line goes high when calibration initiated does return until there valid word data register. duration time from calibration command being issued DRDY going 1/Output Rate. This made 1/Output Rate zero-scale calibration, 1/Output Rate full-scale calibration 1/Output Rate conversion analog input. DRDY before goes during) calibration command write Mode Register, take modulator cycle (MCLK IN/128) before DRDY goes high indicate that calibration progress. Therefore, DRDY should ignored modulator cycle after last calibration command written Mode Register. bipolar input ranges self-calibrating mode, sequence very similar that just outlined. this case, points exactly same above since part configured bipolar operation, output code zero differential input 800000 24-bit mode.
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part also offers Self-Calibration Self-Calibration options. these cases, part performs just zero-scale full-scale calibration respectively full calibration part. full-scale calibration should carried unless part contains valid zero-scale coefficients. These calibrations initiated AD7714 writing appropriate values Self-Calibration Self Calibration) MD2, bits Mode Register. zero-scale full-scale calibration exactly same that described full self-calibration. these cases, duration calibration 1/Output Rate. this time MD2, bits Mode Register return This gives earliest indication that calibration equence complete. DRDY line goes high when calibration initiated does return until there valid word data register. time from calibration command being issued DRDY going 1/Output Rate. This made 1/Output Rate zero-scale full-scale calibration 1/Output Rate conversion analog input. DRDY before goes during) calibration command write Mode Register, take modulator cycle (MCLK IN/128) before DRDY goes high indicate that calibration progress. Therefore, DRDY should ignored modulator cycle after last calibration command written Mode Register. fact that self-calibration performed step calibration offers another feature. After sequence full self calibration been completed, additional offset gain calibrations performed themselves adjust part's zero point gain. Calibrating parameters, either offset gain, will affect other parameter.
System Calibration
conversion should zero-scale reading. DRDY before goes during) calibration command write Mode Register, take modulator cycle (MCLK IN/128) before DRDY goes high indicate that calibration progress. Therefore, DRDY should ignored modulator cycle after last calibration command written Mode Register. After zero-scale point calibrated, full-scale point applied second step calibration process initiated again writing appropriate values MD2, MD0. Again full-scale voltage must before calibration initiated, must remain stable throughout calibration step. full-scale system calibration performed selected gain. duration calibration 1/Output Rate. this time, MD2, bits Mode Register return This gives earliest indication that calibration sequence complete. DRDY line goes high when calibration initiated does return until there valid word data register. time from calibration command being issued DRDY going 1/Output Rate. This made 1/Output Rate full-scale system calibration 1/Output Rate conversion analog input. This conversion analog input same voltage full-scale system calibration and, therefore, resultant word data register from this conversion should full-scale reading. DRDY before goes during) calibration command write Mode Register, take modulator cycle (MCLK IN/128) before DRDY goes high indicate that calibration progress. Therefore, DRDY should ignored modulator cycle after last calibration command written Mode Register. unipolar mode, system calibration performed between endpoints transfer function; bipolar mode, performed between midscale (zero differential voltage) positive full scale. fact that system calibration step calibration offers another feature. After sequence full system calibration been completed, additional offset gain calibrations performed themselves adjust system zero reference point system gain. Calibrating parameters, either system offset system gain, will affect other parameter. full-scale calibration should carried unless part contains valid zero-scale coefficients. System calibration also used remove errors from source impedances analog input when part used unbuffered mode. simple antialiasing filter front introduce gain error analog input voltage system calibration used remove this error.
System calibration allows AD7714 compensate system gain offset errors well internal errors. System calibration performs same slope factor calculations selfcalibration uses voltage values presented system inputs zero- full-scale points. Full System calibration requires step process, System Calibration followed System Calibration. full system calibration, zero-scale point must presented converter first. must applied converter before calibration step initiated remain stable until step complete. Once system zero scale been analog input, System Calibration then initiated writing appropriate values MD2, bits Mode Register. zero-scale system calibration performed selected gain. duration calibration 1/Output Rate. this time, MD2, bits Mode Register return This gives earliest indication that calibration sequence complete. DRDY line goes high when calibration initiated does return until there valid word data register. time from calibration command being issued DRDY going 1/Output Rate. This made 1/Output Rate zero-scale system calibration 1/Output Rate conversion analog input. This conversion analog input same voltage zero-scale system calibration and, therefore, resultant word data register from this
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AD7714
System-Offset Calibration
System-offset calibration variation both system calibration self-calibration. this case, zero-scale point determined exactly same System Calibration. system zero-scale point presented inputs converter. This must applied converter before calibration step initiated remain stable until step complete. Once system zero scale been System-Offset Calibration then initiated writing appropriate values MD2, bits Mode Register. zero-scale system calibration performed selected gain. full-scale calibration performed exactly same Self Calibration. full-scale calibration conversion performed selected gain internally generated voltage VREF/Selected Gain. This step calibration sequence time calibration 1/Output Rate. this time, MD2, bits Mode Register return This gives earliest indication that calibration sequence complete. DRDY line goes high when calibration initiated does return until there valid word data register. duration time from calibration command being issued DRDY going Output Rate. This made 1/Output Rate zeroscale system calibration, 1/Output Rate full-scale self-calibration 1/Output Rate conversion analog input. This conversion analog input same voltage zero-scale system calibration and, therefore, resultant word data register from this conversion should zero-scale reading. DRDY before goes during) calibration command write Mode Register, take modulator cycle (MCLK IN/128) before DRDY goes high indicate that calibration progress. Therefore, DRDY should ignored modulator cycle after last calibration command written Mode Register. unipolar mode, system-offset calibration performed between end-points transfer function; bipolar mode, performed between midscale positive full scale.
Background Calibration
Because background calibration does perform full-scale calibrations, self-calibration should performed before placing part background calibration mode. Removal offset drift this mode leaves gain drift only source error removed from part. typical gain drift AD7714 with temperature ppm/°C. SYNC input FSYNC should exercised when part background calibration mode.
Span Offset Limits
Whenever system calibration mode used, there limits amount offset span which accommodated. overriding requirement determining amount offset gain which accommodated part requirement that positive full-scale calibration limit 1.05 VREF/GAIN. This allows input range above nominal range. in-built headroom AD7714's analog modulator ensures that part will still operate correctly with positive full-scale voltage which beyond nominal. range input span both unipolar bipolar modes minimum value VREF/GAIN maximum value VREF/GAIN. However, span (which difference between bottom AD7714's input range input range) take into account limitation positive full-scale voltage. amount offset which accommodated depends whether unipolar bipolar mode being used. Once again, offset take into account limitation positive full-scale voltage. unipolar mode, there considerable flexibility handling negative (with respect AIN(-)) offsets. both unipolar bipolar modes, range positive offsets which handled part depends selected span. Therefore, determining limits system zero-scale full-scale calibrations, user ensure that offset range plus span range does exceed 1.05 VREF/GAIN. This best illustrated looking examples. part used unipolar mode with required span VREF/GAIN, then offset range which system calibration handle from -1.05 VREF/GAIN +0.25 VREF/ GAIN. part used unipolar mode with required span VREF/GAIN, then offset range which system calibration handle from -1.05 VREF/GAIN +0.05 VREF/GAIN. Similarly, part used unipolar mode required remove offset VREF/GAIN, then span range which system calibration handle 0.85 VREF/GAIN. part used bipolar mode with required span VREF/GAIN, then offset range which system calibration handle from -0.65 VREF/GAIN +0.65 VREF/ GAIN. part used bipolar mode with required span VREF/GAIN, then offset range which system calibration handle from -0.05 VREF/GAIN +0.05 VREF/ GAIN. Similarly, part used bipolar mode required remove offset VREF/GAIN, then span range which system calibration handle 0.85 VREF/GAIN.
AD7714 also offers background calibration mode where part interleaves calibration procedure with normal conversion sequence. background calibration mode, part provides continuous zero-scale self-calibrations; does provide full-scale calibrations. zero-scale point used determining calibration coefficients this mode exactly same Self-Calibration. background calibration mode invoked writing MD2, MD1, bits Mode Register. When invoked, background calibration mode performs zero-scale self calibration after every output update this reduces output data rate AD7714 factor six. advantage that part continually performing offset calibrations automatically updating zero-scale calibration coefficients. result, effects temperature drift, supply sensitivity time drift zero-scale errors automatically removed. When background calibration mode turned part will remain this mode until bits MD2, Mode Register changed. REV.
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AD7714
Power-Up Calibration
power-up, AD7714 performs internal reset which sets contents internal registers known state. There default values loaded registers after power-on reset. default values contain nominal calibration coefficients calibration registers. However, ensure correct calibration device calibration routine should performed after power-up. power dissipation temperature drift AD7714 warm-up time required before initial calibration performed. However, external reference being used, this reference must have stabilized before calibration initiated. Similarly, clock source part generated from crystal resonator across MCLK pins, start-up time oscillator circuit should elapse before calibration initiated part (see below).
USING AD7714 Clocking Oscillator Circuit
When operating with clock frequency 2.4576 MHz, there appreciable difference DVDD current between externally applied clock crystal resonator when operating with DVDD With DVDD fCLK 2.4576 MHz, typical DVDD current increases crystal/resonator supplied clock versus externally applied clock. values crystals resonators this frequency tend result there tends little difference between different crystal resonator types. When operating with clock frequency MHz, value different crystal types varies significantly. result, DVDD current drain varies across crystal types. When using crystal with when using ceramic resonator, increase typical DVDD current over externallyapplied clock with DVDD with DVDD When using crystal with increase typical DVDD current over externally applied clock again with DVDD with DVDD on-chip oscillator circuit also start-up time associated with before oscillating correct frequency correct voltage levels. typical start time circuit with DVDD with DVDD supplies, depending loading capacitances MCLK pins, feedback resistor required across crystal resonator order keep start times around duration. AD7714's master clock appears MCLK device. maximum recommended load this CMOS load. When using crystal ceramic resonator generate AD7714's clock, desirable then this clock clock source system. this case, recommended that MCLK signal buffered with CMOS buffer before being applied rest circuit.
System Synchronization
AD7714 requires master clock input, which external CMOS compatible clock signal applied MCLK with MCLK left unconnected. Alternatively, crystal ceramic resonator correct frequency connected between MCLK MCLK which case clock circuit will function oscillator, providing clock source part. input sampling frequency, modulator sampling frequency, frequency, output update rate calibration time directly related master clock frequency, fCLK Reducing master clock frequency factor will halve above frequencies update rate double calibration time. current drawn from DVDD power supply also directly related fCLK Reducing fCLK factor will halve DVDD current will affect current drawn from AVDD power supply. Using part with crystal ceramic resonator between MCLK MCLK pins generally causes more current drawn from DVDD than when part clocked from driven clock signal MCLK pin. This because on-chip oscillator circuit active case crystal ceramic resonator. Therefore, lowest possible current AD7714 achieved with externally applied clock MCLK with MCLK unconnected unloaded. amount additional current taken oscillator depends number factors-first, larger value capacitor placed MCLK MCLK pins, then larger DVDD current consumption AD7714. Care should taken exceed capacitor values recommended crystal ceramic resonator manufacturers avoid consuming unnecessary DVDD current. Typical values recommended crystal ceramic resonator manufacturers range capacitor values MCLK MCLK kept this range they will result excessive DVDD current. Another factor that influences DVDD current effective series resistance (ESR) crystal which appears between MCLK MCLK pins AD7714. general rule, lower value then lower current taken oscillator circuit.
SYNC input FSYNC bit) allows user reset modulator digital filter without affecting setup conditions part. This allows user start gathering samples analog input from known point time, i.e., rising edge SYNC when written FSYNC. SYNC input also used allow other functions. multiple AD7714s operated from common master clock, they synchronized update their output registers simultaneously. falling edge SYNC input written FSYNC Mode Register) resets digital filter analog modulator places AD7714 into consistent, known state. While SYNC input FSYNC high), AD7714 will maintained this state. rising edge SYNC when written FSYNC bit), modulator filter taken this reset state next clock edge part starts gather input samples again. system using multiple AD7714s, common signal their SYNC inputs will synchronize their operation. This would normally done after each AD7714 performed calibration calibration coefficients loaded output updates will then synchronized with maximum possible difference between output updates individual AD7714s being MCLK cycle.
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AD7714
SYNC input also used start convert command allowing AD7714 operated conventional converter fashion. this mode, rising edge SYNC starts conversion falling edge DRDY indicates when conversion complete. disadvantage this scheme that settling time filter taken into account every data register update. This means that rate which data register updated times slower rate this mode. Since SYNC input FSYNC bit) resets digital filter, full settling-time 1/Output Rate elapse before there word loaded output register part. DRDY signal when SYNC returns high FSYNC goes DRDY signal will reset high SYNC FSYNC) command. This because AD7714 recognizes that there word data register which been read. DRDY line will stay until update data register takes place which time will high tCLK before returning again. read from data register resets DRDY signal high will return until settling time filter elapsed (from SYNC FSYNC command) there valid word data register. DRDY line high when SYNC FSYNC) command issued, DRDY line will return until settling time filter elapsed.
Reset Input
word data register), data register read while part standby. this read operation, DRDY will reset high normal. Placing part standby mode, reduces total current typical when part operated from external master clock provided this master clock stopped. external clock continues standby mode, standby current increases typical with supplies typical with supplies. crystal ceramic resonator used clock source, then total current standby mode typical with supplies with supplies. This because on-chip oscillator circuit continues when part standby mode. This important applications where system clock provided AD7714's clock, that AD7714 produces uninterrupted master clock even when standby mode.
Accuracy
RESET input AD7714 resets logic, digital filter analog modulator while on-chip registers reset their default state. DRDY driven high AD7714 ignores communications registers while RESET input low. When RESET input returns high, AD7714 starts process data DRDY will return 1/Output Rate indicating valid word data register. However, AD7714 operates with default setup conditions after RESET generally necessary registers carry calibration after RESET command. AD7714's on-chip oscillator circuit continues function even when RESET input low. master clock signal continues available MCLK pin. Therefore, applications where system clock provided AD7714's clock, AD7714 produces uninterrupted master clock during RESET commands.
Standby Mode
Sigma-Delta ADCs, like VFCs other integrating ADCs, contain source nonmonotonicity inherently offer missing codes performance. AD7714 achieves excellent linearity high quality, on-chip capacitors, which have very capacitance/voltage coefficient. device also achieves input drift through chopper-stabilized techniques input stage. ensure excellent performance over time temperature, AD7714 uses digital calibration techniques which minimize offset gain error.
Drift Considerations
AD7714 uses chopper stabilization techniques minimize input offset drift. Charge injection analog switches leakage currents sampling node primary sources offset voltage drift converter. input leakage current essentially independent selected gain. Gain drift within converter depends primarily upon temperature tracking internal capacitors. affected leakage currents. Measurement errors offset drift gain drift eliminated time recalibrating converter operating part background calibration mode. Using system calibration mode also minimize offset gain errors signal conditioning circuitry. Integral differential linearity errors significantly affected temperature changes.
POWER SUPPLIES
STANDBY input AD7714 allows user place part power-down mode when required provide conversion results AD7714 retains contents on-chip registers (including data register) while standby mode. When released from standby mode, part starts process data word available data register 1/Output rate from when STANDBY input goes high. STANDBY input does affect digital interface, does affect status DRDY line. DRDY high when STANDBY returns high, will remain high until there valid word data register. DRDY when STANDBY returns high, will remain until data register updated which time DRDY line will return high tCLK before returning again. DRDY when part enters standby mode (indicating valid unread
There specific power sequence required AD7714, either AVDD DVDD supply come first. While latch-up performance AD7714 good, important that power applied AD7714 before signals logic input pins order avoid latch-up. this possible, then current which flows these pins should limited. separate supplies used AD7714 system digital circuitry, then AD7714 should powered first. possible guarantee this, then current limiting resistors should placed series with logic inputs again limit current.
Supply Current
current consumption AD7714 specified supplies range +3.6 range +4.75 +5.25 part operates over +2.85 +5.25 supply range part varies supply voltage varies over this range. Figure shows variation typical
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AD7714
with voltage both external clock 2.4576 external clock +25°C. AD7714 operated unbuffered mode internal boost part turned off. relationship shows that minimized operating part with lower voltages. AD7714 also minimized using external master clock optimizing external components when using on-chip oscillator circuit.
SUPPLY CURRENT (AVDD DVDD)
2.85 MCLK 1MHz MCLK 2.4576MHz
Avoid running digital lines under device these will couple noise onto die. analog ground plane should allowed under AD7714 avoid noise coupling. power supply lines AD7714 should large trace possible provide impedance paths reduce effects glitches power supply line. Fast switching signals like clocks should shielded with digital ground avoid radiating noise other sections board clock signals should never near analog inputs. Avoid crossover digital analog signals. Traces opposite sides board should right angles each other. This will reduce effects feedthrough through board. microstrip technique best always possible with double-sided board. this technique, component side board dedicated ground planes while signals placed solder side. Good decoupling important when using high resolution ADCs. analog supplies should decoupled with tantalum parallel with capacitors AGND. achieve best from these decoupling components, they have placed close possible device, ideally right against device. logic chips should decoupled with disc ceramic capacitors DGND. systems where common supply voltage used drive both AVDD DVDD AD7714, recommended that system's AVDD supply used. This supply should have recommended analog supply decoupling capacitors between AVDD AD7714 AGND recommended digital supply decoupling capacitor between DVDD AD7714 DGND.
Evaluating AD7714 Performance
3.15
3.45
3.75
4.05
4.35
4.65
4.95
5.25
SUPPLY VOLTAGE (AVDD DVDD) Volts
Figure Supply Voltage
Grounding Layout
Since analog inputs reference input differential, most voltages analog modulator common-mode voltages. excellent Common-Mode Rejection part will remove common-mode noise these inputs. analog digital supplies AD7714 independent separately pinned minimize coupling between analog digital sections device. digital filter will provide rejection broadband noise power supplies, except integer multiples modulator sampling frequency. digital filter also removes noise from analog reference inputs provided those noise sources saturate analog modulator. result, AD7714 more immune noise interference that conventional high resolution converter. However, because resolution AD7714 high noise levels from AD7714 low, care must taken with regard grounding layout. printed circuit board which houses AD7714 should designed such that analog digital sections separated confined certain areas board. This facilitates ground planes which separated easily. minimum etch technique generally best ground planes gives best shielding. Digital analog ground planes should only joined place. AD7714 only device requiring AGND DGND connection, then ground planes should connected AGND DGND pins AD7714. AD7714 system where multiple devices require AGND DGND connections, connection should still made point only, star ground point which should established close possible AD7714.
recommended layout AD7714 outlined evaluation board AD7714. evaluation board package includes fully assembled tested evaluation board, documentation, software controlling board over printer port software analyzing AD7714's performance AD7714-5, evaluation board order number EVAL-AD7714-5EB AD7714-3, order number EVAL-AD7714-3EB. Noise levels signals applied AD7714 also affect performance part. AD7714 allows techniques evaluating true performance part, independent analog input signal. These schemes should used after calibration been performed part. first these select AIN6/AIN6 input channel arrangement. this case, differential inputs AD7714 internally shorted together provide zero differential voltage analog modulator. External device, AIN6 input should connected voltage which within allowable common-mode range part. second scheme evaluate part with voltage near input full scale voltage gain this, reference voltage part should applied analog input. This will give fixed full-scale reading from device. zero-scale calibration coefficient read from device, increased number equivalent about decimal this value reloaded zero-scale calibration register, input range will offset such that voltage equal reference voltage
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longer corresponds full-scale reading. This allows user evaluate noise performance part with near full-scale voltage.
DIGITAL INTERFACE
that data read attempted while register being updated. used select device. used decode AD7714 systems where number parts connected serial bus. AD7714 serial interface operate three-wire mode tying input low. this case, SCLK, DOUT lines used communicate with AD7714 status DRDY obtained interrogating Communications Register. Figures show timing diagrams interfacing AD7714 with used decode part. Figure read operation from AD7714's output shift register while Figure shows write operation input shift register. Both diagrams input logic high; operation with input logic simply invert SCLK waveform shown diagrams. possible read same data twice from output register even though DRDY line returns high after first read operation. Care must taken, however, ensure that read operations have been completed before next output update about take place. serial interface reset exercising RESET input part. also reset writing series input. logic written AD7714 line least serial clock cycles serial interface reset. This ensures three-wire systems that interface gets lost, either software error some glitch system, reset back into known state. This state returns interface where AD7714 expecting write operation Communications Register. This operation does itself reset contents registers since interface lost, information which written registers unknown advisable registers again.
AD7714's programmable functions controlled using on-chip registers outlined previously. Data written these registers part's serial interface read access on-chip registers also provided this interface. communications part must start with write operation Communications Register. After power-on RESET, device expects write Communications Register. data written this register determines whether next operation part read write operation also determines which register this read write operation occurs. Therefore, write access other registers part starts with write operation Communications Register followed write selected register. read operation from register part (including output data register) starts with write operation Communications Register followed read operation from selected register. AD7714's serial interface consists five signals, SCLK, DIN, DOUT DRDY. line used transferring data into on-chip registers while DOUT line used accessing data from on-chip registers. SCLK serial clock input device data transfers (either DOUT) take place with respect this SCLK signal. DRDY line used status signal indicate when data ready read from AD7714's data register. DRDY goes when data word available output register. reset high when read operation from data register complete. also goes high prior updating output register indicate when read from device ensure
DRDY
SCLK
DOUT
Figure Read Cycle Timing Diagram (POL
SCLK
Figure Write Cycle Timing Diagram (POL
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AD7714
CONFIGURING AD7714
AD7714 contains eight on-chip registers that accessed serial interface. Communication with these registers initiated writing Communications Register first. Figure outlines flow diagram sequence which used configure registers after power-up reset. flowchart also shows different read options-the first where DRDY polled determine when update
START
data register taken place, second where DRDY Communications Register interrogated data register update taken place. Also included flowing diagram series words which should written registers particular operating conditions. These conditions test channel (AIN6/AIN6), gain burnout current off, filter sync, bipolar mode, 24-bit word length, boost maximum filter word (4000 decimal).
POWER-ON/RESET AD7714
CONFIGURE INITIALIZE µC/µP SERIAL PORT
WRITE COMMUNICATIONS REGISTER SETTING CHANNEL SETTING NEXT OPERATION WRITE FILTER HIGH REGISTER HEX)
WRITE FILTER HIGH REGISTER SETTING REQUIRED VALUES HEX)
WRITE COMMUNICATIONS REGISTER SETTING SAME CHANNEL SETTING NEXT OPERATION WRITE FILTER REGISTER HEX)
WRITE FILTER REGISTER SETTING REQUIRED VALUES HEX)
WRITE COMMUNICATIONS REGISTER SETTING SAME CHANNEL SETTING NEXT OPERATION WRITE MODE REGISTER HEX)
WRITE MODE REGISTER SETTING REQUIRED VALUES INITIATING CALIBRATION HEX)
POLL DRDY POLL DRDY COMMUNICATIONS REGISTER
DRDY LOW?
WRITE COMMUNICATIONS REGISTER SETTING SAME CHANNEL SETTING NEXT OPERATION READ FROM COMMUNICATIONS REGISTER HEX)
WRITE COMMUNICATIONS REGISTER SETTING SAME CHANNEL SETTING NEXT OPERATION READ FROM DATA REGISTER HEX)
READ FROM COMMUNICATIONS REGISTER
READ FROM DATA REGISTER DRDY LOW? WRITE COMMUNICATIONS REGISTER SETTING SAME CHANNEL SETTING NEXT OPERATION READ FROM DATA REGISTER HEX)
READ FROM DATA REGISTER
Figure Flowchart Setting Reading from AD7714
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AD7714
MICROCOMPUTER/MICROPROCESSOR INTERFACING
DVDD DVDD SYNC
AD7714's flexible serial interface allows easy interface most microcomputers microprocessors. flowchart Figure outlines sequence which should followed when interfacing microcontroller microprocessor AD7714. Figures show some typical interface circuits. serial interface AD7714 capability operating from just three wires compatible with interface protocols. three-wire operation makes part ideal isolated systems where minimizing number interface lines minimizes number opto-isolators required system. rise fall times digital inputs AD7714 (especially SCLK input) should longer than Most registers AD7714 8-bit registers which facilitates easy interfacing 8-bit serial ports microcontrollers. Some registers part bits, data transfers these 24-bit registers consist full 24-bit transfer three 8-bit transfers serial port microcontroller. processors microprocessors generally transfer bits data serial data operation. Some these processors, such ADSP-2105, have facility program amount cycles serial transfer. This allows user tailor number bits transfer match register length required register AD7714. Even though some registers AD7714 only eight bits length, communicating with these registers successive write operations handled single 16-bit data transfer required. example, Mode Register updated, processor must first write Communications Register (saying that next operation write Mode Register) then write eight bits Mode Register. This done single 16-bit transfer required because once eight serial clocks write operation Communications Register have been completed part immediately sets itself write operation Mode Register.
AD7714 68HC11 Interface
68HC11
RESET
SCLK
AD7714
MISO MOSI DATA DATA
Figure AD7714 68HC11 Interface
AD7714 capable full duplex operation. AD7714 configured write operation, data appears DATA lines even when SCLK input active. Similarly, AD7714 configured read operation, data presented part DATA line ignored even when SCLK active.
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RESET
AD7714 8XC51
P3.0 DATA DATA
P3.1
SCLK
Figure shows interface between AD7714 68HC11 microcontroller. diagram shows minimum (three-wire) interface with AD7714 hard-wired low. this scheme, DRDY Communications Register monitored determine when Data Register updated. alternative scheme, which increases number interface lines four, monitor DRDY output line from AD7714. monitoring DRDY line done ways. First, DRDY connected 68HC11's port bits (such PC0) which configured input. This port then polled determine status DRDY. second scheme interrupt driven system which case, DRDY output connected input 68HC11. interfaces which require control input AD7714, port bits 68HC11 (such PC1), which configured output, used drive input.
Figure AD7714 8051 Interface
Coding interface between 68HC11 AD7714 given Table this example, DRDY output line AD7714 connected port 68HC11 polled determine status.
AD7714 8051 Interface
68HC11 configured master mode with CPOL logic zero CPHA logic one. When 68HC11 configured like this, SCLK line idles between data transfers. Therefore, input AD7714 should hard-wired low. systems where preferable that SCLK idle high, CPOL 68HC11 should logic input AD7714 should hard-wired logic high. REV. -29-
interface circuit between AD7714 8XC51 microcontroller shown Figure diagram shows minimum number interface connections with AD7714 hard-wired low. case 8XC51 interface minimum number interconnects just two. this scheme, DRDY Communications Register monitored determine when Data Register updated. alternative scheme, which increases number interface lines three, monitor DRDY output line from AD7714. monitoring DRDY line done ways. First, DRDY connected 8XC51's port bits (such
AD7714
P1.0) which configured input. This port then polled determine status DRDY. second scheme interrupt driven system which case, DRDY output connected INT1 input 8XC51. interfaces which require control input AD7714, port bits 8XC51 (such P1.1), which configured output, used drive input. 8XC51 configured Mode serial interface mode. serial interface contains single data line. result, DATA DATA pins AD7714 should connected together. serial clock 8XC51 idles high between data transfers and, therefore, input AD7714 should hard-wired logic high. 8XC51 outputs first write operation while AD7714 expects first data transmitted rearranged before being written output serial register. Similarly, AD7714 outputs first during read operation while 8XC51 expects first. Therefore, data which read into serial buffer needs rearranged before correct data word from AD7714 available accumulator.
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CODE SETTING AD7714
Table gives read write routines code interfacing 68HC11 microcontroller AD7714. sample program sets various registers AD7714 reads 1000 samples from part into 68HC11. setup conditions part exactly same those outlined flowchart Figure example code given here DRDY output polled determine valid word available output register. sequence events this program follows: Write Communications Register, setting channel. Write Filter High Register, setting MSBs filter word setting part 24-bit read, bipolar mode with boost o
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