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AD7714 AD7714-3 AD7714-5 VREF/GAIN11 IN/64 OUT12 BURNOUT14 AD7714AN-5 - Datasheet Archive

Signal Conditioning ADC AD7714* a APPLICATIONS Portable Industrial Instruments Portable Weigh Scales Loop-Powered Systems

3 V/5 V, CMOS, 500 µA Signal Conditioning ADC AD7714 AD7714* a APPLICATIONS Portable Industrial Instruments Portable Weigh Scales Loop-Powered Systems Pressure Transducers FUNCTIONAL BLOCK DIAGRAM AVDD DVDD REF IN() REF IN(+) AD7714 AD7714 AVDD CHARGING BALANCING A/D CONVERTER 1µA AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 SWITCHING MATRIX FEATURES Charge Balancing ADC 24 Bits No Missing Codes 0.0015% Nonlinearity Five-Channel Programmable Gain Front End Gains from 1 to 128 Can Be Configured as Three Fully Differential Inputs or Five Pseudo-Differential Inputs Three-Wire Serial Interface 3 V (AD7714-3 AD7714-3) or 5 V (AD7714-5 AD7714-5) Operation Low Noise (1G CSAMP (7pF ) VBIAS SWITCHING FREQUENCY DEPENDS ON fCLKIN AND SELECTED GAIN Figure 3. Unbuffered Analog Input Structure CSAMP must be charged through RSW and through any external source impedances every input sample cycle. Therefore, in unbuffered mode, source impedances mean a longer charge time for CSAMP and this may result in gain errors on the part. Table XII shows the allowable external resistance/capacitance values, for unbuffered mode, such that no gain error to the 16-bit level is introduced on the part. Table XIII shows the allowable external resistance/capacitance values, once again for unbuffered mode, such that no gain error to the 20-bit level is introduced. Table XII. External R, C Combination for No 16-Bit Gain Error (Unbuffered Mode Only) Gain External Capacitance (pF) 0 1 2 4 8128 50 100 500 1000 5000 368 k 177.2 k 82.8 k 35.2 k 90.6 k 44.2 k 21.2 k 9.6 k 54.2 k 26.4 k 12.6 k 5.8 k 14.6 k 7.2 k 3.4 k 1.58 k 8.2 k 4 k 1.94 k 880 2.2 k 1.12 k 540 240 Table XIII. External R, C Combination for No 20-Bit Gain Error (Unbuffered Mode Only) Gain External Capacitance (pF) 0 1 2 4 8128 50 100 500 1000 5000 290 k 141 k 63.6 k 26.8 k 69 k 33.8 k 16 k 7.2 k 40.8 k 20 k 9.6 k 4.4 k 10.4 k 5 k 2.4 k 1.1 k 5.6 k 2.8 k 1.34 k 600 1.4 k 700 340 160 In buffered mode, the analog inputs look into the high impedance inputs stage of the on-chip buffer amplifier. CSAMP is charged via this buffer amplifier such that source impedances do not affect the charging of CSAMP. This buffer amplifier has an offset leakage current of 1 nA. In this buffered mode, large source impedances result in a dc offset voltage developed across the source impedance but not in a gain error. Input Sample Rate The modulator sample frequency for the AD7714 AD7714 remains at fCLK IN/128 IN/128 (19.2 kHz @ fCLK IN = 2.4576 MHz) regardless of the selected gain. However, gains greater than 1 are achieved by a combination of multiple input samples per modulator cycle and a scaling of the ratio of reference capacitor to input capacitor. As a result of the multiple sampling, the input sample rate of the device varies with the selected gain (see Table XIV). In buffered mode, the input is buffered before the input sampling capacitor. In unbuffered mode, where the analog input looks directly into the sampling capacitor, the effective input impedance is 1/CSAMP.fs where CSAMP is the input sampling capacitance and fs is the input sample rate. 18 REV. B AD7714 AD7714 Table XIV. Input Sampling Frequency vs. Gain Gain Input Sampling Freq (fs) 1 2 4 8 16 32 64 128 fCLK IN/64 IN/64 (38.4 kHz @ fCLK IN = 2.4576 MHz) 2 × fCLK IN/64 IN/64 (76.8 kHz @ fCLK IN = 2.4576 MHz) 4 × fCLK IN/64 IN/64 (153.6 kHz @ fCLK IN = 2.4576 MHz) 8 × fCLK IN/64 IN/64 (307.2 kHz @ fCLK IN = 2.4576 MHz) 8 × fCLK IN/64 IN/64 (307.2 kHz @ fCLK IN = 2.4576 MHz) 8 × fCLK IN/64 IN/64 (307.2 kHz @ fCLK IN = 2.4576 MHz) 8 × fCLK IN/64 IN/64 (307.2 kHz @ fCLK IN = 2.4576 MHz) 8 × fCLK IN/64 IN/64 (307.2 kHz @ fCLK IN = 2.4576 MHz) Burn-Out Current The AD7714 AD7714 contains two 1 µA currents, one source current from AVDD to AIN(+) and one sink from AIN() to AGND. The currents are either both on or off depending on the BO bit of the Mode Register. These currents can be used in checking that a transducer has not burnt-out or gone open circuit before attempting to take measurements on that channel. If the currents are turned on, allowed flow in the transducer, a measurement of the input voltage on the analog input taken and the voltage measured is full scale then it indicates that the transducer has gone open-circuit; if the voltage measured is zero, it indicates that the transducer has gone short-circuit. For normal operation, these burn-out currents are turned off by writing a 0 to the BO bit. For the source current to work correctly, the applied voltage on AIN(+) should not go within 500 mV of AVDD. For the sink current to work correctly, the applied voltage on the AIN() input should not go within 500 mV of AGND. Bipolar/Unipolar Inputs The analog inputs on the AD7714 AD7714 can accept either unipolar or bipolar input voltage ranges. Bipolar input ranges do not imply that the part can handle negative voltages on its analog inputs, since the analog input cannot go more negative than 30 mV to ensure correct operation of the part. The input channels are either fully differential or pseudo-differential (all other channels referenced to AIN6). In either case, the input channels are arranged in pairs with an AIN(+) and AIN(). As a result, the voltage to which the unipolar and bipolar signals on the AIN(+) input are referenced is the voltage on the respective AIN() input. For example, if AIN() is +2.5 V and the AD7714 AD7714 is configured for unipolar operation with a gain of 2 and a VREF of +2.5 V, the input voltage range on the AIN(+) input is +2.5 V to +3.75 V. If AIN() is +2.5 V and the AD7714 AD7714 is configured for bipolar mode with a gain of 2 and a VREF of +2.5 V, the analog input range on the AIN(+) input is +1.25 V to +3.75 V (i.e., 2.5 V ± 1.25 V). If AIN() is at AGND, the part cannot be configured for bipolar ranges in excess of ± 30 mV. Bipolar or unipolar options are chosen by programming the B/U bit of the Filter High Register. This programs the selected channel for either unipolar or bipolar operation. Programming the channel for either unipolar or bipolar operation does not change any of the input signal conditioning; it simply changes the data output coding and the points on the transfer function where calibrations occur. REFERENCE INPUT The AD7714 AD7714's reference inputs, REF IN(+) and REF IN(), provide a differential reference input capability. The commonmode range for these differential inputs is from AGND to AVDD. The nominal reference voltage, VREF (REF IN(+) REV. B REF IN(), for specified operation is +2.5 V for the AD7714-5 AD7714-5 and +1.25 V for the AD7714-3 AD7714-3. The part is functional with VREF voltages down to 1 V but with degraded performance as the output noise will, in terms of LSB size, be larger. REF IN(+) must always be greater than REF IN() for correct operation of the AD7714 AD7714. Both reference inputs provide a high impedance, dynamic load similar to the analog inputs in unbuffered mode. The maximum dc input leakage current is ± 1 nA over temperature and source resistance may result in gain errors on the part. In this case, the sampling switch resistance is 5 k typ and the reference capacitor (CREF) varies with gain. The sample rate on the reference inputs is fCLK IN/64 IN/64 and does not vary with gain. For gains of 1 to 8, CREF is 8 pF; for a gain of 16, it is 5.5 pF, for a gain of 32, it is 4.25 pF, for a gain of 64, it is 3.625 pF and for a gain of 128, it is 3.3125 pF. The output noise performance outlined in Tables I through IV is for an analog input of 0 V and is unaffected by noise on the reference. To obtain the same noise performance as shown in the noise tables over the full input range requires a low noise reference source for the AD7714 AD7714. If the reference noise in the bandwidth of interest is excessive, it will degrade the performance of the AD7714 AD7714. In applications where the excitation voltage for the bridge transducer on the analog input also derives the reference voltage for the part, the effect of the noise in the excitation voltage will be removed as the application is ratiometric. Recommended reference voltage sources for the AD7714-5 AD7714-5 include the AD780 AD780, REF43 REF43 and REF192 REF192 while the recommended reference sources for the AD7714-3 AD7714-3 include the AD589 AD589 and AD1580 AD1580. It is generally recommended to decouple the output of these references to further reduce the noise level. DIGITAL FILTERING The AD7714 AD7714 contains an on-chip low-pass digital filter which processes the output of the part's sigma-delta modulator. Therefore, the part not only provides the analog-to-digital conversion function but it also provides a level of filtering. There are a number of system differences when the filtering function is provided in the digital domain rather than the analog domain and the user should be aware of these. First, since digital filtering occurs after the A-to-D conversion process, it can remove noise injected during the conversion process. Analog filtering cannot do this. Also, the digital filter can be made programmable far more readily than an analog filter. Depending on the digital filter design, this gives the user the capability of programming cutoff frequency and output update rate. On the other hand, analog filtering can remove noise superimposed on the analog signal before it reaches the ADC. Digital filtering cannot do this and noise peaks riding on signals near full scale have the potential to saturate the analog modulator and digital filter, even though the average value of the signal is within limits. To alleviate this problem, the AD7714 AD7714 has overrange headroom built into the sigma-delta modulator and digital filter which allows overrange excursions of 5% above the analog input range. If noise signals are larger than this, consideration should be given to analog input filtering, or to reducing the input channel voltage so that its full scale is half that of the analog input channel full scale. This will provide an overrange capability greater than 100% at the expense of reducing the dynamic range by 1 bit (50%). 19 2 AD7714 AD7714 In addition, the digital filter does not provide any rejection at integer multiples of the digital filter's sample frequency. However, the input sampling on the part provides attenuation at multiples of the digital filter's sampling frequency so that the unattenuated bands actually occur around multiples of the input sampling frequency fs (as defined in Table XIV). Thus, the unattenuated bands occur at n × fs (where n = 1, 2, 3. . .). At these frequencies, there are frequency bands, ± f3 dB wide (f3 dB is the cutoff frequency of the digital filter) at either side where noise passes unattenuated to the output. Filter Characteristics H( f ) = 1 N × where N is the decimal equivalent of the word loaded to the FS0 to FS11 bits of the Filter Registers while the 3 dB frequency is determined by the relationship: 3 dB frequency = 0.262 × filter first notch frequency Group Delay = 3.(N.f/fMOD ) where N is the decimal equivalent of the word loaded to the FS0 to FS11 bits of the Filter Registers and fMOD = fCLK IN/128 IN/128. 3 Sin (N. . f fs) Output Rate = fCLK IN/(N.128) The filter provides a linear phase response with a group delay determined by: The AD7714 AD7714's digital filter is a low-pass filter with a (sinx/x)3 response (also called sinc3). The transfer function for this filter is described in the z-domain by: 1 1 - Z -N H(z) = × N 1 - Z -1 and in the frequency domain by: FS0 FS11 does not alter the profile of the filter response; it changes the frequency of the notches as outlined in the Filter Registers section. The output update and first notch correspond and are determined by the relationship: Since the AD7714 AD7714 contains this on-chip, low-pass filtering, there is a settling time associated with step function inputs and data on the output will be invalid after a step change until the settling time has elapsed. The settling time depends upon the output rate chosen for the filter. The settling time of the filter to a full-scale step input can be up to 4 times the output data period. For a synchronized step input (using the SYNC or FSYNC functions) the settling time is 3 times the output data period. When changing channels on the part, the change from one channel to the other is synchronized so the output settling time is also 3 times the output data period. Thus, in switching between channels, the output data register is not updated until the settling time of the filter has elapsed. 3 Sin (. f fs) Figure 4 shows the filter frequency response for a cutoff frequency of 2.62 Hz which corresponds to a first filter notch frequency of 10 Hz. The plot is shown from dc to 65 Hz. This response is repeated at either side of the input sampling frequency and at either side of multiples of the input sampling frequency. Post-Filtering 0 The on-chip modulator provides samples at a 19.2 kHz output rate with fCLK IN at 2.4576 MHz. The on-chip digital filter decimates these samples to provide data at an output rate which corresponds to the programmed output rate of the filter. Since the output data rate is higher than the Nyquist criterion, the output rate for a given bandwidth will satisfy most application requirements. However, there may be some applications which require a higher data rate for a given bandwidth and noise performance. Applications which need this higher data rate will require some post-filtering following the part's digital filter. 20 40 60 GAIN dB 80 100 120 140 160 180 200 For example, if the required bandwidth is 7.86 Hz but the required update rate is 100 Hz, the data can be taken from the AD7714 AD7714 at the 100 Hz rate giving a 3 dB bandwidth of 26.2 Hz. Post-filtering can be applied to this to reduce the bandwidth and output noise, to the 7.86 Hz bandwidth level, while maintaining an output rate of 100 Hz. 220 240 0 10 20 30 40 FREQUENCY Hz 50 60 Figure 4. Frequency Response of AD7714 AD7714 Filter The response of the filter is similar to that of an averaging filter but with a sharper roll-off. The output rate for the digital filter corresponds with the positioning of the first notch of the filter's frequency response. Thus, for the plot of Figure 4 where the output rate is 10 Hz, the first notch of the filter is at 10 Hz. The notches of this (sinx/x)3 filter are repeated at multiples of the first notch. The filter provides attenuation of better than 100 dB at these notches. For the example given, if the first notch is at 10 Hz, there will be notches (and hence >100 dB rejection) at both 50 Hz and 60 Hz. Post-filtering can also be used to reduce the output noise from the device for bandwidths below 1.26 Hz. At a gain of 128 and a bandwidth of 1.26 Hz, the output rms noise is 140 nV. This is essentially device noise or white noise and since the input is chopped, the noise has a primarily flat frequency response. By reducing the bandwidth below 1.26 Hz, the noise in the resultant passband can be reduced. A reduction in bandwidth by a factor of 2 results in a reduction of approximately 1.25 in the output rms noise. This additional filtering will result in a longer settling time. The cutoff frequency of the digital filter is determined by the value loaded to bits FS0 to FS11 in the Filter High and Filter Low Registers. Programming a different cutoff frequency via 20 REV. B AD7714 AD7714 ANALOG FILTERING The digital filter does not provide any rejection at integer multiples of the input sampling frequency, as outlined earlier. However, due to the AD7714 AD7714's high oversampling ratio, these bands occupy only a small fraction of the spectrum and most broadband noise is filtered. This means that the analog filtering requirements in front of the AD7714 AD7714 are considerably reduced versus a conventional converter with no on-chip filtering. In addition, because the part's common-mode rejection performance of 100 dB extends out to several kHz, common mode noise in this frequency range will be substantially reduced. Depending on the application, however, it may be necessary to provide attenuation prior to the AD7714 AD7714 in order to eliminate unwanted frequencies from these bands which the digital filter will pass. It may also be necessary in some applications to provide analog filtering in front of the AD7714 AD7714 to ensure that differential noise signals outside the band of interest do not saturate the analog modulator. If passive components are placed in front of the AD7714 AD7714, in unbuffered mode, care must be taken to ensure that the source impedance is low enough so as not to introduce gain errors in the system. This significantly limits the amount of passive antialiasing filtering which can be provided in front of the AD7714 AD7714 when it is used in unbuffered mode. However, when the part is used in buffered mode, large source impedances will simply result in a small dc offset error (a 10 k source resistance will cause an offset error of less than 10 µV). Therefore, if the system requires any significant source impedances to provide passive analog filtering in front of the AD7714 AD7714, it is recommended that the part be operated in buffered mode. The AD7714 AD7714 provides a number of calibration options which can be programmed via the MD2, MD1 and MD0 bits of the Mode Register. The different calibration options are outlined in the Mode Register and Calibration Sequences sections. A calibration cycle may be initiated at any time by writing to these bits of the Mode Register. Calibration on the AD7714 AD7714 removes offset and gain errors from the device. A calibration routine should be initiated on the device whenever there is a change in the ambient operating temperature or supply voltage. It should also be initiated if there is a change in the selected gain, filter notch or bipolar/unipolar input range. The AD7714 AD7714 gives the user access to the on-chip calibration registers allowing the microprocessor to read the device's calibration coefficients and also to write its own calibration coefficients to the part from prestored values in E2PROM. This gives the microprocessor much greater control over the AD7714 AD7714's calibration procedure. It also means that the user can verify that the device has performed its calibration correctly by comparing the coefficients after calibration with prestored values in E2PROM. The values in these calibration registers are 24-bit wide. In addition, the span and offset for the part can be adjusted by the user. REV. B The AD7714 AD7714 offers self-calibration, system calibrati