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AD7156 - AD7156
Ultralow Power, 2-Channel Capacitance Converter AD7156
Ultralow power Power supply voltage: Operation power supply current: typical Power-down current: typical Fast response time Conversion time: channel Wake-up time from serial interface: Adaptive environmental compensation capacitance input channels Sensor capacitance (CSENS): Sensitivity modes operation Standalone with fixed settings Interfaced microcontroller user-defined settings detection output flags 2-wire serial interface (I2C-compatible) Operating temperature: -40°C +85°C 10-lead LFCSP package
AD7156 delivers complete signal processing solution capacitive sensors, featuring ultralow power converter with fast response time. AD7156 uses Analog Devices, Inc., capacitance-todigital converter (CDC) technology, which combines features important interfacing real sensors, such high input sensitivity high tolerance both input parasitic ground capacitance leakage current. integrated adaptive threshold algorithm compensates variations sensor capacitance environmental factors like humidity temperature changes dielectric material over time. default, AD7156 operates standalone mode using fixed power-up settings indicates detection digital outputs. Alternatively, AD7156 interfaced microcontroller serial interface, internal registers programmed with user-defined settings, data status read from part. AD7156 operates with power supply. specified over temperature range -40°C +85°C.
APPLICATIONS
Buttons switches Proximity sensing Contactless switching Position detection Level detection Portable products
FUNCTIONAL BLOCK DIAGRAM
CIN1 CSENS1 EXC1 CIN2 CSENS2 EXC2 EXCITATION THRESHOLD DIGITAL FILTER SERIAL INTERFACE
AD7156
THRESHOLD
OUT1
OUT2
07726-001
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. rights reserved.
AD7156 TABLE CONTENTS
Features Applications General Description Functional Block Diagram Revision History Specifications. Timing Specifications Absolute Maximum Ratings. Caution Configuration Function Descriptions Typical Performance Characteristics Theory Operation Capacitance-to-Digital Converter CAPDAC Comparator Threshold Modes Adaptive Threshold Sensitivity. Data Average Hysteresis Timeout. Auto-DAC Adjustment Power-Down Timer Register Descriptions Status Register Data Registers Average Registers Fixed Threshold Registers Sensitivity Registers Timeout Registers. Setup Registers Configuration Register Power-Down Timer Register CAPDAC Registers Serial Number Register. Chip Register Serial Interface Read Operation. Write Operation. AD7156 Reset General Call Hardware Design Considerations Overview Parasitic Capacitance Ground Parasitic Resistance Ground Parasitic Parallel Resistance Parasitic Serial Resistance Input Overvoltage Protection Input Protection Power Supply Decoupling Filtering. Application Examples Outline Dimensions Ordering Guide
REVISION HISTORY
10/08-Revision Initial Version
Rev. Page
AD7156 SPECIFICATIONS
temperature range -40°C +85°C, unless otherwise noted. Table
Parameter CAPACITIVE INPUT Conversion Input Range, 0.05 12.5 0.25 ±VDD/2 1000 ±0.1 Unit %FSR fF/V range ISINK -6.0 VOUT Test Conditions/Comments input range input range input range input range input range input range input range input range Figure Figure Figure Figure Figure Figure Figure pins disconnected pins disconnected Figure
Resolution
Maximum Allowed Capacitance, GND4, Minimum Allowed Resistance, GND4, Maximum Allowed Serial Resistance4, Gain Error Gain Deviation over Temperature4 Gain Matching Between Ranges4 Offset Error4 Offset Deviation over Temperature4 Integral Nonlinearity (INL)4 Channel-to-Channel Isolation4 Power Supply Rejection4 CAPDAC Full Range Resolution (LSB)4 Differential Nonlinearity (DNL)4 Auto-DAC Increment/Decrement4, EXCITATION Voltage4, Frequency Maximum Allowed Capacitance GND4, Minimum Allowed Resistance GND4, LOGIC OUTPUTS (OUT1, OUT2) Output Voltage (VOL) Output High Voltage (VOH) SERIAL INTERFACE INPUTS (SCL, SDA) Input High Voltage (VIH) Input Voltage (VIL) Input Leakage Current Input Capacitance OPEN-DRAIN OUTPUT (SDA) Output Voltage (VOL) Output High Leakage Current (IOH)
Figure Figure Figure Figure Figure Figure ISINK ISOURCE
Rev. Page
AD7156
Parameter POWER REQUIREMENTS VDD-to-GND Voltage Current4, Current Power-Down Mode4, Unit Test Conditions/Comments
Figure Figure Figure Figure
Capacitance units: 10-12 10-15 CAPDAC used shift (offset) input range. total capacitance sensor therefore CAPDAC value conversion input range. With auto-DAC feature, CAPDAC adjusted automatically when input value lower than higher than nominal input range. maximum capacitance sensor connected between EXCx CINx pins equal minimum guaranteed value CAPDAC minimum guaranteed input range. maximum specification production tested supported characterization data initial product release. resolution converter limited output data format output data (least significant bit) size, converter system noise level. noise-free resolution defined level peak-to-peak noise coming from converter itself, with connection pins. These specifications understood separately. combination capacitance ground serial resistance result additional errors, example gain error, gain drift, offset error, offset drift, power supply rejection. Specification production tested guaranteed design. Digital inputs equal GND.
Rev. Page
AD7156
TIMING SPECIFICATIONS
Input Logic Input Logic VDD, temperature range -40°C +85°C, unless otherwise noted. Table
Parameter CONVERTER Conversion Time Wake-Up Time from Power-Down Mode Power-Up Time2, Reset Time2, SERIAL INTERFACE Frequency High Pulse Width, tHIGH Pulse Width, tLOW SCL, Rise Time, SCL, Fall Time, Hold Time (Start Condition), tHD;STA Setup Time (Start Condition), tSU;STA Data Setup Time, tSU;DAT Setup Time (Stop Condition), tSU;STO Data Hold Time (Master), tHD;DAT Bus-Free Time (Between Stop Start Conditions), tBUF
Unit
Test Conditions/Comments Both channels, channel.
Figure
After this period, first clock generated. Relevant repeated start condition.
Conversion time internal clock cycles both channels (nominal clock kHz); internal clock frequency equal specified excitation frequency. Specification production tested supported characterization data initial product release. Wake-up time maximum delay between last edge writing configuration register start conversion. Power-up time maximum delay between crossing minimum level (1.8 either start conversion when ready receive serial interface command. Reset time maximum delay between last edge writing reset command either start conversion when ready receive serial interface command. Sample tested during initial release ensure compliance. input signals specified with input rise/fall times measured between points. Timing reference points inputs outputs. Output load
tLOW
tHD;STA
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
tSU;STA
tSU;STO
tBUF
Figure Serial Interface Timing Diagram
Rev. Page
07726-002
AD7156 ABSOLUTE MAXIMUM RATINGS
25°C, unless otherwise noted. Table
Parameter Positive Supply Voltage Voltage Input Output Rating Association Human Body Model, S5.1 Field-Inducted Charged Device Model Operating Temperature Range Storage Temperature Range Maximum Junction Temperature LFCSP Package Thermal Impedance Thermal Impedance Case Reflow Soldering (Pb-Free) Peak Temperature Time Peak Temperature Rating -0.3 +3.9 -0.3 -40°C +85°C -65°C +150°C 150°C 49°C/W 3°C/W 260(0/-5)°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
CAUTION
Rev. Page
AD7156 CONFIGURATION FUNCTION DESCRIPTIONS
CIN2 CIN1 EXC2
AD7156
VIEW (Not Scale)
OUT2 OUT1 EXC1
07726-003
NOTES EXPOSED MUST CONNECTED MUST ISOLATED (FLOATING).
Figure Configuration
Table Function Descriptions
Mnemonic CIN2 Description Ground Pin. Power Supply Voltage. This should decoupled using impedance capacitor, such
multilayer ceramic capacitor.
Capacitive Input Channel measured capacitance (sensor) connected between EXC2 CIN2 pin. used, this left open circuit connected GND. When conversion performed Channel CIN2 internally connected high impedance input modulator. When conversion performed other channel idle mode power-down mode,
CIN2 internally disconnected left floating part.
CIN1 Capacitive Input Channel measured capacitance (sensor) connected between EXC1 CIN1 pin. used, this left open circuit connected GND. When conversion performed Channel CIN1 internally connected high impedance input modulator. When conversion performed other channel idle mode power-down mode,
CIN1 internally disconnected left floating part.
EXC2 Excitation Output Channel measured capacitance connected between EXC2 CIN2 pin. used, this should left open circuit. When conversion performed Channel EXC2 internally connected output excitation signal driver. When conversion performed other channel idle mode power-down mode, EXC2 internally connected
GND.
EXC1 Excitation Output Channel measured capacitance connected between EXC1 CIN1 pin. used, this should left open circuit. When conversion performed Channel EXC1 internally connected output excitation signal driver. When conversion performed other channel idle mode power-down mode, EXC1 internally connected
GND.
OUT1 OUT2 Logic Output Channel high level this output indicates proximity detected CIN1. Logic Output Channel high level this output indicates proximity detected CIN2. Serial Interface Clock Input. This connects master clock line requires pull-up resistor provided elsewhere system. Serial Interface Bidirectional Data. This connects master data line requires pull-up resistor provided elsewhere system.
Rev. Page
AD7156 TYPICAL PERFORMANCE CHARACTERISTICS
OFFSET ERROR (pF) OFFSET ERROR (fF)
1.8V
3.3V
CAPACITANCE GROUND (pF) 3.3V
07726-004
1.8V
07726-007
1000 1500 CAPACITANCE GROUND (pF)
2000
Figure Capacitance Input Offset Error Capacitance GND, Open Circuit
Figure Capacitance Input Offset Error Capacitance GND, Open Circuit
GAIN ERROR (%FSR) GAIN ERROR (%FSR)
3.3V 1.8V
3.3V
1.8V
07726-005
07726-008
CAPACITANCE GROUND (pF)
1000 1500 CAPACITANCE GROUND (pF)
2000
Figure Capacitance Input Gain Error Capacitance GND,
Figure Capacitance Input Gain Error Capacitance GND,
GAIN ERROR (%FSR) GAIN ERROR (%FSR)
3.3V
3.3V
1.8V
1.8V
07726-006
07726-009
CAPACITANCE GROUND (pF)
1000 1500 CAPACITANCE GROUND (pF)
2000
Figure Capacitance Input Gain Error Capacitance GND,
Figure Capacitance Input Gain Error Capacitance GND,
Rev. Page
AD7156
GAIN ERROR (%FSR)
3.3V
GAIN ERROR (%FSR)
3.3V 1.8V -0.2 1.8V
-0.4
-0.6
07726-010
-0.8
07726-013
RESISTANCE
-1.0
RESISTANCE GROUND
Figure Capacitance Input Gain Error Resistance GND,
Figure Capacitance Input Gain Error Resistance GND,
GAIN ERROR (%FSR)
3.3V
GAIN ERROR (%FSR)
3.3V 1.8V
1.8V
07726-011
RESISTANCE
SERIAL RESISTANCE
Figure Capacitance Input Gain Error Resistance GND,
1.8V 3.3V -0.2
Figure Capacitance Input Gain Error Serial Resistance,
1.8V
GAIN ERROR (%FSR)
GAIN ERROR (%FSR)
3.3V
-0.4
-0.6
-0.8
07726-012
07726-015
-1.0
PARELLEL RESISTANCE
RESISTANCE GROUND
Figure Capacitance Input Gain Error Resistance GND,
Figure Capacitance Input Gain Error Parallel Resistance,
Rev. Page
07726-014
AD7156
OFFSET ERROR (fF)
3.3V 1.8V
(fF)
07726-016
07726-019
CAPDAC CODE
TEMPERATURE (°C)
Figure Capacitance Input Offset Error Temperature, Pins Open Circuit
0.35 0.25 0.15 0.05 -0.05 -0.15 -0.25 -0.35
(µA)
Figure CAPDAC Differential Nonlinearity (DNL),
3.6V 2.7V
GAIN ERROR (%FSR)
1.8V
07726-017
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure Capacitance Input Gain Error Temperature,
16.50 16.25 16.00 FREQUENCY (kHz) 3.6V 1.8V 15.50 15.25 15.00
07726-018
Figure Current Temperature,
(µA)
2.7V
15.75
3.6V 2.7V 1.8V
14.50
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure Frequency Error Temperature,
Figure Power-Down Current Temperature,
Rev. Page
07726-021
14.75
07726-020
AD7156 THEORY OPERATION
3.3V
AD7156
CIN1 EXC1 CIN2 EXC2
CLOCK GENERATOR
POWER-DOWN TIMER
DIGITAL FILTER
SERIAL INTERFACE
PROGRAMMING INTERFACE
CAPDAC
THRESHOLD
OUT1 DIGITAL OUTPUTS
EXCITATION
THRESHOLD
OUT2
Figure AD7156 Block Diagram
AD7156 core high performance capacitance-to-digital converter (CDC) that allows part interfaced directly capacitive sensor. comparators compare results with thresholds, either fixed dynamically adjusted on-chip adaptive threshold algorithm engine. Thus, outputs indicate defined change input sensor capacitance. AD7156 also integrates excitation source, CAPDAC capacitive inputs, input multiplexer, complete clock generator, power-down timer, power supply monitor, control logic, I2C®-compatible serial interface configuring part accessing internal data status, required system (see Figure 22).
CAPACITANCE-TO-DIGITAL CONVERTER (CDC) CLOCK GENERATOR 0x0000 0xFFF0 DATA EXCITATION
07726-031
MODULATOR
DIGITAL FILTER
Figure Simplified Block Diagram
CAPDAC
AD7156 core maximum full-scale input range However, part accept higher input capacitance, caused, example, nonchanging offset capacitance This offset capacitance compensated using programmable on-chip CAPDAC.
CAPDAC 10pF 10pF 14pF
07726-032
CAPACITANCE-TO-DIGITAL CONVERTER
Figure shows simplified functional diagram. converter consists second-order charge balancing modulator third-order digital filter. measured capacitance connected between excitation source modulator input. excitation signal applied capacitor during conversion, modulator continuously samples charge going through digital filter processes modulator output, which stream containing information density. data processed adaptive threshold engine output comparators; data also read through serial interface. AD7156 designed floating capacitive sensors. Therefore, both plates have isolated from ground other fixed potential node system. AD7156 features slew rate limiting excitation voltage output, which decreases energy higher harmonics excitation signal dramatically improves system electromagnetic compatibility (EMC).
0x0000 0xFFF0 DATA
Figure Using CAPDAC
CAPDAC understood negative capacitance connected internally pin. CAPDAC 6-bit resolution monotonic transfer function. Figure shows CAPDAC shift input range measure capacitance between
Rev. Page
07726-030
AD7156
COMPARATOR THRESHOLD MODES
AD7156 comparators their thresholds programmed operate modes: fixed adaptive threshold modes. adaptive mode, threshold dynamically adjusted comparator output indicates fast changes ignores slow changes input (sensor) capacitance. Alternatively, threshold programmed constant (fixed) value, output then indicates change input capacitance that crosses defined fixed threshold. AD7156 logic output (active high) indicates either positive negative change input capacitance, both adaptive fixed threshold modes (see Figure Figure 26).
POSITIVE CHANGE POSITIVE THRESHOLD INPUT CAPACITANCE OUTPUT ACTIVE
INPUT CAPACITANCE
07726-033
INPUT OUTSIDE THRESHOLD WINDOW POSITIVE THRESHOLD INPUT CAPACITANCE NEGATIVE THRESHOLD OUTPUT ACTIVE
07726-036
07726-039
07726-037
OUTPUT TIME
Figure Out-Window (Adaptive) Threshold Mode
ADAPTIVE THRESHOLD
adaptive mode, thresholds dynamically adjusted, ensuring indication fast changes (for example, object moving close capacitive proximity sensor) eliminating slow changes input (sensor) capacitance, usually caused environment changes such humidity temperature changes sensor dielectric material over time (see Figure 29).
FAST CHANGE SLOW CHANGE
OUTPUT TIME
THRESHOLD
OUTPUT ACTIVE OUTPUT TIME
Figure Positive Threshold Mode Indicates Positive Change Input Capacitance
NEGATIVE CHANGE INPUT CAPACITANCE NEGATIVE THRESHOLD OUTPUT ACTIVE
Figure Adaptive Threshold Indicates Fast Changes Eliminates Slow Changes Input Capacitance
SENSITIVITY
adaptive threshold mode, output comparator threshold defined distance (sensitivity) above data average, below data average, both, depending selected threshold mode operation (see Figure 30). sensitivity value programmable range 12-bit converter (see Register Descriptions section).
DATA POSITIVE THRESHOLD SENSITIVITY DATA AVERAGE SENSITIVITY NEGATIVE THRESHOLD OUTPUT ACTIVE
TIME
Figure Negative Threshold Mode Indicates Negative Change Input Capacitance
Additionally, adaptive mode only, comparators work window comparators, indicating input either inside outside selected sensitivity band (see Figure Figure 28).
POSITIVE THRESHOLD INPUT CAPACITANCE NEGATIVE THRESHOLD OUTPUT ACTIVE
07726-035
INPUT INSIDE THRESHOLD WINDOW
07726-034
OUTPUT
TIME
Figure Threshold Sensitivity
OUTPUT TIME
Figure In-Window (Adaptive) Threshold Mode
Rev. Page
AD7156
DATA AVERAGE
adaptive threshold algorithm based average calculated from previous output data, using following equation:
Average(N Average(N Data(N Average(N 2ThrSettling
TIMEOUT
case large, long change capacitive input, when data average adapting condition takes long, timeout set. timeout becomes active (counting) when data goes outside band data average sensitivity. When timeout elapses defined number conversions counted), data average (and thus thresholds), forced follow data value immediately (see Figure 33). timeout independently approaching (for change data toward threshold) receding (for change data away from threshold). Figure Figure Register Descriptions section further information.
DATA AVERAGE SENSITIVITY DATA AVERAGE DATA AVERAGE SENSITIVITY LARGE CHANGE DATA
where: Average(N) average value. Average(N average value from previous cycle. Data(N) latest complete conversion result. ThrSettling parameter, programmable setup registers. more specific case input capacitance waveform step change. response average input capacitance step change (more exactly, response step change output data) exponential settling curve, which characterized following equation:
Average(N Average(0) Change(1 /TimeConst where: Average(N) value average complete conversion cycles after step change input. Average(0) value before step change. TimeConst 2(ThrSettling ThrSettling parameter, programmable setup registers. Figure Register Descriptions section further information.
INPUT CAPACITANCE (CDC DATA) CHANGE
TIMEOUT
TIME
Figure Threshold Timeout After Large Change Data
TIMEOUT APPROACHING INPUT CAPACITANCE THRESHOLD DATA AVERAGE
07726-038
DATA AVERAGE RESPONSE TIME
OUTPUT ACTIVE OUTPUT
07726-042
Figure Data Average Response Data Step Change
TIME
HYSTERESIS
adaptive threshold mode, comparator features hysteresis. hysteresis fixed threshold sensitivity programmed off. comparator does have hysteresis fixed threshold mode.
DATA POSITIVE THRESHOLD
Figure Approaching Timeout Negative Threshold Mode Shortens False Output Trigger
TIMEOUT RECEDING
LARGE CHANGE
HYSTERSIS
INPUT CAPACITANCE THRESHOLD
DATA AVERAGE OUTPUT ACTIVE
07726-040
OUTPUT ACTIVE OUTPUT TIME
07726-041
OUTPUT
TIME
Figure Threshold Hysteresis
Figure Positive Timeout Negative Threshold Mode Shortens Period Missing Output Trigger
Rev. Page
07726-043
AD7156
AUTO-DAC ADJUSTMENT
adaptive threshold mode, part dynamically adjust CAPDAC keep optimal operating capacitive range. When auto-DAC function enabled, CAPDAC value automatically incremented when data average exceeds full range (average 0xA800), CAPDAC value decremented when data average goes below full range (average 0x5800). auto-DAC increment decrement step depends selected capacitive input range (see Setup Registers section). When CAPDAC value reaches threshold further decrementing ignored. Similarly, when CAPDAC value reaches full range, threshold ignored. rest algorithm continuously working, they functional down capacitance input high capacitance input (CAPDAC full range full range), respectively.
POWER-DOWN TIMER
power sensitive applications, AD7156 automatically enter power-down mode after programmed period time which outputs have been activated. AD7156 then returned normal operational mode either serial interface power supply off/on sequence.
Rev. Page
AD7156 REGISTER DESCRIPTIONS
Table Register Summary
Register Status Data High Data Data High Data Average High Average Average High Average Sensitivity/ Threshold High Timeout/ Threshold Setup Sensitivity/ Threshold High Timeout/ Threshold Setup Configuration Power-Down Timer CAPDAC CAPDAC Serial Number Serial Number Serial Number Serial Number Chip
Addr Pointer 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
PwrDown
DacStep2
OUT2
DacStep1
OUT1
C1/C2
RDY2
RDY1
0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
sensitivity adaptive threshold mode)/Ch threshold high byte fixed threshold mode) 0x08 timeout adaptive threshold mode)/CH 1threshold byte fixed threshold mode) 0x86 RngH1 RngL1 Hyst1 ThrSettling1 (4-bit value) (0x0B) sensitivity adaptive threshold mode)/Ch threshold high byte fixed threshold mode) 0x08 timeout adaptive threshold mode)/Ch threshold byte fixed threshold mode) 0x86 RngH2 ThrFixed RngL2 ThrMD1 ThrMD0 Hyst2 ThrSettling2 (4-bit value) (0x0B) EnCh1 EnCh2 Power-down timeout (6-bit value) (0x00) DacValue1 (6-bit value) (0x00) DacValue2 (6-bit value) (0x00)
DacEn1 DacAuto1 DacEn2 DacAuto2 Serial number-Byte (MSB) Serial number-Byte Serial number-Byte Serial number-Byte (LSB) Chip identification code
default values given parentheses.
Rev. Page
AD7156
STATUS REGISTER
Address Pointer 0x00 Bits, Read Only Default Value 0x53 Before Conversion, 0x54 After Conversion
status register indicates status part. register read 2-wire serial interface query status outputs, check finished conversion, check whether CAPDAC been changed auto-DAC function.
Table Status Register
PwrDown
DacStep2
OUT2
DacStep1
OUT1
C1/C2
RDY2
RDY1
default values given parentheses.
Table Status Register Descriptions
Mnemonic PwrDown DacStep2 OUT2 DacStep1 OUT1 C1/C2 RDY2 RDY1 Description PwrDown indicates that part power-down. DacStep2 indicates that Channel CAPDAC value changed after last conversion part auto-DAC function. value updated after each finished conversion this channel. OUT2 indicates that Channel data (CIN2 capacitance) crossed threshold, according selected comparator mode operation. value updated after each finished conversion this channel. DacStep1 indicates that Channel CAPDAC value changed during last conversion part auto-DAC function. value updated after each finished conversion this channel. OUT1 indicates that Channel data (CIN1 capacitance) crossed threshold, according selected comparator mode operation. value updated after each finished conversion this channel. C1/C2 indicates that last finished conversion Channel C1/C2 indicates that last finished conversion Channel RDY2 indicates finished conversion Channel reset back when Channel data register read serial interface after part reset power-up. RDY1 indicates finished conversion Channel reset back when Channel data register read serial interface after part reset power-up.
Rev. Page
AD7156
DATA REGISTERS
Address Pointer 0x01, Address Pointer 0x02 Address Pointer 0x03, Address Pointer 0x04 Bits, Read Only Default Value 0x0000
Data from last complete capacitance-to-digital conversion reflects capacitance input. Only MSBs data registers used result. LSBs always shown Figure data register updated after finished conversion capacitive channel, with exception: when serial interface read operation from data register progress, data register updated capacitance conversion result lost. stop condition serial interface considered read operation. Therefore, prevent incorrect data reading through serial interface, bytes data register should read sequentially using register address pointer autoincrement feature serial interface. nominal AD7156 transfer function ideal transfer function excluding offset and/or gain error) maps input capacitance between zero scale full scale output data codes between 0x3000 0xD000 only (see Table ideal part, linear, with offset error gain error, input capacitance calculated from output data using following equation:
(pF)
Data 12,288 40,960
Input Range (pF)
where Input_Range following same equation written with hexadecimal numbers:
(pF) Data x3000 xA000 Input Range (pF)
With offset error gain error included, equation
(pF)
Input Range (pF) 40,960 Gain Error(%) Offset Error (pF) 100%
Data x3000
Data 12,288
same equation with hexadecimal numbers:
(pF) Input Range (pF) xA000 Gain Error(%) Offset Error (pF) 100%
DATA HIGH
DATA
12-BIT RESULT
07726-044
Figure Data Register
Table AD7156 Capacitance-to-Data Mapping
Data 0x0000 0x3000 0x5800 0x8000 0xA800 0xD000 0xFFF0
Input Capacitance Under range (below Zero scale Quarter scale (+0.5 pF)-auto-DAC step down Midscale Three-quarter scale (+1.5 pF)-auto-DAC step Full scale Over range (above
ideal part with offset gain error, values shown picofarad capacitance input range.
Rev. Page
AD7156
AVERAGE REGISTERS
Address Pointer 0x05, Address Pointer 0x06 Address Pointer 0x07, Address Pointer 0x08 Bits, Read Only Default Value 0x0000
These registers show average calculated from previous data. 12-bit result corresponds MSBs average register. settling time average programming ThrSettling bits setup registers. average register overwritten directly with output data, that history erased timeout enabled elapses. ideal part with gain error, sensitivity calculated using following equation:
Sensitivity (pF) Sens Input Range (pF) 2560
same equation with hexadecimal numbers
Sensitivity (pF)
Sens Input Range (pF) xA00
With gain error included, sensitivity calculated using following equation:
FIXED THRESHOLD REGISTERS
Address Pointer 0x09, Address Pointer 0x0A Address Pointer 0x0C, Address Pointer 0x0D Bits, Read/Write, Factory Preset 0x0886
constant threshold output comparator fixed threshold mode using these registers. 12-bit result corresponds MSBs threshold register. fixed threshold registers share address pointer location chip with sensitivity timeout registers. fixed threshold registers accessible adaptive threshold mode.
Sense Input Range (pF) 2560 Gain Error 100% Sensitivity (pF) same equation with hexadecimal numbers
Sense Input Range (pF) xA00 Gain Error 100% Sensitivity (pF)
TIMEOUT REGISTERS
Address Pointer 0x0A Address Pointer 0x0D Bits, Read/Write, Factory Preset 0x86
Table Timeout Register
[7:4] [3:0] Mnemonic TimeOutApr TimeOutRec Default 0x08 0x06
SENSITIVITY REGISTERS
Address Pointer 0x09 Address Pointer 0x0C Bits, Read/Write, Factory Preset 0x08
Sensitivity registers distance positive threshold above data average, distance negative threshold below data average, adaptive threshold mode.
DATA POSITIVE THRESHOLD SENSITIVITY DATA AVERAGE SENSITIVITY NEGATIVE THRESHOLD OUTPUT ACTIVE
07726-045
These registers timeouts adaptive threshold mode. approaching timeout starts when data crosses data average sensitivity band toward threshold, according selected positive, negative, window threshold mode. approaching timeout elapses after number conversion cycles equals 2TimeOutApr, where TimeOutApr value four most significant bits timeout register. receding timeout starts when data crosses data average sensitivity band away from threshold, according selected positive negative threshold mode. receding timeout used window threshold mode. receding timeout elapses after number conversion cycles equals 2TimeOutRec, where TimeOutRec value four least significant bits timeout register. When either approaching receding timeout elapses (that after defined number conversions counted), data average (and thus thresholds) forced follow data value immediately. When timeout register equals timeouts disabled.
TIME
Figure Threshold Sensitivity
sensitivity 8-bit value mapped lower eight bits 12-bit data, that corresponds 16-bit data register shown Figure
SENSITIVITY
DATA HIGH
DATA
07726-046
12-BIT RESULT
Figure Relation Between Sensitivity Register Data Register
Rev. Page
AD7156
SETUP REGISTERS
Address Pointer 0x0B Address Pointer 0x0E Bits, Read/Write, Factory Preset 0x0B
Table Setup Registers
RngH
RngL
Hyst
ThrSettling (4-Bit Value) (0x0B)
default values given parentheses.
Table Setup Registers Descriptions
Mnemonic RngH RngL Description Range bits input range determine step auto-DAC function. RngH RngL Capacitive Input Range (pF) Auto-DAC Step (CAPDAC LSB) [3:0] Hyst ThrSettling
This should specified operation. Hyst disables hysteresis adaptive threshold mode. This effect fixed threshold mode; hysteresis always disabled fixed threshold mode. Determines dynamic behavior data average thus settling time adaptive thresholds. Data average calculated from previous output data, using equation:
Average( Average(
Data( Average(N ThrSettling
where: Average(N) average value. Average(N average value from previous cycle. Data(N) latest complete conversion result. ThrSettling programmable parameter. response average input capacitance step change (that response change output data) exponential settling curve characterized following equation:
Average(N Average( Change(1 TimeConst
where: Average(N) value average complete conversion cycles after step change input. Average(0) value before step change. TimeConst selected range between 65,536 conversion cycle multiples, steps power programming ThrSettling bits. TimeConst 2(ThrSettling
INPUT CAPACITANCE (CDC DATA) CHANGE
TIME
Figure Data Average Response Data Step Change
Rev. Page
07726-049
DATA AVERAGE RESPONSE
AD7156
CONFIGURATION REGISTER
Address Pointer 0x0F Bits, Read/Write, Factory Preset 0x19
Table Configuration Register
ThrFixed
ThrMD1
ThrMD0
EnCh1
EnCh2
default values given parentheses.
Table 13.Configuration Register Descriptions
Mnemonic ThrFixed Description ThrFixed sets fixed threshold mode; outputs reflect comparison data fixed (constant) value threshold registers. ThrFixed sets adaptive threshold mode; outputs reflect comparison data adaptive thresholds. adaptive threshold dynamically, based history previous data. These bits output comparators mode Output Active When ThrMD1 ThrMD0 Threshold Mode Adaptive Threshold Mode Fixed Threshold Mode Negative Data average sensitivity Data threshold Positive Data average sensitivity Data threshold In-window Data average sensitivity Data average sensitivity Out-window Data average sensitivity Data average sensitivity Enables conversion Channel Enables conversion Channel Converter mode operation setup Mode Description Idle part fully powered performing conversion. Continuous part repeatedly performing conversions Conversion enabled channel(s); channels enabled, part sequentially switching between them. Single conversion part performs single conversion enabled channel; channels enabled, part performs conversions, each channel. After finishing conversion(s), part goes idle mode. Power-down part powers down on-chip circuits, except digital interface. Reserved these modes.
ThrMD1 ThrMD0
EnCh1 EnCh2
Rev. Page
AD7156
POWER-DOWN TIMER REGISTER
Address Pointer 0x10 Bits, Read/Write, Factory Preset 0x40
Table Power-Down Timer Register
Power-down timeout (6-bit value) (0x00)
default values given parentheses.
Table 15.Power-Down Timer Register Descriptions
[5:0] Mnemonic Description This must proper operation. This must proper operation. This defines period duration power-down timeout. comparator outputs have been activated during programmed period, part enters power-down mode automatically. part then returned normal operational mode either serial interface power supply off/on sequence. period programmable steps hours. example, setting value 0x06 sets duration hours. maximum value 0x3F corresponds approximately 10.5 days. value 0x00 disables power-down timeout, part does enter power-down mode automatically.
Power-down timeout
CAPDAC REGISTERS
Address Pointer 0x11 Address Pointer 0x12 Bits, Read/Write, Factory Preset 0xC0
Table CAPDAC Registers
DacEn
DacAuto
DacValue (6-bit value) (0x00)
default values given parentheses.
Table CAPDAC Registers Descriptions
Mnemonic DacEn DacAuto Description DacEn enables capacitive DAC. DacAuto enables auto-DAC function adaptive threshold mode. When auto-DAC function enabled, part dynamically adjusts CAPDAC keep optimal operating capacitive range. CAPDAC value automatically incremented when data average exceeds full range, CAPDAC value decremented when data average goes below full range. auto-DAC increment decrement step depends selected capacitive input range. This effect fixed threshold mode; auto-DAC function always disabled fixed threshold mode. CAPDAC value, Code 0x00 Code 0x3F CAPDAC full range.
[5:0]
DacValue
SERIAL NUMBER REGISTER
Address Pointer 0x13, Address Pointer 0x14, Address Pointer 0x15, Address Pointer 0x16 Bits, Read Only, Factory Preset 0xXXXX
This register holds serial number, unique each individual part.
CHIP REGISTER
Address Pointer 0x17 Bits, Read Only, Factory Preset 0xXX
This register holds chip identification code, used factory manufacturing testing.
Rev. Page
AD7156 SERIAL INTERFACE
AD7156 supports I2C-compatible, 2-wire serial interface. wires serial (interface) called (clock) (data). These wires carry addressing, control, data information time over connected peripheral devices. wire carries data, while wire synchronizes sender receiver during data transfer. devices classified either master slave devices. device that initiates data transfer message called master, whereas device that responds this message called slave. control AD7156 device bus, following protocol must utilized. First, master initiates data transfer establishing start condition, defined highto-low transition while remains high. This indicates that start byte follows. This 8-bit start byte made 7-bit address plus indicator. peripherals connected respond start condition shift next eight bits (7-bit address bit). bits arrive first. peripheral that recognizes transmitted address responds pulling data line during ninth clock pulse. This known acknowledge bit. other devices withdraw from this point maintain idle condition. exception this general call address, which described General Call section. idle condition, device monitors lines waiting start condition correct address byte. determines direction data transfer. Logic start byte means that master writes information addressed peripheral. this case, AD7156 becomes slave receiver. Logic start byte means that master reads information from addressed peripheral. this case, AD7156 becomes slave transmitter. instances, AD7156 acts standard slave device serial bus. start byte address AD7156 0x90 write 0x91 read. continuous conversion mode, address pointers' autoincrementer should used reading conversion result. This means that data bytes should read using multibyte read transaction rather than separate single byte transactions. single byte data read transaction result data bytes from different results being mixed. same applies four data bytes both capacitive channels enabled. user also access unique register (address) one-to-one basis without having update registers. address pointer register contents cannot read. incorrect address pointer location accessed user allows autoincrementer exceed required register address, following applies:
read mode, AD7156 continues output various internal register contents until master device issues acknowledge, start, stop condition. address pointers' autoincrementer contents reset point status register 0x00 address when stop condition received read operation. This allows status register read (polled) continually without having constantly write address pointer. write mode, data invalid address loaded into AD7156 registers, acknowledge issued AD7156.
WRITE OPERATION
When write selected, byte following start byte always register address pointer (subaddress) byte, which points internal registers AD7156. address pointer byte automatically loaded into address pointer register acknowledged AD7156. After address pointer byte acknowledge, stop condition, repeated start condition, another data byte follow from master. stop condition defined low-to-high transition while remains high. stop condition encountered AD7156, returns idle condition address pointer reset 0x00. data byte transmitted after register address pointer byte, AD7156 loads this byte into register that currently addressed address pointer register sends acknowledge, address pointer autoincrementer automatically increments address pointer register next internal register address. Thus, subsequent transmitted data bytes loaded into sequentially incremented addresses.
READ OPERATION
When read selected start byte, register that currently addressed address pointer transmitted line AD7156. This then clocked master device, AD7156 awaits acknowledge from master. acknowledge received from master, address autoincrementer automatically increments address pointer register outputs next addressed register content line transmission master. acknowledge received, AD7156 returns idle state address pointer incremented. address pointers' autoincrementer allows block data written read from starting address subsequent incremental addresses.
Rev. Page
AD7156
repeated start condition encountered after address pointer byte, peripherals connected respond exactly outlined previously start condition; that repeated start condition treated same start condition. When master device issues stop condition, relinquishes control bus, allowing another master device take control bus. Therefore, master wanting retain control issues successive start conditions known repeated start conditions.
GENERAL CALL
When master issues slave address consisting seven with eighth (R/W) this known general call address. general call address addressing every device connected serial bus. AD7156 acknowledges this address reads following data byte. second byte 0x06, AD7156 reset, completely uploading default values. AD7156 does respond serial commands acknowledge) during default values upload approximately AD7156 does acknowledge other general call commands.
AD7156 RESET
reset AD7156 without having reset entire serial bus, explicit reset command provided. This uses particular address pointer word command word reset part upload default settings. AD7156 does respond serial commands acknowledge) during default values upload approximately reset command address word 0xBF.
START ADDR SUBADDRESS
DATA
STOP
Figure Data Transfer
WRITE SEQUENCE
SLAVE ADDR
A(S)
ADDR
A(S)
DATA
A(S)
DATA
A(S)
READ SEQUENCE SLAVE ADDR START STOP A(S) ADDR A(S)
07726-050
SLAVE ADDR
A(S)
DATA
A(M)
DATA
A(M)
07726-051
A(S) ACKNOWLEDGE SLAVE A(M) ACKNOWLEDGE MASTER
A(S) ACKNOWLEDGE SLAVE A(M) ACKNOWLEDGE MASTER
Figure Write Read Sequences
Rev. Page
AD7156 HARDWARE DESIGN CONSIDERATIONS
OVERVIEW
AD7156 interface capacitive sensors. input side, Sensor connected directly between AD7156 pins. connected electrical parameters sensor connection, such parasitic resistance capacitance, affect system performance. Therefore, circuit with additional components capacitive front end, such overvoltage protection, carefully designed, considering AD7156 specified limits information provided this section. output side, AD7156 work standalone device, using power-up default register settings flagging result digital outputs. Alternatively, AD7156 interfaced microcontroller 2-wire serial interface, offering flexibility overwriting AD7156 register values from host with user-specific setup.
RGND1 DATA
PARASITIC RESISTANCE GROUND
RGND2
Figure Parasitic Resistance Ground
PARASITIC CAPACITANCE GROUND
AD7156 result affected leakage current from ground; therefore, should isolated from ground. equivalent resistance between ground should maximized (see Figure 43). more information, Figure Figure
PARASITIC PARALLEL RESISTANCE
CGND1 DATA
DATA
CGND2
07726-052
Figure Parasitic Capacitance Ground Figure Parasitic Parallel Resistance
architecture used AD7156 measures capacitance, connected between pins pins. theory, capacitance, CGND, ground should affect result (see Figure 42). practical implementation circuitry chip implies certain limits, result gradually affected capacitance ground (for information about allowed capacitance information about excitation Table Figure Figure
AD7156 measures charge transfer between pins. resistance connected parallel measured capacitance, (see Figure 44), such parasitic resistance sensor, also transfers charge. Therefore, parallel resistor seen additional capacitance output data. equivalent parallel capacitance error caused parallel resistance) approximately calculated
where: parallel resistance. fEXC excitation frequency. additional information, Figure
Rev. Page
07726-054
07726-053
AD7156
PARASITIC SERIAL RESISTANCE INPUT PROTECTION
68pF 22pF
07726-057
DATA
47pF
Figure AD7156 Protection
07726-055
Figure Parasitic Serial Resistance
AD7156 result affected resistance series with measured capacitance. total serial resistance (RS1 Figure should order hundreds (see Figure 14).
Some applications require additional input filter improving EMC. input filter must carefully designed, considering balance between system capacitance performance system electromagnetic immunity. Figure shows possible input circuit configurations significantly improving system immunity against high frequency noise while only slightly affecting AD7156 performance terms additional gain offset error.
INPUT OVERVOLTAGE PROTECTION
POWER SUPPLY DECOUPLING FILTERING
0.1µF 10µF
07726-056
Figure AD7156 Overvoltage Protection
Figure AD7156 Decoupling Filtering
AD7156 capacitive input internal protection. However, some applications require additional overvoltage protection, depending application-specific requirements. additional circuit capacitive front must carefully designed, especially with respect limits recommended maximum capacitance ground, maximum serial resistance, maximum leakage,
AD7156 good frequency power supply rejection sensitive higher frequency ripple noise, specifically around excitation frequency harmonics. Figure shows possible circuit configuration improving system immunity against ripple noise coupled AD7156 power supply. serial interface connected other circuits system, better connect pull-up resistors other side filter than connect AD7156. AD7156 used standalone mode serial interface used, better connect pull-up resistors directly AD7156 VDD.
Rev. Page
07726-058
AD7156
APPLICATION EXAMPLES
0.1µF
CIN1 CSENS1 EXC1 CIN2 CSENS2 EXC2
AD7156
OUT1 OUT2 LED1 LED2 BATTERY
Figure AD7156 Standalone Operation Application Diagram
3.3V 0.1µF
CIN1 CSENS1 EXC1 CIN2 CSENS2 EXC2
AD7156
HOST MICROCONTROLLER
OUT1 OUT2
IRQ1 IRQ2
07726-059
Figure AD7156 Interfaced Host Microcontroller
07726-060
0.1µF CSENS1 68pF CIN1 22pF EXC1 47pF CSENS2 68pF CIN2 22pF EXC2 47pF OUT2 10µF
3.3V
ADP1720-3.3
VSUPPLY
AD7156
OUT1
OUT1
OUT2
07726-061
Figure AD7156 Standalone Operation with Protection
Rev. Page
AD7156 OUTLINE DIMENSIONS
3.00 0.30 0.23 0.18
*EXPOSED (BOTTOM VIEW)
0.50
INDEX AREA 0.50 0.40 0.30
VIEW
1.74 1.64 1.49
0.80 0.75 0.70 SEATING PLANE
0.80 0.55
2.48 2.38 2.23 0.05 0.02
INDICATOR 0.20)
0.20 *FOR PROPER CONNECTION EXPOSED PLEASE REFER CONFIGURATION FUNCTION DESCRIPTIONS SECTION THIS DATA SHEET.
031208-B
Figure 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] Body, Very Thin, Dual Lead (CP-10-9) Dimensions shown millimeters
ORDERING GUIDE
Model AD7156BCPZ-REEL AD7156BCPZ-REEL71 EVAL-AD7156EBZ1
Temperature Range -40°C +85°C -40°C +85°C
Package Description 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] Evaluation Board
Package Option CP-10-9 CP-10-9
Branding
RoHS Compliant Part.
Rev. Page
AD7156 NOTES
Purchase licensed components Analog Devices sublicensed Associated Companies conveys license purchaser under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
©2008 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D07726-0-10/08(0)
Rev. Page
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