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9DB633 - 9DB633
Output Differential Buffer PCIe Gen3
Recommended Application: output PCIe Gen3 zero-delay/fanout buffer General Description: 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible PCIe Gen2 Gen1. 9DB633 driven differential output pair from 932S421 932SQ420 equivalent main clock generator. attenuates jitter input clock selectable bandwidth maximize performance systems with without Spread-Spectrum clocking. SMBus interface allows control bandwidth bypass options, while clock request (OE#) pins make 9DB633 suitable Express Card applications. Specifications: Cycle-to-cycle jitter Output-to-output skew PCIe Gen3 phase jitter 1.0ps Block Diagram
9DB633
Features/Benefits: pins/Suitable Express Card applications bypass mode/PLL dejitter incoming clock Selectable bandwidth/minimizes jitter peaking downstream PLL's Spread Spectrum Compatible/tracks spreading input clock SMBus Interface/unused outputs disabled Output Features: 0.7V current mode differential HSCL output pairs
OE1# OE4#
DIF1 SRC_IN SRC_IN# SPREAD COMPATIBLE DIF4
PLL_BW SMBDAT SMBCLK
DIF(0,2,3,5) CONTROL LOGIC
IREF
IDT® Output Differential Buffer PCIe Gen3
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
Configuration
PLL_BW SRC_IN SRC_IN# **OE1# DIF_0 DIF_0# DIF_1 DIF_1# DIF_2 DIF_2# SMBDAT
VDDA GNDA IREF **OE4# DIF_5 DIF_5# DIF_4 DIF_4# DIF_3 DIF_3# SMBCLK
Note:Pins preceeded '**' have internal 120K pull down resistors
Power Distribution Table
Number 8,21
Description Differential Outputs SMBus IREF Analog core
IDT® Output Differential Buffer PCIe Gen3
9DB633
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
Description
NAME PLL_BW SRC_IN SRC_IN# **OE1# DIF_0 DIF_0# DIF_1 DIF_1# DIF_2 DIF_2# SMBDAT SMBCLK DIF_3# DIF_3 DIF_4# DIF_4 DIF_5# DIF_5 **OE4# TYPE DESCRIPTION 3.3V input selecting Band Width low, high Differential TRUE input Differential COMPLEMENTARY input Active input enabling pair =disable outputs, enable outputs 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output Power supply, nominal 3.3V Data SMBUS circuitry, tolerant Clock SMBUS circuitry, tolerant Power supply, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output 0.7V differential Complementary clock output 0.7V differential true clock output Ground pin. Power supply, nominal 3.3V 0.7V differential Complementary clock output 0.7V differential true clock output Active input enabling pair =disable outputs, enable outputs This establishes reference current differential current-mode output pairs. This requires fixed precision resistor tied ground order establish appropriate current. ohms standard value. Ground core. 3.3V power core.
IREF GNDA VDDA
Note: Pins preceeded '**' have internal 120K pull down resistors
IDT® Output Differential Buffer PCIe Gen3
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
CONDITIONS UNITS NOTES
Electrical Characteristics Absolute Maximum Ratings
PARAMETER 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Input Voltage Input High Voltage Input High Voltage Storage Temperature Junction Temperature Input protection
SYMBOL VDDA VIHSMB prot
DD+0.5V 5.5V
GND-0.5 Except SMBus interface SMBus clock data pins Human Body Model 2000
Guaranteed design characterization, 100% tested production. Operation under these conditions neither implied guaranteed.
Electrical Characteristics Input/Supply/Common Parameters
TCOM TIND; Supply Voltage +/-5% PARAMETER SYMBOL Ambient Operating Temperature Input High Voltage Input Voltage TCOM TIND Input Current Fibyp Fipll Lpin CINDIF_IN COUT Stabilization Input Modulation Frequency Latency Tdrive_PD# Tfall Trise SMBus Input Voltage SMBus Input High Voltage SMBus Output Voltage SMBus Sink Current Nominal Voltage SCLK/SDATA Rise Time SCLK/SDATA Fall Time SMBus Operating Frequency
CONDITIONS
-200
UNITS NOTES
Commmercial range Industrial range Single-ended inputs, except SMBus, threshold tri-level inputs Single-ended inputs, except SMBus, threshold tri-level inputs Single-ended inputs, GND, Single-ended inputs Inputs with internal pull-up resistors VDD; Inputs with internal pull-down resistors Bypass mode 100MHz mode Logic Inputs, except DIF_IN DIF_IN differential clock inputs Output capacitance From Power-Up after input clock stabilization de-assertion clock Allowable Frequency (Triangular Modulation) start after assertion stop after deassertion output enable after de-assertion Fall time control inputs Rise time control inputs
Input Frequency Inductance Capacitance
100.00
TSTAB
MODIN
LATOE# DRVPD ILSMB IHSMB OLSMB PULLUP DDSMB RSMB FSMB MAXSMB
cycles
PULLUP (Max 0.15) (Min 0.15) (Min 0.15) (Max 0.15) Maximum SMBus operating frequency
VDDSMB 1000
Guaranteed design characterization, 100% tested production. Control input must monotonic from input swing. Time from deassertion until outputs >200 DIF_IN input
differential input clock must running SMBus active IDT® Output Differential Buffer PCIe Gen3
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
Electrical Characteristics Clock Input Parameters
TCOM TIND; Supply Voltage +/-5% PARAMETER Input High Voltage DIF_IN Input Voltage DIF_IN Input Common Mode Voltage DIF_IN Input Amplitude DIF_IN Input Slew Rate DIF_IN Input Leakage Current Input Duty Cycle Input Jitter Cycle Cycle
SYMBOL VIHDIF VILDIF VCOM VSWING dv/dt dtin DIFIn
CONDITIONS Differential inputs (single-ended measurement) Differential inputs (single-ended measurement) Common Mode Input Voltage Peak Peak value Measured differentially Measurement from differential wavefrom Differential Measurement
1150 1000 1450
UNITS NOTES V/ns
Guaranteed design characterization, 100% tested production. Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics 0.7V Current Mode Differential Outputs
TCOM TIND; Supply Voltage +/-5% CONDITIONS UNITS NOTES V/ns Scope averaging Slew rate matching, Scope averaging Statistical measurement single-ended signal Voltage High VHigh using oscilloscope math function. (Scope averaging Voltage VLow -150 Measurement single ended signal using absolute Voltage Vmax 1150 value. (Scope averaging off) Voltage Vmin -300 Vswing Vswing Scope averaging 1506 Crossing Voltage (abs) Vcross_abs Scope averaging Crossing Voltage (var) -Vcross Scope averaging Guaranteed design characterization, 100% tested production. IREF VDD/(3xRR). (1%), IREF 2.32mA. IREF 0.7V ZO=50 (100 differential impedance). Slew rate Slew rate matching
PARAMETER
SYMBOL
Measured from differential waveform Slew rate measured through Vswing voltage range centered around differential This results +/-150mV window around differential
Matching applies rising edge rate Clock falling edge rate Clock#. measured using +/-75mV window centered average cross point where Clock rising meets Clock# falling. median cross point used calculate voltage thresholds oscilloscope edge rate calculations.
Vcross defined voltage where Clock Clock# measured component test board only applies differential rising edge (i.e. Clock rising Clock# falling). total variation Vcross measurements particular system. Note that this subset V_cross_min/max (V_cross absolute) allowed. intent limit Vcross induced modulation setting V_cross_delta smaller than V_cross absolute.
Electrical Characteristics Current Consumption
TCOM TIND; Supply Voltage +/-5% PARAMETER SYMBOL Operating Supply Current Powerdown Current
CONDITIONS
UNITS NOTES
IDD3.3OP DD3.3PD DD3.3PDZ
outputs active @100MHz, Full load; diff pairs driven differential pairs tri-stated
Guaranteed design characterization, 100% tested production.
IDT® Output Differential Buffer PCIe Gen3
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
Electrical Characteristics Output Duty Cycle, Jitter, Skew Characterisitics
TCOM TIND; Supply Voltage +/-5% PARAMETER Bandwidth Jitter Peaking Duty Cycle Duty Cycle Distortion Skew, Input Output Skew, Output Output Jitter, Cycle cycle
SYMBOL JPEAK pdBYP pdPLL tjcyc-cyc
CONDITIONS -3dB point High Mode -3dB point Mode Peak Pass band Gain Measured differentially, Mode Measured differentially, Bypass Mode @100MHz Bypass Mode, Mode mode Additive Jitter Bypass Mode
2500 -250
3660
4500
UNITS NOTES
Guaranteed design characterization, 100% tested production. VDD/(3xRR). (1%), 2.32mA. 0.7V ZO=50. Measured from differential waveform Duty cycle distortion difference duty cycle between output input clock when device operated bypass mode.
Electrical Characteristics PCIe Phase Jitter Parameters
TCOM TIND; Supply Voltage +/-5% PARAMETER SYMBOL jphPCIeG1 jphPCIeG2 CONDITIONS PCIe PCIe Band 10kHz 1.5MHz PCIe High Band 1.5MHz Nyquist (50MHz) PCIe (PLL 2-4MHz, 10MHz) PCIe PCIe Band 10kHz 1.5MHz PCIe High Band 1.5MHz Nyquist (50MHz) PCIe (PLL 2-4MHz, 10MHz) UNITS Notes (p-p) 1,2,3 (rms) (rms) 1,2,4 (rms) (p-p) (rms) (rms) (rms) 1,2,3 1,2,4
Phase Jitter, Mode
jphPCIeG3 jphPCIeG1 Additive Phase Jitter, Bypass Mode
jphPCIeG2
jphPCIeG3
Applies outputs. http://www.pcisig.com complete specs Sample size least 100K cycles. This figures extrapolates 108ps pk-pk cycles 1-12. Subject final radification SIG.
IDT® Output Differential Buffer PCIe Gen3
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
Unit inch inch inch Figure
Reference Clock Common Recommendations Differential Routing Dimension Value length, route non-coupled 50ohm trace length, route non-coupled 50ohm trace length, route non-coupled 50ohm trace 49.9 Down Device Differential Routing length, route coupled microstrip 100ohm differential trace length, route coupled stripline 100ohm differential trace 14.4 Differential Routing Express Connector length, route coupled microstrip 100ohm differential trace 0.25 length, route coupled stripline 100ohm differential trace 0.225 12.6
inch inch
inch inch
Figure Down Device Routing
Express Down Device REF_CLK Input
HCSL Output Buffer
Figure Express Connector Routing
Express Add-in Board REF_CLK Input
HCSL Output Buffer
IDT® Output Differential Buffer PCIe Gen3
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
Alternative Termination LVDS other Common Differential Signals (figure Vdiff Vp-p Note 0.45v 0.22v 1.08 0.58 0.28 78.7 0.80 0.40 78.7 none ICS874003i-02 input compatible 0.60 Standard LVDS
Figure
HCSL Output Buffer
Down Device REF_CLK Input
Cable Connected Coupled Application (figure Component Value Note R5a, 8.2K R6a, 0.350 volts
Figure
Volts
PCIe Device REF_CLK Input
IDT® Output Differential Buffer PCIe Gen3
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
General SMBus serial interface information 9DB633 Write:
Controller (host) sends start bit. Controller (host) sends write address clock will acknowledge Controller (host) sends begining byte location clock will acknowledge Controller (host) sends data byte count clock will acknowledge Controller (host) starts sending Byte through Byte (see Note clock will acknowledge each byte time Controller (host) sends Stop
Read:
Controller (host) will send start bit. Controller (host) sends write address clock will acknowledge Controller (host) sends begining byte location clock will acknowledge Controller (host) will send separate start bit. Controller (host) sends read address clock will acknowledge clock will send data byte count clock sends Byte clock sends Byte through byte X(H) written byte Controller (host) will need acknowledge each byte Controllor (host) will send acknowledge Controller (host) will send stop
Index Block Write Operation
Controlle (Host) starT Slave Address D4(H Rite Beginning Byte Data Byte Count Beginning Byte Byte (Sla
Index Block Read Operation
Controlle (Host) starT Slave Address D4(H Rite Beginning Byte Repeat starT Slave Address D3(H ReaD Data Byte Count Beginning Byte Byte (Sla
Byte stoP
Byte acknowledge stoP
IDT® Output Differential Buffer PCIe Gen3
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
SMBusTable: Device Control Register, READ/WRITE ADDRESS (D4/D5) Byte Name Control Function Type Default controlled Enables SMBus controlled SW_EN SMBus Control device pins registers RESERVED RESERVED RESERVED RESERVED RESERVED Selects High #adjust Bandwidth bypassed enabled Bypasses Enable (fan mode) (ZDB mode) board test SMBusTable: Output Enable Byte 24,23 18,17 11,12 Register Name Control Function Type RESERVED RESERVED PCIEX5 Output Control RESERVED PCIEX3 Output Control PCIEX2 Output Control RESERVED PCIEX0 Output Control
Disable Disable Disable Disable
Enable Enable Enable Enable
Default
SMBusTable: Function Select Register Byte Name Control Function Type RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SMBusTable: Vendor Revision Register Byte Name Control Function Type RID3 RID2 REVISION RID1 RID0 VID3 VID2 VENDOR VID1 VID0
IDT® Output Differential Buffer PCIe Gen3
Default
Default
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
SMBusTable: DEVICE Byte
Name
Control Function Type Device
Default
SMBusTable: Byte Count Register Byte Name Control Function Writing this register will configure many bytes will read back, default bytes. Type Default
IDT® Output Differential Buffer PCIe Gen3
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
28-pin SSOP Package Drawing Dimensions
SSOP SYMBOL VARIATIONS (inch) 9.90 10.50 .390 .413 Millimeters COMMON DIMENSIONS -2.00 0.05 -1.65 1.85 0.22 0.38 0.09 0.25 VARIATIONS 7.40 8.20 5.00 5.60 0.65 BASIC 0.55 0.95 Inches COMMON DIMENSIONS -.079 .002 -.065 .073 .009 .015 .0035 .010 VARIATIONS .291 .323 .197 .220 0.0256 BASIC .022 .037
Reference Doc.: JEDEC Publication MO-150
10-0033
SSOP
IDT® Output Differential Buffer PCIe Gen3
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
28-pin TSSOP Package Drawing Dimensions
4.40 Body, 0.65 Pitch TSSOP (173 mil)
(25.6 mil) Inches COMMON DIMENSIONS -.047 .002 .006 .032 .041 .007 .012 .0035 .008 VARIATIONS 0.252 BASIC .169 .177 0.0256 BASIC .018 .030 VARIATIONS -.004
SYMBOL VARIATIONS
INDEX AREA
Millimeters COMMON DIMENSIONS -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 VARIATIONS 6.40 BASIC 4.30 4.50 0.65 BASIC 0.45 0.75 VARIATIONS -0.10
9.60 9.80 .378
(inch) .386
-CReference Doc.: JEDEC Publication MO-153
SEATING PLANE
10-0035
Ordering Information
Part Order Number 9DB633AFLF 9DB633AFLFT 9DB633AFILF 9DB633AFLIFT 9DB633AGLF 9DB633AGLFT 9DB633AGILF 9DB633AGILFT Shipping Packaging Tubes Tape Reel Tubes Tape Reel Tubes Tape Reel Tubes Tape Reel Package 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin SSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP 28-pin TSSOP Temperature +70°C +70°C +85°C +85°C +70°C +70°C +85°C +85°C
"LF" after package code Pb-Free configuration RoHS compliant. device revision designator (will correlate datasheet revision).
IDT® Output Differential Buffer PCIe Gen3
1668B-07/12/10
9DB633 Output Differential Buffer PCIe Gen3
Datasheet
Revision History
Rev. Originator Issue Date Description 4/30/2010 Initial release Updated names match other devices CLKREQ# becomes PCIEXyy becomes DIF_yy Updated maximum rise/fall time 550ps from 700ps. This translates minimum slew rate 0.67V/ns thus meeting PCIe spec 0.6V/ns. Updated phase jitter tables remove references QPI. Reformatted have common format amongst 9DBx33 6/3/2010 Updated block diagram match item 6/25/2010 Updated electrical tables standard format devices. 6/30/2010 Released final 7/12/2010 Changed "PWD" "Default" SMBus Register descriptions Page
10,11
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