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PIC18F6393/6493/8393/8493 Data Sheet
64/80-Pin High Performance, Flash Microcontrollers with Driver, 12-Bit nanoWatt Technology
2007 Microchip Technology Inc.
DS39896A
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, rfPIC SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2007, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS39896A-page
2007 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
64/80-Pin High-Performance, Flash Microcontrollers with Driver, 12-Bit nanoWatt Technology
Driver Module Features:
Direct Driving Panel Pixels: Software Selectable Programmable Timing module: Multiple timing sources available four commons: Static, 1/2, multiplex Static, bias configuration Drive Panel while Sleep mode Low-Power Operation
Peripheral Highlights:
12-Bit, 12-Channel Analog-to-Digital (A/D) Converter module: Auto-acquisition capability Conversion available during Sleep High-Current Sink/Source mA/25 Four External Interrupts Four Input Change Interrupts Four 8-Bit/16-Bit Timer/Counter modules Real-Time Clock (RTC) Software module: Configurable 24-hour clock, calendar, automatic 100-year 12,800-year, day-of-week calculator Uses Timer1 Capture/Compare/PWM (CCP) modules Master Synchronous Serial Port (MSSP) module Supporting Three-Wire (all four modes) I2CMaster Slave modes Addressable USART module: Supports RS-485 RS-232 Enhanced Addressable USART module: Supports RS-485, RS-232 Auto-wake-up Start Auto-Baud Detect Dual Analog Comparators with Input Multiplexing
Power-Managed Modes:
Run: Peripherals Idle: Off, Peripherals Sleep: Off, Peripherals mode Current Down Typical Idle mode Currents Down Typical Sleep mode Currents Down Typical Timer1 Oscillator: kHz, Watchdog Timer: Typical Two-Speed Oscillator Start-up
Flexible Oscillator Structure:
Four Crystal modes: HSPLL: 4-10 (16-40 internal) Phase Lock Loop (available crystal internal oscillators) External modes, External Clock modes, Internal Oscillator Block: Eight selectable frequencies, from Provides complete range clock speeds from when used with User-tunable compensate frequency drift Secondary Oscillator Using Timer1 Fail-Safe Clock Monitor: Allows safe shutdown device primary secondary clock fails
Special Microcontroller Features:
Compiler Optimized Architecture: Optional extended instruction designed optimize re-entrant code 1000 Erase/Write Cycle Flash Program Memory Typical Flash Retention: Years Typical Priority Levels Interrupts Single-Cycle Hardware Multiplier Extended Watchdog Timer (WDT): Programmable period from 132s stability over temperature In-Circuit Serial Programming(ICSPTM) Pins In-Circuit Debug (ICD) Pins Wide Operating Voltage Range: 2.0V 5.5V Note: This document supplemented "PIC18F6390/6490/8390/8490 Data Sheet" (DS39629). Section "Device Overview".
2007 Microchip Technology Inc.
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Program Memory Device Flash Single-Word SRAM (bytes) Instructions (bytes) 4096 8192 4096 8192 (pixel) 12-Bit (PWM) (channels) MSSP Master I2CY EUSART/ AUSART Data Memory Comparators Timers 8/16-Bit
PIC18F6393 PIC18F6493 PIC18F8393 PIC18F8493
Diagrams
64-Pin TQFP
RE7/CCP2(1)/SEG31
RE4/COM1
RE5/COM2
RE6/COM3
RD1/SEG1
RD2/SEG2
RD3/SEG3
RD4/SEG4
RD5/SEG5
RD6/SEG6
RD0/SEG0
RD7/SEG7
LCDBIAS3
COM0
LCDBIAS2 LCDBIAS1 RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28 RG3/SEG27 MCLR/VPP/RG5 RG4/SEG26 RF7/SS/SEG25 RF6/AN11/SEG24 RF5/AN10/CVREF/SEG23 RF4/AN9/SEG22 RF3/AN8/SEG21 RF2/AN7/C1OUT/SEG20
RB0/INT0 RB1/INT1/SEG8 RB2/INT2/SEG9 RB3/INT3/SEG10 RB4/KBI0/SEG11 RB5/KBI1 RB6/KBI2/PGC OSC2/CLKO/RA6 OSC1/CLKI/RA7 RB7/KBI3/PGD RC5/SDO/SEG12 RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1/SEG13
PIC18F6393 PIC18F6493
RF1/AN6/C2OUT/SEG19
RF0/AN5/SEG18
AVSS RA3/AN3/VREF+/SEG17
RA2/AN2/VREF-/SEG16
RA5/AN4/HLVDIN/SEG15
Note alternate CCP2 multiplexing.
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RA4/T0CKI/SEG14 RC1/T1OSI/CCP2(1)
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
RA1/AN1
RA0/AN0
AVDD
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Diagrams (Continued)
80-Pin TQFP
RH1/SEG46
RH0/SEG47
RE7/CCP2(1)/SEG31
RJ0/SEG32
RH2/SEG45 RH3/SEG44 LCDBIAS2 LCDBIAS1 RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28 RG3/SEG27 MCLR/VPP/RG5 RG4/SEG26 RF7/SS/SEG25 RF6/AN11/SEG24 RF5/AN10/CVREF/SEG23 RF4/AN9/SEG22 RF3/AN8/SEG21 RF2/AN7/C1OUT/SEG20 RH7/SEG43 RH6/SEG42 RJ2/SEG34 RJ3/SEG35 RB0/INT0 RB1/INT1/SEG8 RB2/INT2/SEG9 RB3/INT3/SEG10 RB4/KBI0/SEG11 RB5/KBI1 RB6/KBI2/PGC OSC2/CLKO/RA6 OSC1/CLKI/RA7 RB7/KBI3/PGD RC5/SDO/SEG12 RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1/SEG13 RJ7/SEG36 RJ6/SEG37
PIC18F8393 PIC18F8493
RF1/AN6/C2OUT/SEG19
RF0/AN5/SEG18
RJ4/SEG39
AVSS RA3/AN3/VREF+/SEG17
RA2/AN2/VREF-/SEG16
RA4/T0CKI/SEG14 RC1/T1OSI/CCP2(1)
RA5/AN4/HLVDIN/SEG15
Note alternate CCP2 multiplexing.
2007 Microchip Technology Inc.
RC0/T1OSO/T13CKI
RC7/RX1/DT1
RC6/TX1/CK1
RH5/SEG41
RH4/SEG40
RJ5/SEG38
RA1/AN1
RA0/AN0
AVDD
RJ1/SEG33
RE4/COM1
RE5/COM2
RE6/COM3
RD0/SEG0
RD1/SEG1
RD2/SEG2
RD3/SEG3
RD4/SEG4
RD5/SEG5
RD6/SEG6
RD7/SEG7
LCDBIAS3
COM0
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Table Contents
Device Overview 12-Bit Analog-to-Digital Converter (A/D) Module Special Features Electrical Characteristics Packaging Information. Appendix Revision History. Appendix Device Differences. Appendix Conversion Considerations Appendix Migration from Baseline Enhanced Devices. Appendix migration from Mid-Range Enhanced Devices Appendix Migration from High-End Enhanced Devices Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System.
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VALUED CUSTOMERS
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Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting sales office, please specify which device, revision silicon data sheet (include literature number) using.
Customer Notification System
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2007 Microchip Technology Inc.
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NOTES:
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DEVICE OVERVIEW
This document contains device-specific information following devices: PIC18F6393 PIC18F6493 PIC18F8393 PIC18F8493
Details Individual Family Members
Devices PIC18F6393/6493/8393/8493 family available 64-pin (PIC18F6X93) 80-pin (PIC18F8X93) packages. Block diagrams groups shown Figure Figure 1-2, respectively. devices differentiated from each other following ways: Ports: 64-pin devices bidirectional ports 80-pin devices bidirectional ports Pixels: 64-pin devices SEGs COMs) pixels driven 80-pin devices SEGs COMs) pixels driven Flash Program Memory: PIC18FX393 devices Kbytes PIC18FX493 devices Kbytes other features devices this family identical. These summarized Table 1-1. pinouts devices listed Table Table 1-3. Like Microchip PIC18 devices, members PIC18F6393/6493/8393/8493 family available both standard low-voltage devices. Standard devices with Flash memory, designated with part number (such PIC18F6393), accommodate operating range 4.2V 5.5V. Low-voltage parts, designated "LF" (such PIC18LF6490), function over extended range 2.0V 5.5V.
Note: This data sheet documents only devices' features specifications that addition features specifications PIC18F6390/6490/8390/8490 devices. information features specifications shared PIC18F6393/ 6493/8393/8493 PIC18F6390/6490/ 8390/8490 devices, "PIC18F6390/ 6490/8390/8490 Data Sheet" (DS39629). This family offers advantages PIC18 microcontrollers namely, high computational performance economical price. addition these features, PIC18F6393/6493/8393/8493 family introduces design enhancements that make these microcontrollers logical choice many high-performance, power-sensitive applications.
Special Features
12-Bit Converter: This module incorporates programmable acquisition time, allowing channel selected conversion initiated without waiting sampling period thus, reduces code overhead.
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TABLE 1-1: DEVICE FEATURES
Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources Ports Number Pixels Driver Drive Timers Capture/Compare/PWM Modules Serial Communications 12-Bit Analog-to-Digital Module Resets (and Delays) PIC18F6393 4096 PIC18F6493 8192 PIC18F8393 4096 PIC18F8493 8192
Ports Ports Ports Ports SEGs COMs) SEGs COMs) SEGs COMs) SEGs COMs)
MSSP, AUSART, MSSP, AUSART, MSSP, AUSART, MSSP, AUSART, Enhanced USART Enhanced USART Enhanced USART Enhanced USART Input Channels Input Channels Input Channels Input Channels POR, BOR, POR, BOR, POR, BOR, POR, BOR, RESET Instruction, RESET Instruction, RESET Instruction, RESET Instruction, Stack Full, Stack Full, Stack Full, Stack Full, Stack Underflow Stack Underflow Stack Underflow Stack Underflow (PWRT, OST), (PWRT, OST), (PWRT, OST), (PWRT, OST), MCLR (optional), MCLR (optional), MCLR (optional), MCLR (optional), Instructions; with Extended Instruction Enabled 64-Pin TQFP Instructions; with Extended Instruction Enabled 64-Pin TQFP Instructions; with Extended Instruction Enabled 80-Pin TQFP Instructions; with Extended Instruction Enabled 80-Pin TQFP
Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction
Packages
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FIGURE 1-1:
Table Pointer<21> inc/dec logic
PCLATU PCLATH
PIC18F6X93 (64-PIN) BLOCK DIAGRAM
Data Bus<8> Data Latch Data Memory (3.9 Kbytes) Address Latch Data Address<12> FSR0 FSR1 FSR2 inc/dec logic Access Bank PORTC PORTB PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/SEG16 RA3/AN3/VREF+/SEG17 RA4/T0CKI/SEG14 RA5/AN4/HLVDIN/SEG15 OSC2/CLKO(3)/RA6 OSC1/CLKI(3)/RA7 RB0/INT0 RB1/INT1/SEG8 RB2/INT2/SEG9 RB3/INT3/SEG10 RB4/KBI0/SEG11 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/SEG13 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO/SEG12 RC6/TX1/CK1 RC7/RX1/DT1
Program Counter Level Stack
Address Latch Program Memory (48/64 Kbytes) Data Latch STKPTR
Table Latch
Instruction <16>
Latch
Address Decode
PORTD
Instruction Decode Control
State Machine Control Signals
PRODH PRODL BITOP Multiply ALU<8> PORTF PORTE
RD7/SEG7:RD0/SEG0
OSC1(3) OSC2
Internal Oscillator Block INTRC Oscillator Oscillator Single-Supply Programming In-Circuit Debugger
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor
LCDBIAS1 LCDBIAS2 LCDBIAS3 COM0 RE4/COM1 RE5/COM2 RE6/COM3 RE7/CCP2(1)/SEG31 RF0/AN5/SEG18 RF1/AN6/C2OUT/SEG19 RF2/AN7/C1OUT/SEG20 RF3/AN8/SEG21 RF4/AN9/SEG22 RF5/AN10/CVREF/SEG23 RF6/AN11/SEG24 RF7/SS/SEG25 RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28 RG3/SEG27 RG4/SEG26 MCLR/VPP/RG5(2)
T1OSI T1OSO MCLR(2) VDD,
Precision Band Reference
HLVD
12-Bit
PORTG Timer0 Timer1 Timer2 Timer3
Comparators
CCP1
CCP2
MSSP
EUSART1
AUSART2
Driver
Note
CCP2 multiplexed with when Configuration bit, CCP2MX, set, when CCP2MX set. only available when MCLR functionality disabled. OSC1/CLKI OSC2/CLKO only available select oscillator modes when these pins being used digital I/O. additional information, Section "Oscillator Configurations" "PIC18F6390/6490/8390/8490 Data Sheet" (DS39629).
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FIGURE 1-2:
Table Pointer<21> inc/dec logic
PCLATU PCLATH
PIC18F8X93 (80-PIN) BLOCK DIAGRAM
Data Bus<8> Data Latch Data Memory (3.9 Kbytes) Address Latch PORTB Data Address<12> FSR0 FSR1 FSR2 inc/dec logic Access Bank PORTC PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/SEG16 RA3/AN3/VREF+/SEG17 RA4/T0CKI/SEG14 RA5/AN4/HLVDIN/SEG15 OSC2/CLKO(3)/RA6 OSC1/CLKI(3)/RA7 RB0/INT0 RB1/INT1/SEG8 RB2/INT2/SEG9 RB3/INT3/SEG10 RB4/KBI0/SEG11 RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD RC0/T1OSO/T13CKI RC1/T1OSI/CCP2(1) RC2/CCP1/SEG13 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO/SEG12 RC6/TX1/CK1 RC7/RX1/DT1
Program Counter Level Stack
Address Latch Program Memory (48/64 Kbytes) Data Latch STKPTR
Table Latch
Instruction <16>
Latch
Address Decode PORTD
RD7/SEG7:RD0/SEG0
Instruction Decode Control
State Machine Control Signals PRODH PRODL BITOP Multiply PORTE LCDBIAS1 LCDBIAS2 LCDBIAS3 COM0 RE4/COM1 RE5/COM2 RE6/COM3 RE7/CCP2(1)/SEG31 RF0/AN5/SEG18 RF1/AN6/C2OUT/SEG19 RF2/AN7/C1OUT/SEG20 RF3/AN8/SEG21 RF4/AN9/SEG22 RF5/AN10/CVREF/SEG23 RF6/AN11/SEG24 RF7/SS/SEG25 RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28 RG3/SEG27 RG4/SEG26 MCLR/VPP/RG5(2)
OSC1(3) OSC2
Internal Oscillator Block INTRC Oscillator Oscillator Single-Supply Programming In-Circuit Debugger
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Fail-Safe Clock Monitor
ALU<8>
PORTF
T1OSI T1OSO MCLR(2) VDD,
Precision Band Reference
PORTG
PORTH HLVD 12-Bit Timer0 Timer1 Timer2 Timer3 RH3/SEG47:RH0/SEG44 RH7/SEG40:RH4/SEG43 PORTJ RJ3/SEG35:RJ0/SEG32 Comparators CCP1 CCP2 Driver MSSP EUSART1 AUSART2 RJ7/SEG36:RJ4/SEG39
Note
CCP2 multiplexed with when Configuration bit, CCP2MX, when CCP2MX set. only available when MCLR functionality disabled. OSC1/CLKI OSC2/CLKO only available select oscillator modes when these pins being used digital I/O. additional information, Section "Oscillator Configurations" "PIC18F6390/6490/8390/8490 Data Sheet" (DS39629).
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TABLE 1-2: PIC18F6X93 PINOUT DESCRIPTIONS
Number TQFP Buffer Type Type Description Master Clear (input) programming voltage (input). Master Clear (Reset) input. This active-low Reset device. Programming voltage input. Digital input. Name MCLR/VPP/RG5 MCLR OSC1/CLKI/RA7 OSC1 CLKI
OSC2/CLKO/RA6 OSC2 CLKO
Oscillator crystal external clock input. Oscillator crystal input external clock source input. buffer when configured mode; CMOS otherwise. CMOS External clock source input. Always associated with function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose pin. Oscillator crystal clock output. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. mode, OSC2 outputs CLKO, which frequency OSC1 denotes instruction cycle rate. General purpose pin.
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-2: PIC18F6X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTA bidirectional port. RA0/AN0 RA1/AN1 RA2/AN2/VREF-/SEG16 VREFSEG16 RA3/AN3/VREF+/SEG17 VREF+ SEG17 RA4/T0CKI/SEG14 T0CKI SEG14 RA5/AN4/HLVDIN/SEG15 HLVDIN SEG15 Analog Analog Analog Digital I/O. Analog input Low-Voltage Detect input. SEG15 output LCD. OSC2/CLKO/RA6 pin. OSC1/CLKI/RA7 pin. ST/OD Analog Digital I/O. Open-drain when configured output. Timer0 external clock input. SEG14 output LCD. Analog Analog Analog Digital I/O. Analog input reference voltage (High) input. SEG17 output LCD. Analog Analog Analog Digital I/O. Analog input reference voltage (Low) input. SEG16 output LCD. Analog Digital I/O. Analog input Analog Digital I/O. Analog input Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-2: PIC18F6X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTB bidirectional port. PORTB software programmed internal weak pull-ups inputs. RB0/INT0 INT0 RB1/INT1/SEG8 INT1 SEG8 RB2/INT2/SEG9 INT2 SEG9 RB3/INT3/SEG10 INT3 SEG10 RB4/KBI0/SEG11 KBI0 SEG11 RB5/KBI1 KBI1 RB6/KBI2/PGC KBI2 RB7/KBI3/PGD KBI3 Digital I/O. Interrupt-on-change pin. In-Circuit Debugger ICSP programming data pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger ICSPprogramming clock pin. Digital I/O. Interrupt-on-change pin. Analog Digital I/O. Interrupt-on-change pin. SEG11 output LCD. Analog Digital I/O. External interrupt SEG10 output LCD. Analog Digital I/O. External interrupt SEG9 output LCD. Analog Digital I/O. External interrupt SEG8 output LCD. Digital I/O. External interrupt Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-2: PIC18F6X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTC bidirectional port. RC0/T1OSO/T13CKI T1OSO T13CKI RC1/T1OSI/CCP2 T1OSI CCP2(1) RC2/CCP1/SEG13 CCP1 SEG13 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO/SEG12 SEG12 RC6/TX1/CK1 RC7/RX1/DT1 Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1). Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1). Analog Digital I/O. data out. SEG12 output LCD. Digital I/O. data data I/O. Digital I/O. Synchronous serial clock input/output mode. Synchronous serial clock input/output I2Cmode. Analog Digital I/O. Capture input/Compare output/PWM1 output. SEG13 output LCD. CMOS Digital I/O. Timer1 oscillator input. Capture input/Compare output/PWM2 output. Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-2: PIC18F6X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTD bidirectional port. RD0/SEG0 SEG0 RD1/SEG1 SEG1 RD2/SEG2 SEG2 RD3/SEG3 SEG3 RD4/SEG4 SEG4 RD5/SEG5 SEG5 RD6/SEG6 SEG6 RD7/SEG7 SEG7 Analog Digital I/O. SEG7 output LCD. Analog Digital I/O. SEG6 output LCD. Analog Digital I/O. SEG5 output LCD. Analog Digital I/O. SEG4 output LCD. Analog Digital I/O. SEG3 output LCD. Analog Digital I/O. SEG2 output LCD. Analog Digital I/O. SEG1 output LCD. Analog Digital I/O. SEG0 output LCD. Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-2: PIC18F6X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTE bidirectional port. LCDBIAS1 LCDBIAS1 LCDBIAS2 LCDBIAS2 LCDBIAS3 LCDBIAS3 COM0 COM0 RE4/COM1 COM1 RE5/COM2 COM2 RE6/COM3 COM3 RE7/CCP2/SEG31 CCP2(2) SEG31 Analog Digital I/O. Capture input/Compare output/PWM2 output. SEG31 output LCD. Analog Digital I/O. COM3 output LCD. Analog Digital I/O. COM2 output LCD. Analog Digital I/O. COM1 output LCD. Analog COM0 output LCD. Analog BIAS3 input LCD. Analog BIAS2 input LCD. Analog BIAS1 input LCD. Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-2: PIC18F6X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTF bidirectional port. RF0/AN5/SEG18 SEG18 RF1/AN6/C2OUT/SEG19 C2OUT SEG19 RF2/AN7/C1OUT/SEG20 C1OUT SEG20 RF3/AN8/SEG21 SEG21 RF4/AN9/SEG22 SEG22 RF5/AN10/CVREF/SEG23 AN10 CVREF SEG23 RF6/AN11/SEG24 AN11 SEG24 RF7/SS/SEG25 SEG25 Analog Digital I/O. SPIslave select input. SEG25 output LCD. Analog Analog Digital I/O. Analog input SEG24 output LCD. Analog Analog Analog Digital I/O. Analog input Comparator reference voltage output. SEG23 output LCD. Analog Analog Digital I/O. Analog input SEG22 output LCD. Analog Analog Digital I/O. Analog input SEG21 output LCD. Analog Analog Digital I/O. Analog input Comparator output. SEG20 output LCD. Analog Analog Digital I/O. Analog input Comparator output. SEG19 output LCD. Analog Analog Digital I/O. Analog input SEG18 output LCD. Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-2: PIC18F6X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTG bidirectional port. RG0/SEG30 SEG30 RG1/TX2/CK2/SEG29 SEG29 RG2/RX2/DT2/SEG28 SEG28 RG3/SEG27 SEG27 RG4/SEG26 SEG26 AVSS AVDD Analog Digital I/O. SEG26 output LCD. MCLR/VPP/RG5 pin. Ground reference logic pins. Positive supply logic pins. Ground reference analog modules. Positive supply analog modules. Analog Digital I/O. SEG27 output LCD. Analog Digital I/O. AUSART2 asynchronous receive. AUSART2 synchronous data (see related TX2/CK2). SEG28 output LCD. Analog Digital I/O. AUSART2 asynchronous transmit. AUSART2 synchronous clock (see related RX2/DT2). SEG29 output LCD. Analog Digital I/O. SEG30 output LCD. Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-3: PIC18F8X93 PINOUT DESCRIPTIONS
Number TQFP Buffer Type Type Description Master Clear (input) programming voltage (input). Master Clear (Reset) input. This active-low Reset device. Programming voltage input. Digital input. Name MCLR/VPP/RG5 MCLR OSC1/CLKI/RA7 OSC1 CLKI
OSC2/CLKO/RA6 OSC2 CLKO
Oscillator crystal external clock input. Oscillator crystal input external clock source input. buffer when configured mode; CMOS otherwise. CMOS External clock source input. Always associated with function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose pin. Oscillator crystal clock output. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. mode, OSC2 outputs CLKO, which frequency OSC1 denotes instruction cycle rate. General purpose pin.
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-3: PIC18F8X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTA bidirectional port. RA0/AN0 RA1/AN1 RA2/AN2/VREF-/SEG16 VREFSEG16 RA3/AN3/VREF+/SEG17 VREF+ SEG17 RA4/T0CKI/SEG14 T0CKI SEG14 RA5/AN4/HLVDIN/SEG15 HLVDIN SEG15 Analog Analog Analog Digital I/O. Analog input Low-Voltage Detect input. SEG15 output LCD. OSC2/CLKO/RA6 pin. OSC1/CLKI/RA7 pin. ST/OD Analog Digital I/O. Open-drain when configured output. Timer0 external clock input. SEG14 output LCD. Analog Analog Analog Digital I/O. Analog input reference voltage (High) input. SEG17 output LCD. Analog Analog Analog Digital I/O. Analog input reference voltage (Low) input. SEG16 output LCD. Analog Digital I/O. Analog input Analog Digital I/O. Analog input Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-3: PIC18F8X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTB bidirectional port. PORTB software programmed internal weak pull-ups inputs. RB0/INT0 INT0 RB1/INT1/SEG8 INT1 SEG8 RB2/INT2/SEG9 INT2 SEG9 RB3/INT3/SEG10 INT3 SEG10 RB4/KBI0/SEG11 KBI0 SEG11 RB5/KBI1 KBI1 RB6/KBI2/PGC KBI2 RB7/KBI3/PGD KBI3 Digital I/O. Interrupt-on-change pin. In-Circuit Debugger ICSP programming data pin. Digital I/O. Interrupt-on-change pin. In-Circuit Debugger ICSPprogramming clock pin. Digital I/O. Interrupt-on-change pin. Analog Digital I/O. Interrupt-on-change pin. SEG11 output LCD. Analog Digital I/O. External interrupt SEG10 output LCD. Analog Digital I/O. External interrupt SEG9 output LCD. Analog Digital I/O. External interrupt SEG8 output LCD. Digital I/O. External interrupt Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-3: PIC18F8X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTC bidirectional port. RC0/T1OSO/T13CKI T1OSO T13CKI RC1/T1OSI/CCP2 T1OSI CCP2(1) RC2/CCP1/SEG13 CCP1 SEG13 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO/SEG12 SEG12 RC6/TX1/CK1 RC7/RX1/DT1 Digital I/O. EUSART1 asynchronous receive. EUSART1 synchronous data (see related TX1/CK1). Digital I/O. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1). Analog Digital I/O. data out. SEG12 output LCD. Digital I/O. data data I/O. Digital I/O. Synchronous serial clock input/output mode. Synchronous serial clock input/output I2Cmode. Analog Digital I/O. Capture input/Compare output/PWM1 output. SEG13 output LCD. CMOS Digital I/O. Timer1 oscillator input. Capture input/Compare output/PWM2 output. Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-3: PIC18F8X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTD bidirectional port. RD0/SEG0 SEG0 RD1/SEG1 SEG1 RD2/SEG2 SEG2 RD3/SEG3 SEG3 RD4/SEG4 SEG4 RD5/SEG5 SEG5 RD6/SEG6 SEG6 RD7/SEG7 SEG7 Analog Digital I/O. SEG7 output LCD. Analog Digital I/O. SEG6 output LCD. Analog Digital I/O. SEG5 output LCD. Analog Digital I/O. SEG4 output LCD. Analog Digital I/O. SEG3 output LCD. Analog Digital I/O. SEG2 output LCD. Analog Digital I/O. SEG1 output LCD. Analog Digital I/O. SEG0 output LCD. Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-3: PIC18F8X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTE bidirectional port. LCDBIAS1 LCDBIAS1 LCDBIAS2 LCDBIAS2 LCDBIAS3 LCDBIAS3 COM0 COM0 RE4/COM1 COM1 RE5/COM2 COM2 RE6/COM3 COM3 RE7/CCP2/SEG31 CCP2(2) SEG31 Analog Digital I/O. Capture input/Compare output/PWM2 output. SEG31 output LCD. Analog Digital I/O. COM3 output LCD. Analog Digital I/O. COM2 output LCD. Analog Digital I/O. COM1 output LCD. Analog COM0 output LCD. Analog BIAS3 input LCD. Analog BIAS2 input LCD. Analog BIAS1 input LCD. Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-3: PIC18F8X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTF bidirectional port. RF0/AN5/SEG18 SEG18 RF1/AN6/C2OUT/SEG19 C2OUT SEG19 RF2/AN7/C1OUT/SEG20 C1OUT SEG20 RF3/AN8/SEG21 SEG21 RF4/AN9/SEG22 SEG22 RF5/AN10/CVREF/SEG23 AN10 CVREF SEG23 RF6/AN11/SEG24 AN11 SEG24 RF7/SS/SEG25 SEG25 Analog Digital I/O. slave select input. SEG25 output LCD. Analog Analog Digital I/O. Analog input SEG24 output LCD. Analog Analog Analog Digital I/O. Analog input Comparator reference voltage output. SEG23 output LCD. Analog Analog Digital I/O. Analog input SEG22 output LCD. Analog Analog Digital I/O. Analog input SEG21 output LCD. Analog Analog Digital I/O. Analog input Comparator output. SEG20 output LCD. Analog Analog Digital I/O. Analog input Comparator output. SEG19 output LCD. Analog Analog Digital I/O. Analog input SEG18 output LCD. Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-3: PIC18F8X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTG bidirectional port. RG0/SEG30 SEG30 RG1/TX2/CK2/SEG29 SEG29 RG2/RX2/DT2/SEG28 SEG28 RG3/SEG27 SEG27 RG4/SEG26 SEG26 Analog Digital I/O. SEG26 output LCD. MCLR/VPP/RG5 pin. Analog Digital I/O. SEG27 output LCD. Analog Digital I/O. AUSART2 asynchronous receive. AUSART2 synchronous data (see related TX2/CK2). SEG28 output LCD. Analog Digital I/O. AUSART2 asynchronous transmit. AUSART2 synchronous clock (see related RX2/DT2). SEG29 output LCD. Analog Digital I/O. SEG30 output LCD. Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-3: PIC18F8X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTH bidirectional port. RH0/SEG47 SEG47 RH1/SEG46 SEG46 RH2/SEG45 SEG45 RH3/SEG44 SEG44 RH4/SEG40 SEG40 RH5/SEG41 SEG41 RH6/SEG42 SEG42 RH7/SEG43 SEG43 Analog Digital I/O. SEG43 output LCD. Analog Digital I/O. SEG42 output LCD. Analog Digital I/O. SEG41 output LCD. Analog Digital I/O. SEG40 output LCD. Analog Digital I/O. SEG44 output LCD. Analog Digital I/O. SEG45 output LCD. Analog Digital I/O. SEG46 output LCD. Analog Digital I/O. SEG47 output LCD. Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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TABLE 1-3: PIC18F8X93 PINOUT DESCRIPTIONS (CONTINUED)
Number TQFP Buffer Type Type Description PORTJ bidirectional port. RJ0/SEG32 SEG32 RJ1/SEG33 SEG33 RJ2/SEG34 SEG34 RJ3/SEG35 SEG35 RJ4/SEG39 SEG39 RJ5/SEG38 SEG38 RJ6/SEG37 SEG37 RJ7/SEG36 SEG36 AVSS AVDD Analog Digital I/O. SEG36 output LCD. Ground reference logic pins. Positive supply logic pins. Ground reference analog modules. Positive supply analog modules. Analog Digital I/O. SEG37 output LCD. Analog Digital SEG38 output LCD. Analog Digital I/O. SEG39 output LCD. Analog Digital I/O. SEG35 output LCD. Analog Digital I/O. SEG34 output LCD. Analog Digital I/O. SEG33 output LCD. Analog Digital I/O. SEG32 output LCD. Name
Legend: compatible input CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels Analog Analog input Input Output Power Open-Drain diode VDD) Note Default assignment CCP2 when Configuration bit, CCP2MX, set. Alternate assignment CCP2 when Configuration bit, CCP2MX, cleared.
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12-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
ADCON0 register, shown Register 2-1, controls operation module. ADCON1 register, shown Register 2-2, configures functions port pins. ADCON2 register, shown Register 2-3, configures clock source, programmed acquisition time justification.
Analog-to-Digital (A/D) Converter module converts analog input signal 12-bit digital number. module inputs both PIC18F6393/6493 (64-pin) PIC18F8393/8493 (80-pin) devices. module five registers: Result High Register (ADRESH) Result Register (ADRESL) Control Register (ADCON0) Control Register (ADCON1) Control Register (ADCON2)
REGISTER 2-1:
Legend: Readable Value
ADCON0: CONTROL REGISTER
R/W-0 CHS3 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read CHS3:CHS0: Analog Channel Select bits 0000 Channel (AN0) 0001 Channel (AN1) 0010 Channel (AN2) 0011 Channel (AN3) 0100 Channel (AN4) 0101 Channel (AN5) 0110 Channel (AN6) 0111 Channel (AN7) 1000 Channel (AN8) 1001 Channel (AN9) 1010 Channel (AN10) 1011 Channel (AN11) 1100 Unimplemented(1) 1101 Unimplemented(1) 1110 Unimplemented(1) 1111 Unimplemented(1) GO/DONE: Conversion Status When ADON conversion progress Idle ADON: Converter module enabled Converter module disabled Performing conversion unimplemented channels will return floating input measurement.
Note
REGISTER 2-2:
ADCON1: CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
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REGISTER 2-2:
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ADCON1: CONTROL REGISTER (CONTINUED)
VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0
Unimplemented: Read VCFG1:VCFG0: Voltage Reference Configuration bits
VREF+ AVDD External VREF+ AVDD External VREF+ VREFAVSS AVSS External VREFExternal VREF-
PCFG3:PCFG0: Port Configuration Control bits
AN10 AN11 PCFG<3:0> 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
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Analog input
Digital
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REGISTER 2-3:
R/W-0 ADFM Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ADCON2: CONTROL REGISTER
R/W-0 ACQT2 R/W-0 ACQT1 R/W-0 ACQT0 R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0
ADFM: Result Format Select Right justified Left justified Unimplemented: Read ACQT2:ACQT0: Acquisition Time Select bits TAD(1) ADCS2:ADCS0: Conversion Clock Select bits (clock derived from oscillator)(1) FOSC/64 FOSC/16 FOSC/4 (clock derived from oscillator)(1) FOSC/32 FOSC/8 FOSC/2 clock source selected, delay (instruction cycle) added before clock starts. This allows SLEEP instruction executed before starting conversion.
Note
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analog reference voltage software selectable either device's positive negative supply voltage (VDD VSS), voltage level RA3/AN3/ VREF+/SEG17 RA2/AN2/VREF-/SEG16 pins. Converter unique feature being able operate while device Sleep mode. operate Sleep, conversion clock must derived from A/D's internal oscillator. output sample hold input into converter, which generates result successive approximation. device Reset forces registers their Reset state. This forces module turned conversion progress aborted. Each port associated with Converter configured analog input digital I/O. ADRESH ADRESL registers contain result conversion. When conversion complete, result loaded into ADRESH:ADRESL register pair, GO/DONE (ADCON0<1>) cleared Interrupt Flag bit, ADIF, set. block diagram module shown Figure 2-1.
FIGURE 2-1:
BLOCK DIAGRAM
CHS3:CHS0 1011 1010 1001 1000 0111 0110 0101 0100 VAIN 12-Bit Converter (Input Voltage) 0011 0010 VCFG1:VCFG0 AVDD(1) Reference Voltage VREF+ VREFX0
AN11 AN10
0001 0000
AVSS(1)
Note
pins have diode protection VSS.
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value ADRESH:ADRESL registers unknown following Power-on Brown-out Resets affected other Reset. After module been configured desired, selected channel must acquired before conversion started. analog input channels must have their corresponding TRIS bits selected input. determine acquisition time, Section "A/D Acquisition Requirements". After this acquisition time elapsed, conversion started. acquisition time programmed occur between setting GO/DONE actual start conversion. following steps should followed perform conversion: Configure module: Configure analog pins, voltage reference digital (ADCON1) Select input channel (ADCON0) Select acquisition time (ADCON2) Select conversion clock (ADCON2) Turn module (ADCON0) Configure interrupt desired): Clear ADIF ADIE Wait required acquisition time required). Start conversion: GO/DONE (ADCON0<1>) Wait conversion complete either: Polling GO/DONE cleared Waiting interrupt Read Result registers (ADRESH:ADRESL); clear bit, ADIF, required. next conversion, step step required. conversion time defined TAD. minimum wait required before next acquisition starts.
FIGURE 2-2:
FFFh FFEh Digital Code Output
TRANSFER FUNCTION
003h 002h 001h 000h 4094.5 4095.5 4094 4095
Analog Input Voltage
FIGURE 2-3:
ANALOG INPUT MODEL
0.6V Sampling Switch
VAIN
CPIN
0.6V
ILEAKAGE ±100
CHOLD
Legend: CPIN Input Capacitance Threshold Voltage ILEAKAGE Leakage Current various junctions Interconnect Resistance Sampling Switch Sample/Hold Capacitance (from DAC) CHOLD Sampling Switch Resistance
Sampling Switch
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Acquisition Requirements
Converter meet specified accuracy, charge holding capacitor (CHOLD) must allowed fully charge input channel voltage level. analog input model shown Figure 2-3. source impedance (RS) internal sampling switch (RSS) impedance directly affect time required charge capacitor, CHOLD. sampling switch (RSS) impedance varies over device voltage (VDD). source impedance affects offset voltage analog input (due leakage current). maximum recommended impedance analog sources After analog input channel selected (changed), channel must sampled least minimum acquisition time before starting conversion. Note: When conversion started, holding capacitor disconnected from input pin. calculate minimum acquisition time, Equation used. This equation assumes that error used (4096 steps 12-bit A/D). error maximum error allowed meet specified resolution. Equation shows calculation minimum required acquisition time, TACQ. This calculation based following application system assumptions: CHOLD Conversion Error Temperature 85°C (system max.)
EQUATION 2-1:
TACQ
ACQUISITION TIME
Amplifier Settling Time Holding Capacitor Charging Time Temperature Coefficient TAMP TCOFF
EQUATION 2-2:
VHOLD
MINIMUM CHARGING TIME
(VREF (VREF/4096)) e(-TC/CHOLD(RIC RS))) (CHOLD)(RIC ln(1/4096)
EQUATION 2-3:
TACQ TAMP TCOFF
CALCULATING MINIMUM REQUIRED ACQUISITION TIME
TAMP TCOFF (Temp 25°C)(0.02 µs/°C) (85°C 25°C)(0.02 µs/°C) -(CHOLD)(RIC ln(1/4096) -(25 ln(0.0002441) 1.56 1.56 2.96
Temperature coefficient only required temperatures 25°C. Below 25°C, TCOFF
TACQ
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Selecting Configuring Acquisition Time Selecting Conversion Clock
ADCON2 register allows user select acquisition time that occurs each time GO/DONE set. also gives users option automatically determined acquisition time. Acquisition time with ACQT2:ACQT0 bits (ADCON2<5:3>), which provide range TAD. When GO/DONE set, module continues sample input selected acquisition time, then automatically begins conversion. Since acquisition time programmed, there need wait acquisition time between selecting channel setting GO/DONE bit. Manual acquisition selected when ACQT2:ACQT0 000. When GO/DONE set, sampling stopped conversion begins. user responsible ensuring required acquisition time passed between selecting desired input channel setting GO/DONE bit. This option also default Reset state ACQT2:ACQT0 bits compatible with devices that offer programmable acquisition times. either case, when conversion completed, GO/DONE cleared, ADIF flag begins sampling currently selected channel again. acquisition time programmed, there nothing indicate acquisition time ended conversion begun.
conversion time defined TAD. conversion requires 12-bit conversion. source conversion clock software selectable. There seven possible options TAD: TOSC TOSC TOSC TOSC TOSC TOSC Internal Oscillator
correct conversions, conversion clock (TAD) must short possible, greater than minimum TAD. (See parameter more information.) Table shows resultant times derived from device operating frequencies clock source selected.
TABLE 2-1:
DEVICE OPERATING FREQUENCIES
Clock Source (TAD) Operation TOSC TOSC TOSC TOSC TOSC TOSC RC(1) ADCS2:ADCS0 Assumes Min. Maximum FOSC 2.50 5.00 10.00 20.00 40.00 40.00 1.00 MHz(2)
Note
source typical time device frequencies above MHz, device must Sleep entire conversion FOSC divider should used instead; otherwise, accuracy specification met.
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Operation Power-Managed Modes Configuring Analog Port Pins
ADCON1, TRISA, TRISF TRISH registers configure port pins. port pins needed analog inputs must have their corresponding TRIS bits (input). TRIS cleared (output), digital output level (VOH VOL) will converted. operation independent state CHS3:CHS0 bits TRIS bits. Note When reading PORT register, pins configured analog input channels will read cleared level). Analog conversion pins configured digital pins performed. voltage will accurately converted. Analog levels defined digital input cause digital input buffer consume current device's specification limits.
selection automatic acquisition time conversion clock determined part clock source frequency while power-managed mode. expected operate while device power-managed mode, ADCS2:ADCS0 bits ADCON2 should updated accordance with clock source used. ACQT2:ACQT0 bits need adjusted ADCS2:ADCS0 bits adjust time clock speed. After entering mode, acquisition conversion started. Once started, device should continue clocked same clock source until conversion been completed. desired, device placed into corresponding Idle mode during conversion. device clock frequency less than MHz, clock source should selected. Operation Sleep mode requires clock selected. ACQT2:ACQT0 bits `000' conversion started, conversion will delayed instruction cycle allow execution SLEEP instruction entry Sleep mode. IDLEN (OSCCON<7>) must have already been cleared prior starting conversion.
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Conversions
Figure shows operation Converter after GO/DONE been ACQT2:ACQT0 bits cleared. conversion started after following instruction allow entry into Sleep mode before conversion begins. Figure shows operation Converter after GO/DONE been set, ACQT2:ACQT0 bits `010' acquisition time been selected before conversion starts. Clearing GO/DONE during conversion will abort current conversion. Result register pair will updated with partially completed conversion sample. This means ADRESH:ADRESL registers will continue contain value last completed conversion last value written ADRESH:ADRESL registers). After conversion completed aborted, wait required before next acquisition started. After this wait, acquisition selected channel automatically started. Note: GO/DONE should same instruction that turns A/D. Code should wait least after enabling before beginning acquisition conversion cycle.
Discharge
discharge phase used initialize value holding capacitor. array discharged before every sample. This feature helps optimize unity gain amplifier, circuit always needs charge capacitor array, rather than charge/discharge based previous-measure values.
FIGURE 2-4:
CONVERSION CYCLES (ACQT<2:0> 000, TACQ
Discharge (typically
TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD12 TAD13 TAD1
Conversion starts Holding capacitor disconnected from analog input (typically GO/DONE
following cycle: ADRESH:ADRESL loaded, GO/DONE cleared, ADIF set, holding capacitor connected analog input
FIGURE 2-5:
CONVERSION CYCLES (ACQT<2:0> 010, TACQ TAD)
Cycles TAD1 Discharge (typically
TACQT Cycles
Automatic Acquisition Time
Conversion starts (Holding capacitor disconnected)
GO/DONE (Holding capacitor continues acquiring input)
following cycle: ADRESH:ADRESL loaded, GO/DONE cleared, ADIF set, holding capacitor connected analog input
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ECCP2 Trigger
conversion started Special Event Trigger ECCP2 module. This requires that CCP2M3:CCP2M0 bits (CCP2CON<3:0>) programmed `1011' that module enabled (ADON set). When trigger occurs, GO/DONE will set, starting acquisition conversion, Timer1 Timer3) counter will reset zero. Timer1 Timer3) reset automatically repeat acquisition period with minimal software overhead (moving ADRESH:ADRESL desired location). appropriate analog input channel must selected minimum acquisition period either timed user, appropriate TACQ time selected before Special Event Trigger sets GO/DONE (starts conversion). module enabled (ADON cleared), Special Event Trigger will ignored module will still reset Timer1 Timer3) counter.
TABLE 2-2:
Name INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 TRISA TRISF TRISH(2)
REGISTERS ASSOCIATED WITH OPERATION
TMR0IE RC1IF RC1IE RC1IP INT0IE TX1IF TX1IE TX1IP RBIE SSP1IF SSP1IE SSP1IP BCL1IF BCL1IE BCL1IP TMR0IF CCP1IF CCP1IE CCP1IP HLVDIF HLVDIE HLVDIP INT0IF TMR2IF TMR2IE TMR2IP TMR3IF TMR3IE TMR3IP RBIF TMR1IF TMR1IE TMR1IP CCP2IF CCP2IE CCP2IP Reset Values
GIE/GIEH PEIE/GIEL OSCFIF OSCFIE OSCFIP ADIF ADIE ADIP CMIF CMIE CMIP
Result Register High Byte Result Register Byte ADFM TRISA7(1) TRISF7 TRISH7 TRISA6(1) TRISF6 TRISH6 CHS3 VCFG1 ACQT2 TRISA5 TRISF5 TRISH5 CHS2 VCFG0 ACQT1 TRISA4 TRISF4 TRISH4 CHS1 PCFG3 ACQT0 TRISA3 TRISF3 TRISH3 CHS0 PCFG2 ADCS2 TRISA2 TRISF2 TRISH2 GO/DONE PCFG1 ADCS1 TRISA1 TRISF1 TRISH1 ADON PCFG0 ADCS0 TRISA0 TRISF0 TRISH0
Legend: unimplemented, read `0'. Shaded cells used conversion. Note PORTA<7:6> their direction bits individually configured port pins based various primary oscillator modes. When disabled, these bits read `0'. These registers implemented 64-pin devices. these Reset values, "PIC18F6390/6490/8390/8490 Data Sheet" (DS39629).
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Note:
SPECIAL FEATURES
additional details Configuration bits, refer Section 23.1 "Configuration Bits" "PIC18F6390/6490/8390/8490 Data Sheet" (DS39629). Device information presented this section PIC18F6393/6493/8393/8493 devices only.
Device Registers
Device registers "read-only" registers. They identify device type revision device programmers read firmware using table reads.
PIC18F6393/6493/8393/8493 devices include several features intended maximize reliability minimize cost through elimination external components. These include: Device Registers
TABLE 3-1:
File Name
DEVICE
DEV2 DEV10 DEV1 DEV9 DEV0 DEV8 REV4 DEV7 REV3 DEV6 REV2 DEV5 REV1 DEV4 REV0 DEV3 Default/ Unprogrammed Value xxxx xxxx(1) xxxx xxxx(1)
3FFFFEh DEVID1 3FFFFFh DEVID2
Legend: unknown Note Register Register DEVID values. DEVID registers read-only cannot programmed user.
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REGISTER 3-1:
DEV2 Legend: Read-only Programmable Unimplemented bit, read Unchanged from programmed state Value when device unprogrammed DEV2:DEV0: Device bits Register complete listing. REV4:REV0: Revision bits These bits used indicate device revision.
DEVID1: DEVICE REGISTER PIC18F6393/6493/8393/8493 DEVICES
DEV1 DEV0 REV4 REV3 REV2 REV1 REV0
REGISTER 3-2:
DEV10 Legend: Read-only
DEVID2: DEVICE REGISTER PIC18F6393/6493/8393/8493 DEVICES
DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3
Programmable
Unimplemented bit, read Unchanged from programmed state
Value when device unprogrammed DEV10:DEV3: Device bits Device PIC18F6393 PIC18F6493 PIC18F8393 PIC18F8493
DEV10:DEV3 (DEVID2<7:0>) 0001 1010 0000 1110 0001 1010 0000 1110
DEV2:DEV0 (DEVID1<7:5>)
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ELECTRICAL CHARACTERISTICS
Note: Other than some basic data, this section documents only PIC18F6393/6493/8393/8493 devices' specifications that differ from those PIC18F6390/6490/8390/8490 devices. detailed information electrical specifications shared PIC18F6393/6493/8393/8493 PIC18F6390/6490/8390/8490 devices, "PIC18F6390/6490/8390/8490 Data Sheet" (DS39629).
Absolute Maximum Ratings()
Ambient temperature under bias.-40°C +125°C Storage temperature -65°C +150°C Voltage with respect (except MCLR) -0.3V (VDD 0.3V) Voltage with respect -0.3V +7.5V Voltage MCLR with respect (Note +13.25V Total power dissipation (Note .1.0W Maximum current .300 Maximum current into .250 Input clamp current, VDD). Output clamp current, VDD) Maximum output current sunk pin.25 Maximum output current sourced Maximum current sunk ports .200 Maximum current sourced ports .200 Note Power dissipation calculated follows: PDIS {IDD IOH} {(VDD VOH) IOH} (VOL IOL) Voltage spikes below MCLR/VPP/RG5 pin, inducing currents greater than cause latch-up. Thus, series resistor 50-100 should used when applying "low" level MCLR/VPP/ pin, rather than pulling this directly VSS.
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device those other conditions above those indicated operation listings this specification implied. Exposure maximum rating conditions extended periods affect device reliability.
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FIGURE 4-1: PIC18F6393/6493/8393/8493 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V 5.5V 5.0V PIC18FX393/X493 4.2V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
Voltage
Frequency
FIGURE 4-2:
PIC18LF6393/6493/8393/8493 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V 5.5V 5.0V PIC18LFX393/X493 4.2V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
Voltage
Frequency
FMAX (16.36 MHz/V) (VDDAPPMIN 2.0V) Note: VDDAPPMIN minimum voltage PIC® device application.
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TABLE 4-1:
Param EOFF
CONVERTER CHARACTERISTICS: PIC18F6393/6493/8393/8493 (INDUSTRIAL)
Characteristic Resolution Integral Linearity Error Differential Linearity Error Offset Error Gain Error Monotonicity 3.0V 0.3V VREFL Guaranteed(1) 0.3V 3.0V VREFH ±2.0 ±2.0 +1.5/-1.0 +1.5/-1.0 ±2.00 ±2.00 Units 3.0V 5.0V 3.0V 5.0V 3.0V 5.0V 3.0V 5.0V Conditions VREF 3.0V VREF 3.0V VREF 3.0V VREF 3.0V VREF 3.0V VAIN VREF 12-bit resolution 12-bit resolution 12-bit resolution
VREF Reference Voltage Range (VREFH VREFL) VREFH Reference Voltage High VREFL Reference Voltage VAIN ZAIN Analog Input Voltage Recommended Impedance Analog Voltage Source VREF Input Current(2)
IREF
During VAIN acquisition. During conversion cycle.
Note
conversion result never decreases with increase input voltage missing codes. VREFH current from RA3/AN3/VREF+/SEG17 VDD, whichever selected VREFH source. VREFL current from RA2/AN2/VREF-/SEG16 VSS, whichever selected VREFL source.
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FIGURE 4-3: CONVERSION TIMING
ADCON0, (Note CLK(1)
DATA
ADRES ADIF
OLD_DATA
NEW_DATA
DONE SAMPLING STOPPED
SAMPLE Note
clock source selected time added before clock starts. This allows SLEEP instruction executed. This minimal delay (typically ns), which also disconnects holding capacitor from analog input.
TABLE 4-2:
Param Symbol
CONVERSION REQUIREMENTS
Characteristic Clock Period PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX 12.5(1) 25.0(1) (Note Units Conditions TOSC based, VREF 3.0V 3.0V; TOSC based, VREF full range mode 3.0V; mode
TCNV TACQ TSWC TDIS
Conversion Time (not including acquisition time)(2) Acquisition Time(3) Switching Time from Convert Sample Discharge Time
Note
time clock period dependent device frequency clock divider. ADRES registers read following cycle. time holding capacitor acquire "New" input voltage when voltage changes full scale after conversion (VDD VDD). source impedance (RS) input channels following cycle device clock.
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2007 Microchip Technology Inc.
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PACKAGING INFORMATION
packaging information, "PIC18F6390/6490/ 8390/8490 Data Sheet" (DS39629).
2007 Microchip Technology Inc.
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NOTES:
DS39896A-page
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APPENDIX REVISION HISTORY APPENDIX
Revision (September 2007)
Original data sheet PIC18F6393/6493/8393/ 8493 devices.
DEVICE DIFFERENCES
differences between devices listed this data sheet shown Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
PIC18F6393 PIC18F6493 PIC18F8393 PIC18F8493
Features Number Pixels Driver Drive Ports Flash Program Memory Packages
Ports Ports Ports Ports Kbytes 64-Pin TQFP Kbytes 64-Pin TQFP Kbytes 80-Pin TQFP Kbytes 80-Pin TQFP
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APPENDIX CONVERSION CONSIDERATIONS APPENDIX MIGRATION FROM BASELINE ENHANCED DEVICES
This appendix discusses considerations converting from previous versions device ones listed this data sheet. Typically, these changes differences process technology used. example this type conversion from PIC16C74A PIC16C74B. Applicable
This section discusses migrate from Baseline device (i.e., PIC16C5X) Enhanced device (i.e., PIC18FXXX). following list modifications over PIC16C5X microcontroller family: Currently Available
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APPENDIX MIGRATION FROM MID-RANGE ENHANCED DEVICES APPENDIX MIGRATION FROM HIGH-END ENHANCED DEVICES
detailed discussion differences between mid-range devices (i.e., PIC16CXXX) enhanced devices (i.e., PIC18FXXX) provided AN716, "Migrating Designs from PIC16C74A/74B PIC18C442". changes discussed, while devicespecific, generally applicable mid-range enhanced device migrations. This Application Note available Literature Number DS00716.
detailed discussion migration pathway differences between high-end devices (i.e., PIC17CXXX) enhanced devices (i.e., PIC18FXXX) provided AN726, "PIC17CXXX PIC18CXXX Migration". This Application Note available Literature Number DS00726.
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NOTES:
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INDEX
Converter Interrupt, Configuring Acquisition Requirements ADCON0 Register. ADCON1 Register. ADCON2 Register. ADRESH Register. ADRESL Register Analog Port Pins, Configuring. Associated Registers Configuring Module. Conversion Clock (TAD) Conversion Requirements Conversion Status (GO/DONE Bit) Conversions Converter Characteristics Discharge. Operation Power-Managed Modes Selecting Configuring Acquisition Time Special Event Trigger (ECCP2) Transfer Function. ECCP2 Trigger Absolute Maximum Ratings ADCON0 Register. GO/DONE Bit. ADCON1 Register. ADCON2 Register. ADRESH Register. ADRESL Register Analog-to-Digital Converter. A/D.
Electrical Characteristics Converter. Absolute Maximum Ratings Low-Power Voltage-Frequency Graph Voltage-Frequency Graph Equations Acquisition Time Minimum Charging Time Calculating Minimum Required Acquisition Time Errata
Internet Address Interrupt Sources Conversion Complete
Driver Features
Microchip Internet Site. Microcontroller Special Features. Migration from Baseline Enhanced Devices Migration from High-End Enhanced Devices. Migration from Mid-Range Enhanced Devices
Oscillator Structure Features
Block Diagrams Analog Input Model PIC18F6X93 PIC18F8X93
Packaging Information. Peripheral Highlights. Diagrams 64-Pin TQFP. 80-Pin TQFP. Functions AVDD AVDD AVSS AVSS COM0 LCDBIAS1 LCDBIAS2 LCDBIAS3 MCLR/VPP/RG5. OSC1/CLKI/RA7. OSC2/CLKO/RA6 RA0/AN0. RA1/AN1. RA2/AN2/VREF-/SEG16. RA3/AN3/VREF+/SEG17. RA4/T0CKI/SEG14.
Compare (ECCP2 Module) Special Event Trigger. Conversion Considerations Customer Change Notification Service Customer Notification Service. Customer Support
Device Differences Device Registers Device Overview Details Individual Devices Features (table). Special Features Documentation Most Current Versions Related Data Sheet.
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RA5/AN4/HLVDIN/SEG15 RB0/INT0 RB1/INT1/SEG8. RB2/INT2/SEG9. RB3/INT3/SEG10. RB4/KBI0/SEG11. RB5/KBI1 RB6/KBI2/PGC RB7/KBI3/PGD RC0/T1OSO/T13CKI RC1/T1OSI/CCP2 RC2/CCP1/SEG13. RC3/SCK/SCL RC4/SDI/SDA RC5/SDO/SEG12 RC6/TX1/CK1 RC7/RX1/DT1 RD0/SEG0 RD0/SEG1 RD1/SEG1 RD2/SEG2 RD3/SEG3 RD4/SEG4 RD5/SEG5 RD6/SEG6 RD7/SEG7 RE4/COM1. RE5/COM2. RE6/COM3. RE7/CCP2/SEG31 RF0/AN5/SEG18. RF1/AN6/C2OUT/SEG19 RF2/AN7/C1OUT/SEG20 RF3/AN8/SEG21. RF4/AN9/SEG22. RF5/AN10/CVREF/SEG23 RF6/AN11/SEG24. RF7/SS/SEG25 RG0/SEG30 RG1/TX2/CK2/SEG29 RG2/RX2/DT2/SEG28 RG3/SEG27 RG4/SEG26 RG5. RH0/SEG47 RH1/SEG46 RH2/SEG45 RH3/SEG44 RH4/SEG40 RH5/SEG41 RH6/SEG42 RH7/SEG43 RJ0/SEG32 RJ1/SEG33 RJ2/SEG34 RJ3/SEG35 RJ4/SEG39 RJ5/SEG38 RJ6/SEG37 RJ7/SEG36 VDD. VDD. Pinout Descriptions PIC18F6X93 PIC18F8X93 Power-Managed Modes Operation Features Product Identification System
Reader Response. Registers ADCON0 (A/D Control ADCON1 (A/D Control ADCON2 (A/D Control DEVID1 (Device DEVID2 (Device Revision History.
Special Features Device Registers
Timing Diagrams Conversion.
Address WWW, On-Line Support
DS39896A-page
2007 Microchip Technology Inc.
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MICROCHIP SITE
Microchip provides online support site www.microchip.com. This site used means make files information easily available customers. Accessible using your favorite Internet browser, site contains following information: Product Support Data sheets errata, application notes sample programs, design resources, user's guides hardware support documents, latest software releases archived software General Technical Support Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing Business Microchip Product selector ordering guides, latest Microchip press releases, listing seminars events, listings Microchip sales offices, distributors factory representatives
CUSTOMER SUPPORT
Users Microchip products receive assistance through several channels: Distributor Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative field application engineer (FAE) support. Local sales offices also available help customers. listing sales offices locations included back this document. Technical support available through site http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current Microchip products. Subscribers will receive e-mail notification whenever there changes, updates, revisions errata related specified product family development tool interest. register, access Microchip site www.microchip.com, click Customer Change Notification follow registration instructions.
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READER RESPONSE
intention provide with best documentation possible ensure successful your Microchip product. wish provide your comments organization, clarity, subject matter, ways which documentation better serve you, please your comments Technical Publications Manager (480) 792-4150. Please list following information, this outline provide with your comments about this document. Technical Publications Manager Reader Response Total Pages Sent
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DS39896A-page
2007 Microchip Technology Inc.
PIC18F6393/6493/8393/8493
PRODUCT IDENTIFICATION SYSTEM
order obtain information, e.g., pricing delivery, refer factory listed sales office. PART Device Temperature Range Package Pattern Examples:
Device(1), PIC18F6393, PIC18F6493, PIC18F8393, PIC18F8493 range: 4.2V 5.5V PIC18LF6393, PIC18LF6493, PIC18LF8393, PIC18LF8493 range: 2.0V 5.5V -40°C +85°C -40°C +125°C (Industrial) (Extended) PIC18LF6393-I/PT Industrial temp., TQFP package, Extended limits, pattern #301. PIC18LF6393-I/PT Industrial temp., TQFP package, Extended limits. PIC18F6393-E/PT Extended temp., TQFP package, normal limits.
Temperature Range
Package Pattern
TQFP (Thin Quad Flatpack) Note Standard Voltage Range Wide Voltage Range tape reel TQFP packages only.
QTP, SQTP, Code Special Requirements (blank otherwise)
2007 Microchip Technology Inc.
DS39896A-page
WORLDWIDE SALES SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Address: www.microchip.com Atlanta Duluth, Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, Tel: 765-864-8360 Fax: 765-864-8387 Angeles Mission Viejo, Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 China Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256
ASIA/PACIFIC
India Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 82-2-558-5934 Malaysia Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Hsin Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
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