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1 - 22 of about 22 for 80386SL |
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First line: 80386SL CL-CD1284 Parallel Port (Peripheral-side) Abstract: .. 80386SL processor . The ECP and EPP modes operate at data rates as high as 2 Mbytes/sec. The IEEE 1284 port is implemented as two func-tional blocks: a data pipeline that includes the 64-byte FIFO .. Tags: intel 80386SL specification of 80386sl processor CD1284 CD1283 80386SL* CL-CD1284 |
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First line: specification of 80386sl processor parallel port scanner 'CIRRUS LOGIC CL-CD1284 Preliminary Product Bulletin Parallel Port High-speed, bidirectional, multi-protocol parallel port: Hardware implementation modes IEEE 1284 specification: (Enhanced Parallel Port) mode (Extended Capabilities Port) mode Abstract: .. , Reverse Byte IBM-PS/2 style , ECP, and EPP as implemented on the Intel05 80386SL processor . ECP and EPP modes operate at data rates as high as 2 Mbytes/second. CIRRUS LOGIC The IEEE 12B4 port .. Tags: parallel port scanner specification of 80386sl processor datasheet abstract.. |
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First line: 28F008SA 8-MBIT (1-MBIT FLASHFILEtm MEMORY High-Density Symmetrically Blocked Architecture Sixteen 64-Kbyte Blocks Extended Cycling Capability Block Erase Cycles Million Block Erase Cycles Chip Automated Byte Write Block Erase Command User Interface Abstract: .. SBHE' PST ART" 80386Sl. T. ::::: PCWO PW/IO" pw/RFLSHOCS' PRDY# -+} ~ ROCS., ---------TO OTHER .. Tags: datasheet abstract.. |
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First line: LH28F008SAHT-T9 Flash Memory 8Mbit (1Mbitx8) Abstract: .. 80386SL μPLD. Figure 3. LH28F008SA Array Interface to 386SL Microprocessor Superset through PI Bus Including RY/BY# Masking and Selective Powerdown , for DRAM Backup during System SUSPEND .. Tags: FBT Hr 82360sl 80386SL LH28F008SAHT-T9 |
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First line: LH28F008SAT-85 Abstract: .. 80386SL μPLD. Figure 3. LH28F008SA Array Interface to 386SL Microprocessor Superset through PI Bus Including RY/BY# Masking and Selective Powerdown , for DRAM Backup during System SUSPEND .. Tags: 82360sl* 80386SL* 386SL LH28F008SAT-85 |
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First line: 3x106 LH28F008SAN-12 Abstract: .. 80386SL μPLD. Figure 3. LH28F008SA Array Interface to 386SL Microprocessor Superset through PI Bus Including RY/BY# Masking and Selective Powerdown , for DRAM Backup during System SUSPEND .. Tags: 3x106 82360sl 80386SL LH28F008SAN-12 |
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First line: LH28F008SAR-85 Abstract: .. 80386SL μPLD. Figure 3. LH28F008SA Array Interface to 386SL Microprocessor Superset through PI Bus Including RY/BY# Masking and Selective Powerdown , for DRAM Backup during System SUSPEND .. Tags: 82360sl 80386SL LH28F008SAR-85 |
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First line: LH28F008SAN-85 Abstract: .. 80386SL μPLD. Figure 3. LH28F008SA Array Interface to 386SL Microprocessor Superset through PI Bus Including RY/BY# Masking and Selective Powerdown , for DRAM Backup during System SUSPEND .. Tags: AT91SAM7X128-AU 82360sl 80386SL LH28F008SAN-85 |
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First line: LH28F008SAN-85 Abstract: .. 80386SL μPLD. Figure 3. LH28F008SA Array Interface to 386SL Microprocessor Superset through PI Bus Including RY/BY# Masking and Selective Powerdown , for DRAM Backup during System SUSPEND .. Tags: AT91SAM7X128-AU 82360sl 80386SL LH28F008SAN-85 |
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First line: ry 536 LH28F008SA 40-PIN TSOP Flash Memory Abstract: .. 80386SL. μPLD. LH28F008SA. LH28F008SA. CS. TO OTHER LH28F008SA's. EPLD s RESET. PWRGOOD. PSTART .. Tags: ry 536 82360sl* 80386SL 386SL LH28F008SA |
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First line: VT83C465 8th. Fl., Chung-cheng Rd.,Hsin-tien Taipei, Taiwan, R.O.C. TEL: 886-2-218-5452 FAX: 886-2-218-5453 VT83C465 PCMCIA SOCKET CONTROLLER Abstract: .. When IRQ15 is RI_OUT, this pin is used to resume the CPU using RI pin of the 80386SL set. 150 TO 4ma. IRQ12 System Interrupt Request 12 : In IRQ mode this is. signal indicates an interrupt request. When .. Tags: CL-PD6720* 80386SL 386SL* VT83C465 |
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First line: W 20 K85 HARP LHF08S17 FEATURES PRODUCT OVERVIEW PRINCIPLES OPERATION OPERATION COMMAND DEFINITIONS EXTENDED BLOCK ERASE/BYTE WRITE CYCLING Abstract: .. SsHE PSTART 80386SL PCMD PMIIO. T. ~ ~ ..,PLO. esc 1-+ CE. A~l~ ~,. -. -~! ~ LH28=~AXX' WE OE RD. -} CSl. _S,S!i!. __ CS TOOTHER. 1-+. iNA. 8 "~ en a:> a:> X. x x X :.: X. II. II. II. II. II. II. II. II. II. II. u~ .. Tags: W 20 K85 datasheet abstract.. |
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First line: Product Spot-cations CUADP InlciiiMlcd C'iivniis LH28F008SAR-85 Flash Memory (x8) (Model No.: LHF08S50) Spec No.: EL105019 Issue Date: August 1998 LHF08S50 Abstract: .. .. SAo.16r:' LA17_2Q LATCH SBHE# PSTART# 80386SL PCMO# PM/IO# PW/R# FLSHDCS# PRDY# VGACS# SOQ.1S ~' TRL. SA l_ 16, LA17-20 SAo, LA21-22 AQ.19 ~~: __ CE# .:'.-. Vpp. j"~ ~ -fJ p PLO. CSL 1# _~Sttl .. Tags: datasheet abstract.. |
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First line: CSIhJI LH28F008SAT-85 Rash Memory (Model No.: LHF08S49) SpecNo.: BJ05017 Issue Date: August 1998 LHF08S49 this document carefully contains material protected international copyright law. reproduction, full part, this material prohibited without express written permission company. using products cove Abstract: .. PSTART#~ 80386Sl PCMO# PMlIO# PW/R# FlSHOCS# PROY# VGACS# SOO-'5. -. fB~ I'PlO. CE# 1-+ 1--+ ~ ~} RO# CS# TO OTHER LH28FOO8SA's WE# OE# }j C LL. 8. Vpp. f C LL C 8. Vpp. C 1--+ ICs ,# WR# :r: '" -' WE# :r: '" - .. Tags: datasheet abstract.. |
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First line: 80386 programmers manual pir chip a1283 CL-CD1283 'CIRRUS LOGIC Preliminary Data Book Parallel Port High-speed, bidirectional, multi-protocol parallel port: Hardware implementation modes IEEE (Standard) 1284 specification (including automatic negotiation): mode Reverse-Byte mode Abstract: .. PS/2® style , ECP, and EPP as implemented on the Intel® 80386SL processor . ECP and EPP both operate at data rates as high as 2 Mbytes/second. The IEEE STD 1284-compatible port is implemented .. Tags: a1283 pir chip 80386 programmers manual PIR 203 S 74245 buffer datasheet abstract.. |
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First line: 290446 INTEL CORP (HEMORY/PLD/ 46Ebl7b QQ7b353 flTb 28F200BX-T/B, 28F002BX-T/B MBIT (128K 256K BOOT BLOCK FLASH MEMORY FAMILY x8/x16 Input/Output Architecture 28F200BX-T, 28F200BX-B High Performance High Integration 16-bit 32-bit CPUs x8-only input/Output Architecture Abstract: .. SAo-16 28F200BX-T 80386SL. 5V. SV. GPIO. ..--_. R0t.41S/a. 290448-4. Figure 1. 28F200BX .. Tags: 290446 80386SL intel 80386SL datasheet abstract.. |
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First line: irrte1 OKlFOKRMYOOM] 28F400BX-T/B, 28F004BX-T/B MBIT (256K x16,512K BOOT BLOCK FLASH MEMORY FAMILY x8/x16 Input/Output Architecture 28F400BX-T, 28F400BX-B High Performance High Integration 16-bit 32-bit CPUs x8-only input/Output Architecture 28F004BX-T, 28F004BX-B Space Constrained 8-bit Application Abstract: .. "0-17 80386SL ROMCSO# MEMRD# MEMWR# +5V ROt.lI6/8# GPIO CE# OE# WE# BYTE# 28F400BX-T 5V. 290451-4. Figure 1. 28F400BX Interface to INTEL386SL Microprocessor Superset. A, 6, IS. " As -A, 5 ALE. r=A. ADDRESS .. Tags: datasheet abstract.. |
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First line: intel 28f200bx inte! 28F200BX-T/B, 28F002BX-T/B 2-MBIT (128K 256K BOOT BLOCK FLASH MEMORY FAMILY x8/x16 Input/Output Architecture 28F200BX-T, 28F200BX-B High Performance High Integration 16-bit 32-bit CPUs x8-only input/Output Architecture 28F002BX-T 28F002BX-B Space Constrained 8-bit Applications O Abstract: .. 80386SL. ROMCSO# MEMRD# CE# OE# WE# 28F200BX-T. 5V. BYTE# 5V ROMI6/8# GP10. 290448-4. Figure 1 .. Tags: intel 28f200bx datasheet abstract.. |
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First line: INTEL CORP PIENORY/PLD/ 4flSbl7b QQ7b440 28F400BX-T/B, 28F004BX-T/B MBIT (256K x16, 512K BOOT BLOCK FLASH MEMORY FAMILY x8/x16 Input/Output Architecture 28F400BX-T, 28F400BX-B High Performance High Integration 16-bit 32-bit CPUs x8-only input/Output Architecture 28F004BX-B Space Constrained 8-bit Ap Abstract: .. SAo-17 5V 80386SL. WE +5V ROM16 8 GPIO. 290451-4. Figure 1. 28F400BX Interface to INTEL386SLTM Microprocessor Superset. P,S: 18. ~ As -P,s ALE ADo-A~ .. " ADDRESS LATCHES LE. Fll ~ J. A. \r ~ T" ADDRESS .. Tags: datasheet abstract.. |
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First line: 80386 programmers manual schematic diagram of laptop motherboard CD1284 IEEE 1284-Compatible Parallel Interface Controller with High-Speed Asynchronous Serial Ports Abstract: .. , Reverse Byte IBM PS/2 style , ECP, and EPP as implemented on the Intel 80386SL processor . ECP and EPP both operate at data rates as high as 2 Mbytes/sec. The IEEE 1284 port is implemented .. Tags: schematic diagram of laptop motherboard 80386 programmers manual intel 80386SL pir schematic IC 74245 ic 4800 for laptop motherboard E-102 DC PIR CONTROLLER CD1284 CD1283 automatic room power controller using scr 80386SL 80286 instruction set 74245 BUFFER IC CD1284 |
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First line: 74245 BIDIRECTIONAL BUFFER IC IC 74245 A1284 CL-CD1284 Parallel Port (Peripheral-side) Abstract: .. 80386SL processor . ECP and. EPP both operate at data rates as high as 2 Mbytes/sec. The IEEE 1284 port is implemented as two func-tional blocks: a data pipeline, which includes the 64-byte FIFO .. Tags: A1284 74245 BIDIRECTIONAL BUFFER IC Semiconductor Device Data Book 1996 pir schematic pipeline ARCHITECTURE OF 80386 logic data book IC 74245 DC PIR CONTROLLER computer interface with parallel port to control CL-CD1284-10QC-E CD1284 CD1283 BPV23NF CL-CD1284 |
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First line: 74245 BIDIRECTIONAL BUFFER IC CL-CD1284 Parallel Port (Peripheral-side) High-speed, bidirectional, multi-protocol parallel port: Hardware implementation modes IEEE (Standard) 1284 specification (including automatic negotiation) mode Abstract: .. OVERVIEW cont IBM® PS/2® style , ECP, and EPP as implemented on the Intel® 80386SL processor . ECP and EPP both operate at data rates as high as 2 Mbytes/sec. The IEEE 1284 port is implemented .. Tags: 74245 BIDIRECTIONAL BUFFER IC ALL TYPE IC DATA AND manual substitution BOOK specification of 80386sl processor 74245 BUFFER IC IC 74245 datasheet abstract.. |
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