74LVQ373
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74LVQ373 - 74LVQ373
74LVQ373
VOLTAGE CMOS OCTAL D-TYPE LATCH WITH STATE OUTPUTS INVERTING
HIGH SPEED: (TYP.) COMPATIBLE WITH OUTPUTS POWER DISSIPATION: (MAX.) TA=25°C NOISE: VOLP 0.4V (TYP.) 3.3V TRANSMISSION LINE OUTPUT DRIVE CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: |IOH| 12mA (MIN) LEVELS GUARANTEED BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) 3.6V (1.2V Data Retention) FUNCTION COMPATIBLE WITH SERIES IMPROVED LATCH-UP IMMUNITY
TSSOP
Table Order CodePACKAGE TSSOP 74LVQ373MTR 74LVQ373TTR
DESCRIPTION 74LVQ373 voltage CMOS OCTAL D-TYPE LATCH with STATE OUTPUT INVERTING fabricated with sub-micron silicon gate double-layer metal wiring C2MOS technology. ideal power noise 3.3V applications. These D-Type latch controlled latch Figure Connection Logic Symbol
enable input (LE) output enable input (OE). While inputs held high level, outputs will follow data input precisely. When taken low, outputs will latched precisely logic level input data. While (OE) input low, outputs will normal logic state (high logic level) while high level outputs will high impedance state. inputs outputs equipped with protection circuits against static discharge, giving them immunity transient excess voltage.
July 2004
Rev.
1/13
74LVQ373
Figure Input Output Equivalent Circuit Table Description
16,19 SYMBOL NAME FUNCTION State Output Enable Input (Active LOW) 3-State Latch Outputs Data Inputs Latch Enable Input Ground (0V) Positive Supply Voltage
Table Truth Table
INPUTS OUTPUT CHANGE*
Don't Care; High Impedance outputs latched time when input taken logic level
Figure Logic Diagram
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74LVQ373
Table Absolute Maximum RatingSymbol Tstg Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current Storage Temperature Lead Temperature sec) Parameter Value -0.5 -0.5 -0.5 +150 Unit
IGND Ground Current
Absolute Maximum Ratings those values beyond which damage device occur. Functional operation under these conditions implied
Table Recommended Operating ConditionSymbol dt/dv Supply Voltage (note Input Voltage Output Voltage Operating Temperature Input Rise Fall Time 3.0V (note Parameter Value Unit ns/V
Truth Table guaranteed: 1.2V 3.6V from 0.8V
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74LVQ373
Table SpecificationTest Condition Symbol Parameter 25°C Min. IO=-50 IO=-12 IO=-24 Level Output Voltage IO=50 IO=12 IO=24 Input Leakage Current High Impedance Output Leakage Current Quiescent Supply Current Dynamic Output Current (note VOLD VOHD ±0.25 0.002 0.36 2.58 2.99 2.48 0.44 0.55 ±2.5 Typ. Max. Value 85°C Min. 2.48 0.44 0.55 ±5.0 Max. 125°C Min. Max. Unit
High Level Input Voltage Level Input Voltage High Level Output Voltage
IOLD IOHD
Maximum test duration 2ms, output loaded time Incident wave switching guaranteed transmission lines with impedances
Table Dynamic Switching CharacteristicTest Condition Symbol Parameter 25°C Min. Typ. -0.8 -0.5 Max. Value 85°C Min. Max. 125°C Min. Max. Unit
VOLP VOLV VIHD
VILD
Dynamic Voltage Quiet Output (note Dynamic High Voltage Input (note Dynamic Voltage Input (note
Worst case package. number outputs defined (n). Data inputs driven 3.3V, (n-1) outputs switching output GND. number data inputs switching. (n-1) switching 3.3V. Inputs under test switching: 3.3V threshold (VILD), threshold (VIHD), f=1MHz.
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74LVQ373
Table Electrical Characteristics Input 3ns)
Test Condition Symbol Parameter 3.3(*) 3.3(*) 3.3(*)
Value 25°C Min. Typ. Max. 11.5 11.5 14.0 11.5 14.0 11.5 85°C Min. Max. 13.5 10.5 13.5 10.5 16.0 13.5 16.0 13.5 125°C Min. Max. 15.5 12.0 15.5 12.0 18.5 15.5 18.5 15.5 Unit
tPLH tPHL tPLH tPHL tPLZ tPHZ tPZL tPZH tOSLH tOSHL
Propagation Delay Time Propagation Delay Time Output Disable Time Output Enable Time Pulse Width HIGH Setup Time HIGH Hold Time HIGH Output Output Skew Time (note1,
3.3(*) 3.3(*)
Skew defined absolute value difference between actual propagation delay outputs same device switching same direction, either HIGH (tOSLH |tPLHm tPLHn|, tOSHL |tPHLm tPHLn|) Parameter guaranteed design Voltage range 3.3V 0.3V
Table Capacitive CharacteristicTest Condition Symbol Parameter 10MHz 25°C Min. Typ. Max. Value 85°C Min. Max. 125°C Min. Max. Unit
COUT
Input Capacitance Output Capacitance Power Dissipation Capacitance (note
defined value IC's internal equivalent capacitance which calculated from operating current consumption without load. (Refer Test Circuit). Average operating current obtained following equation. ICC(opr) ICC/8 (per Latch)
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74LVQ373
Figure Test Circuit
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
50pF equivalent (includes probe capacitance) equivalent ZOUT pulse generator (typically
SWITCH Open 2VCC Open
Figure Waveform Propagation Delays, Minimum Pulse Width, Setup Hold Times (f=1MHz; duty cycle)
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74LVQ373
Figure Waveform Output Enable Disable Times (f=1MHz; duty cycle)
Figure Waveform Propagation Delay Time (f=1MHz; duty cycle)
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74LVQ373
SO-20 MECHANICAL DATA
DIM. 10.00 0.25 MIN. 2.35 0.33 0.23 12.60 1.27 10.65 0.75 1.27 0.100 0.394 0.010 0.016 MAX. 2.65 0.30 0.51 0.32 13.00 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 0.004 inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299
0016022D
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74LVQ373
TSSOP20 MECHANICAL DATA
DIM. MIN. 0.45 0.60 0.05 0.19 0.09 0.65 0.75 0.018 0.024 MAX. 0.15 1.05 0.30 0.20 4.48 0.002 0.031 0.007 0.004 0.252 0.244 0.169 0.256 0.252 0.173 0.0256 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.260 0.260 0.176 inch
IDENTIFICATION
0087225C
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74LVQ373
Tape Reel SO-20 MECHANICAL DATA
DIM. MIN. 10.8 13.2 11.9 12.8 20.2 30.4 13.4 12.1 0.425 0.520 0.122 0.153 0.468 MAX. 13.2 0.504 0.795 2.362 1.197 0.433 0.528 0.130 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
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74LVQ373
Tape Reel TSSOP20 MECHANICAL DATA
DIM. MIN. 11.9 12.8 20.2 22.4 12.1 0.268 0.272 0.067 0.153 0.468 MAX. 13.2 0.504 0.795 2.362 0.882 0.276 0.280 0.075 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
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74LVQ373
Table Revision History
Date 29-Jul-2004 Revision Description Changes Ordering Codes Revision pag.
12/13
74LVQ373
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics other names property their respective owners 2004 STMicroelectronics Rights Reserved STMicroelectronics group companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States America www.st.com
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